Data detection on serial communication link

Abstract

A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit including a plurality of sub-circuits. The data detection circuit performs a comparison of a reference voltage to a magnitude of a signal received via the communication link encoding a serial data stream consisting of a plurality of data symbols. Using a result of the comparison, the data detection circuitry may activate an indication indicative of the presence of data on the communication link. Once valid, the speed detection circuit checks the number of transitions to determine the rate at which the data is being transmitted. In response to determining that the rate of the data being transmitted exceeds a threshold, the receiver circuit activates one or more sub-circuits of the plurality of sub-circuits.

Description

Technical Field

[0001] The present disclosure relates to the field of high-speed communication interface design, and in particular to detecting the presence of data on a serial communication link. Background Art

[0002] Computing systems often include multiple interconnected integrated circuits. In some cases, the integrated circuits can communicate using communication channels or links to send and receive data bits. The communication channels can support parallel communication, where multiple data bits are sent in parallel, or serial communication, where data bits are sent one bit at a time in a serial manner.

[0003] Data sent between integrated circuits can be encoded to facilitate transmission. For example, in the case of serial communication, the data can be encoded to provide transitions between logic states sufficient to allow clock and data recovery circuits to operate. Alternatively, in the case of parallel communication, the data can be encoded to reduce switching noise or improve signal integrity.

[0004] During data transmission, the physical characteristics of the communication channel may attenuate the transmitted signal associated with a particular data bit. For example, the impedance of the wiring included in the communication channel or link may attenuate certain frequency ranges of the transmitted signal. In addition, impedance mismatches between the wiring included in the communication channel and the equipment coupled to the communication channel may cause reflections of the transmitted signal, which may degrade subsequent transmitted signals corresponding to other data bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an embodiment of a receiver circuit for a serial communications link in a computer system.

[0006] Figure 2 is a block diagram of an implementation of a data detection circuit.

[0007] Figure 3 is a block diagram of an implementation of a speed detection circuit.

[0008] Figure 4 is a block diagram of an implementation of a receiver circuit.

[0009] Figure 5 is a block diagram of a computer system including a transmitter circuit and a receiver circuit.

[0010] Figure 6 is a diagram depicting sampling of a signal used in a serial communication link to determine transitions.

[0011] Figure 7 is a flow chart of an embodiment of a method for detecting data on a serial link.

[0012] Figure 8is a block diagram of one embodiment of a system on a chip including a detector circuit.

[0013] Fig. 9 is a block diagram of various embodiments of a computer system that may include a receiver circuit.

[0014] Fig.10 An example of a non-transitory computer-readable storage medium storing circuit design information is illustrated.

[0015] Although the embodiments described in the present disclosure may be subject to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and the specific embodiments thereof are not intended to limit the embodiments to the particular forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims. DETAILED DESCRIPTION

[0016] The computing system may include one or more integrated circuits, such as, for example, a central processing unit (CPU) and a memory. The various integrated circuits of the computing system may communicate via a serial or parallel interface. In a parallel interface, multiple data bits are transmitted simultaneously, while in a serial interface, data is transmitted as a series of sequential single data bits. When a serial interface is used to transmit data between two devices included in the computing system, the data may be sent according to different protocols. For example, a return-to-zero (RZ) protocol, a non-return-to-zero (NRZ) protocol, a pulse amplitude modulation (PAM), or any suitable combination thereof may be used to send data.

[0017] Serial data streams are often sent without an accompanying clock signal. In this case, the clock signal is recovered from the serial data stream (in a process known as "clock recovery") and is used to sample the serial data stream to determine the values ​​of the included data symbols. Various techniques can be used to recover the clock signal. For example, a receiver circuit can generate a clock signal with a frequency that is approximately the same as the frequency of the clock signal used to create the data stream. A phase-locked loop circuit can then be used to phase-align the clock signal with the transitions in the serial data stream. Alternatively, the serial data stream can be oversampled, i.e., sampled at a frequency higher than the frequency of the clock signal used to generate the serial data stream.

[0018] In some computer systems, a communication link may operate in different modes. For example, in addition to a high-speed data mode, some communication links also have an idle mode, a low-speed periodic signaling mode. Depending on the operation of the computer system, the communication link may switch between different modes. For example, in response to activation of a sleep or power-down mode of the computer system, the communication link may be placed in an idle mode during which no data is sent.

[0019] A receiver circuit coupled to a communication link must monitor the communication in order to determine the state of the communication link. Different circuits within the receiver circuit may be used for different modes of the communication link. Circuits for a particular mode may be disabled when the mode is not being used, and must be re-enabled when the particular mode is detected on the communication link. Failure to detect a change in the communication link mode may result in loss of transmitted data. For example, circuits within a receiver circuit suitable for use with a low-speed mode may not be sufficient to correctly sample and recover data transmitted in a high-speed mode.

[0020] The embodiments illustrated in the accompanying drawings and described below provide techniques for monitoring the mode of a communication link. Such monitoring includes detecting data sent on the communication link and determining whether the data being sent is high-speed data. By detecting the presence of high-speed data on the serial link, portions of the receiver circuit can be powered on to prevent data loss, which would require retransmission, thereby increasing the latency to resume communication on the serial communication link.

[0021] Figure 1 A block diagram depicting an embodiment of a receiver subsystem is illustrated in As shown, the receiver subsystem 100 includes a signal detection circuit 101 , a speed detection circuit 102 , and a data receiver circuit 103 .

[0022] The signal detection circuit 101 is configured to perform a comparison of the magnitude of the signal 105 with a reference voltage 107. In various embodiments, the signal 105 is transmitted via a communication link 111 and encodes a serial data stream including data symbols 112. The signal detection circuit 101 is also configured to use the result of the comparison to activate a signal present indicator 108. As described below, the signal detection circuit 101 can be configured to use a reference adjustment signal 115 to adjust the value of the reference voltage 107.

[0023] The speed detection circuit 102 is configured to generate a speed signal 109 based on the number of transitions of the signal 105 within the reference time period 113 in response to the activation of the signal presence indicator 108. In some embodiments, the speed detection circuit 102 can use samples 116 generated by the data receiver circuit 103 to determine the number of transitions of the signal 105. As described below, the duration of the reference time period 113 can be adjusted based on the electrical characteristics of the communication link 111 and the receiver subsystem 100. In various embodiments, the activation of the speed signal 109 can correspond to the detection that the data rate of the data symbol 106 exceeds a threshold. In various embodiments, the speed detection circuit 102 is also configured to generate a reference adjustment signal 115 based on the amplitude of the signal 105.

[0024] As used herein, when a signal is activated, it is set to a logic or voltage level that activates a load circuit or device. Depending on the load circuit, the logic level can be a high logic level or a low logic level. For example, the valid state of a signal coupled to a p-channel metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), or a gate-all-around field effect transistor (GAAFET) is a low logic level (referred to as a "low-state active signal"), while the valid state of a signal coupled to an n-channel MOSFET, FinFET, or GAAFET is a high logic level (referred to as a "high-state active signal").

[0025] The data receiver circuit 103 includes subcircuits 114 and is configured to activate one or more of the subcircuits 114 in response to activation of the speed signal 109. As described below, the subcircuits 114 may include filter circuits, equalization circuits, data and clock recovery circuits, etc. In addition, the data receiver circuit 103 is configured to sample the signal 105 to generate samples 116. In various embodiments, the data receiver circuit 103 is further configured to process the samples 116 to generate recovered data symbols 110. It is noted that in some embodiments, the data receiver circuit 103 may be configured to adjust the sampling threshold based on the reference adjustment signal 115.

[0026] Go to Figure 2 , depicts a block diagram of an embodiment of the signal detection circuit 101. As shown, the signal detection circuit 101 includes a reference generator circuit 201 and a comparator circuit 202.

[0027] The reference generator circuit 201 is configured to generate a reference voltage 107. In various embodiments, the reference generator circuit 201 may be further configured to adapt or change the value of the reference voltage 107 using the reference adjustment signal 115. In some cases, the reference generator circuit 201 may be configured to increase the value of the reference voltage 107 in response to determining that the magnitude of the signal 105 has exceeded the initial value of the reference voltage 107. In some embodiments, the reference generator circuit 201 may also be configured to reset the value of the reference voltage 107 to the initial value in response to determining that the communication link or bus through which the signal 105 propagated has entered an idle or dormant state. Note that in some embodiments, the initial value of the reference voltage 107 and the adapted value of the reference voltage 107 may be programmable.

[0028] Reference generator circuit 201 may be implemented using a bandgap reference circuit, a voltage scaling circuit, or any other circuit suitable for generating a reference voltage value. In some cases, reference generator circuit 201 may be configured to generate reference voltage 107 to be independent of temperature and / or supply voltage levels.

[0029] Comparator circuit 202 is configured to generate signal presence indicator 108 using signal 105 and reference voltage 107. In various embodiments, comparator circuit 202 may be configured to compare the voltage level of signal 105 to reference voltage 107 and use the result of the comparison to generate signal presence indicator 108. Note that while comparator circuit 202 is depicted as comparing two signals, in other embodiments, additional comparators may be employed where multiple signals are used to transmit data symbol 106 to receiver subsystem 100.

[0030] In various embodiments, comparator circuit 202 may be implemented using a differential amplifier circuit or any other circuit suitable for comparing respective voltage levels of two or more signals. Where signal presence indicator 108 is a digital signal, comparator circuit 202 may be implemented using a Schmitt trigger circuit or other suitable circuit.

[0031] Figure 3 , a block diagram of the speed detection circuit 102 is depicted in FIG. As shown in the figure, the speed detection circuit 102 includes a logic circuit 301 and a filter circuit 302 .

[0032] Logic circuit 302 is configured to generate speed signal 109 and reference adjustment signal 115 using samples 116. In various embodiments, to generate speed signal 109, logic circuit 302 is configured to determine the number of samples detected in samples 116 during sample window 306 in response to activation of enable signal 305. In various embodiments, the width of sample window 306 may correspond to reference time period 113. Logic circuit 302 is further configured to activate speed signal 109 in response to determining that the number of samples in samples 116 during sample window 306 is greater than a threshold. In response to deactivation of enable signal 305, logic circuit 302 is further configured to maintain speed signal 109 in a deactivated or inactive state.

[0033] In various embodiments, logic circuit 302 may be configured to change the value of reference adjustment signal 115 based on one or more values ​​of sampled signal 304. In some cases, in response to detecting an increase in the number of samples 116 measured within consecutive sample windows in sample window 306, logic circuit 302 may be configured to increase the value of reference adjustment signal 115. In various embodiments, reference adjustment signal 115 may be a digital signal including a plurality of bits encoding information indicating a desired value of reference voltage 107. Alternatively, reference adjustment signal 115 may be an analog signal used by reference generator circuit 201 to adjust the value of reference voltage 107.

[0034] Logic circuit 302 may be implemented using a microcontroller, a state machine, or any other suitable combination of sequential and combinational logic circuits. In some embodiments, logic circuit 302 may be configured to receive information indicating an operating characteristic of a computer system including receiver subsystem circuit 100, and adjust the duration of sample window 306 based on the received information. In various embodiments, such information may include temperature, noise levels on communication link 111, power supply voltage levels, etc. Alternatively, logic circuit may include one or more register circuits that may be programmed with different values ​​for sample window 306.

[0035] When the amplitude of signal 105 approaches reference voltage 107, the output of comparator circuit 202 may switch between a high logic level and a low logic level due to tolerances of circuit elements in comparator circuit 202 and variations in reference voltage 107 due to power supply noise, etc. Therefore, there may be a range of voltage levels of signal 105 during which the value of signal present indicator 108 may be changing. To remedy this problem, a filter is employed.

[0036] Filter circuit 303 is configured to generate enable signal 305 using signal presence indicator 108. In various embodiments, filter circuit 303 may be configured to perform a digital filter operation on signal presence indicator 108 to generate enable signal 305. The digital filter operation may include performing a plurality of averaging operations. In some embodiments, filter circuit 303 may be programmable to account for changes in the operating characteristics of a computer system including receiver subsystem 100. In various embodiments, filter circuit 303 may be implemented using a state machine or any other suitable combination of sequential and combinational logic circuits.

[0037] Go to Figure 4 , depicts a block diagram of the data receiver circuit 103. As shown, the data receiver circuit 103 includes a front-end circuit 401, a sampling circuit 402, a recovery circuit 403, and an equalization circuit 404. In various embodiments, one or more of the front-end circuit 401, the sampling circuit 402, the recovery circuit 403, and the equalization circuit 404 may be included in the sub-circuit 114.

[0038] Front-end circuit 401 is configured to use signal 105 to generate equalized signal 405. In various embodiments, front-end circuit 401 can be implemented using filter circuits and automatic gain control circuits. In some embodiments, front-end circuit 401 can use continuous-time linear equalization techniques, while in other embodiments, front-end circuit 401 can use any suitable equalization techniques.

[0039] The sampling circuit 402 is configured to generate samples 116 using a combination of the equalized signal 405 and the adjustment signal 407, as well as an edge clock 410 and a data clock 411. In various embodiments, the sampling circuit 402 may employ a plurality of clipping circuits configured to compare the combination of the equalized signal 405 and the adjustment signal 407 with corresponding thresholds to generate the samples 116. In some cases, the sampling circuit 402 is further configured to adjust the threshold based on the reference adjustment signal 115. In some embodiments, the reference adjustment signal 115 may actuate one or more analog switches to select a different threshold from a plurality of thresholds. Alternatively, the reference adjustment signal 115 may adjust a bias voltage and / or current within a reference generator circuit to change the threshold.

[0040] In other embodiments, sampling circuit 402 may include one or more analog-to-digital converter circuits configured to generate a plurality of bits whose values ​​encode the amplitude of the combination of equalized signal 405 and adjustment signal 407 at a particular point in time. In various embodiments, the time at which the output of the analog-to-digital converter circuit is captured may be controlled by edge clock 410 and data clock 411.

[0041] In various embodiments, edge clock 411 and data clock 411 are synchronized to transitions of signal 105 corresponding to changes in data symbol 112. Sampling circuit 402 is configured to sample the combination of equalized signal 405 and adjustment signal 407 near transitions using the rising and falling edges of edge clock 410. In a similar manner, sampling circuit 402 is configured to sample the combination of equalized signal 405 and adjustment signal 407 between transitions using data clock 411.

[0042] The recovery circuit 403 is configured to use the samples 116 to generate the recovered data 408, the recovered clock 409, the edge clock 410, and the data clock 411. In various embodiments, the recovery circuit 403 may perform various operations (e.g., feed-forward equalization) to generate the recovered data 408. In some cases, the recovery circuit 403 may operate on multiple symbols in parallel. In this case, the recovery circuit 403 may wait until a certain number of samples have been received from the received samples 406 before performing certain clock and data recovery operations. In some embodiments, the recovery circuit 403 may include a phase-locked loop circuit, a delay-locked loop circuit, or any other suitable circuit to generate the edge clock 410 so that the edge clock is aligned with the transition of the combination of the equalized signal 405 and the adjustment signal 407. The recovery circuit 403 may employ similar circuits to generate the data clock 411 with a known phase difference (e.g., 90 degrees) relative to the edge clock 410.

[0043] The equalization circuit 404 is configured to generate an adjustment signal 407 using the recovered data 408 and the recovered clock 409. In various embodiments, the equalization circuit 404 may be implemented using a decision feedback equalization (DFE) circuit configured to scale an analog voltage level using a plurality of symbols included in the recovered data 408 to generate the adjustment signal 407 in order to eliminate inter-symbol interference (ISI) that occurs when the signal 105 is transmitted over the communication link 111.

[0044] As described above, a detector circuit such as receiving subsystem 100 may be used in a computer system having a communication link. Figure 5 A block diagram of an embodiment of such a computer system is depicted in As shown, computer system 500 includes devices 501 and 502 coupled via a communication bus 507 .

[0045] Device 501 includes circuit block 503 and transmitter circuit 504. In various embodiments, device 501 may be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block on an integrated circuit that may be included in a computer system. Note that while device 501 depicts only a single circuit block and a single transmitter circuit, in other embodiments, additional circuit blocks and additional transmitter circuits may be employed.

[0046] Transmitter circuit 504 is configured to serially transmit a signal corresponding to data received from circuit block 503 via communication bus 507. Such a signal may differentially encode one or more bits so that at a particular point in time, the difference between the corresponding voltage levels of lines 508A and 508B corresponds to a particular bit value. In some cases, the generation of the signal may include encoding the bits before transmission. It should be noted that although communication bus 507 is depicted as including two lines, any suitable number of lines may be used in other embodiments. In some cases, transmitter circuit 504 may be further configured to generate a transmit signal according to one of a variety of communication protocols, such as a USB protocol.

[0047] Device 502 includes signal detection circuit 101, receiver circuit 505, and circuit block 506. Similar to device 501, device 502 may be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block configured to receive data from transmitter circuit 504. In various embodiments, receiver circuit 505 may be configured to place certain sub-circuits within receiver circuit 505 into a sleep or power-down state when communication bus 507 is idle. As described above, signal detection circuit 101 is configured to generate an enable signal when data transmission is resumed on communication bus 507. The enable signal is used by receiver circuit 505 to reactivate any circuit block that has previously been placed into a sleep or power-down state.

[0048] In some embodiments, devices 501 and 502 may be fabricated on a common integrated circuit. In other embodiments, devices 501 and 502 may be located on different integrated circuits mounted on a common substrate or circuit board. In this case, communication bus 507 may include metal or other conductive traces on the substrate or circuit board. Although only two devices are depicted in computer system 500, any suitable number of devices may be employed in other embodiments.

[0049] Go to Figure 6 , illustrates a waveform depicting sampling of a signal used in a serial communication link to determine a transition. Note that the waveforms are examples, and in a sequential implementation, the relative timing of the waveforms may be different. In various implementations, the edge clock 307 may be 90 degrees out of phase with the data clock 308.

[0050] As described above, once signal detection circuit 101 determines the presence of data on communication link 111, edge clock 307 and data clock 308 may be aligned using transitions of signal 105. Edge clock 307 and data clock 308 may be aligned using a clock recovery circuit or any other suitable method for aligning clocks with transitions of signal 105.

[0051] At time t1, the rising edge of edge clock 307 is used to sample signal 105. At time t2, the falling edge of edge clock 307 is used to sample signal 105. In various embodiments, the sample from time t1 is compared to the sample from t3. In response to determining that the two samples have different values, sampling circuit 301 is configured to detect a transition of signal 105 that occurs between times t1 and t3.

[0052] At time t2, the falling edge of data clock 308 is used to sample signal 105, and at time t4, the rising edge of data clock 308 is used to sample signal 105. In various embodiments, sampling circuit 301 is configured to compare the sample taken at time t2 with the sample taken at time t4. Since data clock 308 should be sampling signal 105 during a valid data period, two samples can be used to determine whether a transition has occurred. In some cases, such information can be relayed to the clock recovery circuit to adjust the timing of data clock 308.

[0053] In some embodiments, sampling circuit 301 may be configured to compare a sample taken at time t2 with a sample taken at time t3. If the two samples do not have the same value, sampling circuit 301 is configured to indicate a transition. By using both the rising and falling edges of edge clock 307 and data clock 308, the granularity with which sampling circuit 301 samples signal 105 may be very fine. In the event that a transition is detected in an unexpected location (e.g., between time t3 and t4), the timing of edge clock 307 and data clock 308 may be adjusted. In a similar manner, if a transition is not detected where a transition is expected (e.g., between time t1 and t2), the timing of edge clock 308 and data clock 308 may be further adjusted.

[0054] It should be noted that the comparison of the above samples is only an example. In other embodiments, the samples taken at the rising and falling edges of the edge clock 307 and the data clock 308 can be compared according to any suitable algorithm.

[0055] In summary, various embodiments of a serial data receiver circuit including a detector circuit are disclosed. In general, an apparatus is contemplated in which a signal detection circuit is configured to perform a first comparison of the amplitude of at least one signal with a reference voltage. In various embodiments, the at least one signal encodes a serial data stream including a plurality of data symbols. The signal detection circuit is further configured to activate a signal presence indicator using the result of the comparison. The speed detection circuit is configured to generate an enable signal based on the number of transitions of the serial data stream within a reference time period in response to activation. The receiver circuit includes a plurality of subcircuits, and the receiver circuit is configured to activate one or more of the plurality of subcircuits in response to activation of the enable signal.

[0056] In other embodiments, to generate the enable signal, the speed detection circuit is further configured to sample the at least one signal to generate a plurality of samples and use the plurality of samples to determine the number of transitions of the serial data stream within a reference time period. The speed detection circuit may be further configured to perform a second comparison of the number of transitions with a threshold value and use the result of the second comparison to activate the enable signal.

[0057] In some embodiments, the speed detection circuit is further configured to filter to generate a filtered valid signal, and in response to determining that the filtered valid signal has a specific value, sample the at least one signal to generate the plurality of samples. In various embodiments, the speed detection circuit is further configured to adjust the value of the reference time period using one or more operating characteristics of a computer system including the receiver circuit.

[0058] In various embodiments, to sample the at least one signal, the speed detection circuit is further configured to sample the at least one signal using a first edge of the clock signal to generate a first sample, and to sample the at least one signal using a second edge of the clock signal to generate a second sample. In this case, to perform the second comparison, the speed detection circuit is further configured to compare the first sample with the second sample. In other embodiments, the data detection circuit is further configured to set the reference voltage to an initial value, and to modify the value of the reference voltage in response to determining that the amplitude of the at least one signal exceeds the initial value of the reference voltage.

[0059] Go to Figure 7 , illustrates a flow chart depicting an embodiment of a method for detecting data on a communication link. Figure 1 The methods of various receiver subsystems such as receiver subsystem 100 depicted in FIG. 7 begin at block 701 .

[0060] The method includes receiving, by a detector circuit via a communication link, one or more signals encoding a serial data stream including a plurality of data symbols (block 702). In various embodiments, the serial data stream may be encoded as one of a variety of communication protocols, such as a USB protocol.

[0061] The method also includes: performing, by the detector circuit, a first comparison of the amplitude of at least one of the plurality of signals with a reference voltage (block 703). In various embodiments, the method may also include: setting the reference voltage to an initial value, and modifying the value of the reference voltage in response to determining that the amplitude of the at least one signal exceeds the initial value of the reference voltage.

[0062] The method also includes generating, by the detector circuit, a signal presence indicator using the result of the first comparison (block 704). In some embodiments, generating may include generating a digital value based on the result of the first comparison.

[0063] The method also includes: in response to activating the signal presence indicator, sampling the at least one signal by the detector circuit to generate a plurality of samples (block 705). In some embodiments, the method also includes: filtering by the detector circuit to generate a filtered valid signal, and sampling the at least one signal by the detector circuit in response to determining that the filtered valid signal has a particular value to generate the plurality of samples. In various embodiments, the method may also include: sampling the at least one signal using one or more thresholds, and adjusting the one or more thresholds in response to determining that the amplitude of the at least one signal exceeds the initial value of the reference voltage.

[0064] In other embodiments, sampling the at least one signal includes: sampling the at least one signal using a first edge of a clock signal to generate a first sample, and sampling the at least one signal using a second edge of the clock signal to generate a second sample. The method may also include: determining the number of transitions includes comparing the first sample to the second sample. It is noted that while the method describes the use of a single clock signal, in other embodiments, different clock signals (e.g., an edge clock signal and a data clock signal) may be used to sample the at least one signal, and different samples from the different clock signals may be compared to determine the number of transitions.

[0065] The method also includes determining, by the detector circuit, a number of transitions of the serial data stream during a reference time period using the plurality of samples (block 706). In some embodiments, the method may also include determining a value of the reference time period using one or more operating characteristics of a computer system including the detector circuit. In various embodiments, the one or more operating characteristics may include a noise level of the communication link, a temperature of the computer system, a voltage level of a power supply node coupled to the detector circuit, or any other suitable operating characteristic of the computer system.

[0066] The method also includes activating one or more sub-circuits of a plurality of sub-circuits included in a receiver circuit coupled to the communication link based on the number of transitions (block 707). In various embodiments, activating the one or more sub-circuits may include performing a second comparison of the number of transitions with a threshold value, and generating an enable signal using a result of the second comparison. The method may also include activating the one or more sub-circuits in response to activating the enable signal.

[0067] In other embodiments, the method may include, in response to activating the one or more sub-circuits, recovering, by the receiver circuit, one or more data symbols of the plurality of data symbols from the one or more signals. The method ends at block 708 .

[0068] exist Figure 8 A block diagram of a system on a chip (SoC) is illustrated in FIG. In the illustrated embodiment, SoC 800 includes processor circuitry 801, memory circuitry 802, analog / mixed signal circuitry 803, and input / output circuitry 804, each of which is coupled to a communication bus 805. In various embodiments, SoC 800 may be configured for use in a desktop computer, a server, or in a mobile computing application such as, for example, a tablet computer, a laptop computer, or a wearable computing device.

[0069] In various embodiments, processor circuit 801 may represent a general purpose processor that performs computing operations. For example, processor circuit 801 may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA).

[0070] In various embodiments, memory circuit 802 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Figure 8 A single memory circuit is illustrated in FIG. 1 , but in other embodiments, any suitable number of memory circuits may be employed.

[0071] The analog / mixed signal circuit 803 may include a crystal oscillator circuit, a phase-locked loop (PLL) circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit (all not shown). In other embodiments, the analog / mixed signal circuit 803 may be configured to perform power management tasks by including an on-chip power supply and voltage regulator.

[0072] Input / output circuitry 804 may be configured to coordinate data transfers between SoC 800 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., magnetic or optical media based storage devices, including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, input / output circuitry 804 may be configured to implement a Universal Serial Bus (USB) protocol or an IEEE 1394 The version of the agreement, and include Figure 1 Receiver subsystem 100 depicted in an embodiment of the present invention.

[0073] The input / output circuitry 804 may also be configured to coordinate data transfers between the SoC 800 and one or more devices (e.g., other computing systems or integrated circuits) coupled to the SoC 800 via a network. In one embodiment, the input / output circuitry 804 may be configured to perform the data processing necessary to implement an Ethernet (IEEE 802.3) networking standard such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, but it is contemplated that any suitable networking standard may be implemented. In some embodiments, the input / output circuitry 804 may be configured to implement multiple discrete network interface ports.

[0074] Now go to Fig. 9, illustrates various types of systems that may include any of the circuits, devices, or systems described above. Systems or devices 900 that may incorporate or otherwise utilize one or more of the techniques described herein may be used in a wide variety of fields. For example, system or device 900 may be used as part of the hardware of a system such as a desktop computer 910, a laptop computer 920, a tablet computer 930, a cellular or mobile phone 940, or a television 950 (or a set-top box coupled to a television).

[0075] Similarly, the disclosed elements can be used in a wearable device 960, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. The wearable device can also be designed to perform only health monitoring functions, such as monitoring the user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices that can be implanted in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0076] The system or device 900 may also be used in various other contexts. For example, the system or device 900 may be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 970. Further, the system or device 900 may be implemented in a wide range of dedicated everyday devices, including common devices 980 in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is generally referred to as the "Internet of Things" (IoT). Elements may also be implemented in various modes of transportation. For example, the system or device 900 may be used for control systems, guidance systems, entertainment systems, etc. of various types of vehicles 990.

[0077] Fig. 9 The applications shown in are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable game devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0078] Fig.10 1010 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1020 is configured to process design information 1015 stored on a non-transitory computer-readable storage medium 1010 and to manufacture an integrated circuit 1030 based on the design information 1015.

[0079] The non-transitory computer-readable storage medium 1010 may include any of various suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1010 may be an installation medium, for example, a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, RambusRAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 1010 may also include other types of non-transitory memories or combinations thereof. The non-transitory computer-readable storage medium 1010 may include two or more memory media that may reside in different locations (for example, in different computer systems connected by a network).

[0080] The design information 1015 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1015 may be used by the semiconductor manufacturing system 1020 to manufacture at least a portion of the integrated circuit 1030. The format of the design information 1015 may be recognizable by at least one semiconductor manufacturing system, such as, for example, the semiconductor manufacturing system 1020. In some embodiments, the design information 1015 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in the integrated circuit 1030 may also be included in the design information 1015. Such cell libraries may include information indicating a device or transistor level netlist, mask design data, characterization data, etc. of the cells included in the cell library.

[0081] In various embodiments, integrated circuit 1030 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, design information 1015 may include information related to the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0082] Semiconductor manufacturing system 1020 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1020 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0083] In various embodiments, integrated circuit 1030 is configured to operate according to the circuit design specified by design information 1015, which may include performing any of the functions described herein. For example, integrated circuit 1030 may include any of the various elements shown or described herein. In addition, integrated circuit 1030 may be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein may be performed by multiple connected integrated circuits.

[0084] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0085] ***

[0086] This disclosure includes references to "embodiments," which are non-limiting, specific implementations of the disclosed concepts. References to "an embodiment," "one embodiment," "a specific embodiment," "some embodiments," "various embodiments," etc., do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including the specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of this disclosure. Not all of these embodiments will necessarily exhibit any or all of the potential advantages described herein.

[0087] Unless otherwise stated, the specific embodiments are not intended to limit the scope of the claims drafted based on the disclosure of the disclosed form, even if only a single example is described for a particular feature. Therefore, the disclosed embodiments are intended to be illustrative rather than restrictive, without any statement to the contrary. This patent application is intended to cover such alternatives, modifications, and equivalents, which will be obvious to those skilled in the art having the benefit of this disclosure.

[0088] The specific features, structures or characteristics may be combined in any suitable manner consistent with the present disclosure. Therefore, the present disclosure is intended to include any feature or combination of such features disclosed herein (explicitly or implicitly), or any generalization thereof. Therefore, new claims may be made during the prosecution of the present application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the attached claims, features of the dependent claims may be combined with features of the independent claims, and features from the corresponding independent claims may be combined in any suitable manner rather than just by the specific combinations listed in the attached claims.

[0089] For example, although the appended dependent claims are drafted so that each dependent claim is dependent on a single other claim, additional dependencies are also contemplated. It is also contemplated that a claim drafted in one legal type (e.g., apparatus) may inspire a corresponding claim of another legal type (e.g., method), where appropriate.

[0090] ***

[0091] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0092] Unless the context clearly dictates otherwise, references to singular forms such as “a,” “an,” and “the” are intended to mean “one or more.” Thus, reference to “an item” in a claim does not exclude additional instances of that item.

[0093] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0094] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0095] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," covering x but not y, y but not x, and both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0096] The expressions "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "at least one of ... w, x, y, and z" refers to at least one element of the elements in the set [w, x, y, z], thereby covering all possible combinations in the list of options. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0097] In this disclosure, various "labels" may precede a noun. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to a particular feature.

[0098] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0099] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function.

[0100] The phrase “configured to” perform one or more tasks in the appended claims is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution, it will use the phrase “means for [performing the function]” to describe the claim element.

[0101] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence a determination. That is, a determination may be based only on specified factors or on specified factors as well as other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0102] The phrase "in response to" describes one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, the effect may be responsive only to those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B performing A." The phrase specifies that B is the factor that triggers the performance of A. The phrase does not exclude that performing A may also be responsive to some other factor, such as C. The phrase is also intended to cover embodiments in which A is performed only in response to B.

Claims

1. A device, comprising: A data detection circuit, wherein the data detection circuit is configured to: performing a first comparison of a magnitude of at least one signal to a reference voltage, wherein the at least one signal encodes a serial data stream including a plurality of data symbols; as well as using a result of said first comparison to activate a signal present indicator; a speed detection circuit configured to generate a speed detection signal based on a number of transitions of the serial data stream within a reference time period in response to activation of the signal presence indicator; and A receiver circuit includes a plurality of sub-circuits, wherein the receiver circuit is configured to activate one or more of the plurality of sub-circuits in response to activation of the speed detection signal.

2. The apparatus of claim 1 , wherein the receiver circuit is further configured to sample at least one signal to generate a plurality of samples, and wherein to generate the speed detection signal, the speed detection circuit is further configured to: determining a number of transitions of the serial data stream within a reference time period using the plurality of samples; performing a second comparison of the number of transitions with a threshold; and The result of the second comparison is used to activate the speed detection signal. 3 . The apparatus of claim 2 , wherein the speed detection circuit is further configured to filter the data valid signal to generate a filtered valid signal.

4. The apparatus of claim 2, wherein the speed detection circuit is further configured to adjust the value of the reference time period using one or more operating characteristics of a computer system including the receiver circuit.

5. The apparatus of claim 2, wherein to sample the at least one signal, the receiver circuit is further configured to: sampling the at least one signal using a first edge of a clock signal to generate a first sample; and sampling the at least one signal using a second edge of the clock signal to generate a second sample; and To perform the second comparison, the speed detection circuit is further configured to compare the first sample with the second sample.

6. The apparatus according to claim 1, wherein the data detection circuit is further configured to: setting the reference voltage to an initial value; and The value of the reference voltage is modified in response to determining that the magnitude of the at least one signal exceeds the initial value of the reference voltage.

7. A method comprising: receiving, by a detector circuit via a communication link, one or more signals encoding a serial data stream including a plurality of data symbols; performing, by the detector circuit, a first comparison of the magnitude of at least one of the one or more signals with a reference voltage; generating, by the detector circuit, a signal presence indicator using a result of the first comparison; in response to activating the signal presence indicator, sampling, by the detector circuit, the at least one signal to generate a plurality of samples; using the plurality of samples, by the detector circuit, to determine a number of transitions of the serial data stream during a reference time period; as well as One or more sub-circuits of a plurality of sub-circuits included in a receiver circuit coupled to the communication link are activated based on the number of transitions.

8. The method of claim 7, wherein activating the one or more sub-circuits comprises: performing a second comparison of the number of transitions with a threshold; using a result of the second comparison to generate an enable signal; as well as The one or more sub-circuits are activated in response to activating the enable signal.

9. The method according to claim 7, further comprising: The value of the reference time period is determined using one or more operating characteristics of a computer system including the detector circuit.

10. The method according to claim 7, further comprising: Setting the reference voltage to an initial value; as well as The value of the reference voltage is modified in response to determining that the magnitude of the at least one signal exceeds the initial value of the reference voltage.

11. The method according to claim 7, further comprising: filtering, by the detector circuit, the data valid signal to generate a filtered valid signal; as well as The at least one signal is sampled by the detector circuit in response to determining that the filtered valid signal has a particular value to generate the plurality of samples.

12. The method of claim 7, wherein sampling the at least one signal by the detector circuit comprises: sampling the at least one signal using a first edge of a clock signal to generate a first sample; as well as sampling the at least one signal using a second edge of the clock signal to generate a second sample; and Determining the number of transitions includes comparing the first sample with the second sample.

13. The method according to claim 7, further comprising: In response to activating the one or more sub-circuits, one or more data symbols of the plurality of data symbols are recovered by the receiver circuit from the one or more signals.

14. A device, comprising: a first device configured to transmit one or more signals via a communication link, wherein the one or more signals encode a serial data stream comprising a plurality of data symbols; and a second device coupled to the communication link, wherein the second device comprises a detector circuit configured to: receiving the one or more signals via the communication link; performing a first comparison of the magnitude of at least one of the one or more signals with a reference voltage; generating a signal presence indicator using a result of said first comparison; responsive to activation of the signal presence indicator, sampling the at least one signal to generate a plurality of samples; as well as determining a number of transitions of the serial data stream during a reference time period using the plurality of samples; and Wherein the second device further comprises a receiver circuit comprising a plurality of sub-circuits, and wherein the receiver circuit is configured to activate one or more of the plurality of sub-circuits based on the number of transitions.

15. The apparatus of claim 14, wherein the detector circuit is further configured to: performing a second comparison of the number of transitions with a threshold; and using the result of the second comparison to generate an enable signal; and Wherein the receiver circuit is further configured to activate the one or more sub-circuits in response to activation of the enable signal.

16. The apparatus of claim 14, wherein the detector circuit is further configured to determine a value of the reference time period using one or more operating characteristics of a computer system including the first device and the second device.

17. The apparatus of claim 14, wherein the detector circuit is further configured to: setting the reference voltage to an initial value; and The value of the reference voltage is modified in response to determining that the magnitude of the at least one signal exceeds the initial value of the reference voltage.

18. The apparatus of claim 14, wherein the detector circuit is further configured to: filtering the data valid signal to generate a filtered valid signal; and The at least one signal is sampled to generate the plurality of samples in response to determining that the filtered valid signal has a particular value.

19. The apparatus of claim 14, wherein to sample the at least one signal, the detector circuit is further configured to: sampling the at least one signal using a first edge of a clock signal to generate a first sample; and The at least one signal is sampled using a second edge of the clock signal to generate a second sample.

20. The apparatus of claim 19, wherein to determine the number of transitions, the detector circuit is further configured to include comparing the first sample to the second sample.

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