Display panel and display device

Abstract

The invention discloses a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate, the substrate is provided with a first display area, and the first display area comprises a plurality of pixel circuit areas and a light-transmitting area; the plurality of pixel circuit groups are located in the pixel circuit area, each pixel circuit group comprises a plurality of pixel circuits, and the minimum distance between the adjacent pixel circuit groups is larger than the minimum distance between the adjacent pixel circuits in the pixel circuit groups; a plurality of types of first signal lines, partial types of first signal lines in the plurality of types of first signal lines including metal signal lines, and the remaining types of first signal lines including transparent signal lines; the orthographic projection of at least part of the light emitting units in the plurality of light emitting units on the substrate is overlapped with the orthographic projection of at least part of the line segments in the plurality of types of first signal lines on the substrate. By adopting the display panel, the phenomenon of undesirable via holes around the first display area is reduced, and the display uniformity of the display panel is improved.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display panels have been widely used due to their advantages such as self-luminescence, low driving voltage, and fast response speed.

[0003] Summary of the Invention

[0004] The embodiments of the present application provide a display panel and a display device, and the solutions are as follows:

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0006] A base substrate having a first display area, wherein the first display area includes a plurality of pixel circuit areas and a light-transmitting area;

[0007] a plurality of pixel circuit groups located in the plurality of pixel circuit areas, the pixel circuit groups including a plurality of pixel circuits, the minimum distance between adjacent pixel circuit groups being greater than the minimum distance between adjacent pixel circuits within the pixel circuit groups; and a plurality of types of first signal lines connected to the plurality of pixel circuits, some types of the first signal lines including metal signal lines and others including transparent signal lines, at least some line segments of the plurality of types of first signal lines being located in the light-transmitting area;

[0008] A plurality of light-emitting units are located in the first display area, the plurality of pixel circuit groups are configured to drive the plurality of light-emitting units to emit light, and the orthographic projections of at least some of the plurality of light-emitting units on the base substrate overlap with the orthographic projections of at least some of the line segments of the plurality of types of first signal lines located in the light-transmitting area on the base substrate.

[0009] In one possible implementation, at least some of the line segments in the metal signal line are located in the light-transmitting area, and the orthographic projection of at least some of the multiple light-emitting units on the base substrate overlaps with the orthographic projection of at least some of the line segments in the metal signal line on the base substrate.

[0010] In a possible implementation, at least some of the line segments in the transparent signal line are located in the light-transmitting area, and the orthographic projection of at least some of the multiple light-emitting units on the base substrate overlaps with the orthographic projection of at least some of the line segments in the transparent signal line on the base substrate.

[0011] In one possible implementation, the multiple pixel circuit groups include multiple first pixel circuit groups and multiple second pixel circuit groups, the multiple first pixel circuit groups are arranged in multiple rows, the multiple second pixel circuit groups are arranged in multiple rows, a row of second pixel circuit groups is arranged between any two adjacent rows of first pixel circuit groups, and in any row of first pixel circuit groups and a row of second pixel circuit groups adjacent to any row of first pixel circuit groups, the position of the spacing area between any two adjacent first pixel circuit groups corresponds to the position of a second pixel circuit group.

[0012] In a possible implementation, each pixel circuit group includes at least one pixel circuit unit, where the pixel circuit unit includes a first pixel circuit, a second pixel circuit, and a third pixel circuit, and the second pixel circuit is located between the first pixel circuit and the third pixel circuit;

[0013] The light emitting unit includes a first light emitting element, two second light emitting elements and a third light emitting element;

[0014] The first light-emitting element is connected to the first pixel circuit, and an orthographic projection of an anode of the first light-emitting element on the substrate at least partially overlaps with an orthographic projection of a pixel circuit group where the first pixel circuit is located on the substrate;

[0015] The two second light-emitting elements are both connected to the second pixel circuit, and the orthographic projections of the anodes of the two second light-emitting elements on the base substrate are respectively located on two opposite sides of the orthographic projection of the second pixel circuit on the base substrate;

[0016] The third light-emitting element is connected to the third pixel circuit, and the orthographic projection of the anode of the third light-emitting element on the base substrate at least partially overlaps with the orthographic projection of the pixel circuit group where the third pixel circuit is located on the base substrate.

[0017] In a possible implementation, the orthographic projection of the anode of the first light-emitting element on the base substrate is located within the orthographic projection of the pixel circuit group where the first pixel circuit is located on the base substrate;

[0018] The orthographic projections of the anodes of the two second light-emitting elements on the substrate do not overlap with the orthographic projections of the pixel circuit group where the second pixel circuit is located on the substrate;

[0019] The orthographic projection of the anode of the third light-emitting element on the base substrate is located within the orthographic projection of the pixel circuit group where the third pixel circuit is located on the base substrate.

[0020] In a possible implementation, the first light-emitting element, the second light-emitting element, and the third light-emitting element are respectively a blue light-emitting element, a green light-emitting element, and a red light-emitting element; the first pixel circuit, the second pixel circuit, and the third pixel circuit of the pixel circuit unit of the first pixel circuit group are respectively a pixel circuit driving the blue light-emitting element, a pixel circuit driving the green light-emitting element, and a pixel circuit driving the red light-emitting element;

[0021] The first pixel circuit, the second pixel circuit, and the third pixel circuit of the pixel circuit unit of the second pixel circuit group are respectively a pixel circuit for driving the blue light-emitting element, a pixel circuit for driving the green light-emitting element, and a pixel circuit for driving the red light-emitting element; or

[0022] The first pixel circuit, the second pixel circuit, and the third pixel circuit of the pixel circuit unit of the second pixel circuit group are respectively a pixel circuit for driving the red light-emitting element, a pixel circuit for driving the green light-emitting element, and a pixel circuit for driving the blue light-emitting element.

[0023] In a possible implementation, the metal signal line in the first signal line includes a first portion, a second portion, and a third portion, the third portion is located between the first portion and the second portion, and two ends of the third portion are connected to the first portion and the second portion respectively;

[0024] The first portion and the second portion are respectively connected to pixel circuits in two adjacent pixel circuit groups, and the orthographic projection of the third portion on the base substrate at least partially overlaps with the orthographic projection of the anode of the second light-emitting element on the base substrate.

[0025] In one possible implementation, the orthographic projection of the anode of a second light-emitting element on the substrate at least partially overlaps with the orthographic projection of the third portion of at least two of the metal signal lines on the substrate, and the overlapping portion between the third portion of at least two of the metal signal lines and the anode of the second light-emitting element is symmetrically arranged based on the symmetry axis of the anode of the second light-emitting element.

[0026] In a possible implementation, the anodes of the first light-emitting element, the second light-emitting element, and the third light-emitting element are all circular in shape.

[0027] In a possible implementation, the anodes of the two second light-emitting elements are connected via a first connecting line, and the first connecting line is connected to the second pixel circuit.

[0028] In a possible implementation, the types of the first signal lines include a first reset signal line, a second reset signal line, a first reset power line, a second reset power line, a third reset power line, a first gate signal line, a second gate signal line, a data signal line, a light emitting control signal line, and a driving power line;

[0029] The pixel circuit comprises:

[0030] a first transistor, wherein a gate of the first transistor is connected to the first reset signal line, a first electrode of the first transistor is connected to the first reset power line, and a second electrode of the first transistor is connected to the first node;

[0031] a second transistor, wherein a gate of the second transistor is connected to the first gate signal line, a first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to the second node;

[0032] a third transistor, wherein a gate of the third transistor is connected to the second node, a first electrode of the third transistor is connected to the first node, and a second electrode of the third transistor is connected to a third node;

[0033] a fourth transistor, wherein a gate of the fourth transistor is connected to the second gate signal line, a first electrode of the fourth transistor is connected to the data signal line, and a second electrode of the fourth transistor is connected to the third node;

[0034] a fifth transistor, wherein a gate of the fifth transistor is connected to the light emission control signal line, a first electrode of the fifth transistor is connected to the third node, and a second electrode of the fifth transistor is connected to the driving power line;

[0035] a sixth transistor, wherein a gate of the sixth transistor is connected to the light-emission control signal line, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to the anode of the light-emitting element;

[0036] a seventh transistor, wherein a gate of the seventh transistor is connected to the second reset signal line, a first electrode of the seventh transistor is connected to the second reset power line, and a second electrode of the seventh transistor is connected to the anode of the light-emitting element;

[0037] an eighth transistor, wherein a gate of the eighth transistor is connected to the second reset signal line, a first electrode of the eighth transistor is connected to the third reset power line, and a second electrode of the eighth transistor is connected to the third node;

[0038] A storage capacitor, wherein two ends of the storage capacitor are connected to the driving power line and the second node respectively.

[0039] In a possible implementation, the second transistor is an N-type transistor, and the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type transistors.

[0040] In a possible implementation, the second transistor is an oxide thin film transistor, and the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all low-temperature polysilicon thin film transistors.

[0041] In a possible implementation, each pixel circuit unit corresponds to two first reset power lines, three second reset power lines, and one third reset power line;

[0042] For each pixel circuit unit, the orthographic projections of the two first reset power lines on the base substrate at least partially overlap with the orthographic projections of the first pixel circuit on the base substrate and the orthographic projections of the third pixel circuit on the base substrate, respectively, and the two first reset power lines are connected to the first pixel circuit and the third pixel circuit, respectively, the two first reset power lines are connected via a second connecting line, and the second connecting line is connected to the second pixel circuit, wherein an extension direction of the second connecting line is perpendicular to an extension direction of the first reset power line;

[0043] The orthographic projections of the three second reset power lines on the base substrate at least partially overlap with the orthographic projections of the first pixel circuit on the base substrate, the orthographic projections of the second pixel circuit on the base substrate, and the orthographic projections of the third pixel circuit on the base substrate, respectively, and the three second reset power lines are connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit, respectively;

[0044] An orthographic projection of the third reset power line on the base substrate at least partially overlaps with an orthographic projection of the second pixel circuit on the base substrate, and the third reset power line is connected to the second pixel circuit. The third reset power line is connected to the first pixel circuit and the third pixel circuit via a third connecting line, wherein an extension direction of the third connecting line is perpendicular to an extension direction of the third reset power line.

[0045] In a possible implementation, the three second reset power lines are connected via a fourth connecting line, wherein an extending direction of the fourth connecting line is perpendicular to an extending direction of the second reset power line.

[0046] In a possible implementation, in an arrangement direction of the first pixel circuit, the second pixel circuit, and the third pixel circuit, an orientation of the first pixel circuit is opposite to an orientation of the second pixel circuit;

[0047] Each pixel circuit unit corresponds to two driving power lines respectively;

[0048] For each pixel circuit unit, the orthographic projection of a driving power line on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit on the substrate and the orthographic projection of the second pixel circuit on the substrate, and is connected to the first pixel circuit and the second pixel circuit; the orthographic projection of another driving power line on the substrate at least partially overlaps with the orthographic projection of the third pixel circuit on the substrate, and is connected to the third pixel circuit.

[0049] In a possible implementation, the two driving power lines are connected via a fifth connecting line, wherein an extending direction of the fifth connecting line is perpendicular to an extending direction of the driving power line.

[0050] In a possible implementation, the types of the first signal lines include at least two of gate signal lines, light emitting control signal lines, first reset signal lines, second reset signal lines, data signal lines, reset power lines, and driving power lines.

[0051] In a possible implementation, the partial types of first signal lines include at least one of a data signal line, a gate signal line, and a light emitting control signal line.

[0052] In a possible implementation, each of the first signal lines of some types is a metal signal line.

[0053] In a possible implementation, each of the first signal lines of the partial types includes a metal signal line and a transparent signal line connected in parallel.

[0054] In a possible implementation, the base substrate further has a second display area, and the second display area is adjacent to the first display area;

[0055] The display panel further includes a plurality of types of second signal lines located in the second display area;

[0056] For each type of the first reset signal line, the second reset signal line, the first reset power line, the second reset power line, the third reset power line, the first gate signal line, the second gate signal line, the data signal line, the light-emitting control signal line and the driving power line, at least one end of each second signal line of the type is connected to a first signal line of the type, wherein the second signal line is a metal signal line, and the width of the metal signal line included in the first signal line is smaller than the width of the second signal line.

[0057] In a possible implementation, the metal signal line is located in a gate layer or a source / drain layer.

[0058] In a second aspect, an embodiment of the present application provides a display panel, comprising:

[0059] A base substrate having a first display area, wherein the first display area includes a plurality of pixel circuit areas and a light-transmitting area;

[0060] a plurality of pixel circuit groups located in the plurality of pixel circuit areas, the pixel circuit groups comprising a first number of pixel circuits arranged along a first direction, the minimum distance between adjacent pixel circuit groups being greater than the minimum distance between adjacent pixel circuits within the pixel circuit groups;

[0061] a plurality of first signal lines extending along a second direction, the first direction intersecting the second direction, at least one pixel circuit group among the plurality of pixel circuit groups being connected to a second number of first signal lines, the second number of first signal lines being electrically connected via connecting lines, and for each pixel circuit group among the at least one pixel circuit group, each first signal line among the second number of first signal lines being respectively connected to at least one pixel circuit in the pixel circuit group, at least some line segments of the first signal lines being located in the light-transmitting area, and the connecting lines being located in the pixel circuit area, wherein the second number is not greater than the first number; and

[0062] A plurality of light-emitting units are located in the first display area, the plurality of pixel circuit groups are configured to drive the plurality of light-emitting units to emit light, and the orthographic projection of at least some of the plurality of light-emitting units on the base substrate overlaps with the orthographic projection of at least some line segments in the first signal line on the base substrate.

[0063] In one possible implementation, the multiple pixel circuit groups include multiple first pixel circuit groups and multiple second pixel circuit groups, the multiple first pixel circuit groups are arranged in multiple rows, the multiple second pixel circuit groups are arranged in multiple rows, a row of second pixel circuit groups is arranged between any two adjacent rows of first pixel circuit groups, and in any row of first pixel circuit groups and a row of second pixel circuit groups adjacent to any row of first pixel circuit groups, the position of the spacing area between any two adjacent first pixel circuit groups corresponds to the position of a second pixel circuit group.

[0064] In a possible implementation, each pixel circuit group includes at least one pixel circuit unit, where the pixel circuit unit includes a first pixel circuit, a second pixel circuit, and a third pixel circuit, and the second pixel circuit is located between the first pixel circuit and the third pixel circuit;

[0065] The light emitting unit includes a first light emitting element, two second light emitting elements and a third light emitting element;

[0066] The first light-emitting element is connected to the first pixel circuit, and an orthographic projection of an anode of the first light-emitting element on the substrate at least partially overlaps with an orthographic projection of a pixel circuit group where the first pixel circuit is located on the substrate;

[0067] The two second light-emitting elements are both connected to the second pixel circuit, and the orthographic projections of the anodes of the two second light-emitting elements on the base substrate are respectively located on two opposite sides of the orthographic projection of the second pixel circuit on the base substrate;

[0068] The third light-emitting element is connected to the third pixel circuit, and the orthographic projection of the anode of the third light-emitting element on the base substrate at least partially overlaps with the orthographic projection of the pixel circuit group where the third pixel circuit is located on the base substrate.

[0069] In a possible implementation, the first signal line includes a first reset power line, the connecting line includes a second connecting line, each pixel circuit unit in the pixel circuit group is connected to two first reset power lines respectively, and the two first reset power lines are electrically connected through the second connecting line;

[0070] For each pixel circuit unit, the orthographic projections of the two first reset power lines on the base substrate at least partially overlap with the orthographic projections of the first pixel circuit on the base substrate and the orthographic projections of the third pixel circuit on the base substrate, and the two first reset power lines are connected to the first pixel circuit and the third pixel circuit, respectively;

[0071] The second connecting line is connected to the second pixel circuit.

[0072] In a possible implementation, the first signal line includes a second reset power line, the connecting line includes a fourth connecting line, each pixel circuit unit in the pixel circuit group is connected to three second reset power lines respectively, and the three second reset power lines are electrically connected through the fourth connecting line;

[0073] For each pixel circuit unit, the orthographic projections of the three second reset power lines on the substrate at least partially overlap with the orthographic projections of the first pixel circuit on the substrate, the orthographic projections of the second pixel circuit on the substrate, and the orthographic projections of the third pixel circuit on the substrate, and the three second reset power lines are respectively connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit.

[0074] In a possible implementation, the first signal line includes a third reset power line, the connecting line includes a third connecting line, each pixel circuit unit in the pixel circuit group is connected to a third reset power line, and the third reset power line is connected to the third connecting line;

[0075] For each pixel circuit unit, an orthographic projection of the third reset power line on the base substrate at least partially overlaps with an orthographic projection of the second pixel circuit on the base substrate, and the third reset power line is connected to the second pixel circuit;

[0076] The third connecting line is connected to the first pixel circuit and the third pixel circuit.

[0077] In a possible implementation, the first signal line includes a driving power line, the connecting line includes a fifth connecting line, each pixel circuit unit in the pixel circuit group is connected to two driving power lines respectively, and the two driving power lines are electrically connected through the fifth connecting line;

[0078] For each pixel circuit unit, the orthographic projection of a driving power line on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit on the substrate and the orthographic projection of the second pixel circuit on the substrate, and is connected to the first pixel circuit and the second pixel circuit; the orthographic projection of another driving power line on the substrate at least partially overlaps with the orthographic projection of the third pixel circuit on the substrate, and is connected to the third pixel circuit.

[0079] In a third aspect, an embodiment of the present application provides a display device, comprising an optical sensor and a display panel as described above, wherein the orthographic projection of the optical sensor on the display panel at least partially overlaps with a first display area in the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0081] FIG1 is a top view of a display panel provided in an embodiment of the present application;

[0082] FIG2 is a schematic diagram of a partial structure of a first display area provided in an embodiment of the present application;

[0083] FIG3 is a schematic diagram of a partial structure of a first signal line and a second signal line provided in an embodiment of the present application;

[0084] FIG4 is a schematic diagram of a partial structure of a first signal line and a second signal line provided in an embodiment of the present application;

[0085] FIG5 is a schematic diagram of a partial structure of a first display area provided in an embodiment of the present application;

[0086] FIG6 is a schematic structural diagram of a pixel circuit group provided in an embodiment of the present application;

[0087] FIG7 is a schematic diagram of a partial structure of a first display area provided in an embodiment of the present application;

[0088] FIG8 is a schematic structural diagram of a pixel circuit group provided in an embodiment of the present application;

[0089] FIG9 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0090] FIG10 is a schematic diagram of an arrangement of a first signal line provided in an embodiment of the present application;

[0091] FIG11 is a schematic structural diagram of a pixel circuit group provided in an embodiment of the present application;

[0092] FIG12 is a schematic diagram of an arrangement of driving signal lines provided in an embodiment of the present application;

[0093] FIG13 is a cross-sectional view of a display panel provided in an embodiment of the present application;

[0094] FIG14 is a partial schematic diagram of an active layer in a display panel provided in an embodiment of the present application;

[0095] FIG15 is a partial schematic diagram of a first gate layer in a display panel provided in an embodiment of the present application;

[0096] FIG16 is a schematic diagram of partial superposition of an active layer and a first gate layer in a display panel provided by an embodiment of the present application;

[0097] FIG17 is a partial schematic diagram of a second gate layer in a display panel provided in an embodiment of the present application;

[0098] FIG18 is a schematic diagram of partial superposition of an active layer, a first gate layer, and a second gate layer in a display panel provided by an embodiment of the present application;

[0099] FIG19 is a partial schematic diagram of an oxide layer in a display panel provided in an embodiment of the present application;

[0100] FIG20 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, and an oxide layer in a display panel provided by an embodiment of the present application;

[0101] FIG21 is a partial schematic diagram of a third gate layer in a display panel provided in an embodiment of the present application;

[0102] FIG22 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, and a third gate layer in a display panel provided by an embodiment of the present application;

[0103] FIG23 is a partial schematic diagram of a first interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0104] 24 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, and a first interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0105] FIG25 is a partial schematic diagram of a second interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0106] 26 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, and a second interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0107] FIG27 is a partial schematic diagram of a first source and drain electrode layer in a display panel provided in an embodiment of the present application;

[0108] FIG28 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, and a first source and drain electrode layer in a display panel provided by an embodiment of the present application;

[0109] FIG29 is a partial schematic diagram of a passivation layer in a display panel provided in an embodiment of the present application;

[0110] FIG30 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, and a passivation layer in a display panel provided by an embodiment of the present application;

[0111] FIG31 is a partial schematic diagram of a first transparent wiring layer in a display panel provided in an embodiment of the present application;

[0112] FIG32 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, a passivation layer, and a first transparent wiring layer in a display panel provided by an embodiment of the present application;

[0113] FIG33 is a partial schematic diagram of a first planar layer in a display panel provided in an embodiment of the present application;

[0114] FIG34 is a schematic diagram of a partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, a passivation layer, a first transparent wiring layer, and a first planarization layer in a display panel provided by an embodiment of the present application;

[0115] FIG35 is a partial schematic diagram of a second transparent wiring layer in a display panel provided in an embodiment of the present application;

[0116] FIG36 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarization layer, and a second transparent wiring layer in a display panel provided by an embodiment of the present application;

[0117] FIG37 is a partial schematic diagram of a second planar layer in a display panel provided in an embodiment of the present application;

[0118] FIG38 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarizing layer, a second transparent wiring layer, and a second planarizing layer in a display panel provided by an embodiment of the present application;

[0119] FIG39 is a partial schematic diagram of a second source-drain layer in a display panel provided in an embodiment of the present application;

[0120] FIG40 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarizing layer, a second transparent wiring layer, a second planarizing layer, and a second source and drain electrode layer in a display panel provided by an embodiment of the present application;

[0121] FIG41 is a partial schematic diagram of a third planar layer in a display panel provided in an embodiment of the present application;

[0122] FIG42 is a schematic diagram of a partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarizing layer, a second transparent wiring layer, a second planarizing layer, a second source-drain electrode layer, and a third planarizing layer in a display panel provided by an embodiment of the present application;

[0123] FIG43 is a partial schematic diagram of an anode layer in a display panel provided in an embodiment of the present application;

[0124] FIG44 is a schematic diagram of a partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarizing layer, a second transparent wiring layer, a second planarizing layer, a second source-drain electrode layer, a second source-drain electrode layer, a third planarizing layer, and an anode layer in a display panel provided by an embodiment of the present application;

[0125] FIG45 is a partial schematic diagram of an active layer in another display panel provided by an embodiment of the present application;

[0126] FIG46 is a partial schematic diagram of a first gate layer in another display panel provided by an embodiment of the present application;

[0127] FIG47 is a schematic diagram of partial superposition of an active layer and a first gate layer in another display panel provided by an embodiment of the present application;

[0128] FIG48 is a partial schematic diagram of a second gate layer in another display panel provided by an embodiment of the present application;

[0129] FIG49 is a schematic diagram showing a partial superposition of an active layer, a first gate layer, and a second gate layer in another display panel provided by an embodiment of the present application;

[0130] FIG50 is a partial schematic diagram of an oxide layer in another display panel provided in an embodiment of the present application;

[0131] FIG51 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, and an oxide layer in another display panel provided by an embodiment of the present application;

[0132] FIG52 is a partial schematic diagram of a third gate layer in another display panel provided by an embodiment of the present application;

[0133] FIG53 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, and a third gate layer in another display panel provided by an embodiment of the present application;

[0134] FIG54 is a partial schematic diagram of a first interlayer dielectric layer in another display panel provided by an embodiment of the present application;

[0135] FIG55 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, and a first interlayer dielectric layer in another display panel provided by an embodiment of the present application;

[0136] FIG56 is a partial schematic diagram of a second interlayer dielectric layer in another display panel provided by an embodiment of the present application;

[0137] FIG57 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, and a second interlayer dielectric layer in another display panel provided by an embodiment of the present application;

[0138] FIG58 is a partial schematic diagram of a first source and drain layer in another display panel provided by an embodiment of the present application;

[0139] FIG59 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, and a first source and drain electrode layer in another display panel provided by an embodiment of the present application;

[0140] FIG60 is a partial schematic diagram of a passivation layer in another display panel provided in an embodiment of the present application;

[0141] FIG61 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, and a passivation layer in another display panel provided by an embodiment of the present application;

[0142] FIG62 is a partial schematic diagram of a second transparent wiring layer in another display panel provided by an embodiment of the present application;

[0143] FIG63 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarization layer, and a second transparent wiring layer in another display panel provided by an embodiment of the present application;

[0144] FIG64 is a partial schematic diagram of a second planar layer in another display panel provided in an embodiment of the present application;

[0145] FIG65 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarizing layer, a second transparent wiring layer, and a second planarizing layer in another display panel provided by an embodiment of the present application;

[0146] FIG66 is a partial schematic diagram of a second source-drain layer in another display panel provided by an embodiment of the present application;

[0147] FIG67 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source and drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarizing layer, a second transparent wiring layer, a second planarizing layer, and a second source and drain electrode layer in another display panel provided by an embodiment of the present application;

[0148] FIG68 is a partial schematic diagram of a third planar layer in another display panel provided by an embodiment of the present application;

[0149] FIG69 is a schematic diagram of a partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarizing layer, a second transparent wiring layer, a second planarizing layer, a second source-drain electrode layer, and a third planarizing layer in another display panel provided by an embodiment of the present application;

[0150] FIG70 is a partial schematic diagram of an anode layer in another display panel provided in an embodiment of the present application;

[0151] FIG71 is a schematic diagram of a partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain electrode layer, a passivation layer, a first transparent wiring layer, a first planarizing layer, a second transparent wiring layer, a second planarizing layer, a second source-drain electrode layer, a second source-drain electrode layer, a third planarizing layer, and an anode layer in another display panel provided by an embodiment of the present application;

[0152] Figure 72 is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0153] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0154] An embodiment of the present application provides a display panel, which includes a base substrate 1, a plurality of pixel circuit groups 2, a plurality of types of first signal lines 3, and a plurality of light-emitting units.

[0155] As shown in Figure 1, the substrate 1 has a first display area 11, which can be used to set an optical sensor. Optionally, the optical sensor can be a front-facing camera, and the first display area 11 can be a full display with camera (FDC) area. The substrate 1 can also have a second display area 12, which is adjacent to the first display area 11. Optionally, the second display area 12 can be the remaining display area of ​​the substrate 1 except the first display area 11.

[0156] The first display area 11 may include multiple pixel circuit areas 111 and light-transmitting areas 112 . Each pixel circuit area 111 may be used to set a pixel circuit group 2 . The light-transmitting area 112 is an area where no pixel circuit group 2 is set, and its transmittance is higher than that of the pixel circuit area 111 .

[0157] Multiple pixel circuit groups 2 are located in multiple pixel circuit areas 111 of the first display area 11. As shown in Figure 2, each pixel circuit group 2 includes multiple pixel circuits 21, and the minimum distance between adjacent pixel circuit groups 2 is greater than the minimum distance between adjacent pixel circuits 21 in the pixel circuit group 2. In this way, compared with the arrangement of multiple pixel circuits uniformly arranged in the second display area 12, multiple pixel circuits 21 are gathered together in the first display area 11 to form a pixel circuit group 2, which can reduce the area occupied by these multiple pixel circuits 21, thereby increasing the area of ​​the light-transmitting area 112 in the first display area 11, and thereby improving the light transmittance of the first display area 11.

[0158] Multiple types of first signal lines 3 are connected to the pixel circuits 21 located in the first display area 11 for transmitting signals thereto. As shown in Figures 3 and 4 , in addition to the first signal lines 3 connected to the pixel circuits 21 located in the first display area 11, the display panel also includes multiple types of second signal lines 4 located in the second display area 12, which are connected to multiple pixel circuits located in the second display area 12. For each type of the first reset signal line Preset, the second reset signal line Preset_H, the first reset power line vinit1, the second reset power line vinit2, the third reset power line vinit3, the first gate signal line Gate_N, the second gate signal line Gate_P, the data signal line Data, the light-emitting control signal line EM and the driving power line VDD, at least one end of each second signal line 4 of this type is connected to the first signal line 3 of this type. The second signal line 4 can be used to transmit a signal to the pixel circuit connected to the second signal line 4, and can also be used to transmit a signal to the first signal line 3 connected to the second signal line. After receiving the signal, the first signal line 3 transmits it to the pixel circuit 21 connected to the first signal line 3 and located in the first display area 11.

[0159] Optionally, the first signal lines may include at least two types of gate signal lines Gate, emission control signal lines EM, first reset signal lines Preset, second reset signal lines Preset_H, data signal lines Data, reset power lines vinit, and drive power lines VDD. The data signal lines Data, reset power lines vinit, and drive signal lines VDD are longitudinal first signal lines 3 as shown in FIG3 , and the gate signal lines Gate, emission control signal lines EM, first reset signal lines Preset, and second reset signal lines Preset_H are transverse first signal lines 3 as shown in FIG4 .

[0160] Multiple light-emitting units are located in the first display area 11, and multiple pixel circuit groups 2 are configured to drive the multiple light-emitting units to emit light. Optionally, each light-emitting unit is electrically connected to a pixel circuit 21 in the pixel circuit group 2, and the pixel circuit 21 is used to drive the light-emitting unit to emit light.

[0161] The orthographic projections of at least some of the multiple light-emitting units on the base substrate 1 overlap with the orthographic projections of at least some of the line segments of the multiple types of first signal lines 3 located in the light-transmitting area 112 on the base substrate 1. This reduces the area of ​​the light-transmitting area 112 blocked by the light-emitting units and the first signal lines 3, thereby improving the light transmittance of the first display area 11.

[0162] Optionally, the light-emitting unit may be located in the pixel circuit area 111 or in the light-transmitting area 112 , or a portion of the light-emitting unit may be located in the pixel circuit area 111 and another portion in the light-transmitting area 112 . This is not limited in the embodiments of the present application.

[0163] In the under-screen camera area of ​​the display panel in the related art, the signal lines connected to the pixel circuit are all transparent signal lines, and the signal lines in other display areas except the under-screen camera area are all metal signal lines. Since the resistance of the transparent signal line is much greater than that of the metal signal line, the difference in resistance between the two is large. Therefore, a more obvious via defect phenomenon will be generated around the under-screen camera area, resulting in uneven display of the display panel.

[0164] In the embodiment of the present application, some types of first signal lines 3 among the multiple types of first signal lines 3 in the first display area 11 are set to include metal signal lines, and the resistance of these types of first signal lines 3 is reduced by the metal signal lines, and the difference between the resistance of these types of first signal lines 3 and the resistance of the second signal lines 4 in the second display area 12 is reduced, thereby reducing the poor via phenomenon around the first display area 11 and improving the display uniformity of the display panel.

[0165] In the embodiment of the present application, the resistance of the first signal line 3 is reduced by configuring the first signal line 3 to include a metal signal line. There are many ways to configure the metal signal line, two of which are described below as examples:

[0166] The first arrangement of the metal signal lines: each of the first signal lines 3 of some types is a metal signal line.

[0167] In implementation, among the multiple types of first signal lines 3, some types of first signal lines 3 that have a greater impact on display brightness can be set as metal signal lines, and the remaining first signal lines 3 can be set as transparent signal lines. In this way, the difference between the resistance of this part of the first signal lines 3 and the resistance of the second signal lines 4 connected to the first signal lines 3 is smaller, or even reduced to 0, thereby improving the light transmittance of the first display area 11 while effectively reducing the poor via phenomenon around the first display area 11, thereby improving the display uniformity.

[0168] The second arrangement of the metal signal lines: each of the first signal lines 3 of some types includes a metal signal line and a transparent signal line connected in parallel.

[0169] In implementation, among the multiple types of first signal lines 3, some types of first signal lines 3 that have a greater impact on display brightness can be set as metal signal lines and transparent signal lines connected in parallel, that is, while using the transparent signal line to connect the first signal line 3 to the pixel circuit 21, the metal signal line is used to connect the first signal line 3 to the same pixel circuit 21. In this way, the parallel connection of the transparent signal line and the metal signal line can be realized, and the resistance of the transparent signal line is reduced by the metal signal line, thereby reducing the resistance difference between the first signal line 3 and the second signal line 4 connected to the first signal line 3, thereby reducing the poor via phenomenon around the first display area 11.

[0170] Optionally, in order to improve the light transmittance of the first display area 11, the occupied space of the pixel circuit group can be reduced as much as possible. When the occupied space of the pixel circuit group is small, the width of the metal signal line included in the above-mentioned partial type of first signal line 3 can be reduced to be smaller than the width of the second signal line 4, thereby ensuring the light transmittance of the first display area 11.

[0171] In this case, connecting a metal signal line with a slightly smaller width in parallel with the transparent signal line can also reduce the resistance of the first signal line 3 to a certain extent, thereby reducing the resistance difference between the first signal line 3 and the second signal line 4 connected to the first signal line 3, thereby reducing the poor via phenomenon around the first display area 11.

[0172] Optionally, the material of the transparent signal line in the embodiment of the present application is a conductive transparent material, for example, indium tin oxide (ITO).

[0173] The first signal line 3 including the metal signal line provided in the present application is of a type that has a greater impact on display brightness, and may include a longitudinal signal line or a transverse signal line.

[0174] Optionally, some types of first signal lines 3 may include at least one of a data signal line Data, a gate signal line Gate, and a light emitting control signal line EM.

[0175] The data signal line Data is a longitudinal signal line that has a greater impact on display brightness. Therefore, if the data signal line Data in the first display area 11 is set to include a metal signal line, the vertical via defect phenomenon in the first display area 11 can be effectively reduced.

[0176] The gate signal line Gate and the light-emitting control signal line EM are horizontal signal lines that have a greater impact on the display brightness. When setting, only the gate signal line Gate in the first display area 11 can be set to include a metal signal line, or only the light-emitting control signal line EM in the first display area 11 can be set to include a metal signal line, or both the gate signal line Gate and the light-emitting control signal line EM in the first display area 11 can be set to include a metal signal line, thereby reducing the defective via phenomenon in the horizontal direction of the first display area 11.

[0177] In an embodiment of the present application, the first signal line 3 can be arranged in a variety of ways. Optionally, at least part of the line segments of the metal signal line included in the first signal line 3 can be located in the light-transmitting area 112, and the orthographic projection of at least part of the multiple light-emitting units on the base substrate 1 overlaps with the orthographic projection of at least part of the line segments of the metal signal line on the base substrate 1.

[0178] The metal signal line and some of the light-emitting units in the light-emitting unit will block the light-transmitting area 112, thereby causing the light transmittance of the light-transmitting area 112 to decrease. In the embodiment of the present application, the partial line segments of the metal signal line located in the light-transmitting area 112 and at least some of the light-emitting units in the light-emitting unit are arranged in the same area, thereby improving the light transmittance of the light-transmitting area 112.

[0179] Optionally, at least some of the line segments of the transparent signal line included in the first signal line 3 are located in the light-transmitting area 112, and the orthographic projections of at least some of the plurality of light-emitting units on the base substrate 1 overlap with the orthographic projections of at least some of the transparent signal line on the base substrate 1. Similarly, by arranging the line segments of the transparent signal line located in the light-transmitting area 112 and at least some of the light-emitting units in the same area, the light transmittance of the light-transmitting area 112 is improved.

[0180] FIG5 is a partial structural diagram of multiple pixel circuit groups 2 in a first display area 11 according to an embodiment of the present application. Referring to FIG5 , in this embodiment, the multiple pixel circuit groups 2 include multiple first pixel circuit groups 2A and multiple second pixel circuit groups 2B. The multiple first pixel circuit groups 2A are arranged in multiple rows, each row of the first pixel circuit groups 2A includes multiple pixel circuits 21. The multiple second pixel circuit groups 2B are arranged in multiple rows, each row of the second pixel circuit groups 2B also includes multiple pixel circuits 21.

[0181] A row of second pixel circuit groups 2B is arranged between any two adjacent rows of first pixel circuit groups 2A, that is: in two adjacent rows of pixel circuit groups 2 in the first display area 11, one row of pixel circuit groups 2 is the first pixel circuit group 2A, and the other row of pixel circuit groups 2 is the second pixel circuit group 2B, and multiple rows of first pixel circuit groups 2A and multiple rows of second pixel circuit groups 2B are arranged alternately.

[0182] Furthermore, in any row of first pixel circuit groups 2A and a row of second pixel circuit groups 2B adjacent to the row of pixel circuit groups 2A, the position of the spacing region between any two adjacent first pixel circuit groups 2A corresponds to the position of one second pixel circuit group 2B.

[0183] It can be understood that the row direction of the multiple first pixel circuit groups 2A arranged in a row can be considered as a first direction parallel to the plane where the base substrate 1 is located. The first direction can be any direction and is not limited in this embodiment of the present application.

[0184] Each pixel circuit group 2 in the first pixel circuit group 2A and the second pixel circuit group 2B has the following structure:

[0185] Each pixel circuit group 2 includes at least one pixel circuit unit, and the pixel circuit unit includes a first pixel circuit 211, a second pixel circuit 212, and a third pixel circuit 213. That is, each pixel circuit group 2 may include one or more pixel circuit units. For example, the pixel circuit group 2 shown in FIG5 includes one pixel circuit unit, and the pixel circuit unit includes three pixel circuits (a first pixel circuit 211, a second pixel circuit 212, and a third pixel circuit 213). Alternatively, the pixel circuit group may include six pixel circuits, nine pixel circuits, and so on, which is not limited in the embodiments of the present application.

[0186] In each pixel circuit unit, the second pixel circuit 212 is located between the first pixel circuit 211 and the third pixel circuit 213. The first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 are arranged along the row direction of the plurality of pixel circuit groups 2. It can be understood that the row direction here is the first direction mentioned above.

[0187] FIG6 is a schematic diagram of the structure of a pixel circuit group 2 provided in an embodiment of the present application. Referring to FIG6 , the pixel circuit group 2 includes a pixel circuit unit, namely, a first pixel circuit 211 , a second pixel circuit 212 and a third pixel circuit 213 .

[0188] Each light emitting unit may include a first light emitting element, two second light emitting elements and a third light emitting element, and at least one light emitting unit corresponds to a pixel circuit unit.

[0189] Among them, the first light-emitting element is connected to the first pixel circuit 211, that is, the anode of the first light-emitting element is connected to the first pixel circuit 211, and the first pixel circuit 211 can drive the first light-emitting element to emit light. In the embodiment of the present application, the orthographic projection of the anode 51 of the first light-emitting element on the base substrate 1 at least partially overlaps with the orthographic projection of the pixel circuit group 2 where the first pixel circuit 211 is located on the base substrate 1. Since the anode 51 of the first light-emitting element blocks light, overlapping at least part of the anode 51 of the first light-emitting element with at least part of the pixel circuit group 2 where the first pixel circuit 211 is located can effectively reduce the shading area of ​​the anode 51 of the first light-emitting element to the first display area 11, thereby improving the light transmittance of the first display area 11.

[0190] Both second light-emitting elements are connected to the second pixel circuit 212, that is, the anodes 52 of the two second light-emitting elements are connected to the second pixel circuit 212. In this way, one second pixel circuit 212 drives the two second light-emitting elements to emit light. Compared with the conventional pixel arrangement, the space of one second pixel circuit 212 is reduced, thereby improving the light transmittance of the first display area 11.

[0191] Furthermore, the orthographic projections of the anodes 52 of the two second light-emitting elements on the substrate 1 are located on opposite sides of the orthographic projection of the second pixel circuit 212 on the substrate 1. Referring to FIG6 , the orthographic projections of the anodes 52 of the two second light-emitting elements on the substrate 1 are located on two sides of the second pixel circuit 212, and the orthographic projections of the anodes 52 of the two second light-emitting elements on the substrate 1, the orthographic projection of the first pixel circuit 211 on the substrate 1, and the orthographic projection of the third pixel circuit 213 on the substrate 1 surround the four sides of the orthographic projection of the second pixel circuit 212 on the substrate 1. Optionally, the anodes 52 of the two second light-emitting elements can be symmetrically arranged, and their axes of symmetry can be parallel to the first direction.

[0192] Optionally, the connection between the anodes 52 of the two second light-emitting elements and the second pixel circuit 212 can be: the anodes 52 of the two second light-emitting elements are connected via a first connection line L1, and the first connection line L1 is connected to the second pixel circuit 212. Optionally, the material of the first connection line L1 can be the anode material.

[0193] The third light-emitting element is connected to the third pixel circuit 213, that is, the anode 53 of the third light-emitting element is connected to the third pixel circuit 213, and the third pixel circuit 213 drives the third light-emitting element to emit light. In the embodiment of the present application, the orthographic projection of the anode 53 of the third light-emitting element on the substrate 1 at least partially overlaps with the orthographic projection of the pixel circuit group 2 where the third pixel circuit 213 is located on the substrate 1. Since the anode 53 of the third light-emitting element blocks light, overlapping at least a portion of the anode 53 of the third light-emitting element with at least a portion of the pixel circuit group 2 where the third pixel circuit 213 is located can effectively reduce the area blocked by the anode 53 of the third light-emitting element on the first display area 11, thereby improving the light transmittance of the first display area 11.

[0194] The orthographic projection of the anode 53 of the third light-emitting element on the substrate 1 is located within the orthographic projection of the third pixel circuit 213 on the substrate 1. Since the anode 53 of the third light-emitting element is light-shielding, it is set in the area where the third pixel circuit 213, which is also light-shielding, is located. This can reduce the blocking effect of the anode 53 of the third light-emitting element on the transparent area of ​​the first display area 11, thereby improving the light transmittance of the first display area 11.

[0195] Optionally, the orthographic projection of the anode 51 of the first light-emitting element on the substrate substrate 1 can be located within the orthographic projection of the pixel circuit group 2 where the first pixel circuit 211 is located on the substrate substrate 1, the orthographic projections of the anodes 52 of the two second light-emitting elements on the substrate substrate 1 do not overlap with the orthographic projection of the pixel circuit group 2 where the second pixel circuit 212 is located on the substrate substrate 1, and the orthographic projection of the anode 53 of the third light-emitting element on the substrate substrate 1 is located within the orthographic projection of the pixel circuit group 2 where the third pixel circuit 213 is located on the substrate substrate 1.

[0196] In this way, by setting the anode 51 of the first light-emitting element in the area of ​​the pixel circuit group 2 where the first pixel circuit 211 that is also shielded is located, the blocking effect of the anode 51 of the first light-emitting element on the light-transmitting area 112 of the first display area 11 can be minimized, thereby improving the light transmittance of the first display area 11.

[0197] It can be understood that the above-mentioned orthographic projection of the anode 51 of the first light-emitting element on the substrate 1 is located within the orthographic projection of the first pixel circuit 211 on the substrate 1, which means that the orthographic projection of the anode 51 of the first light-emitting element on the substrate 1 is located within the smallest square area where the orthographic projection of the first pixel circuit 211 on the substrate 1 is located, or within the smallest complete shape area of ​​other shapes.

[0198] Similarly, by setting the anode 53 of the third light-emitting element in the area of ​​the pixel circuit group 2 where the third pixel circuit 213, which is also light-shielded, is located, the blocking effect of the anode 53 of the third light-emitting element on the light-transmitting area 112 of the first display area 11 can be minimized, thereby improving the light transmittance of the first display area 11.

[0199] In order to ensure uniform arrangement of the multiple light-emitting elements in the first display area 11, on the basis of arranging the anodes 52 of the two second light-emitting elements on both sides of the second pixel circuit 212, it is also possible to arrange that the orthographic projections of the anodes 52 of the two second light-emitting elements on the base substrate 1 do not overlap with the orthographic projections of the pixel circuit group 2 where the second pixel circuit 212 is located on the base substrate 1, that is, the anodes 52 of the two second light-emitting elements can be located in the light-transmitting area 112 of the first display area 11. In this way, while reducing the obstruction of the light-transmitting area 112 by the anode 51 of the first light-emitting element and the anode 53 of the third light-emitting element, the uniformity of the distribution of the anode 51 of the first light-emitting element, the anode 52 of the second light-emitting element and the anode 53 of the third light-emitting element is ensured.

[0200] In summary, in the above-mentioned pixel circuit group 2, the position setting of the anode 51 of the first light-emitting element, the anode 52 of the second light-emitting element and the anode 53 of the third light-emitting element ensures that the multiple light-emitting elements in the first display area 11 and the second display area 12 are evenly arranged, while improving the light transmittance of the first display area 11.

[0201] Optionally, the anode 51 of the first light-emitting element, the anode 52 of the second light-emitting element, and the anode 53 of the third light-emitting element may all be circular in shape. Under the same area, the circular shape has a larger aperture ratio.

[0202] Optionally, based on the structural arrangement of the above pixel circuit group 2, the color distribution of the pixel circuits in the first pixel circuit group 2A and the second pixel circuit group 2B may be arranged as follows:

[0203] The first light emitting element, the second light emitting element and the third light emitting element may be a blue light emitting element, a green light emitting element and a red light emitting element respectively, and display an image by emitting blue light, green light and red light.

[0204] Correspondingly, as shown in Figure 5, the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 of the pixel circuit unit of the first pixel circuit group 2A can be a pixel circuit for driving a blue light-emitting element, a pixel circuit for driving a green light-emitting element, and a pixel circuit for driving a red light-emitting element, respectively, and the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 of the pixel circuit unit of the second pixel circuit group 2B can also be a pixel circuit for driving a blue light-emitting element, a pixel circuit for driving a green light-emitting element, and a pixel circuit for driving a red light-emitting element, respectively.

[0205] Alternatively, as shown in Figure 7, the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 of the pixel circuit unit of the second pixel circuit group 2B can be a pixel circuit for driving a red light-emitting element, a pixel circuit for driving a green light-emitting element, and a pixel circuit for driving a blue light-emitting element, respectively.

[0206] Figure 8 is a schematic diagram of the structure of a pixel circuit group 2 in the display panel shown in Figure 2. In Figure 8, one type of vertical signal line is configured to include a metal signal line, and the transverse signal lines and the remaining types of vertical signal lines are transparent signal lines. Referring to Figure 8, the metal signal line in the first signal line 3 may include a first portion 31, a second portion 32, and a third portion 33. The third portion 33 is located between the first portion 31 and the second portion 32, and the two ends of the third portion 33 are respectively connected to the first portion 31 and the second portion 32.

[0207] The first portion 31 and the second portion 32 are respectively connected to the pixel circuits 21 in two adjacent pixel circuit groups 2 . The orthographic projection of the third portion on the base substrate 1 at least partially overlaps with the orthographic projection of the anode 52 of the second light-emitting element on the base substrate 1 .

[0208] Such an arrangement can make the orthographic projection of a portion of the metal signal line (the third part 33) on the base substrate 1 at least partially overlap with the orthographic projection of the anode 52 of the third light-emitting element on the base substrate 1, thereby reducing the obstruction of the transparent area of ​​the first display area 11 by the metal signal line, thereby improving the light transmittance of the first display area 11.

[0209] Optionally, the orthographic projections of the anode 52 of the second light-emitting element on the base substrate 1 at least partially overlap with the orthographic projections of the third portions 33 of at least two metal signal lines on the base substrate 1. In this way, the third portions 33 of multiple metal signal lines can be overlapped with the anode of the second light-emitting element 52, thereby further improving the light transmittance of the first display area 11.

[0210] The overlapping portions of the at least two third portions 33 of the metal signal lines and the anode 52 of the second light-emitting element can be symmetrically arranged about the axis of symmetry of the anode 52 of the second light-emitting element, thereby improving the flatness of the anode 52 of the second light-emitting element. For example, when the anode 52 of the second light-emitting element is circular, the two third portions 33 can be symmetrical about a line passing through the center of the anode 52 of the second light-emitting element.

[0211] Optionally, each pixel circuit 21 in each pixel circuit group 2 may include eight transistors and one storage capacitor Cst (ie, 8T1C), as shown in, for example, FIG. 8 and FIG. 9 .

[0212] FIG9 is an equivalent circuit diagram of a pixel circuit 21 in the display panel shown in FIG2. Referring to FIG9, the pixel circuit 21 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst.

[0213] The types of first signal lines may include a first reset signal line Preset, a second reset signal line Preset_H, a first reset power line vinit1, a second reset power line vinit2, a third reset power line vinit3, a first gate signal line Gate_N, a second gate signal line Gate_P, a data signal line Data, a light emitting control signal line EM, and a driving power line VDD.

[0214] The gate of the first transistor T1 is connected to the first reset signal line Preset, the first electrode of the first transistor T1 is connected to the first reset power line vinit1, and the second electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can also be called a reset transistor.

[0215] The gate of the second transistor T2 is connected to the first gate signal line Gate_N, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor is connected to the second node N2. The second transistor T2 can also be called a compensation transistor.

[0216] The gate of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can also be called a driving transistor.

[0217] The gate of the fourth transistor T4 is connected to the second gate signal line Gate_P, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the third node N3. The fourth transistor T4 can be a data writing transistor in the pixel circuit.

[0218] The gate of the fifth transistor T5 is connected to the light emission control signal line EM, the first electrode of the fifth transistor T5 is connected to the third node N3, and the second electrode of the fifth transistor T5 is connected to the driving power supply line VDD. Since the gate of the fifth transistor T5 is connected to the light emission control signal line EM, the fifth transistor T5 can also be called a light emission control transistor.

[0219] The gate of the sixth transistor T6 is connected to the light-emission control signal line EM, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting element. Since the gate of the sixth transistor T6 is connected to the light-emission control signal line EM, the sixth transistor T6 can also be called a light-emission control transistor.

[0220] The gate of the seventh transistor T7 is connected to the second reset signal line Preset_H, the first electrode of the seventh transistor T7 is connected to the second reset power line vinit2, and the second electrode of the seventh transistor T7 is connected to the anode of the light emitting element. The seventh transistor T7 can be a reset transistor in the pixel circuit.

[0221] The gate of the eighth transistor T8 is connected to the second reset signal line Preset_H, the first electrode of the eighth transistor T8 is connected to the third reset power line vinit3, and the second electrode of the eighth transistor T8 is connected to the third node N3. The eighth transistor T8 can be a reset transistor in the pixel circuit.

[0222] Two ends of the storage capacitor Cst are connected to the driving power line VDD and the second node N2 respectively.

[0223] Optionally, the storage capacitor Cst may include a first capacitor plate Cst1 and a second capacitor plate Cst2. In an embodiment of the present application, the first capacitor plate Cst1 may be referred to as one end, the first end, or the first storage capacitor electrode of the storage capacitor Cst, and the second capacitor plate Cst2 may be referred to as the other end, the second end, or the second storage capacitor electrode of the storage capacitor Cst.

[0224] In an embodiment of the present application, the type of the first signal line 3 including a metal signal line may be some types of signal lines among the above-mentioned first reset signal line Preset, second reset signal line Preset_H, first reset power line vinit1, second reset power line vinit2, third reset power line vinit3, first gate signal line Gate_N, second gate signal line Gate_P, data signal line Data, light-emitting control signal line EM and driving power line VDD.

[0225] Optionally, the second transistor T2 may be an N-type transistor, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may all be P-type transistors.

[0226] Optionally, each N-type transistor recorded in the embodiment of the present application may be an oxide thin film transistor, and each P-type transistor may be an LTPS (Low Temperature Poly-silicon) thin film transistor. The oxide material may include indium gallium zinc oxide (IGZO), that is, the oxide thin film transistor may be an IGZO thin film transistor. The pixel circuit composed of the eight transistors may also be referred to as an LTPO pixel circuit. A display panel in which the pixel circuit of the display panel is the LTPO pixel circuit may be referred to as an LTPO display panel.

[0227] Fig. 10 is a schematic diagram showing the arrangement of various types of first signal lines 3 in a pixel circuit group 2 in the display panel shown in Fig. 2. Referring to Fig. 10, it can be seen that the pixel circuit group 2 includes one pixel circuit unit, namely, three pixel circuits 21.

[0228] Each type of horizontal signal line (including the first reset signal line Preset, the second reset signal line Preset_H, the first gate signal line Gate_N, the second gate signal line Gate_P, and the light-emitting control signal line EM) runs through the pixel circuit group 2 and is respectively connected to each pixel circuit 21 in the pixel circuit group 2.

[0229] For the data signal line Data in the vertical signal line, it includes data signal line Data-1, data signal line Data-2 and data signal line Data-3. As shown in Figures 8 and 10, the data signal line Data-1 runs through the first pixel circuit 211 and is connected to the first pixel circuit 211, the data signal line Data-2 runs through the second pixel circuit 212 and is connected to the second pixel circuit 212, and the data signal line Data-3 runs through the third pixel circuit 213 and is connected to the third pixel circuit 213.

[0230] For the first reset power line vinit1, the second reset power line vinit2 and the third reset power line vinit3 in the longitudinal signal lines, referring to FIG10 , the following settings may be performed:

[0231] Each pixel circuit unit corresponds to two first reset power lines vinit1 (including vinit1-1 and vinit1-2), three second reset power lines vinit2 (including vinit2-1, vinit2-2 and vinit2-3) and one third reset power line vinit3, that is, each pixel circuit unit needs to be connected to two first reset power lines vinit1, three second reset power lines vinit2 and one third reset power line vinit3.

[0232] For each pixel circuit unit, the orthographic projections of the two first reset power lines vinit1 on the substrate substrate 1 at least partially overlap with the orthographic projections of the first pixel circuit 211 on the substrate substrate 1 and the orthographic projections of the third pixel circuit 213 on the substrate substrate 1, and the two first reset power lines vinit1 are respectively connected to the first pixel circuit 211 and the third pixel circuit 213, that is, the first reset power line vinit1-1 and the first reset power line vinit1-2 respectively pass through the first pixel circuit 211 and the third pixel circuit 213, and are respectively connected to the first pixel circuit 211 and the third pixel circuit 213 through vias.

[0233] Furthermore, the two first reset power lines vinit1 are connected via a second connection line L2, which is connected to the second pixel circuit 212. The extension direction of the second connection line L2 intersects that of the first reset power line vinit1. For example, the extension direction of the second connection line L2 can be perpendicular to the extension direction of the first reset power line vinit1, or the angle formed between the extension direction of the second connection line L2 and the extension direction of the first reset power line vinit1 is not 90 degrees. These configurations can be made based on requirements and the arrangement of the first signal lines 3, and are not limited in this embodiment of the present application. The second connection line L2 has its ends connected to the first reset power lines vinit1 located on both sides of the second pixel circuit 212, passing through the second pixel circuit 212 and achieving connection with the second pixel circuit 212. The orthographic projections of the two first reset power lines vinit1 and the second connection line L2 on the substrate 1 form an I-shape.

[0234] In this way, the two first reset power lines vinit1 are connected through the second connecting line L2, and the two first reset power lines vinit1 are connected to the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213, so that the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 can receive the same first reset power signal, thereby improving the stability of the first reset power signal received by the pixel circuit unit.

[0235] Optionally, the second connection line L2 may be a metal connection line located in a metal layer in the pixel circuit 21 .

[0236] The orthographic projections of the three second reset power lines vinit2 on the substrate 1 at least partially overlap with the orthographic projections of the first pixel circuit 211 on the substrate 1, the orthographic projections of the second pixel circuit 212 on the substrate 1, and the orthographic projections of the third pixel circuit 213 on the substrate 1, and the three second reset power lines vinit2 are respectively connected to the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213, that is: the three second reset power lines vinit2 respectively pass through the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213, and are respectively connected to the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 through vias.

[0237] Optionally, as shown in FIG10 , the three second reset power lines vinit2 can also be connected via a fourth connection line L4, wherein the extension direction of the fourth connection line L4 intersects the extension direction of the second reset power line vinit2. For example, the extension direction of the fourth connection line L4 can be perpendicular to the extension direction of the second reset power line vinit2, or the angle formed between the extension direction of the fourth connection line L4 and the extension direction of the second reset power line vinit2 is not 90 degrees, etc., and can be configured according to requirements and the arrangement of each first signal line 3, which is not limited in this embodiment of the present application. In this way, the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 can receive the same second reset power signal, thereby improving the stability of the second reset power signal received by the pixel circuit unit.

[0238] Optionally, the fourth connection line L4 may be a metal connection line located in a metal layer in the pixel circuit 21 .

[0239] The orthographic projection of the third reset power line vinit3 on the base substrate 1 at least partially overlaps with the orthographic projection of the second pixel circuit 212 on the base substrate 1, and the third reset power line vinit3 is connected to the second pixel circuit 212, that is, the third reset power line vinit3 passes through the second pixel circuit 212 and is connected to the second pixel circuit 212 through a via.

[0240] Furthermore, the third reset power line vinit3 is connected to the first pixel circuit 211 and the third pixel circuit 213 via a third connection line L3. The extension direction of the third connection line L3 intersects the extension direction of the third reset power line vinit3. For example, the extension direction of the third connection line L3 can be perpendicular to the extension direction of the third reset power line vinit3, or the angle formed between the extension direction of the third connection line L3 and the extension direction of the third reset power line vinit3 is not 90 degrees. This configuration can be tailored to the needs and the arrangement of the first signal lines 3, and is not limited in this embodiment of the present application. The third connection line L3 extends in two directions perpendicular to and opposite to the extension direction of the third reset power line vinit3, such that the orthographic projections of the third connection line L3 and the third reset power line vinit3 on the substrate 1 form a cross.

[0241] While the third connection line L3 is connected to the third reset power line vinit3, its two ends are respectively connected to the first pixel circuit 211 and the third pixel circuit 213. In this way, the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 can receive the same third reset power signal, thereby improving the stability of the third reset power signal received by the pixel circuit unit.

[0242] Optionally, the third connection line L3 may be a metal connection line located in a metal layer in the pixel circuit 21 .

[0243] The arrangement of the first reset power line vinit1, the second reset power line vinit2 and the third reset power line vinit3 saves the space occupied by the pixel circuit group 2 while improving the stability of the first reset power signal, the second reset power signal and the third reset power signal received by the pixel circuit unit.

[0244] For the driving power lines VDD in the vertical signal, referring to FIG. 10 , the following configuration may be performed: each pixel circuit unit corresponds to two driving power lines VDD.

[0245] Correspondingly, referring to FIG. 11 , the structural arrangement of the three pixel circuits 21 in the pixel circuit unit may be such that, in the arrangement direction of the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213, the first pixel circuit 211 is oriented opposite to the second pixel circuit 212. That is, at least a portion of the pattern of the first pixel circuit 211 is symmetrical to at least a portion of the pattern of the second pixel circuit 212.

[0246] Referring to Figures 10 and 12, in this case, for each pixel circuit unit, the orthographic projection of a driving power line VDD on the substrate substrate 1 at least partially overlaps with the orthographic projection of the first pixel circuit 211 on the substrate substrate 1 and the orthographic projection of the second pixel circuit 212 on the substrate substrate 1, and is connected to the first pixel circuit 211 and the second pixel circuit 212, that is, the driving power line VDD runs through the first pixel circuit 211 and the second pixel circuit 212, and is connected to the first pixel circuit 211 and the second pixel circuit 212 through vias.

[0247] Since the first pixel circuit 211 and the second pixel circuit 212 are arranged in opposite directions, the driving power line VDD can be set between the first pixel circuit 211 and the second pixel circuit 212, so as to realize a solution in which one driving power line VDD drives two pixel circuits 21, thereby reducing the number of driving power lines VDD and improving the light transmittance of the first display area 11.

[0248] It can be understood that the connection point of the first pixel circuit 211 connected to the driving power line VDD needs to be set at a position close to the second pixel circuit 212. Similarly, the connection point of the second pixel circuit 212 connected to the driving power line VDD needs to be set at a position close to the first pixel circuit 211. In this way, the connection point on the first pixel circuit 211 and the connection point on the second pixel circuit 212 can be connected to the same driving power line VDD.

[0249] The orthographic projection of the other driving power line VDD on the base substrate 1 at least partially overlaps with the orthographic projection of the third pixel circuit 213 on the base substrate 1, and is connected to the third pixel circuit 213, that is, the other driving power line VDD passes through the third pixel circuit 213 and is connected to the third pixel circuit 213 through a via. Optionally, the orientation of the third pixel circuit 213 can be the same as the orientation of the first pixel circuit 211, or the orientation of the third pixel circuit 213 can be the same as the orientation of the second pixel circuit 212, which is not limited in this embodiment of the present application.

[0250] Optionally, the second pixel circuit 212 and the third pixel circuit 213 can be arranged in opposite directions, and the orthographic projection of a driving power line VDD on the substrate substrate 1 at least partially overlaps with the orthographic projection of the second pixel circuit 212 on the substrate substrate 1 and the orthographic projection of the third pixel circuit 213 on the substrate substrate 1, and is connected to the second pixel circuit 212 and the third pixel circuit 213; the orthographic projection of another driving power line VDD on the substrate substrate 1 at least partially overlaps with the orthographic projection of the first pixel circuit 211 on the substrate substrate 1, and is connected to the first pixel circuit 211.

[0251] Optionally, the two driving power lines VDD may be further connected via a fifth connection line L5, wherein the extension direction of the fifth connection line L5 intersects with, for example, is perpendicular to, the extension direction of the driving power line VDD. In this way, the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 can receive the same driving power signal, thereby improving the stability of the pixel circuit unit receiving the driving power signal.

[0252] FIG13 is a cross-sectional view of a display panel provided in an embodiment of the present application. Referring to FIG13, in an embodiment of the present application, the display panel may include a bottom shield metal layer BSM, a buffer layer, an active layer a, a first gate insulating layer GI1, a first gate layer b, a second gate insulating layer GI2, a second gate layer c, a third gate insulating layer GI3, an oxide layer d, a fourth gate insulating layer GI4, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, a passivation layer i, a first transparent wiring layer k, a first planarization layer m, a second transparent wiring layer n, a second planarization layer p, a second source and drain electrode layer q, and a third planarization layer r, which constitute pixel circuits 21 and are stacked sequentially in a direction away from the substrate 1.

[0253] It should be noted that FIG13 is only for illustrating the stacking relationship of each film layer.

[0254] In the embodiment of the present application, the second transistor T2 is an oxide thin film transistor, and thus the second transistor T2 may be composed of a second gate layer c, an oxide layer d, and a third gate layer e. The material of the oxide layer d may be IGZO.

[0255] For example, the second transistor T2 may be a dual-gate transistor, the second gate layer c may include a bottom gate gate pattern of the second transistor T2, the oxide layer d may include an oxide pattern of the second transistor T2, and the third gate layer e may include a top gate gate pattern of the second transistor T2.

[0256] In addition, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are all LTPS thin film transistors, and thus the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can be composed of an active layer a, a first gate layer b and a first source and drain layer h.

[0257] For example, the active layer a may include an active pattern of a first transistor T1, an active pattern of a third transistor T3, an active pattern of a fourth transistor T4, an active pattern of a fifth transistor T5, an active pattern of a sixth transistor T6, an active pattern of a seventh transistor T7, and an active pattern of an eighth transistor T8.

[0258] The first gate layer b may include gate patterns of first, third, fourth, fifth, sixth, seventh, and eighth transistors T1, T3, T4, T5, T6, T7, and T8.

[0259] In an embodiment of the present application, a bottom shielding metal layer (BSM) may be located between the base substrate 1 and the active layer a, and the orthographic projection of the active pattern of the third transistor T3 on the base substrate 1 is located within the orthographic projection of the pattern in the bottom shielding metal layer on the base substrate 1, thereby insulating the base substrate 1 from the driving transistor (the third transistor T3) and preventing the base substrate 1 from being energized and thereby affecting the characteristics of the driving transistor itself.

[0260] The buffer layer buffer is located on a side of the bottom shielding metal layer away from the substrate 1 and is used to insulate the bottom shielding metal layer from the active layer a.

[0261] In an embodiment of the present application, the transparent signal lines in the horizontal signal lines (including the first reset signal line Preset, the second reset signal line Preset_H, the first gate signal line Gate_N, the second gate signal line Gate_P, and the light-emitting control signal line EM) of the multiple types of first signal lines 3 can be located in the first transparent routing layer k, the metal signal lines in the horizontal signal lines in the multiple types of first signal lines 3 can be located in the first source and drain layer h, the transparent signal lines in the vertical signal lines (including the first reset power line vinit1, the second reset power line vinit2, the third reset power line vinit3, the drive power line VDD, and the data signal line Data) of the multiple types of first signal lines 3 can be located in the second transparent routing layer n, and the metal signal lines in the vertical signal lines in the multiple types of first signal lines 3 can be located in the second source and drain layer q.

[0262] The second connection line L2 can be located on the first source and drain electrode layer h, and the third connection line L3 can be located on the third gate layer e. It is understood that in this example, the fourth connection line L4 and the fifth connection line L5 are not provided. If the fourth connection line L4 and the fifth connection line L5 are provided, they can be provided on any layer with space for placement among the first gate layer b, the second gate layer c, the third gate layer, and the first source and drain electrode layer h, and this embodiment of the application is not limited to this.

[0263] In order to clearly identify each film layer, the following describes each film layer when the pixel circuit 21 includes eight transistors in the form of each single layer and a step-by-step stacking method:

[0264] 1. The following describes a solution in which the data signal lines Data (including Data-1 connected to the first pixel circuit 211, Data-2 connected to the second pixel circuit 212, and Data-3 connected to the third pixel circuit 213) all include metal signal lines and transparent signal lines connected in parallel, and the first signal lines 3 of other types are transparent signal lines:

[0265] In this case, the display panel may include an active layer a, a first gate insulating layer, a first gate layer b, a second gate insulating layer, a second gate layer c, a third gate insulating layer, an oxide layer d, a fourth gate insulating layer, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain layer h, a passivation layer i, a first transparent wiring layer k, a first flat layer m, a second transparent wiring layer n, a second flat layer p, a second source and drain layer q and a third flat layer r, which constitute the pixel circuit 21 and are stacked in sequence along the direction away from the base substrate 1.

[0266] It should be noted that the pixel circuit group 2 composed of the patterns of the various film layers introduced below includes a pixel circuit unit, which includes a first pixel circuit 211, a second pixel circuit 212 and a third pixel circuit 213 arranged from left to right. In the arrangement direction of the first pixel circuit 211, the second pixel circuit 212 and the third pixel circuit 213, the orientation of the first pixel circuit 211 is relative to the orientation of the second pixel circuit 212, and the orientation of the third pixel circuit 213 is the same as the orientation of the first pixel circuit 211, wherein the relative arrangement means that at least part of the pattern of the first pixel circuit 211 is symmetrically arranged with at least part of the pattern of the second pixel circuit 212.

[0267] Figure 14 is a partial schematic diagram of an active layer a in a display panel provided in an embodiment of the present application. Referring to Figure 14 , the active layer a can have a curved or bent shape and includes active patterns (channel regions) and doping patterns (source and drain doping regions) for the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The active patterns and doping patterns for each of the transistors in the same pixel circuit 21 are integrated.

[0268] Among them, the first pixel circuit 211 includes active patterns (channel regions) of the first transistor T1-1, the third transistor T3-1, the fourth transistor T4-1, the fifth transistor T5-1, the sixth transistor T6-1, the seventh transistor T7-1 and the eighth transistor T8-1, and source and drain doping region patterns located on both sides of the active patterns of each transistor.

[0269] The second pixel circuit 212 includes active patterns (channel regions) and doping region patterns (source and drain doping regions) of the first transistor T1-2, the third transistor T3-2, the fourth transistor T4-2, the fifth transistor T5-2, the sixth transistor T6-2, the seventh transistor T7-2, and the eighth transistor T8-2.

[0270] The third pixel circuit 213 includes active patterns (channel regions) and doping region patterns (source-drain doping regions) of the first transistor T1-3, the third transistor T3-3, the fourth transistor T4-3, the fifth transistor T5-3, the sixth transistor T6-3, the seventh transistor T7-3, and the eighth transistor T8-3.

[0271] It should be noted that the active layer a may include an integrally formed low-temperature polysilicon layer, and the source and drain regions may be made conductive by doping, etc., to achieve electrical connection between the various structures. In other words, the semiconductor layer of each transistor in each pixel circuit is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., a source and drain region) and an active pattern, with the active patterns of different transistors separated.

[0272] The active layer a can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0273] The display panel may further include a first gate insulating layer located on a side of the active layer a away from the base substrate 1 , for insulating the active layer a from a first gate layer b to be formed subsequently.

[0274] Figure 15 is a partial schematic diagram of a first gate layer b in a display panel provided in an embodiment of the present application, and Figure 16 is a partial schematic diagram of the superposition of an active layer a and a first gate layer b in a display panel provided in an embodiment of the present application. The first gate layer b is located on a side of the first gate insulating layer away from the base substrate 1. Referring to Figures 15 and 16, the first gate layer b may include a second capacitor plate Cst2, a first gate pattern b1 of the first transistor T1, a third gate pattern b3 of the third transistor T3, a fourth gate pattern b4 of the fourth transistor T4, a fifth gate pattern b5 of the fifth transistor T5, a sixth gate pattern b6 of the sixth transistor T6, a seventh gate pattern b7 of the seventh thin-film transistor T7, and an eighth gate pattern b8 of the eighth transistor T8.

[0275] The first pixel circuit 211 includes a second capacitor plate Cst2-1, a first gate pattern b1-1 of a first transistor T1-1, a third gate pattern b3-1 of a third transistor T3-1, a fourth gate pattern b4-1 of a fourth transistor T4-1, a fifth gate pattern b5-1 of a fifth transistor T5-1, a sixth gate pattern b6-1 of a sixth transistor T6-1, a seventh gate pattern b7-1 of a seventh thin-film transistor T7-1, and an eighth gate pattern b8-1 of an eighth transistor T8-1. The third gate pattern b3-1 of the third transistor T3-1 and the second capacitor plate Cst2-1 can be considered to be an integrated structure.

[0276] The second pixel circuit 212 includes a second capacitor plate Cst2-2, a first gate pattern b1-2 of the first transistor T1-2, a third gate pattern b3-2 of the third transistor T3-2, a fourth gate pattern b4-2 of the fourth transistor T4-2, a fifth gate pattern b5-2 of the fifth transistor T5-2, a sixth gate pattern b6-2 of the sixth transistor T6-2, a seventh gate pattern b7-2 of the seventh thin-film transistor T7-2, and an eighth gate pattern b8-2 of the eighth transistor T8-2. The third gate pattern b3-2 of the third transistor T3-2 and the second capacitor plate Cst2-2 can be considered to be an integrated structure.

[0277] The third pixel circuit 213 includes a second capacitor plate Cst2-3, a first gate pattern b1-3 of the first transistor T1-3, a third gate pattern b3-3 of the third transistor T3-3, a fourth gate pattern b4-3 of the fourth transistor T4-3, a fifth gate pattern b5-3 of the fifth transistor T5-3, a sixth gate pattern b6-3 of the sixth transistor T6-3, a seventh gate pattern b7-3 of the seventh thin-film transistor T7-3, and an eighth gate pattern b8-3 of the eighth transistor T8-3. The third gate pattern b3-3 of the third transistor T3-3 and the second capacitor plate Cst2-3 can be considered to be an integrated structure.

[0278] It should be noted that the dotted rectangular boxes in Figure 16 show the overlapping parts of the first gate layer b and the active layer a. As the channel region of each transistor, the active layer a on both sides of each channel region is conductively connected through processes such as ion doping to serve as the first and second electrodes of each transistor. The source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiment of the present application, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode, so the first and second electrodes of all or part of the transistors in the embodiment of the present application can be interchangeable as needed.

[0279] The display panel may further include a second gate insulating layer located on a side of the first gate layer b away from the base substrate 1 , for insulating the first gate layer b from a subsequently formed second gate layer c.

[0280] Figure 17 is a partial schematic diagram of a second gate layer c in a display panel provided in an embodiment of the present application. Figure 18 is a partial schematic diagram of the superimposed active layer a, first gate layer b, and second gate layer c in a display panel provided in an embodiment of the present application. The second gate layer c is located on a side of the second gate insulating layer away from the base substrate 1. Referring to Figures 17 and 18, the second gate layer c may include a first capacitor plate Cst1 and a bottom gate pattern c2 located in the second gate layer c of the second transistor T2.

[0281] The first pixel circuit 211 includes a first capacitor plate Cst1-1 and a bottom gate pattern c2-1 located on the second gate layer c of the second transistor T2-1. The first capacitor plate Cst1-1 located on the second gate layer c at least partially overlaps with the second capacitor plate Cst2-1 located on the first gate layer b to form a storage capacitor Cst-1. The bottom gate pattern c2-1 also serves as a portion of the first gate signal line Gate_N located on the second gate layer c.

[0282] The second pixel circuit 212 includes a first capacitor plate Cst1-2 and a bottom gate pattern c2-2 located in the second gate layer c of the second transistor T2-2. The first capacitor plate Cst1-2 located in the second gate layer c at least partially overlaps with the second capacitor plate Cst2-2 located in the first gate layer b to form a storage capacitor Cst-2. The bottom gate pattern c2-2 is also used for a portion of the first gate signal line Gate_N located in the second gate layer c.

[0283] The third pixel circuit 213 includes a first capacitor plate Cst1-3 and a bottom gate pattern c2-3 located in the second gate layer c of the second transistor T2-3. The first capacitor plate Cst1-3 located in the second gate layer c at least partially overlaps with the second capacitor plate Cst2-3 located in the first gate layer b to form a storage capacitor Cst-3. The bottom gate pattern c2-3 also serves as a portion of the first gate signal line Gate_N located in the second gate layer c.

[0284] In addition, a third gate insulating layer may be formed on the second gate layer c to insulate the second gate layer c from the subsequently formed oxide layer d.

[0285] Figure 19 is a partial schematic diagram of an oxide layer d in a display panel provided in an embodiment of the present application. Figure 20 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, and an oxide layer d in a display panel provided in an embodiment of the present application. Oxide layer d is located on a side of the third gate insulating layer that is distal from the base substrate 1. Referring to Figures 19 and 20, oxide layer d may include an oxide pattern for forming the second transistor T2-1 of the first pixel circuit 211, an oxide pattern for forming the second transistor T2-2 of the second pixel circuit 212, and an oxide pattern for forming the second transistor T2-3 of the third pixel circuit 213.

[0286] In addition, a fourth gate insulating layer may be formed on the oxide layer d to insulate the oxide layer d from a third gate layer e to be formed subsequently.

[0287] Figure 21 is a partial schematic diagram of a third gate layer e in a display panel provided in an embodiment of the present application. Figure 22 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, and the third gate layer e in a display panel provided in an embodiment of the present application. The third gate layer e is located on a side of the fourth gate insulating layer away from the base substrate 1. Referring to Figures 21 and 22, the third gate layer e may include a top gate pattern e2-1 of the second transistor T2-1 in the first pixel circuit 211, a top gate pattern e2-2 of the second transistor T2-2 in the second pixel circuit 212, a top gate pattern e2-3 of the second transistor T2-3 in the third pixel circuit 213, and a third connection line L3. In which, the top gate pattern e2-1 of the second transistor T2-1 at least partially overlaps with the bottom gate pattern c2-1 of the second transistor T2-1 located in the second gate layer c, thereby forming the second transistor T2-1 in the first pixel circuit 211, the top gate pattern e2-2 of the second transistor T2-2 at least partially overlaps with the bottom gate pattern c2-2 of the second transistor T2-2 located in the second gate layer c, thereby forming the second transistor T2-2 in the second pixel circuit 212, and the top gate pattern e2-3 of the second transistor T2-3 at least partially overlaps with the bottom gate pattern c2-3 of the second transistor T2-3 located in the second gate layer c, thereby forming the second transistor T2-3 in the second pixel circuit 213.

[0288] In addition, two interlayer dielectric layers, namely a first interlayer dielectric layer f and a second interlayer dielectric layer g, may be formed on the third gate layer e to insulate the third gate layer e from the subsequently formed first source and drain layer h.

[0289] Figure 23 is a partial schematic diagram of the first interlayer dielectric layer f in a display panel provided in an embodiment of the present application, and Figure 24 is a partial superposition schematic diagram of the active layer a, the first gate layer b, the second gate layer c, the oxide layer d, the third gate layer e and the first interlayer dielectric layer f in a display panel provided in an embodiment of the present application.

[0290] Figure 25 is a partial schematic diagram of the second interlayer dielectric layer g in a display panel provided in an embodiment of the present application, and Figure 26 is a partial superposition schematic diagram of the active layer a, the first gate layer b, the second gate layer c, the oxide layer d, the third gate layer e, the first interlayer dielectric layer f and the second interlayer dielectric layer g in a display panel provided in an embodiment of the present application.

[0291] In order to facilitate the illustration of the first vias f1 in the first interlayer dielectric layer f and the second vias g1 in the second interlayer dielectric layer g, filling patterns are used to represent the first vias f1 and the second vias g1 in Figures 23 to 26, and other areas without filling patterns are used to represent areas where the first interlayer dielectric layer f and the second interlayer dielectric layer g have solid materials.

[0292] It should be noted that each via hole opened in the interlayer dielectric layer is used to connect the subsequently formed film layer with the film layer on the side of the interlayer dielectric layer close to the base substrate 1, that is, each via hole is a via hole for connecting the film layers.

[0293] Figure 27 is a partial schematic diagram of a first source and drain electrode layer h in a display panel provided in an embodiment of the present application, and Figure 28 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, and a first source and drain electrode layer h in a display panel provided in an embodiment of the present application. Referring to Figures 27 and 28 , the first source and drain electrode layer h may include:

[0294] A second connecting line L2;

[0295] The first pixel circuit 211 includes a first source-drain pattern h1-1, a second source-drain pattern h2-1, a third source-drain pattern h3-1, a fourth source-drain pattern h4-1, a fifth source-drain pattern h5-1, a sixth source-drain pattern h6-1, a seventh source-drain pattern h7-1, an eighth source-drain pattern h8-1, a ninth source-drain pattern h9-1, a tenth source-drain pattern h10-1, an eleventh source-drain pattern h11-1, a twelfth source-drain pattern h12-1, a thirteenth source-drain pattern h13-1, and a fourteenth source-drain pattern h14-1;

[0296] The second pixel circuit 212 includes a first source-drain pattern h1-2, a third source-drain pattern h3-2, a fifth source-drain pattern h5-2, a sixth source-drain pattern h6-2, an eighth source-drain pattern h8-2, a tenth source-drain pattern h10-1, an eleventh source-drain pattern h11-2, a thirteenth source-drain pattern h13-2, and a fourteenth source-drain pattern h14-2;

[0297] In addition, the third pixel circuit 213 includes a first source-drain pattern h1-3, a second source-drain pattern h2-2, a third source-drain pattern h3-3, a fourth source-drain pattern h4-2, a fifth source-drain pattern h5-3, a sixth source-drain pattern h6-3, a seventh source-drain pattern h7-2, an eighth source-drain pattern h8-3, a ninth source-drain pattern h9-2, a tenth source-drain pattern h10-2, an eleventh source-drain pattern h11-3, a twelfth source-drain pattern h12-2, a thirteenth source-drain pattern h13-3 and a fourteenth source-drain pattern h14-3.

[0298] For the first pixel circuit 211:

[0299] The first source-drain pattern h1-1 is used to connect the first electrode of the first transistor T1-1, the second connection line L2, and the first transparent wiring pattern k1 located in the first transparent wiring layer k described later. The first source-drain pattern h1-1 and the second connection line L2 can be an integrated structure;

[0300] The second source-drain pattern h2-1 is used to connect the first gate pattern b1-1 located on the first gate layer b of the first transistor T1-1 and the first reset signal line Preset located on the first transparent wiring layer k to be described later;

[0301] a third source-drain pattern h3-1, for connecting the second electrode of the first transistor T1-1, the first electrode of the second transistor T2-1, the first electrode of the third transistor T3-1, and the first electrode of the sixth transistor T6-1;

[0302] The fourth source-drain pattern h4-1 is used to connect the bottom gate pattern c2-1 of the second transistor T2-1 located in the second gate layer c, the top gate pattern e2-1 of the second transistor T2-1 located in the third gate layer e, and the first gate signal line Gate_N located in the first transparent wiring layer k described later;

[0303] a fifth source-drain pattern h5-1, configured to connect the second electrode of the second transistor T2-1, the second capacitor plate Cst2-1 of the storage capacitor Cst-1 located on the first gate layer b, and the third gate pattern b3-1 of the third transistor T3-1 located on the first gate layer b;

[0304] a sixth source-drain pattern h6-1, for connecting the second electrode of the third transistor T3-1, the second electrode of the fourth transistor T4-1, the first electrode of the fifth transistor T5-1, and the second electrode of the eighth transistor T8-1;

[0305] The seventh source-drain pattern h7-1 is used to connect the fourth gate pattern b4-1 of the fourth transistor T4-1 located on the first gate layer b and the second gate signal line Gate_P located on the first transparent wiring layer k to be described later;

[0306] An eighth source-drain pattern h8-1 is used to connect the first electrode of the fourth transistor T4-1 and a second transparent wiring pattern k2 located in the first transparent wiring layer k to be described later;

[0307] a ninth source / drain pattern h9-1 for connecting a fifth gate pattern b5-1 of the fifth transistor T5-1 located on the first gate layer b, a sixth gate pattern b6-1 of the sixth transistor T6-1 located on the first gate layer b, and a light emission control signal EM located on the first transparent wiring layer k to be described later;

[0308] a tenth source / drain pattern h10-1, connected to the second electrode of the fifth transistor T5-1, the first capacitor plate Cst1-1 of the storage capacitor Cst-1 located on the second gate layer c, and a third transparent wiring pattern k3 located on the first transparent wiring layer k to be described later;

[0309] An eleventh source-drain pattern h11-1 is used to connect the second electrode of the sixth transistor T6-1, the second electrode of the seventh transistor T7-1, and a seventh transparent wiring pattern k7 located in the first transparent wiring layer k to be described later;

[0310] A twelfth source-drain pattern h12-1 is used to connect the seventh gate pattern b7-1 of the seventh transistor T7-1 located on the first gate layer b, the eighth gate pattern b8-1 of the eighth transistor T8-1 located on the first gate layer b, and a second reset signal line Preset_H located on the first transparent wiring layer k to be described later;

[0311] A thirteenth source-drain pattern h13-1 is used to connect the first electrode of the eighth transistor T8-1 and the third connection line L3 located on the third gate layer e;

[0312] The fourteenth source-drain pattern h14-1 is used to connect the first electrode of the seventh transistor T7-1, the fifth transparent wiring pattern k5 and the sixth transparent wiring pattern k6 located in the first transparent wiring layer k to be introduced later, and will be specifically described below with respect to the first transparent wiring layer k.

[0313] For the second pixel circuit 212:

[0314] A first source-drain pattern h1-2 is used to connect the first electrode of the first transistor T1-2 and the second connection line L2. The first source-drain pattern h1-2 and the second connection line L2 can be an integral structure;

[0315] a third source-drain pattern h3-2, for connecting the second electrode of the first transistor T1-2, the first electrode of the second transistor T2-2, the first electrode of the third transistor T3-2, and the first electrode of the sixth transistor T6-2;

[0316] a fifth source-drain pattern h5-2, used to connect the second electrode of the second transistor T2-2, the second capacitor plate Cst2-2 of the storage capacitor Cst-2 located on the first gate layer b, and the third gate pattern b3-2 of the third transistor T3-2 located on the first gate layer b;

[0317] a sixth source-drain pattern h6-2, for connecting the second electrode of the third transistor T3-2, the second electrode of the fourth transistor T4-2, the first electrode of the fifth transistor T5-2, and the second electrode of the eighth transistor T8-2;

[0318] an eighth source-drain pattern h8-2, used to connect the first electrode of the fourth transistor T4-2 and a ninth transparent wiring pattern k9 located in the first transparent wiring layer k to be described later;

[0319] a tenth source-drain pattern h10-1, used to connect the second electrode of the fifth transistor T5-2, the first capacitor plate Cst1-2 of the storage capacitor Cst-2 located on the second gate layer c, and a third transparent trace pattern k3 located on the first transparent trace layer k to be described later;

[0320] an eleventh source-drain pattern h11-2, used to connect the second electrode of the sixth transistor T6-2, the second electrode of the seventh transistor T7-2, and a twelfth transparent wiring pattern k12 located in the first transparent wiring layer k to be described later;

[0321] A thirteenth source-drain pattern h13-2 is used to connect the first electrode of the eighth transistor T8-2, the third connection line L3 located on the third gate layer e, and the fourth transparent wiring pattern k4 located on the first transparent wiring layer k to be described later;

[0322] The fourteenth source-drain pattern h14-2 is used to connect the first electrode of the seventh transistor T7-2, the tenth transparent wiring pattern k10 and the eleventh transparent wiring pattern k11 located in the first transparent wiring layer k to be introduced later, and will be specifically described below with respect to the first transparent wiring layer k.

[0323] In the embodiment of the present application, the first gate patterns b1-1, b1-2, and b1-3 located in the first gate layer b can be arranged as an integrated structure. In this way, for the second pixel circuit 212, the first gate pattern b1-2 located in the first gate layer b of the first transistor T1-2 and the first gate pattern b1-2 located in the first gate layer b of the first transistor T1-2 can be connected to the first reset signal line Preset located in the first transparent wiring layer k described later through the integrated structure of the first gate patterns.

[0324] The bottom gate patterns c2-1, c2-2, and c2-3 located in the second gate layer c may be configured as an integrated structure, and the top gate patterns e2-1, e2-2, and e2-3 located in the third gate layer e may be configured as an integrated structure. In this way, for the second pixel circuit 212, the bottom gate pattern c2-2 located in the second gate layer c of the second transistor T2-2 and the top gate pattern e2-2 located in the third gate layer e of the second transistor T2-2 may be connected to the first gate signal line Gate_N located in the first transparent wiring layer k described later through the integrated structure of the bottom gate pattern and the integrated structure of the top gate pattern, respectively.

[0325] The fourth gate patterns b4-1, b4-2, and b4-3 located on the first gate layer b may also be provided as an integrated structure. Thus, for the second pixel circuit 212, the fourth gate pattern b4-2 located on the first gate layer b of the fourth transistor T4-2 may be implemented as the second gate signal line Gate_P located on the first transparent wiring layer k described later through the integrated structure of the fourth gate pattern.

[0326] The fifth gate patterns b5-1, b6-1, and b5-2 located on the second gate layer b and the sixth gate patterns b6-2, b5-3, and b6-3 located on the second gate layer b may also be configured as an integrated structure. Thus, for the second pixel circuit 212, the fifth gate pattern b5-2 located on the second gate layer b of the fifth transistor T5-2 and the sixth gate pattern b6-2 located on the first gate layer b of the sixth transistor T6-2 may be configured as an integrated structure to implement the light emission control signal EM located on the first transparent wiring layer k described later.

[0327] The seventh gate pattern b7-1, b7-2, b7-3 and the eighth gate pattern b8-1, b8-2, b8-3 located on the first gate layer b can also be set as an integrated structure. In this way, for the second pixel circuit 212, the seventh gate pattern b7-2 of the seventh transistor T7-2 located on the first gate layer b and the eighth gate pattern b8-2 of the eighth transistor T8-2 located on the first gate layer b can be realized through the integrated structure of the seventh gate pattern and the eighth gate pattern, and the second reset signal line Preset_H located on the first transparent wiring layer k to be introduced later can be realized.

[0328] For the third pixel circuit 213:

[0329] A first source-drain pattern h1-3 is used to connect the first electrode of the first transistor T1-3 and the second connection line L2. The first source-drain pattern h1-3 and the second connection line L2 can be an integral structure;

[0330] The second source-drain pattern h2-2 is used to connect the first gate pattern b1-3 located on the first gate layer b of the first transistor T1-3 and the first reset signal line Preset located on the first transparent wiring layer k to be described later;

[0331] a third source-drain pattern h3-3, for connecting the second electrode of the first transistor T1-3, the first electrode of the second transistor T2-3, the first electrode of the third transistor T3-3, and the first electrode of the sixth transistor T6-3;

[0332] The fourth source-drain pattern h4-2 is used to connect the bottom gate pattern c2-3 of the second transistor T2-3 located in the second gate layer c, the top gate pattern e2-3 of the second transistor T2-3 located in the third gate layer e, and the first gate signal line Gate_N located in the first transparent wiring layer k described later;

[0333] a fifth source-drain pattern h5-3, used to connect the second electrode of the second transistor T2-3, the second capacitor plate Cst2-3 of the storage capacitor Cst-3 located on the first gate layer b, and the third gate pattern b3-3 of the third transistor T3-3 located on the first gate layer b;

[0334] a sixth source-drain pattern h6-3, for connecting the second electrode of the third transistor T3-3, the second electrode of the fourth transistor T4-3, the first electrode of the fifth transistor T5-3, and the second electrode of the eighth transistor T8-3;

[0335] The seventh source-drain pattern h7-2 is used to connect the fourth gate pattern b4-3 of the fourth transistor T4-3 located on the first gate layer b and the second gate signal line Gate_P located on the first transparent wiring layer k to be described later;

[0336] an eighth source-drain pattern h8-3, used to connect the first electrode of the fourth transistor T4-3 and a sixteenth transparent wiring pattern k16 located in the first transparent wiring layer k to be described later;

[0337] a ninth source / drain pattern h9-2, connected to a fifth gate pattern b5-3 of the fifth transistor T5-3 located on the first gate layer b, a sixth gate pattern b6-3 of the sixth transistor T6-3 located on the first gate layer b, and a light emitting control signal EM located on the first transparent wiring layer k to be described later;

[0338] a tenth source / drain pattern h10-2, configured to connect the second electrode of the fifth transistor T5-3, the first capacitor plate Cst1-3 of the storage capacitor Cst-3 located on the second gate layer c, and a driving power line VDD-2 located on the second transparent wiring layer n, described later. The driving power line VDD-2 is the same driving power line connected to the third pixel circuit 213;

[0339] an eleventh source-drain pattern h11-3, used to connect the second electrode of the sixth transistor T6-3, the second electrode of the seventh transistor T7-3, and a fifteenth transparent wiring pattern k15 located in the first transparent wiring layer k to be described later;

[0340] A twelfth source-drain pattern h12-2 is used to connect the seventh gate pattern b7-3 of the seventh transistor T7-3 located on the first gate layer b, the eighth gate pattern b8-3 of the eighth transistor T8-3 located on the first gate layer b, and a second reset signal line Preset_H located on the first transparent wiring layer k to be described later;

[0341] The thirteenth source-drain pattern h13 - 3 is used to connect the first electrode of the eighth transistor T8 - 3 and the third connection line L3 located on the third gate layer e. In this way, the thirteenth source-drain pattern h13-2 can be used to realize the connection between the first electrode of the eighth transistor T8-2 constituting the second pixel circuit 212, the third connection line L3, and the fourth transparent routing pattern k4 located in the first transparent routing layer k to be introduced later. Furthermore, the fourth transparent routing k4 can be used to realize the connection between the first electrode of the eighth transistor T8-2 constituting the second pixel circuit 212, the third connection line L3, and the third reset power line vinit3 located in the second transparent routing layer n to be introduced later. At the same time, the thirteenth source-drain patterns h13-1 and h13-3 can also realize the connection between the first electrode of the eighth transistor T8-1 constituting the first pixel circuit 211 and the third connection line L3, and the connection between the first electrode of the eighth transistor T8-3 of the third pixel circuit 213 and the third connection line L3. In summary, the connection between the three pixel circuits 21 and the third reset power line vinit3 is realized through one third reset power line vinit3 and one third connection line L3.

[0342] The fourteenth source and drain pattern h14-3 is used to connect the first electrode of the seventh transistor T7-3, the fifth transparent routing pattern k5-1 and the sixth transparent routing pattern k13 and the fourteenth transparent routing pattern k14 located on the first transparent routing layer k to be introduced later. The specific description will be made below regarding the first transparent routing layer k, wherein the fourteenth source and drain patterns h14-3 and h14-2 can be an integrated structure.

[0343] In addition, a passivation layer i may be formed on the first source and drain electrode layer h, so as to insulate the first source and drain electrode layer h from a first transparent wiring layer k to be formed subsequently.

[0344] Figure 29 is a partial schematic diagram of a passivation layer i in a display panel provided in an embodiment of the present application. Figure 30 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, and the passivation layer i in a display panel provided in an embodiment of the present application. The passivation layer i is located on the side of the first source and drain electrode layer h that is away from the base substrate 1.

[0345] To facilitate illustration of the third vias i1 in the passivation layer, FIG29 and FIG30 use a filled pattern to represent the vias. Other areas without a filled pattern represent areas of the passivation layer i containing solid material. It should be noted that the third vias i1 defined in the passivation layer i are used to connect a subsequently formed film layer to the film layer on the side of the passivation layer i closer to the base substrate 1. In other words, the third vias i1 are vias for connecting film layers.

[0346] FIG31 is a partial schematic diagram of a first transparent wiring layer k in a display panel provided in an embodiment of the present application. FIG32 is a partial superimposed schematic diagram of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain layer h, a passivation layer i, and a first transparent wiring layer k in a display panel provided in an embodiment of the present application. The first transparent wiring layer k is located on the side of the passivation layer i away from the base substrate 1. Referring to FIG31 and FIG32, the first transparent wiring layer k includes:

[0347] A first reset signal line Preset, a second reset signal line Preset_H, a first gate signal line Gate_N, a second gate signal line Gate_P, and a light-emitting control signal line EM. It can be understood that, on both sides of each pixel circuit group 2 in the first direction, a line segment corresponding to the first reset signal line Preset, a line segment corresponding to the second reset signal line Preset_H, a line segment corresponding to the first gate signal line Gate_N, a line segment corresponding to the second gate signal line Gate_P, and a line segment corresponding to the light-emitting control signal line EM are provided. These line segments are used to connect two adjacent pixel circuit groups 2 in the first direction;

[0348] A first transparent wiring pattern k1 is used to connect the first source and drain pattern h1-1 located on the first source and drain layer h and the first reset power line vinit1-1 located on the second transparent wiring layer n described later, wherein the first reset power line vinit1-1 is the first reset power line vinit1 that runs through the first pixel circuit 211 and is connected to the first pixel circuit 211;

[0349] The second transparent wiring pattern k2 is used to connect the eighth source-drain pattern h8-1 located on the first source-drain layer h and the data signal line Data-1 located on the second transparent wiring layer n described later, wherein the data signal line Data-1 is the data signal line Data connected to the first pixel circuit 211;

[0350] a third transparent wiring pattern k3, configured to connect a tenth source / drain pattern h10-1 located on the first source / drain layer h and a driving power signal line VDD-1 located on the second transparent wiring layer n, which will be described later. The driving power signal line VDD-1 is the driving power signal line VDD that runs through the first pixel circuit 211 and the second pixel circuit 212 and is connected to the first pixel circuit 211 and the second pixel circuit 212;

[0351] a fourth transparent wiring pattern k4, used to connect the thirteenth source and drain pattern h13-2 located on the first source and drain layer h and a third reset power line vinit3 located on the second transparent wiring layer n to be described later;

[0352] The fifth transparent routing pattern k5 and the sixth transparent routing pattern k6 are used to connect the two ends of the fourteenth source-drain pattern h14-1 located on the first source-drain layer h to the second reset power line vinit2-1 located on the second transparent routing layer n, which will be described later. The two second reset power lines vinit2-1 located above and below the first pixel circuit 211 can be connected via the fourteenth source-drain pattern h14-1, thereby forming the second reset power line vinit2 located above and below the first pixel circuit 211 and the fourteenth source-drain pattern h14-1.

[0353] a seventh transparent wiring pattern k7, used to connect the eleventh source and drain pattern h11 located on the first source and drain layer h and the seventeenth transparent wiring pattern n1 located on the second transparent wiring layer n to be described later;

[0354] An eighth transparent wiring pattern k8 is used to connect the second connection line L2 located on the first source and drain electrode layer h and the second reset power line vinit1-2 located on the second transparent wiring layer n to be described later;

[0355] a ninth transparent wiring pattern k9, configured to connect the eighth source / drain pattern h8-2 located on the first source / drain layer h and a data signal line Data-2 located on the second transparent wiring layer n, which will be described later. The data signal line Data-2 is the data signal line Data connected to the second pixel circuit 212;

[0356] The tenth transparent routing pattern k10 and the eleventh transparent routing pattern k11 are used to connect the two ends of the fourteenth source-drain pattern h14-2 located on the first source-drain layer h to the second reset power line vinit2-2 located on the second transparent routing layer n, which will be described later. The two second reset power lines vinit2-2 located above and below the second pixel circuit 212 can be connected via the fourteenth source-drain pattern h14-2, thereby forming the second reset power line vinit2 located above and below the second pixel circuit 212 and the fourteenth source-drain pattern h14-2.

[0357] The twelfth transparent wiring pattern k12 is used to connect the eleventh source and drain pattern h11-2 located on the first source and drain layer h and the eighteenth transparent wiring pattern n2 located on the second transparent wiring layer n to be described later;

[0358] The thirteenth transparent routing pattern k13 and the fourteenth transparent routing pattern k14 are used to connect the two ends of the fourteenth source-drain pattern h14-3 located on the first source-drain layer h to the second reset power line vinit2-3 located on the second transparent routing layer n described later. The two second reset power lines vinit2-3 located above and below the third pixel circuit 213 can be connected via the fourteenth source-drain pattern h14-3, thereby forming the second reset power line vinit2 that runs through the third pixel circuit 213 together with the fourteenth source-drain pattern h14-3.

[0359] A fifteenth transparent wiring pattern k15 is used to connect the eleventh source and drain pattern h11-3 located on the first source and drain layer h and the nineteenth transparent wiring pattern n3 located on the second transparent wiring layer n to be described later;

[0360] a sixteenth transparent wiring pattern k16, configured to connect the eighth source-drain pattern h8-3 located on the first source-drain layer h and a data signal line Data-3 located on the second transparent wiring layer n, which will be described later. The data signal line Data-3 is the data signal line Data connected to the third pixel circuit 213;

[0361] In addition, a first flat layer m may be formed on the first transparent wiring layer k to insulate the first transparent wiring layer k from a second transparent wiring layer n to be formed subsequently.

[0362] Figure 33 is a partial schematic diagram of a first planar layer m in a display panel provided in an embodiment of the present application. Figure 34 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, a passivation layer i, a first transparent wiring layer k, and a first planar layer m in a display panel provided in an embodiment of the present application. The first planar layer m is located on a side of the first transparent wiring layer k away from the base substrate 1.

[0363] To facilitate illustration of the fourth vias m1 in the first planar layer m, Figures 33 and 34 use fill patterns to represent the fourth vias m1. Other areas without fill patterns represent areas of the first planar layer m containing solid material. It should be noted that the fourth vias m1 in the first planar layer m are used to connect a subsequently formed membrane layer to the membrane layer on the side of the first planar layer m closest to the base substrate 1. In other words, the fourth vias m1 are vias for connecting membrane layers.

[0364] Figure 35 is a partial schematic diagram of a second transparent wiring layer n in a display panel provided in an embodiment of the present application. Figure 36 is a partial superimposed schematic diagram of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, a passivation layer i, a first transparent wiring layer k, a first planar layer m, and a second transparent wiring layer n in a display panel provided in an embodiment of the present application. The second transparent wiring layer n is located on a side of the first planar layer m away from the base substrate 1. Referring to Figures 35 and 36, the second transparent wiring layer n may include:

[0365] A first reset power line vinit1 includes vinit1-1 and vinit1-2, vinit1-1 and vinit1-2 are connected via a second connection line L2 of the first source-drain layer h, vinit1-1 is connected to the first pixel circuit 211, vinit1-2 is connected to the third pixel circuit 213, and the second connection line L2 is connected to the second pixel circuit 212;

[0366] A second reset power line vinit2 includes vinit2-1, vinit2-2, and vinit2-3, vinit2-1 is connected to the first pixel circuit 211, vinit2-2 is connected to the second pixel circuit 212, and vinit2-3 is connected to the third pixel circuit 213;

[0367] A third reset power line vinit3 is connected to the second pixel circuit 212 and the third connection line L3, and the third connection line L3 is connected to the first pixel circuit 211 and the third pixel circuit 213;

[0368] A driving power line VDD includes VDD-1 and VDD-2, wherein VDD-1 is connected to the first pixel circuit 211 and the second pixel circuit 212, and VDD-2 is connected to the third pixel circuit 213;

[0369] Data signal lines Data, including Data-1, Data-2, and Data-3, where Data-1 is connected to the first pixel circuit 211, Data-2 is connected to the second pixel circuit 212, and Data-3 is connected to the third pixel circuit 213;

[0370] The seventeenth transparent wiring pattern n1 is used to connect the seventh transparent wiring pattern k7 located on the first transparent wiring layer k and the fifteenth source-drain pattern q1 located on the second source-drain layer q to be described later;

[0371] An eighteenth transparent wiring pattern n2 is used to connect the twelfth transparent wiring pattern k12 located on the first transparent wiring layer k and the seventeenth source-drain pattern q3 located on the second source-drain layer q to be described later;

[0372] The nineteenth transparent wiring pattern n3 is used to connect the fifteenth transparent wiring pattern k15 located on the first transparent wiring layer k and the eighteenth source-drain pattern q4 located on the second source-drain layer q to be described later.

[0373] In addition, a second flat layer p may be formed on the second transparent wiring layer n to insulate the second transparent wiring layer n from a second source and drain electrode layer q to be formed subsequently.

[0374] Figure 37 is a partial schematic diagram of a second planar layer p in a display panel provided in an embodiment of the present application. Figure 38 is a partial schematic diagram of the superposition of the active layer a, first gate layer b, second gate layer c, oxide layer d, third gate layer e, first interlayer dielectric layer f, second interlayer dielectric layer g, first source and drain electrode layer h, passivation layer i, first transparent wiring layer k, first planar layer m, second transparent wiring layer n, and second planar layer p in a display panel provided in an embodiment of the present application. The second planar layer p is located on the side of the second transparent wiring layer n away from the base substrate 1.

[0375] To facilitate illustration of the fifth vias p1 in the second planar layer p, Figures 37 and 38 use fill patterns to represent the fifth vias p1. Other areas without fill patterns represent areas of the second planar layer p containing solid material. It should be noted that the fifth vias p1 in the second planar layer p are used to connect a subsequently formed membrane layer to the membrane layer on the side of the second planar layer p closest to the base substrate 1. In other words, the fifth vias p1 are vias for connecting membrane layers.

[0376] Figure 39 is a partial schematic diagram of a second source and drain electrode layer q in a display panel provided in an embodiment of the present application. Figure 40 is a partial superimposed schematic diagram of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, a passivation layer i, a first transparent wiring layer k, a first flat layer m, a second transparent wiring layer n, a second flat layer p, and a second source and drain electrode layer q in a display panel provided in an embodiment of the present application. The second source and drain electrode layer q is located on a side of the second flat layer p away from the base substrate 1. Referring to Figures 39 and 40, the second source and drain electrode layer q may include:

[0377] The fifteenth source-drain pattern q1 is used to connect the seventeenth transparent wiring pattern n1 located on the second transparent wiring layer n and the anode 51 of the first light-emitting element located on the anode layer to be described later;

[0378] A sixteenth source / drain pattern q2 is configured to be connected to the driving power signal line VDD-1 located on the second transparent wiring layer n to achieve parallel connection of a section of the line. This reduces the resistance of the driving power signal line VDD-1 by connecting a section of the metal signal line in parallel to the transparent signal line of the driving power signal line VDD-1, thereby reducing the occurrence of defective vias in the vertical direction of the first display area 11 and improving display uniformity.

[0379] a seventeenth source-drain pattern q3, used to connect the eighteenth transparent wiring pattern n2 located in the second transparent wiring layer n and the first connection line L1 located in the anode layer to be described later, so as to realize connection between the seventeenth source-drain pattern q3 and the anode 52 of the second light-emitting element located in the anode layer to be described later through the first connection line L1;

[0380] an eighteenth source-drain pattern q4, configured to connect a nineteenth transparent trace pattern n3 located in the second transparent trace layer n and an anode 53 of a third light-emitting element located in the anode layer, described later. The eighteenth source-drain pattern q4 includes a line segment, the orthographic projection of the line segment on the base substrate 1 and the orthographic projection of the data signal line Data-3' described later on the base substrate 1 both at least partially overlap with the orthographic projection of the anode 53 of the third light-emitting element on the base substrate 1. The overlapping portion of the line segment with the anode 53 of the third light-emitting element and the overlapping portion of the data signal line Data-3' with the anode 53 of the third light-emitting element may be symmetrically arranged about an axis of symmetry of the anode 53 of the third light-emitting element, thereby improving the flatness of the anode 53 of the third light-emitting element.

[0381] The data signal line Data includes Data-1', Data-2' and Data-3'. Data-1' is connected to Data-1 located on the second transparent wiring layer n, Data-2' is connected to Data-2 located on the second transparent wiring layer n, and Data-3' is connected to Data-3 located on the second transparent wiring layer n, thereby realizing a parallel connection between the metal signal line and the transparent signal line.

[0382] It should be noted that Data-4' marked in Figures 39 and 40 is not connected to the pixel circuit group A in Figure 40, but is connected to the pixel circuit group B below it. In an embodiment of the present application, the orthographic projection of the metal signal line on the base substrate 1 can be set to at least partially overlap with the orthographic projection of the adjacent pixel circuit group 2 on the base substrate 1. For example, the orthographic projection of Data-4' in Figure 40 on the base substrate 1 at least partially overlaps with the orthographic projection of the pixel circuit group A on the base substrate 1. In this way, the blocking effect of the metal signal line on the transparent area in the first display area 11 can be reduced, thereby improving the light transmittance of the first display area 11.

[0383] In addition, a third planar layer r may be formed on the second source-drain electrode layer q to insulate the second source-drain electrode layer q from the anode layer of the light-emitting element.

[0384] Figure 41 is a partial schematic diagram of a third planar layer r in a display panel provided in an embodiment of the present application. Figure 42 is a partial schematic diagram of the superposition of the active layer a, first gate layer b, second gate layer c, oxide layer d, third gate layer e, first interlayer dielectric layer f, second interlayer dielectric layer g, first source and drain electrode layer h, passivation layer i, first transparent wiring layer k, first planar layer m, second transparent wiring layer n, second planar layer p, second source and drain electrode layer q, and third planar layer r in a display panel provided in an embodiment of the present application. The third planar layer r is located on the side of the second source and drain electrode layer q away from the base substrate 1.

[0385] To facilitate illustration of the sixth vias r1 in the third planar layer r, Figures 41 and 42 use a fill pattern to represent the sixth vias r1. Other areas without fill patterns represent areas of the third planar layer r containing solid material. It should be noted that the sixth vias r1 in the third planar layer r are used to connect a subsequently formed membrane layer to a membrane layer on the side of the third planar layer r closer to the base substrate 1. In other words, the sixth vias r1 are vias for connecting membrane layers.

[0386] Figure 43 is a partial schematic diagram of an anode layer in a display panel provided in an embodiment of the present application. Figure 44 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, a passivation layer i, a first transparent wiring layer k, a first planar layer m, a second transparent wiring layer n, a second planar layer p, a second source and drain electrode layer q, a third planar layer r, and an anode layer in a display panel provided in an embodiment of the present application. The anode layer is located on the side of the third planar layer r away from the base substrate 1.

[0387] 43 and 44 , the anode layer may include an anode 51 of a first light-emitting element, an anode 52 of a second light-emitting element, an anode 53 of a third light-emitting element, and a first connecting line L1. The anode 51 of the first light-emitting element is connected to the fifteenth source-drain pattern q1 located in the second source-drain layer q, and both ends of the first connecting line L1 are connected to the anodes 52 of the two second light-emitting elements. The first connecting line L1 is connected to the seventeenth source-drain pattern q3 located in the second source-drain layer q, and the anode 53 of the third light-emitting element is connected to the eighteenth source-drain pattern q4 located in the second source-drain layer q.

[0388] In combination with Figures 14 to 44, some types of first signal lines 3 include data signal lines Data (including Data-1, Data-2 and Data-3), and these some types of first signal lines 3 are metal signal lines and transparent signal lines connected in parallel, that is, the data signal lines Data include a transparent signal line located in the second transparent routing layer n and a metal signal line located in the second source and drain layer q.

[0389] The other types of first signal lines 3 include a first reset signal line Preset, a second reset signal line Preset_H, a first gate signal line Gate_N, a second gate signal line Gate_P, a light emitting control signal line EM, a first reset power line vinit1 (including vinit1-1 and vinit1-2), a second reset power line vinit2 (including vinit2-1, vinit2-2 and vinit2-3), a third reset power line vinit3 and a driving power line VDD (including VDD-1 and VDD-2). The other types of first signal lines 3 are all transparent. The first transparent signal line is located in the first transparent wiring layer k, and the first reset signal line Preset, the second reset signal line Preset_H, the first gate signal line Gate_N, the second gate signal line Gate_P, and the light-emitting control signal line EM are located in the first transparent wiring layer k, and the first reset power line vinit1 (including vinit1-1 and vinit1-2), the second reset power line vinit2 (including vinit2-1, vinit2-2 and vinit2-3), the third reset power line vinit3 and the driving power line VDD (including VDD-1 and VDD-2) are located in the second transparent wiring layer n.

[0390] In particular, the first pixel circuit 211 and the second pixel circuit 212 in the pixel circuit group 2 share a driving power line VDD-1. In order to reduce the resistance of the driving power line VDD-1, a metal line segment (the eighteenth source-drain pattern q2) is set in the second source-drain layer q, and the metal line segment (the eighteenth source-drain pattern q2) is connected in parallel to the driving power line VDD-1 located in the second transparent wiring layer n.

[0391] The second connection line L2 for connecting the first reset power lines vinit1-1 and vinit1-2 and the second pixel circuit 212 is located in the first source and drain layer h, and the third connection line L3 for connecting the third reset power line vinit3, the first pixel circuit 211 and the third pixel circuit 213 is located in the third gate layer e.

[0392] 2. Take as an example a solution in which the first gate signal line Gate_N, the second gate signal line Gate_P, the light emitting control signal line EM, the first reset signal line Preset, and the second reset signal line Preset_H are all metal signal lines, and the first signal lines 3 of other types are transparent signal lines:

[0393] In this case, the display panel may include an active layer a, a first gate insulating layer, a first gate layer b, a second gate insulating layer, a second gate layer c, a third gate insulating layer, an oxide layer d, a fourth gate insulating layer, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain layer h, a passivation layer i, a second transparent wiring layer n, a second flat layer p, a second source and drain layer q and a third flat layer r, which constitute the pixel circuit 21 and are stacked in sequence along the direction away from the base substrate 1.

[0394] It should be noted that the pixel circuit group 2 composed of the patterns of the various film layers introduced below includes a pixel circuit unit, which includes a first pixel circuit 211, a second pixel circuit 212 and a third pixel circuit 213 arranged from left to right. In the arrangement direction of the first pixel circuit 211, the second pixel circuit 212 and the third pixel circuit 213, the orientation of the first pixel circuit 211 is relative to the orientation of the second pixel circuit 212, and the orientation of the third pixel circuit 213 is the same as the orientation of the first pixel circuit 211, wherein the relative arrangement means that at least part of the pattern of the first pixel circuit 211 is symmetrically arranged with at least part of the pattern of the second pixel circuit 212.

[0395] Figure 45 is a partial schematic diagram of an active layer a in a display panel provided in an embodiment of the present application. Referring to Figure 45 , the active layer a can have a curved or bent shape. The active layer a includes active patterns (channel regions) and doping patterns (source and drain doping regions) for the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The active patterns and doping patterns for each of the transistors in the same pixel circuit 21 are integrated.

[0396] The first pixel circuit 211 includes active patterns (channel regions) and doping region patterns (source and drain doping regions) of a first transistor T1-1, a third transistor T3-1, a fourth transistor T4-1, a fifth transistor T5-1, a sixth transistor T6-1, a seventh transistor T7-1, and an eighth transistor T8-1.

[0397] The second pixel circuit 212 includes active patterns (channel regions) and doping region patterns (source and drain doping regions) of the first transistor T1-2, the third transistor T3-2, the fourth transistor T4-2, the fifth transistor T5-2, the sixth transistor T6-2, the seventh transistor T7-2, and the eighth transistor T8-2.

[0398] The third pixel circuit 213 includes active patterns (channel regions) and doping region patterns (source-drain doping regions) of the first transistor T1-3, the third transistor T3-3, the fourth transistor T4-3, the fifth transistor T5-3, the sixth transistor T6-3, the seventh transistor T7-3, and the eighth transistor T8-3.

[0399] It should be noted that the active layer a may include an integrally formed low-temperature polysilicon layer, and the source and drain regions may be made conductive by doping, etc., to achieve electrical connection between the various structures. In other words, the semiconductor layer of each transistor in each pixel circuit is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., a source and drain region) and an active pattern, with the active patterns of different transistors separated.

[0400] The active layer a can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0401] The display panel may further include a first gate insulating layer located on a side of the active layer a away from the base substrate 1 , for insulating the active layer a from a first gate layer b to be formed subsequently.

[0402] Figure 46 is a partial schematic diagram of a first gate layer b in a display panel provided in an embodiment of the present application, and Figure 47 is a partial schematic diagram of the superposition of an active layer a and a first gate layer b in a display panel provided in an embodiment of the present application. The first gate layer b is located on a side of the first gate insulating layer away from the base substrate 1. Referring to Figures 46 and 47, the first gate layer b may include:

[0403] A first reset signal line Preset and a second reset signal line Preset_H;

[0404] the second capacitor plate Cst2, the first gate pattern b1 of the first transistor T1, the third gate pattern b3 of the third transistor T3, the fourth gate pattern b4 of the fourth transistor T4, the fifth gate pattern b5 of the fifth transistor T5, the sixth gate pattern b6 of the sixth transistor T6, the seventh gate pattern b7 of the seventh thin-film transistor T7, and the eighth gate pattern b8 of the eighth transistor T8, wherein the third gate pattern b3 of the third transistor T3 and the second capacitor plate Cst2 can be considered to be an integral structure, the first reset signal line Preset and the first gate pattern b1 of the first transistor T1 can be an integral structure, the second reset signal line Preset_H, the seventh gate pattern b7 of the seventh thin-film transistor T7, and the eighth gate pattern b8 of the eighth transistor T8 can be an integral structure, and the fifth gate pattern b5 of the fifth transistor T5 and the sixth gate pattern b6 of the sixth transistor T6 can be an integral structure;

[0405] a ninth gate pattern b9 for connecting the gate of the fourth transistor T4 and a second gate signal line Gate_P located in the first source / drain layer h, which will be described later. The ninth gate pattern b9 and the fourth gate pattern b4 (including b4-1, b4-2, and b4-3 described below) of the fourth transistor T4 may form an integral structure. The second gate signal line Gate_P is located between two adjacent pixel circuit groups 2 in the same row. In a plurality of pixel circuit groups 2 located in the same row, the ninth gate pattern b9 in each pixel circuit group 2 connects the second gate signal line Gate_P located between two adjacent pixel circuit groups 2, thereby forming the second gate signal line Gate_P that runs through the plurality of pixel circuit groups 2 in the row.

[0406] The tenth gate pattern b10 is used to connect the fifth gate pattern b5 of the fifth transistor T5, the sixth gate pattern b6 of the sixth transistor T6 and the light-emitting control signal line EM located in the first source and drain layer h to be introduced later, wherein the tenth gate pattern b10, the fifth gate pattern b5 of the fifth transistor T5 (including the following b5-1, b5-2 and b5-3) and the sixth gate pattern b6 of the sixth transistor T6 (including the following b6-1, b6-2 and b6-3) can all be an integrated structure, and the light-emitting control signal line EM is located between two adjacent pixel circuit groups 2 in the same row. In the multiple pixel circuit groups 2 located in the same row, the tenth gate pattern b10 in each pixel circuit group 2 connects the light-emitting control signal line EM located between the two adjacent pixel circuit groups 2, thereby forming a light-emitting control signal line EM of the multiple pixel circuit groups 2 running through the row.

[0407] The first pixel circuit 211 includes a second capacitor plate Cst2-1, a first gate pattern b1-1 of the first transistor T1-1, a third gate pattern b3-1 of the third transistor T3-1, a fourth gate pattern b4-1 of the fourth transistor T4-1, a fifth gate pattern b5-1 of the fifth transistor T5-1, a sixth gate pattern b6-1 of the sixth transistor T6-1, a seventh gate pattern b7-1 of the seventh thin-film transistor T7-1, and an eighth gate pattern b8-1 of the eighth transistor T8-1. The third gate pattern b3-1 of the third transistor T3-1 and the second capacitor plate Cst2-1 can be considered to be an integrated structure.

[0408] The second pixel circuit 212 includes a second capacitor plate Cst2-2, a first gate pattern b1-2 of the first transistor T1-2, a third gate pattern b3-2 of the third transistor T3-2, a fourth gate pattern b4-2 of the fourth transistor T4-2, a fifth gate pattern b5-2 of the fifth transistor T5-2, a sixth gate pattern b6-2 of the sixth transistor T6-2, a seventh gate pattern b7-2 of the seventh thin-film transistor T7-2, and an eighth gate pattern b8-2 of the eighth transistor T8-2. The third gate pattern b3-2 of the third transistor T3-2 and the second capacitor plate Cst2-2 can be considered to be an integrated structure.

[0409] The third pixel circuit 213 includes a second capacitor plate Cst2-3, a first gate pattern b1-3 of the first transistor T1-3, a third gate pattern b3-3 of the third transistor T3-3, a fourth gate pattern b4-3 of the fourth transistor T4-3, a fifth gate pattern b5-3 of the fifth transistor T5-3, a sixth gate pattern b6-3 of the sixth transistor T6-3, a seventh gate pattern b7-3 of the seventh thin-film transistor T7-3, and an eighth gate pattern b8-3 of the eighth transistor T8-3. The third gate pattern b3-3 of the third transistor T3-3 and the second capacitor plate Cst2-3 can be considered to be an integrated structure.

[0410] It should be noted that the dotted rectangular boxes in Figure 47 show the overlapping parts of the first gate layer b and the active layer a. As the channel region of each transistor, the active layer a on both sides of each channel region is conductively connected through processes such as ion doping to serve as the first and second electrodes of each transistor. The source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiment of the present application, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode, so the first and second electrodes of all or part of the transistors in the embodiment of the present application can be interchangeable as needed.

[0411] The display panel may further include a second gate insulating layer located on a side of the first gate layer b away from the base substrate 1 , for insulating the first gate layer b from a subsequently formed second gate layer c.

[0412] Figure 48 is a partial schematic diagram of a second gate layer c in a display panel provided in an embodiment of the present application. Figure 49 is a partial schematic diagram of the superimposed active layer a, first gate layer b, and second gate layer c in a display panel provided in an embodiment of the present application. The second gate layer c is located on the side of the second gate insulating layer away from the base substrate 1. Referring to Figures 48 and 49, the second gate layer c may include a first capacitor plate Cst1 and a bottom gate pattern c2 located in the second gate layer c of the second transistor T2.

[0413] The first pixel circuit 211 includes a first capacitor plate Cst1-1 and a bottom gate pattern c2-1 located on the second gate layer c of the second transistor T2-1. The first capacitor plate Cst1-1 located on the second gate layer c at least partially overlaps with the second capacitor plate Cst2-1 located on the first gate layer b to form a storage capacitor Cst-1. The bottom gate pattern c2-1 also serves as a portion of the first gate signal line Gate_N located on the second gate layer c.

[0414] The second pixel circuit 212 includes a first capacitor plate Cst1-2 and a bottom gate pattern c2-2 located in the second gate layer c of the second transistor T2-2. The first capacitor plate Cst1-2 located in the second gate layer c at least partially overlaps with the second capacitor plate Cst2-2 located in the first gate layer b to form a storage capacitor Cst-2. The bottom gate pattern c2-2 is also used for a portion of the first gate signal line Gate_N located in the second gate layer c.

[0415] The third pixel circuit 213 includes a first capacitor plate Cst1-3 and a bottom gate pattern c2-3 located in the second gate layer c of the second transistor T2-3. The first capacitor plate Cst1-3 located in the second gate layer c at least partially overlaps with the second capacitor plate Cst2-3 located in the first gate layer b to form a storage capacitor Cst-3. The bottom gate pattern c2-3 also serves as a portion of the first gate signal line Gate_N located in the second gate layer c.

[0416] In addition, a third gate insulating layer may be formed on the second gate layer c to insulate the second gate layer c from the subsequently formed oxide layer d.

[0417] Figure 50 is a partial schematic diagram of an oxide layer d in a display panel provided in an embodiment of the present application. Figure 51 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, and an oxide layer d in a display panel provided in an embodiment of the present application. Oxide layer d is located on a side of the third gate insulating layer that is distal from the base substrate 1. Referring to Figures 50 and 51 , oxide layer d may include an oxide pattern for forming the second transistor T2-1 of the first pixel circuit 211, an oxide pattern for forming the second transistor T2-2 of the second pixel circuit 212, and an oxide pattern for forming the second transistor T2-3 of the third pixel circuit 213.

[0418] In addition, a fourth gate insulating layer may be formed on the oxide layer d to insulate the oxide layer d from a third gate layer e to be formed subsequently.

[0419] Figure 52 is a partial schematic diagram of a third gate layer e in a display panel provided in an embodiment of the present application. Figure 53 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, and a third gate layer e in a display panel provided in an embodiment of the present application. The third gate layer e is located on a side of the fourth gate insulating layer away from the base substrate 1. Referring to Figures 52 and 53, the third gate layer e may include:

[0420] A third connecting line L3;

[0421] a top gate pattern e2 of the second transistor T2, wherein the top gate pattern e2 of the second transistor T2 includes the top gate pattern e2-1 of the second transistor T2-1 in the first pixel circuit 211, the top gate pattern e2-2 of the second transistor T2-2 in the second pixel circuit 212, and the top gate pattern e2-3 of the second transistor T2-3 in the third pixel circuit 213, wherein the top gate pattern e2-1 of the second transistor T2-1 at least partially overlaps with the bottom gate pattern c2-1 of the second transistor T2-1 located in the second gate layer c, Thus, the second transistor T2-1 in the first pixel circuit 211 is formed. The top gate pattern e2-2 of the second transistor T2-2 at least partially overlaps with the bottom gate pattern c2-2 of the second transistor T2-2 located in the second gate layer c, thereby forming the second transistor T2-2 in the second pixel circuit 212. The top gate pattern e2-3 of the second transistor T2-3 at least partially overlaps with the bottom gate pattern c2-3 of the second transistor T2-3 located in the second gate layer c, thereby forming the second transistor T2-3 in the second pixel circuit 213.

[0422] The eleventh gate pattern e1 is used to connect the gate of the second transistor T2 and the first gate signal line Gate_N located in the first source and drain layer h described later, wherein the eleventh gate pattern e1 and the top gate pattern e2-1, the top gate pattern e2-2 and the top gate pattern e2-3 can be an integrated structure, and the first gate signal line Gate_N is located between two adjacent pixel circuit groups 2 in the same row. In the multiple pixel circuit groups 2 located in the same row, the eleventh gate pattern e1 in each pixel circuit group 2 connects the first gate signal line Gate_N located between the two adjacent pixel circuit groups 2, thereby forming the first gate signal line Gate_N that runs through the multiple pixel circuit groups 2 in the row.

[0423] In addition, two interlayer dielectric layers, namely a first interlayer dielectric layer f and a second interlayer dielectric layer g, may be formed on the third gate layer e to insulate the third gate layer e from the subsequently formed first source and drain layer h.

[0424] Figure 54 is a partial schematic diagram of the first interlayer dielectric layer f in a display panel provided in an embodiment of the present application, and Figure 55 is a partial superposition schematic diagram of the active layer a, the first gate layer b, the second gate layer c, the oxide layer d, the third gate layer e and the first interlayer dielectric layer f in a display panel provided in an embodiment of the present application.

[0425] Figure 56 is a partial schematic diagram of the second interlayer dielectric layer g in a display panel provided in an embodiment of the present application, and Figure 57 is a partial superposition schematic diagram of the active layer a, the first gate layer b, the second gate layer c, the oxide layer d, the third gate layer e, the first interlayer dielectric layer f and the second interlayer dielectric layer g in a display panel provided in an embodiment of the present application.

[0426] In order to facilitate the illustration of the seventh vias f2 of the first interlayer dielectric layer f and the eighth vias g2 in the second interlayer dielectric layer g, Figures 54 to 57 use filling patterns to represent the seventh vias f2 and the eighth vias g2, and other areas where no filling patterns are drawn are used to represent areas where the first interlayer dielectric layer f and the second interlayer dielectric layer g have solid materials.

[0427] It should be noted that each via hole opened in the interlayer dielectric layer is used to connect the subsequently formed film layer with the film layer on the side of the interlayer dielectric layer close to the base substrate 1, that is, each via hole is a via hole for connecting the film layers.

[0428] Figure 58 is a partial schematic diagram of a first source and drain electrode layer h in a display panel provided in an embodiment of the present application. Figure 59 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, and a first source and drain electrode layer h in a display panel provided in an embodiment of the present application. Referring to Figures 58 and 59, the first source and drain electrode layer h may include:

[0429] a second connection line L2, a first gate signal line Gate_N, a second gate signal line Gate_P, and a light emitting control signal line EM;

[0430] The first pixel circuit 211 includes a nineteenth source-drain pattern h19-1, a twentieth source-drain pattern h20-1, a twenty-first source-drain pattern h21-1, a twenty-second source-drain pattern h22-1, a twenty-third source-drain pattern h23-1, a twenty-fourth source-drain pattern h24-1, a twenty-fifth source-drain pattern h25-1, a twenty-sixth source-drain pattern h26-1, a twenty-seventh source-drain pattern h27-1, a twenty-eighth source-drain pattern h28-1, a twenty-ninth source-drain pattern h29-1, and a thirtieth source-drain pattern h30-1;

[0431] The second pixel circuit 212 includes a nineteenth source-drain pattern h19-2, a twentieth source-drain pattern h20-2, a twenty-second source-drain pattern h22-2, a twenty-third source-drain pattern h23-2, a twenty-fifth source-drain pattern h25-2, a twenty-seventh source-drain pattern h27-1, a twenty-eighth source-drain pattern h28-2, a twenty-ninth source-drain pattern h29-2, and a thirtieth source-drain pattern h30-2;

[0432] In addition, the third pixel circuit 213 includes a nineteenth source-drain pattern h19-3, a twentieth source-drain pattern h20-3, a twenty-first source-drain pattern h21-2, a twenty-second source-drain pattern h22-3, a twenty-third source-drain pattern h23-3, a twenty-fourth source-drain pattern h24-2, a twenty-fifth source-drain pattern h25-3, a twenty-sixth source-drain pattern h26-2, a twenty-seventh source-drain pattern h27-2, a twenty-eighth source-drain pattern h28-3, a twenty-ninth source-drain pattern h29-3 and a thirtieth source-drain pattern h30-3.

[0433] For the first pixel circuit 211:

[0434] A nineteenth source / drain pattern h19-1 is used to connect the first electrode of the first transistor T1-1, the second connection line L2, and the first reset power line vinit1-1 located in the second transparent wiring layer n, which will be described later. The nineteenth source / drain pattern h19-1 and the second connection line L2 may be integrally formed.

[0435] a twentieth source-drain pattern h20-1, for connecting the second electrode of the first transistor T1-1, the first electrode of the second transistor T2-1, the first electrode of the third transistor T3-1, and the first electrode of the sixth transistor T6-1;

[0436] a twenty-first source / drain pattern h21-1, configured to connect a bottom gate pattern c2-1 located in the second gate layer c of the second transistor T2-1, a top gate pattern e2-1 located in the third gate layer e of the second transistor T2-1, and the first gate signal line Gate_N; wherein the twenty-first source / drain pattern h21-1 and the first gate signal line Gate_N may be integrally formed;

[0437] A twenty-second source-drain pattern h22-1 is used to connect the second electrode of the second transistor T2-1, the second capacitor plate Cst2-1 of the storage capacitor Cst-1 located on the first gate layer b, and the third gate pattern b3-1 of the third transistor T3-1 located on the first gate layer b;

[0438] a twenty-third source-drain pattern h23-1, for connecting the second electrode of the third transistor T3-1, the second electrode of the fourth transistor T4-1, the first electrode of the fifth transistor T5-1, and the second electrode of the eighth transistor T8-1;

[0439] a twenty-fourth source-drain pattern h24-1, used to connect the fourth gate pattern b4-1 of the fourth transistor T4-1 located on the first gate layer b and the second gate signal line Gate_P, wherein the twenty-fourth source-drain pattern h24-1 and the second gate signal line Gate_P may be an integral structure;

[0440] A twenty-fifth source-drain pattern h25-1 is used to connect the first electrode of the fourth transistor T4-1 and the data signal line Data-1 located in the second transparent wiring layer n to be described later;

[0441] a twenty-sixth source-drain pattern h26-1, configured to connect the fifth gate pattern b5-1 located on the second gate layer b of the fifth transistor T5-1, the sixth gate pattern b6-1 located on the first gate layer b of the sixth transistor T6-1, and the light-emitting control signal EM; wherein the twenty-sixth source-drain pattern h26-1 and the light-emitting control signal EM may be integrally formed;

[0442] A twenty-seventh source-drain pattern h27-1 is used to connect the second electrode of the fifth transistor T5-1, the first capacitor plate Cst1-1 of the storage capacitor Cst-1 located on the second gate layer c, and a driving power line VDD-1 located on the second transparent wiring layer n described later;

[0443] A twenty-eighth source-drain pattern h28-1 is used to connect the second electrode of the sixth transistor T6-1, the second electrode of the seventh transistor T7-1, and a twentieth transparent wiring pattern n4 located in the second transparent wiring layer n to be described later;

[0444] A twenty-ninth source-drain pattern h29-1 is used to connect the first electrode of the eighth transistor T8-1 and the third connection line L3 located on the third gate layer e;

[0445] The thirtieth source-drain pattern h30-1 is used to connect the first electrode of the seventh transistor T7-1 and the two second reset power lines vinit2-1 located in the second transparent wiring layer n to be introduced later. The second reset power line vinit2-1 is located between two adjacent pixel circuit groups 2 in the same column. In the multiple pixel circuit groups 2 located in the same column, the thirtieth source-drain pattern h30-1 in each pixel circuit group 2 can connect the second reset power line vinit2-1 located between two adjacent pixel circuit groups 2, thereby forming a second reset power line vinit2-1 of multiple pixel circuit groups 2 running through the column.

[0446] For the second pixel circuit 212:

[0447] A nineteenth source-drain pattern h19-2 is used to connect the first electrode of the first transistor T1-2 and the second connection line L2. The nineteenth source-drain pattern h19-1 and the second connection line L2 can be an integral structure;

[0448] a twentieth source-drain pattern h20-2, for connecting the second electrode of the first transistor T1-2, the first electrode of the second transistor T2-2, the first electrode of the third transistor T3-2, and the first electrode of the sixth transistor T6-2;

[0449] A twenty-second source-drain pattern h22-2 is used to connect the second electrode of the second transistor T2-2, the second capacitor plate Cst2-2 of the storage capacitor Cst-2 located on the first gate layer b, and the third gate pattern b3-2 of the third transistor T3-2 located on the first gate layer b;

[0450] A twenty-third source-drain pattern h23-2 is used to connect the second electrode of the third transistor T3-2, the second electrode of the fourth transistor T4-2, the first electrode of the fifth transistor T5-2, and the second electrode of the eighth transistor T8-2;

[0451] A twenty-fifth source-drain pattern h25-2 is used to connect the first electrode of the fourth transistor T4-2 and the data signal line Data-2 located in the second transparent wiring layer n to be described later;

[0452] A twenty-seventh source-drain pattern h27-1 is used to connect the second electrode of the fifth transistor T5-2, the first capacitor plate Cst1-2 of the storage capacitor Cst-2 located on the second gate layer c, and a driving power line VDD-1 located on the second transparent wiring layer n described later;

[0453] A twenty-eighth source-drain pattern h28-2 is used to connect the second electrode of the sixth transistor T6-2, the second electrode of the seventh transistor T7-2, and a twenty-first transparent wiring pattern n5 located in the second transparent wiring layer n to be described later;

[0454] A twenty-ninth source-drain pattern h29-2 is used to connect the first electrode of the eighth transistor T8-2 and the third connection line L3 located on the third gate layer e;

[0455] The thirtieth source-drain pattern h30-2 is used to connect the first electrode of the seventh transistor T7-2 and the two second reset power lines vinit2-2 located in the second transparent wiring layer n to be introduced later. The second reset power line vinit2-2 is located between two adjacent pixel circuit groups 2 in the same column. In the multiple pixel circuit groups 2 located in the same column, the thirtieth source-drain pattern h30-2 in each pixel circuit group 2 can connect the second reset power line vinit2-2 located between two adjacent pixel circuit groups 2, thereby forming a second reset power line vinit2-2 of multiple pixel circuit groups 2 running through the column.

[0456] For the third pixel circuit 213:

[0457] The nineteenth source-drain pattern h19-3 is used to connect the first electrode of the first transistor T1-3, the second connection line L2, and the first reset power line vinit1-2 located on the second transparent wiring layer n described later. The nineteenth source-drain pattern h19-3 and the second connection line L2 can be an integral structure;

[0458] a twentieth source-drain pattern h20-3, used to connect the second electrode of the first transistor T1-3, the first electrode of the second transistor T2-3, the first electrode of the third transistor T3-3, and the first electrode of the sixth transistor T6-3;

[0459] a twenty-first source / drain pattern h21-2, configured to connect a bottom gate pattern c2-3 located in the second gate layer c of the second transistor T2-3, a top gate pattern e2-3 located in the third gate layer e of the second transistor T2-3, and the first gate signal line Gate_N; wherein the twenty-first source / drain pattern h21-1 and the first gate signal line Gate_N may be integrally formed;

[0460] A twenty-second source-drain pattern h22-3 is used to connect the second electrode of the second transistor T2-3, the second capacitor plate Cst2-3 of the storage capacitor Cst-1 located on the first gate layer b, and the third gate pattern b3-3 of the third transistor T3-3 located on the first gate layer b;

[0461] A twenty-third source-drain pattern h23-3 is used to connect the second electrode of the third transistor T3-3, the second electrode of the fourth transistor T4-3, the first electrode of the fifth transistor T5-3, and the second electrode of the eighth transistor T8-3;

[0462] a twenty-fourth source-drain pattern h24-2, used to connect the fourth gate pattern b4-3 of the fourth transistor T4-3 located on the first gate layer b and the second gate signal line Gate_P, wherein the twenty-fourth source-drain pattern h24-2 and the second gate signal line Gate_P may be an integral structure;

[0463] A twenty-fifth source-drain pattern h25-3 is used to connect the first electrode of the fourth transistor T4-3 and the data signal line Data-3 located in the second transparent wiring layer n to be described later;

[0464] a twenty-sixth source-drain pattern h26-2, configured to connect the fifth gate pattern b5-3 of the fifth transistor T5-3 located on the second gate layer b, the sixth gate pattern b6-3 of the sixth transistor T6-3 located on the first gate layer b, and the emission control signal EM; wherein the twenty-sixth source-drain pattern h26-2 and the emission control signal EM may be integrally formed;

[0465] A twenty-seventh source-drain pattern h27-2 is used to connect the second electrode of the fifth transistor T5-3, the first capacitor plate Cst1-3 of the storage capacitor Cst-3 located on the second gate layer c, and a driving power line VDD-2 located on the second transparent wiring layer n described later;

[0466] A twenty-eighth source-drain pattern h28-3 is used to connect the second electrode of the sixth transistor T6-3, the second electrode of the seventh transistor T7-3, and a twenty-second transparent wiring pattern n6 located in the second transparent wiring layer n to be described later;

[0467] A twenty-ninth source-drain pattern h29-3 is used to connect the first electrode of the eighth transistor T8-3 and the third connection line L3 located on the third gate layer e;

[0468] The thirtieth source-drain pattern h30-3 is used to connect the first electrode of the seventh transistor T7-3 and the two second reset power lines vinit2-3 located in the second transparent wiring layer n to be introduced later. The second reset power line vinit2-3 is located between two adjacent pixel circuit groups 2 in the same column. In the multiple pixel circuit groups 2 located in the same column, the thirtieth source-drain pattern h30-3 in each pixel circuit group 2 can connect the second reset power line vinit2-3 located between two adjacent pixel circuit groups 2, thereby forming a second reset power line vinit2-3 of multiple pixel circuit groups 2 running through the column.

[0469] In addition, a passivation layer i may be formed on the first source and drain electrode layer h, so as to insulate the first source and drain electrode layer h from a second transparent wiring layer n to be formed subsequently.

[0470] Figure 60 is a partial schematic diagram of a passivation layer i in a display panel provided in an embodiment of the present application. Figure 61 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, and the passivation layer i in a display panel provided in an embodiment of the present application. The passivation layer i is located on the side of the first source and drain electrode layer h that is away from the base substrate 1.

[0471] To facilitate illustration of each ninth via hole i2 in the passivation layer, a fill pattern is used to represent the via hole in Figures 60 and 61. Other areas without fill patterns are used to represent areas of the passivation layer i containing solid material. It should be noted that each ninth via hole i2 in the passivation layer i is used to connect a subsequently formed film layer to the film layer on the side of the passivation layer i closer to the base substrate 1. In other words, each ninth via hole i2 is a via hole for connecting film layers.

[0472] Figure 62 is a partial schematic diagram of a second transparent wiring layer n in a display panel provided in an embodiment of the present application. Figure 63 is a partial superimposed schematic diagram of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, a passivation layer i, and a second transparent wiring layer n in a display panel provided in an embodiment of the present application. The second transparent wiring layer n is located on the side of the passivation layer i away from the base substrate 1. Referring to Figures 62 and 63, the second transparent wiring layer n includes:

[0473] A first reset power line vinit1 includes vinit1-1 and vinit1-2, vinit1-1 and vinit1-2 are connected via a second connection line L2 of the first source-drain layer h, vinit1-1 is connected to the first pixel circuit 211, vinit1-2 is connected to the third pixel circuit 213, and the second connection line L2 is connected to the second pixel circuit 212;

[0474] A second reset power line vinit2 includes vinit2-1, vinit2-2, and vinit2-3, vinit2-1 is connected to the first pixel circuit 211, vinit2-2 is connected to the second pixel circuit 212, and vinit2-3 is connected to the third pixel circuit 213;

[0475] A third reset power line vinit3 is connected to the second pixel circuit 212 and the third connection line L3, and the third connection line L3 is connected to the first pixel circuit 211 and the third pixel circuit 213;

[0476] A driving power line VDD includes VDD-1 and VDD-2, wherein VDD-1 is connected to the first pixel circuit 211 and the second pixel circuit 212, and VDD-2 is connected to the third pixel circuit 213;

[0477] Data signal lines Data, including Data-1, Data-2, and Data-3, where Data-1 is connected to the first pixel circuit 211, Data-2 is connected to the second pixel circuit 212, and Data-3 is connected to the third pixel circuit 213;

[0478] a twentieth transparent wiring pattern n4, used for connecting the twenty-eighth source-drain pattern h28-1 located on the first source-drain layer h and the thirty-first source-drain pattern q5 located on the second source-drain layer q to be described later;

[0479] A twenty-first transparent wiring pattern n5 is used to connect the twenty-eighth source-drain pattern h28-2 located on the first source-drain layer h and the thirty-third source-drain pattern q7 located on the second source-drain layer q to be described later;

[0480] The twenty-second transparent wiring pattern n6 is used to connect the twenty-eighth source-drain pattern h28-3 located on the first source-drain layer h and the thirty-fourth source-drain pattern q8 located on the second source-drain layer q to be described later.

[0481] It can be understood that the multiple repeated first signal lines 3 of the same type shown in Figures 62 and 63, including the first reset power line vinit1 (including vinit1-1 and vinit1-2), the second reset power line vinit2 (including vinit2-1, vinit2-2 and vinit2-3), the third reset power line vinit3, the drive power line VDD (including VDD-1 and VDD-2), and the data signal line Data (including Data-1, Data-2 and Data-3), are respectively connected to different pixel circuit groups 2.

[0482] In addition, a second flat layer p may be formed on the second transparent wiring layer n to insulate the second transparent wiring layer n from a second source and drain electrode layer q to be formed subsequently.

[0483] Figure 64 is a partial schematic diagram of a second planar layer p in a display panel provided in an embodiment of the present application. Figure 65 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, a passivation layer i, a second transparent wiring layer n, and a second planar layer p in a display panel provided in an embodiment of the present application. The second planar layer p is located on a side of the second transparent wiring layer n away from the base substrate 1.

[0484] To facilitate illustration of the tenth via holes p2 in the second planar layer p, Figures 64 and 65 use a fill pattern to represent the tenth via holes p2. Other areas without fill patterns represent areas of the second planar layer p containing solid material. It should be noted that the tenth via holes p2 in the second planar layer p are used to connect a subsequently formed membrane layer to the membrane layer on the side of the second planar layer p closer to the base substrate 1. In other words, the tenth via holes p2 are via holes for connecting membrane layers.

[0485] Figure 66 is a partial schematic diagram of a second source-drain electrode layer q in a display panel provided in an embodiment of the present application. Figure 67 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source-drain electrode layer h, a passivation layer i, a second transparent wiring layer n, a second planar layer p, and a second source-drain electrode layer q in a display panel provided in an embodiment of the present application. The second source-drain electrode layer q is located on a side of the second planar layer p away from the base substrate 1. Referring to Figures 66 and 67, the second source-drain electrode layer q may include:

[0486] A thirty-first source-drain pattern q5 is used to connect the twentieth transparent wiring pattern n4 located on the second transparent wiring layer n and the anode 51 of the first light-emitting element located on the anode layer to be described later;

[0487] The thirty-second source / drain pattern q6 is configured to be connected to the driving power signal line VDD-1 located on the second transparent wiring layer n to achieve parallel connection of a section of the line. This reduces the resistance of the driving power signal line VDD-1 by connecting a section of the metal signal line in parallel to the transparent signal line of the driving power signal line VDD-1, thereby reducing the occurrence of defective vias in the vertical direction of the first display area 11 and improving display uniformity.

[0488] a thirty-third source / drain pattern q7, configured to connect the twenty-first transparent trace pattern n5 located in the second transparent trace layer n and the first connection line L1 located in the anode layer, so as to achieve connection between the thirty-third source / drain pattern q7 and the anode 52 of the second light-emitting element located in the anode layer, which will be described later, through the first connection line L1;

[0489] The thirty-fourth source-drain pattern q8 is used to connect the twenty-second transparent wiring pattern n6 located in the second transparent wiring layer n and the anode 53 of the third light-emitting element located in the anode layer to be described later.

[0490] In addition, a third planar layer r may be formed on the second source-drain electrode layer q to insulate the second source-drain electrode layer q from the anode layer of the light-emitting element.

[0491] Figure 68 is a partial schematic diagram of a third planar layer r in a display panel provided in an embodiment of the present application. Figure 69 is a partial schematic diagram of the superposition of the active layer a, first gate layer b, second gate layer c, oxide layer d, third gate layer e, first interlayer dielectric layer f, second interlayer dielectric layer g, first source and drain electrode layer h, passivation layer i, second transparent wiring layer n, second planar layer p, second source and drain electrode layer q, and third planar layer r in a display panel provided in an embodiment of the present application. The third planar layer r is located on the side of the second source and drain electrode layer q that is away from the base substrate 1.

[0492] To facilitate illustration of the eleventh via holes r2 in the third planar layer r, FIG68 and FIG69 use a fill pattern to represent the eleventh via holes r2. Other areas without fill patterns represent areas of the third planar layer r containing solid material. It should be noted that the eleventh via holes r2 in the third planar layer r are used to connect a subsequently formed film layer with the film layer on the side of the third planar layer r closer to the base substrate 1. In other words, the eleventh via holes r2 are via holes for connecting film layers.

[0493] Figure 70 is a partial schematic diagram of an anode layer in a display panel provided in an embodiment of the present application. Figure 71 is a partial schematic diagram of the superposition of an active layer a, a first gate layer b, a second gate layer c, an oxide layer d, a third gate layer e, a first interlayer dielectric layer f, a second interlayer dielectric layer g, a first source and drain electrode layer h, a passivation layer i, a second transparent wiring layer n, a second planar layer p, a second source and drain electrode layer q, a third planar layer r, and an anode layer in a display panel provided in an embodiment of the present application. The anode layer is located on the side of the third planar layer r away from the base substrate 1.

[0494] Referring to Figures 70 and 71, the anode layer may include an anode 51 of a first light-emitting element, an anode 52 of a second light-emitting element, an anode 53 of a third light-emitting element and a first connecting line L1, the anode 51 of the first light-emitting element is connected to the thirty-first source-drain pattern q5 located in the second source-drain layer q, both ends of the first connecting line L1 are connected to the anodes 52 of the two second light-emitting elements, and the first connecting line L1 is connected to the thirty-third source-drain pattern q7 located in the second source-drain layer q, and the anode 53 of the third light-emitting element is connected to the thirty-fourth source-drain pattern q8 located in the second source-drain layer q.

[0495] In conjunction with Figures 44 to 71, some types of first signal lines 3 include a first reset signal line Preset, a second reset signal line Preset_H, a first gate signal line Gate_N, a second gate signal line Gate_P, and a light-emitting control signal line EM. These types of first signal lines are 3-bit metal signal lines, that is, the first reset signal line Preset and the second reset signal line Preset_H are located in the first gate layer b, the first gate signal line Gate_N, the second gate signal line Gate_P and the light-emitting control signal line EM are located in the first source and drain layer h. In particular, multiple first gate signal lines Gate_N in the same row need to be connected to the eleventh gate pattern e1 located in the third gate layer e of the multiple pixel circuit groups 2 in the row, multiple second gate signal lines Gate_P in the same row need to be connected to the ninth gate pattern b9 located in the first gate layer b of the multiple pixel circuit groups 2 in the row, and multiple light-emitting control signal lines EM in the same row need to be connected to the tenth gate pattern b10 located in the first gate layer b of the multiple pixel circuit groups 2 in the row.

[0496] The other types of first signal lines 3 include the first reset power line vinit1 (including vinit1-1 and vinit1-2), the second reset power line vinit2 (including vinit2-1, vinit2-2 and vinit2-3), the third reset power line vinit3, the drive power line VDD (including VDD-1 and VDD-2) and the data signal line Data (including Data-1, Data-2 and Data-3). The other types of first signal lines 3 are all transparent signal lines, that is, the first reset power line vinit1 (including vinit1-1 and vinit1-2), the second reset power line vinit2 (including vinit2-1, vinit2-2 and vinit2-3), the third reset power line vinit3, the drive power line VDD (including VDD-1 and VDD-2) and the data signal line Data (including Data-1, Data-2 and Data-3) are located in the second transparent routing layer n.

[0497] In particular, the first pixel circuit 211 and the second pixel circuit 212 in the pixel circuit group 2 share a driving power line VDD-1. In order to reduce the resistance of the driving power line VDD-1, a metal line segment (the thirty-second source-drain pattern q4) is set in the second source-drain layer q, and the metal line segment (the thirty-second source-drain pattern q4) is connected in parallel to the driving power line VDD-1 located in the second transparent wiring layer n.

[0498] The second connection line L2 for connecting the first reset power lines vinit1-1 and vinit1-2 and the second pixel circuit 212 is located in the first source and drain layer h, and the third connection line L3 for connecting the third reset power line vinit3, the first pixel circuit 211 and the third pixel circuit 213 is located in the third gate layer e.

[0499] To sum up, the embodiments of the present application provide a display panel, in which, among multiple types of first signal lines 3, some types of first signal lines 3 that have a greater impact on display brightness are set to include metal signal lines, and the resistance of the first signal lines 3 is reduced by the metal signal lines. In this way, the difference between the resistance of the first signal lines 3 in the first display area 11 and the resistance of the signal lines in the display areas other than the first display area 11 in the display panel can be reduced, thereby reducing the poor via phenomenon around the first display area 11 and improving the display uniformity of the display panel.

[0500] In the embodiment of the present application, referring to FIG. 3 and FIG. 5 , the display panel includes a base substrate 1 , a plurality of pixel circuit groups 2 , a plurality of first signal lines 3 and a plurality of light-emitting units.

[0501] The base substrate 1 has a first display area 11, which can be used to accommodate an optical sensor. Alternatively, the optical sensor can be a front-facing camera, and the first display area 11 can be a full display with camera (FDC) area. The base substrate 1 can also have a second display area 12, adjacent to the first display area 11. Alternatively, the second display area 12 can be the remaining display area of ​​the base substrate 1 excluding the first display area 11.

[0502] The first display area 11 may include multiple pixel circuit areas 111 and light-transmitting areas 112 . Each pixel circuit area 111 may be used to set a pixel circuit group 2 . The light-transmitting area 112 is an area where no pixel circuit group 2 is set, and its transmittance is higher than that of the pixel circuit area 111 .

[0503] Multiple pixel circuit groups 2 are located in multiple pixel circuit areas 111 of the first display area 11. As shown in Figure 2, each pixel circuit group 2 includes a first number of pixel circuits 21 arranged along a first direction, and the minimum distance between adjacent pixel circuit groups 2 is greater than the minimum distance between adjacent pixel circuits 21 in the pixel circuit group 2. In this way, compared with the arrangement of multiple pixel circuits uniformly arranged in the second display area 12, the multiple pixel circuits 21 are gathered together in the first display area 11 to form a pixel circuit group 2, which can reduce the area occupied by these multiple pixel circuits 21, thereby increasing the area of ​​the light-transmitting area 112 in the first display area 11, and thereby improving the light transmittance of the first display area 11.

[0504] Optionally, the first direction may be a row direction of the pixel circuit arrangement, or other directions, which is not limited in the embodiment of the present application.

[0505] Multiple first signal lines 3 are connected to the pixel circuits 21 located in the first display area 11 for transmitting signals thereto. The first signal lines 3 extend along a second direction, where the second direction intersects the first direction. The angle formed between the second direction and the first direction can be any angle, for example, an acute angle or a right angle, etc., which is not limited in this embodiment of the present application.

[0506] At least one pixel circuit group 2 among the plurality of pixel circuit groups 2 in the first display area 11 is connected to a second number of first signal lines 3. The second number of first signal lines 3 connected to the same pixel circuit group 2 can be electrically connected to one another via connecting wires, i.e., the connecting wires connect the second number of first signal lines 3 in series. The second number is no greater than the first number, i.e., the number of first signal lines connected to a pixel circuit group 2 is no greater than the number of pixel circuits 21 included in the pixel circuit group 2.

[0507] For each pixel circuit group 2 in at least one pixel circuit group 2, each first signal line 3 in the second number of first signal lines 3 is respectively connected to at least one pixel circuit 21 in the pixel circuit group 2, and the connecting line is connected to the pixel circuit 21 in the pixel circuit group that is connected to the first signal line 3.

[0508] At least part of the line segments of the first signal line 3 are located in the light-transmitting area 112, and the connecting line is located in the pixel circuit area 111. Therefore, by adopting the present application, the number of first signal lines 3 that need to be connected to each pixel circuit group 2 is reduced, and the blocking area of ​​the first signal line 3 on the light-transmitting area 112 is reduced, thereby improving the light transmittance of the light-transmitting area 112, and further improving the performance of the display panel.

[0509] Multiple light-emitting units are located in the first display area 11, and multiple pixel circuit groups 2 are configured to drive the multiple light-emitting units to emit light. The orthographic projections of at least some of the multiple light-emitting units on the base substrate 1 overlap with the orthographic projections of at least some line segments of the first signal lines 3 on the base substrate 1. In this way, the first signal lines 3, which partially block the light-transmitting area 112, are positioned below the light-emitting units that are also located in and partially block the light-transmitting area 112. This reduces the area of ​​the light-transmitting area 112 blocked by the first signal lines 3, thereby increasing the light transmittance of the light-transmitting area 112 and thereby improving the performance of the display panel.

[0510] Optionally, referring to Figure 5, in an embodiment of the present application, the multiple pixel circuit groups 2 include multiple first pixel circuit groups 2A and multiple second pixel circuit groups 2B, the multiple first pixel circuit groups 2A are arranged in multiple rows, and the multiple second pixel circuit groups 2B are arranged in multiple rows, and a row of second pixel circuit groups 2B is arranged between any two adjacent rows of first pixel circuit groups 2A, that is: in two adjacent rows of pixel circuit groups 2 in the first display area 11, one row of pixel circuit groups 2 is the first pixel circuit group 2A, and the other row of pixel circuit groups 2 is the second pixel circuit group 2B, and the multiple rows of first pixel circuit groups 2A and the multiple rows of second pixel circuit groups 2B are arranged alternately.

[0511] Moreover, in any row of first pixel circuit groups 2A and a row of second pixel circuit groups 2B adjacent to the first pixel circuit group 2A, the position of the spacing region between any two adjacent first pixel circuit groups 2A corresponds to the position of one second pixel circuit group 2B.

[0512] Each pixel circuit group 2 in the first pixel circuit group 2A and the second pixel circuit group 2B has the following structure:

[0513] Each pixel circuit group 2 includes at least one pixel circuit unit, and the pixel circuit unit includes a first pixel circuit 211, a second pixel circuit 212, and a third pixel circuit 213. That is, each pixel circuit group 2 may include one or more pixel circuit units. For example, the pixel circuit group 2 shown in FIG5 includes one pixel circuit unit, and the pixel circuit unit includes three pixel circuits (a first pixel circuit 211, a second pixel circuit 212, and a third pixel circuit 213). Alternatively, the pixel circuit group may include six pixel circuits, nine pixel circuits, and so on, which is not limited in the embodiments of the present application.

[0514] In each pixel circuit unit, the second pixel circuit 212 is located between the first pixel circuit 211 and the third pixel circuit 213 , and the first pixel circuit 211 , the second pixel circuit 212 and the third pixel circuit 213 are arranged along the first direction.

[0515] FIG6 is a schematic diagram of the structure of a pixel circuit group 2 provided in an embodiment of the present application. Referring to FIG6 , the pixel circuit group 2 includes a pixel circuit unit, namely, a first pixel circuit 211 , a second pixel circuit 212 and a third pixel circuit 213 .

[0516] Each light emitting unit may include a first light emitting element, two second light emitting elements and a third light emitting element, and at least one light emitting unit corresponds to a pixel circuit unit.

[0517] The first light-emitting element is connected to the first pixel circuit 211, that is, the anode of the first light-emitting element is connected to the first pixel circuit 211, and the first pixel circuit 211 can drive the first light-emitting element to emit light. In the embodiment of the present application, the orthographic projection of the anode 51 of the first light-emitting element on the base substrate 1 at least partially overlaps with the orthographic projection of the pixel circuit group 2 where the first pixel circuit 211 is located on the base substrate 1.

[0518] The two second light-emitting elements are both connected to the second pixel circuit 212 , that is, the anodes 52 of the two second light-emitting elements are connected to the second pixel circuit 212 .

[0519] Furthermore, the orthographic projections of the anodes 52 of the two second light-emitting elements on the substrate 1 are located on opposite sides of the orthographic projection of the second pixel circuit 212 on the substrate 1. Referring to FIG6 , the orthographic projections of the anodes 52 of the two second light-emitting elements on the substrate 1 are located on two sides of the second pixel circuit 212, and the orthographic projections of the anodes 52 of the two second light-emitting elements on the substrate 1, the orthographic projection of the first pixel circuit 211 on the substrate 1, and the orthographic projection of the third pixel circuit 213 on the substrate 1 surround the four sides of the orthographic projection of the second pixel circuit 212 on the substrate 1. Optionally, the anodes 52 of the two second light-emitting elements can be symmetrically arranged, and their axes of symmetry can be parallel to the first direction.

[0520] The third light-emitting element is connected to the third pixel circuit 213, that is, the anode 53 of the third light-emitting element is connected to the third pixel circuit 213, and the third pixel circuit 213 drives the third light-emitting element to emit light. In the embodiment of the present application, the orthographic projection of the anode 53 of the third light-emitting element on the substrate 1 at least partially overlaps with the orthographic projection of the pixel circuit group 2 where the third pixel circuit 213 is located on the substrate 1.

[0521] The orthographic projection of the anode 53 of the third light-emitting element on the substrate 1 is located within the orthographic projection of the third pixel circuit 213 on the substrate 1. Since the anode 53 of the third light-emitting element is light-shielding, it is set in the area where the third pixel circuit 213, which is also light-shielding, is located. This can reduce the blocking effect of the anode 53 of the third light-emitting element on the transparent area of ​​the first display area 11, thereby improving the light transmittance of the first display area 11.

[0522] 9 , the pixel circuit 21 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 , an eighth transistor T8 and a storage capacitor Cst.

[0523] The types of first signal lines may include a first reset signal line Preset, a second reset signal line Preset_H, a first reset power line vinit1, a second reset power line vinit2, a third reset power line vinit3, a first gate signal line Gate_N, a second gate signal line Gate_P, a data signal line Data, a light emitting control signal line EM, and a driving power line VDD.

[0524] The gate of the first transistor T1 is connected to the first reset signal line Preset, the first electrode of the first transistor T1 is connected to the first reset power line vinit1, and the second electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can also be called a reset transistor.

[0525] The gate of the second transistor T2 is connected to the first gate signal line Gate_N, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor is connected to the second node N2. The second transistor T2 can also be called a compensation transistor.

[0526] The gate of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can also be called a driving transistor.

[0527] The gate of the fourth transistor T4 is connected to the second gate signal line Gate_P, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the third node N3. The fourth transistor T4 can be a data writing transistor in the pixel circuit.

[0528] The gate of the fifth transistor T5 is connected to the light emission control signal line EM, the first electrode of the fifth transistor T5 is connected to the third node N3, and the second electrode of the fifth transistor T5 is connected to the driving power supply line VDD. Since the gate of the fifth transistor T5 is connected to the light emission control signal line EM, the fifth transistor T5 can also be called a light emission control transistor.

[0529] The gate of the sixth transistor T6 is connected to the light-emission control signal line EM, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting element. Since the gate of the sixth transistor T6 is connected to the light-emission control signal line EM, the sixth transistor T6 can also be called a light-emission control transistor.

[0530] The gate of the seventh transistor T7 is connected to the second reset signal line Preset_H, the first electrode of the seventh transistor T7 is connected to the second reset power line vinit2, and the second electrode of the seventh transistor T7 is connected to the anode of the light emitting element. The seventh transistor T7 can be a reset transistor in the pixel circuit.

[0531] The gate of the eighth transistor T8 is connected to the second reset signal line Preset_H, the first electrode of the eighth transistor T8 is connected to the third reset power line vinit3, and the second electrode of the eighth transistor T8 is connected to the third node N3. The eighth transistor T8 can be a reset transistor in the pixel circuit.

[0532] Two ends of the storage capacitor Cst are connected to the driving power line VDD and the second node N2 respectively.

[0533] Optionally, referring to FIG. 10 , the first signal line 3 may include a first reset power line vinit1 , and correspondingly, the connection line may include a second connection line L2 , wherein the second connection line L2 is located in the pixel circuit area 111 .

[0534] Each pixel circuit unit in the pixel circuit group 2 may be respectively connected to two first reset power lines vinit1 (including vinit1 - 1 and vinit1 - 2 ), and the two first reset power lines vinit1 may be electrically connected via a second connection line L2 .

[0535] For each pixel circuit unit, the orthographic projections of the two first reset power lines vinit1 on the substrate substrate 1 at least partially overlap with the orthographic projections of the first pixel circuit 211 on the substrate substrate 1 and the orthographic projections of the third pixel circuit 213 on the substrate substrate 1, and the two first reset power lines vinit1 are respectively connected to the first pixel circuit 211 and the third pixel circuit 213, that is, the first reset power line vinit1-1 and the first reset power line vinit1-2 respectively pass through the first pixel circuit 211 and the third pixel circuit 213, and are respectively connected to the first pixel circuit 211 and the third pixel circuit 213 through vias.

[0536] Furthermore, the second connection line L2 is connected to the second pixel circuit 212. The two ends of the second connection line L2 are connected to the first reset power line vinit1 located on both sides of the second pixel circuit 212. The second connection line L2 passes through the second pixel circuit 212 and connects to the second pixel circuit 212. The orthographic projections of the first reset power line vinit1 and the second connection line L2 on the base substrate 1 form an I-shape.

[0537] Optionally, each pixel circuit unit included in the pixel circuit group 2 may be connected to the same second connection line L2, or each pixel circuit unit included in the pixel circuit group 2 may be connected to different second connection lines L2.

[0538] Specifically, when each pixel circuit unit included in the pixel circuit group 2 can be connected to the same second connection line L2, that is, the connection line corresponding to each pixel circuit group 2 includes only one second connection line L2, the multiple first reset power lines vinit1 connected to the multiple pixel circuit units in the pixel circuit group 2 are all connected to the second connection line L2, and the second connection line L2 is connected to the second pixel circuits 212 in the multiple pixel circuit units in the pixel circuit group 2.

[0539] Alternatively, when each pixel circuit unit included in the pixel circuit group 2 can be respectively connected to different second connection lines L2, that is, the connection lines corresponding to each pixel circuit group 2 can include multiple second connection lines L2, each pixel circuit unit included in the pixel circuit group 2 is respectively connected to two first reset power lines vinit1 and one second connection line L2. For each pixel circuit unit, the two first reset power lines vinit1 are respectively connected to the first pixel circuit 211 and the third pixel circuit 213, and the two first reset power lines vinit1 are both connected to the second connection line L2, and the second connection line L2 is connected to the second pixel circuit 212.

[0540] In this way, compared with the solution of setting three first reset power lines vinit1 in the related art, the embodiment of the present application reduces one first reset power line vinit1, reducing its blocking area of ​​the light-transmitting area 112, thereby improving the light transmittance of the light-transmitting area 112, and further improving the display performance of the display panel.

[0541] Optionally, referring to FIG. 10 , the first signal line 3 may include a second reset power line vinit2 , and correspondingly, the connection line may include a fourth connection line L4 , wherein the fourth connection line L4 is located in the pixel circuit region 111 .

[0542] Each pixel circuit unit in the pixel circuit group 2 is respectively connected to three second reset power lines vinit2 (including vinit2 - 1 , vinit2 - 2 and vinit2 - 3 ). The three second reset power lines vinit2 can be electrically connected via a fourth connection line L4 .

[0543] For each pixel circuit unit, the orthographic projections of the three second reset power lines vinit2 on the substrate substrate 1 at least partially overlap with the orthographic projections of the first pixel circuit 211 on the substrate substrate 1, the orthographic projections of the second pixel circuit 212 on the substrate substrate 1, and the orthographic projections of the third pixel circuit 213 on the substrate substrate 1, and the three second reset power lines vinit2 are respectively connected to the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213, that is: the three second reset power lines vinit2 respectively pass through the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213, and are respectively connected to the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 through vias.

[0544] The fourth connection line L4 is used to connect the three second reset power lines vinit2 together, thereby improving the stability of signal transmission of the second reset power lines vinit2. In addition, the fourth connection line L4 does not block the light-transmitting area 112.

[0545] Optionally, the pixel circuit group 2 may correspond to one fourth connection line L4, or the pixel circuit group 2 may correspond to multiple fourth connection lines L4 (ie, each pixel circuit unit included in the pixel circuit group 2 corresponds to one fourth connection line L4).

[0546] Specifically, when the pixel circuit group 2 can correspond to a fourth connection line L4, that is, the connection line corresponding to each pixel circuit group 2 includes only one fourth connection line L4, the multiple second reset power lines vinit2 connected to the multiple pixel circuit units in the pixel circuit group 2 are all connected to the fourth connection line L4.

[0547] Alternatively, when each pixel circuit unit included in the pixel circuit group 2 corresponds to a fourth connection line L4 respectively, that is, the connection lines corresponding to each pixel circuit group 2 can include multiple fourth connection lines L4, each pixel circuit unit included in the pixel circuit group 2 is connected to three second reset power lines vinit2 respectively. For each pixel circuit unit, the three second reset power lines vinit2 are all connected to a fourth connection line L4, and the second reset power lines vinit2 connected to different pixel circuit units are connected to different fourth connection lines L4.

[0548] Optionally, referring to FIG. 10 , the first signal line 3 may include a third reset power line vinit3 , and correspondingly, the connection line may include a third connection line L3 , wherein the third connection line L3 is located in the pixel circuit area 111 .

[0549] Each pixel circuit unit in the pixel circuit group 2 is connected to a third reset power line vinit3 , and the third reset power line vinit3 is connected to the third connection line L3 .

[0550] For each pixel circuit unit, the orthographic projection of the third reset power line vinit3 on the substrate 1 at least partially overlaps with the orthographic projection of the second pixel circuit 212 on the substrate 1, and the third reset power line vinit3 is connected to the second pixel circuit 212, that is, the third reset power line vinit3 passes through the second pixel circuit 212 and is connected to the second pixel circuit 212 through a via.

[0551] Furthermore, the third connection line L3 is connected to the first pixel circuit 211 and the third pixel circuit 213. The extension direction of the third connection line L3 intersects the extension direction of the third reset power line vinit3. The third connection line L3 extends in two directions perpendicular to and opposite to the extension direction of the third reset power line vinit3, such that the orthographic projections of the third connection line L3 and the third reset power line vinit3 on the base substrate 1 form a cross.

[0552] While the third connection line L3 is connected to the third reset power line vinit3, its two ends are respectively connected to the first pixel circuit 211 and the third pixel circuit 213. In this way, the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213 can receive the same third reset power signal, thereby improving the stability of the third reset power signal received by the pixel circuit unit.

[0553] Optionally, each pixel circuit unit included in the pixel circuit group 2 may be connected to the same third connection line L3, or each pixel circuit unit included in the pixel circuit group 2 may be connected to different third connection lines L3.

[0554] Specifically, when each pixel circuit unit included in the pixel circuit group 2 can be connected to the same third connection line L3, that is, the connection line corresponding to each pixel circuit group 2 includes only one third connection line L3, the multiple third reset power lines vinit3 connected to the multiple pixel circuit units in the pixel circuit group 2 are all connected to the third connection line L3, and the third connection line L3 is connected to the first pixel circuit 211 and the third pixel circuit 213 in the multiple pixel circuit units in the pixel circuit group 2.

[0555] Alternatively, when each pixel circuit unit included in the pixel circuit group 2 can be respectively connected to a different third connection line L3, that is, the connection line corresponding to each pixel circuit group 2 can include multiple third connection lines L3, each pixel circuit unit included in the pixel circuit group 2 is respectively connected to a third reset power line vinit3 and a third connection line L3. For each pixel circuit unit, the third reset power line vinit3 is connected to the second pixel circuit 212, and the third reset power line vinit3 is connected to the third connection line L3, and the third connection line L3 is connected to the first pixel circuit 211 and the third pixel circuit 213.

[0556] In this way, compared with the solution of setting three first reset power lines vinit3 in the related art, the embodiment of the present application reduces one first reset power line vinit3, reducing its blocking area of ​​the light-transmitting area 112, thereby improving the light transmittance of the light-transmitting area 112, and further improving the display performance of the display panel.

[0557] Optionally, referring to FIG. 10 , the first signal line 3 may include a driving power line VDD, and the corresponding connection line may include a fifth connection line L5 , wherein the fifth connection line L5 is located in the pixel circuit region 111 .

[0558] Each pixel circuit unit in the pixel circuit group 2 is respectively connected to two driving power lines VDD, and the two driving power lines VDD may be electrically connected via a fifth connection line L5.

[0559] Correspondingly, referring to FIG. 11 , the structural arrangement of the three pixel circuits 21 in the pixel circuit unit may be such that, in the arrangement direction of the first pixel circuit 211, the second pixel circuit 212, and the third pixel circuit 213, the first pixel circuit 211 is oriented opposite to the second pixel circuit 212. That is, at least a portion of the pattern of the first pixel circuit 211 is symmetrical to at least a portion of the pattern of the second pixel circuit 212.

[0560] Referring to Figures 10 and 12, in this case, for each pixel circuit unit, the orthographic projection of a driving power line VDD on the substrate substrate 1 at least partially overlaps with the orthographic projection of the first pixel circuit 211 on the substrate substrate 1 and the orthographic projection of the second pixel circuit 212 on the substrate substrate 1, and is connected to the first pixel circuit 211 and the second pixel circuit 212, that is, the driving power line VDD runs through the first pixel circuit 211 and the second pixel circuit 212, and is connected to the first pixel circuit 211 and the second pixel circuit 212 through vias.

[0561] Since the first pixel circuit 211 and the second pixel circuit 212 are arranged in opposite directions, the driving power line VDD can be set between the first pixel circuit 211 and the second pixel circuit 212, so as to realize a solution in which one driving power line VDD drives two pixel circuits 21, thereby reducing the number of driving power lines VDD and improving the light transmittance of the first display area 11.

[0562] It can be understood that the connection point of the first pixel circuit 211 connected to the driving power line VDD needs to be set at a position close to the second pixel circuit 212. Similarly, the connection point of the second pixel circuit 212 connected to the driving power line VDD needs to be set at a position close to the first pixel circuit 211. In this way, the connection point on the first pixel circuit 211 and the connection point on the second pixel circuit 212 can be connected to the same driving power line VDD.

[0563] The orthographic projection of the other driving power line VDD on the base substrate 1 at least partially overlaps with the orthographic projection of the third pixel circuit 213 on the base substrate 1, and is connected to the third pixel circuit 213, that is, the other driving power line VDD passes through the third pixel circuit 213 and is connected to the third pixel circuit 213 through a via. Optionally, the orientation of the third pixel circuit 213 can be the same as the orientation of the first pixel circuit 211, or the orientation of the third pixel circuit 213 can be the same as the orientation of the second pixel circuit 212, which is not limited in this embodiment of the present application.

[0564] Using the fifth connection line L5 to connect the two driving power lines VDD together can enable the first pixel circuit 211, the second pixel circuit 212 and the third pixel circuit 213 to receive the same driving power signal, thereby improving the stability of the pixel circuit unit receiving the driving power signal.

[0565] Optionally, the pixel circuit group 2 may correspond to one fifth connection line L5, or the pixel circuit group 2 may correspond to multiple fifth connection lines L5 (ie, each pixel circuit unit included in the pixel circuit group 2 corresponds to one fifth connection line L5).

[0566] Specifically, when the pixel circuit group 2 can correspond to a fifth connection line L5, that is, the connection line corresponding to each pixel circuit group 2 only includes one fifth connection line L5, the multiple driving power lines VDD connected to the multiple pixel circuit units in the pixel circuit group 2 are all connected to the fifth connection line L5.

[0567] Alternatively, when each pixel circuit unit included in the pixel circuit group 2 corresponds to a fifth connection line L5 respectively, that is, the connection lines corresponding to each pixel circuit group 2 can include multiple fifth connection lines L5, each pixel circuit unit included in the pixel circuit group 2 is connected to two driving power lines VDD respectively, and for each pixel circuit unit, the two driving power lines VDD are connected to a fifth connection line L5, and the driving power lines VDD connected to different pixel circuit units are connected to different fifth connection lines L5.

[0568] The arrangement of the above-mentioned first reset power line vinit1, second reset power line vinit2, third reset power line vinit3 and driving power line VDD not only improves the light transmittance of the light-transmitting area 112, but also improves the stability of the first reset power signal, second reset power signal, third reset power signal and driving power signal received by the pixel circuit unit.

[0569] Optionally, the type of the first signal line 3 may include at least one of a first reset power line vinit1 , a second reset power line vinit2 , a third reset power line vinit3 and a driving power line VDD.

[0570] For this embodiment, other relevant features may be the same as those of the above embodiment, and reference may be made to the detailed description of the above embodiment, and the embodiment of the present application will not be repeated here.

[0571] Figure 72 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Referring to Figure 72, the display device may include any of the display panels 01 provided in the above embodiments and an optical sensor 02, wherein the orthographic projection of the optical sensor 02 on the display panel 01 at least partially overlaps with the first display area 11 of the display panel 01.

[0572] In a display device, the optical sensor 02 is typically mounted on the non-display side of the display panel 01, with the light-sensitive side of the optical sensor 02 facing the display panel 01. In the embodiment of the present application, the optical sensor 02 may include a front-facing camera, a proximity light sensor, a 3D sensing module, or other optical sensors, which can receive light from the display side of the display device to perform their corresponding functions.

[0573] In the embodiment of the present application, the display device can be an active-matrix organic light-emitting diode (AMOLED) display device, a passive-matrix organic light-emitting diode (PMOLED) display device, a quantum dot light-emitting diode (QLED) display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame or a navigation system, or any other product or component with a display function.

[0574] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0575] It will be understood that, although the terms first and second, etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another region, layer or part. Therefore, the first element, component, region, layer or part discussed above may be referred to as a second element, component, region, layer or part without departing from the teachings of the present disclosure.

[0576] Spatially relative terms such as “under,” “over,” “left,” “right,” and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, the element described as “under other elements or features” will be oriented “over other elements or features.” Therefore, the exemplary term “under” can encompass both orientations of over and under. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as “between two layers,” it can be the only layer between the two layers, or one or more intermediate layers can also be present.

[0577] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the existence of the features, integral bodies, steps, operations, elements and / or parts when used in this specification, but do not exclude the existence of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups or add one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In this specification, the specific features, structures, materials or characteristics of description can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples without contradicting each other.

[0578] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0579] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: A base substrate, wherein the base substrate has a first display area, wherein the first display area includes a plurality of pixel circuit areas and a light-transmitting area; a plurality of pixel circuit groups located in the plurality of pixel circuit areas, the pixel circuit groups comprising a plurality of pixel circuits, the minimum distance between adjacent pixel circuit groups being greater than the minimum distance between adjacent pixel circuits within the pixel circuit groups; and a plurality of types of first signal lines connected to the plurality of pixel circuits, some types of first signal lines of the plurality of types of first signal lines comprising metal signal lines and other types of first signal lines comprising transparent signal lines, at least some line segments of the plurality of types of first signal lines being located in the light-transmitting area; A plurality of light-emitting units are located in the first display area, the plurality of pixel circuit groups are configured to drive the plurality of light-emitting units to emit light, and the orthographic projection of at least some of the plurality of light-emitting units on the base substrate overlaps with the orthographic projection of at least some of the line segments of the plurality of types of first signal lines located in the light-transmitting area on the base substrate.

2. The display panel according to claim 1, characterized in that: At least some line segments of the metal signal line are located in the light-transmitting area, and the orthographic projection of at least some of the plurality of light-emitting units on the base substrate overlaps with the orthographic projection of at least some line segments of the metal signal line on the base substrate.

3. The display panel according to claim 1, characterized in that: At least some line segments of the transparent signal line are located in the light-transmitting area, and the orthographic projection of at least some of the plurality of light-emitting units on the base substrate overlaps with the orthographic projection of at least some line segments of the transparent signal line on the base substrate.

4. The display panel according to claim 1, characterized in that: The multiple pixel circuit groups include multiple first pixel circuit groups and multiple second pixel circuit groups, the multiple first pixel circuit groups are arranged in multiple rows, the multiple second pixel circuit groups are arranged in multiple rows, a row of second pixel circuit groups is arranged between any two adjacent rows of first pixel circuit groups, and in any row of first pixel circuit groups and a row of second pixel circuit groups adjacent to any row of first pixel circuit groups, the position of the spacing area between any two adjacent first pixel circuit groups corresponds to the position of a second pixel circuit group.

5. The display panel according to claim 4, characterized in that: Each pixel circuit group includes at least one pixel circuit unit, wherein the pixel circuit unit includes a first pixel circuit, a second pixel circuit and a third pixel circuit, wherein the second pixel circuit is located between the first pixel circuit and the third pixel circuit; The light-emitting unit includes a first light-emitting element, two second light-emitting elements and a third light-emitting element; The first light-emitting element is connected to the first pixel circuit, and an orthographic projection of an anode of the first light-emitting element on the substrate at least partially overlaps with an orthographic projection of a pixel circuit group where the first pixel circuit is located on the substrate; The two second light-emitting elements are both connected to the second pixel circuit, and the orthographic projections of the anodes of the two second light-emitting elements on the base substrate are respectively located on two opposite sides of the orthographic projection of the second pixel circuit on the base substrate; The third light emitting element is connected to the third pixel circuit, and the orthographic projection of the anode of the third light emitting element on the substrate at least partially overlaps with the orthographic projection of the pixel circuit group where the third pixel circuit is located on the substrate.

6. The display panel according to claim 5, characterized in that: The orthographic projection of the anode of the first light emitting element on the base substrate is located within the orthographic projection of the pixel circuit group where the first pixel circuit is located on the base substrate; The orthographic projections of the anodes of the two second light-emitting elements on the base substrate do not overlap with the orthographic projections of the pixel circuit group where the second pixel circuit is located on the base substrate; The orthographic projection of the anode of the third light emitting element on the base substrate is located within the orthographic projection of the pixel circuit group where the third pixel circuit is located on the base substrate.

7. The display panel according to claim 5, characterized in that: The first light-emitting element, the second light-emitting element and the third light-emitting element are respectively a blue light-emitting element, a green light-emitting element and a red light-emitting element, and the first pixel circuit, the second pixel circuit and the third pixel circuit of the pixel circuit unit of the first pixel circuit group are respectively a pixel circuit driving the blue light-emitting element, a pixel circuit driving the green light-emitting element and a pixel circuit driving the red light-emitting element; The first pixel circuit, the second pixel circuit, and the third pixel circuit of the pixel circuit unit of the second pixel circuit group are respectively a pixel circuit for driving the blue light emitting element, a pixel circuit for driving the green light emitting element, and a pixel circuit for driving the red light emitting element; or, The first pixel circuit, the second pixel circuit, and the third pixel circuit of the pixel circuit unit of the second pixel circuit group are respectively a pixel circuit for driving the red light-emitting element, a pixel circuit for driving the green light-emitting element, and a pixel circuit for driving the blue light-emitting element.

8. The display panel according to claim 5, characterized in that: The metal signal line in the first signal line includes a first part, a second part and a third part, the third part is located between the first part and the second part, and two ends of the third part are connected to the first part and the second part respectively; The first portion and the second portion are respectively connected to pixel circuits in two adjacent pixel circuit groups, and the orthographic projection of the third portion on the base substrate at least partially overlaps with the orthographic projection of the anode of the second light-emitting element on the base substrate.

9. The display panel according to claim 8, characterized in that: The orthographic projections of an anode of a second light-emitting element on the substrate at least partially overlap with the orthographic projections of the third portions of at least two of the metal signal lines on the substrate, and the overlapping portions between the third portions of at least two of the metal signal lines and the anode of the second light-emitting element are symmetrically arranged based on the symmetry axis of the anode of the second light-emitting element.

10. The display panel according to claim 5, characterized in that: The anodes of the first light-emitting element, the second light-emitting element, and the third light-emitting element are all circular in shape.

11. The display panel according to claim 5, characterized in that: Anodes of the two second light emitting elements are connected via a first connecting line, and the first connecting line is connected to the second pixel circuit.

12. The display panel according to claim 5, characterized in that: The types of the first signal lines include a first reset signal line, a second reset signal line, a first reset power line, a second reset power line, a third reset power line, a first gate signal line, a second gate signal line, a data signal line, a light emitting control signal line and a driving power line; The pixel circuit comprises: a first transistor, wherein a gate of the first transistor is connected to the first reset signal line, a first electrode of the first transistor is connected to the first reset power line, and a second electrode of the first transistor is connected to a first node; a second transistor, wherein a gate of the second transistor is connected to the first gate signal line, a first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to a second node; a third transistor, wherein a gate of the third transistor is connected to the second node, a first electrode of the third transistor is connected to the first node, and a second electrode of the third transistor is connected to a third node; a fourth transistor, wherein a gate of the fourth transistor is connected to the second gate signal line, a first electrode of the fourth transistor is connected to the data signal line, and a second electrode of the fourth transistor is connected to the third node; a fifth transistor, wherein a gate of the fifth transistor is connected to the light emitting control signal line, a first electrode of the fifth transistor is connected to the third node, and a second electrode of the fifth transistor is connected to the driving power line; a sixth transistor, wherein a gate of the sixth transistor is connected to the light emitting control signal line, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to an anode of the light emitting element; a seventh transistor, wherein a gate of the seventh transistor is connected to the second reset signal line, a first electrode of the seventh transistor is connected to the second reset power line, and a second electrode of the seventh transistor is connected to the anode of the light emitting element; an eighth transistor, wherein a gate of the eighth transistor is connected to the second reset signal line, a first electrode of the eighth transistor is connected to the third reset power line, and a second electrode of the eighth transistor is connected to the third node; A storage capacitor, wherein two ends of the storage capacitor are respectively connected to the driving power line and the second node.

13. The display panel according to claim 12, characterized in that: The second transistor is an N-type transistor, and the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all P-type transistors.

14. The display panel according to claim 13, characterized in that: The second transistor is an oxide thin film transistor, and the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all low temperature polysilicon thin film transistors.

15. The display panel according to claim 12, characterized in that: Each pixel circuit unit corresponds to two first reset power lines, three second reset power lines and one third reset power line respectively; For each pixel circuit unit, the orthographic projections of the two first reset power lines on the substrate substrate overlap at least partially with the orthographic projections of the first pixel circuit on the substrate substrate and the orthographic projections of the third pixel circuit on the substrate substrate, respectively, and the two first reset power lines are connected to the first pixel circuit and the third pixel circuit, respectively, the two first reset power lines are connected via a second connecting line, and the second connecting line is connected to the second pixel circuit, wherein an extension direction of the second connecting line is perpendicular to an extension direction of the first reset power line; The orthographic projections of the three second reset power lines on the base substrate at least partially overlap with the orthographic projections of the first pixel circuit on the base substrate, the orthographic projections of the second pixel circuit on the base substrate, and the orthographic projections of the third pixel circuit on the base substrate, respectively, and the three second reset power lines are connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit, respectively; The orthographic projection of the third reset power line on the substrate at least partially overlaps with the orthographic projection of the second pixel circuit on the substrate, and the third reset power line is connected to the second pixel circuit, and the third reset power line is connected to the first pixel circuit and the third pixel circuit through a third connecting line, wherein an extension direction of the third connecting line is perpendicular to an extension direction of the third reset power line.

16. The display panel according to claim 15, characterized in that: The three second reset power lines are connected via a fourth connection line, wherein an extending direction of the fourth connection line is perpendicular to an extending direction of the second reset power line.

17. The display panel according to claim 12, characterized in that: In the arrangement direction of the first pixel circuit, the second pixel circuit and the third pixel circuit, the orientation of the first pixel circuit is arranged opposite to the orientation of the second pixel circuit; Each pixel circuit unit corresponds to two driving power lines respectively; For each pixel circuit unit, the orthographic projection of a driving power line on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit on the substrate and the orthographic projection of the second pixel circuit on the substrate, and is connected to the first pixel circuit and the second pixel circuit; the orthographic projection of another driving power line on the substrate at least partially overlaps with the orthographic projection of the third pixel circuit on the substrate, and is connected to the third pixel circuit.

18. The display panel according to claim 17, characterized in that: The two driving power lines are connected via a fifth connecting line, wherein an extending direction of the fifth connecting line is perpendicular to an extending direction of the driving power line.

19. The display panel according to claim 1, characterized in that: The types of the first signal lines include at least two of a gate signal line, a light emission control signal line, a first reset signal line, a second reset signal line, a data signal line, a reset power line, and a driving power line.

20. The display panel according to claim 1, characterized in that: The partial types of first signal lines include at least one of a data signal line, a gate signal line, and a light emission control signal line.

21. The display panel according to claim 1, characterized in that: Each of the first signal lines of the partial types is a metal signal line.

22. The display panel according to claim 1, characterized in that: Each of the first signal lines of the partial types includes a metal signal line and a transparent signal line connected in parallel.

23. The display panel according to claim 22, characterized in that: The base substrate also has a second display area, and the second display area is adjacent to the first display area; The display panel further includes a plurality of types of second signal lines located in the second display area; For each type of the first reset signal line, the second reset signal line, the first reset power line, the second reset power line, the third reset power line, the first gate signal line, the second gate signal line, the data signal line, the light emitting control signal line and the driving power line, at least one end of each second signal line of the type is connected to a first signal line of the type, wherein the second signal line is a metal signal line, and the width of the metal signal line included in the first signal line is smaller than the width of the second signal line.

24. The display panel according to claim 1, characterized in that: The metal signal line is located in the gate layer or the source and drain layer.

25. A display panel, characterized in that: The display panel comprises: A base substrate, wherein the base substrate has a first display area, wherein the first display area includes a plurality of pixel circuit areas and a light-transmitting area; A plurality of pixel circuit groups, located in the plurality of pixel circuit areas, the pixel circuit groups comprising a first number of pixel circuits arranged along a first direction, the minimum distance between adjacent pixel circuit groups being greater than the minimum distance between adjacent pixel circuits within the pixel circuit groups; a plurality of first signal lines extending along a second direction, the first direction intersecting the second direction, at least one pixel circuit group among the plurality of pixel circuit groups being connected to a second number of first signal lines, the second number of first signal lines being electrically connected via connecting lines, for each pixel circuit group among the at least one pixel circuit group, each first signal line among the second number of first signal lines being respectively connected to at least one pixel circuit in the pixel circuit group, at least part of the line segments of the first signal lines being located in the light-transmitting area, and the connecting lines being located in the pixel circuit area, wherein the second number is not greater than the first number; and, A plurality of light-emitting units are located in the first display area, the plurality of pixel circuit groups are configured to drive the plurality of light-emitting units to emit light, and the orthographic projection of at least some of the plurality of light-emitting units on the base substrate overlaps with the orthographic projection of at least some line segments in the first signal line on the base substrate.

26. The display panel according to claim 25, characterized in that: The multiple pixel circuit groups include multiple first pixel circuit groups and multiple second pixel circuit groups, the multiple first pixel circuit groups are arranged in multiple rows, the multiple second pixel circuit groups are arranged in multiple rows, a row of second pixel circuit groups is arranged between any two adjacent rows of first pixel circuit groups, and in any row of first pixel circuit groups and a row of second pixel circuit groups adjacent to any row of first pixel circuit groups, the position of the spacing area between any two adjacent first pixel circuit groups corresponds to the position of a second pixel circuit group.

27. The display panel according to claim 26, characterized in that: Each pixel circuit group includes at least one pixel circuit unit, wherein the pixel circuit unit includes a first pixel circuit, a second pixel circuit and a third pixel circuit, wherein the second pixel circuit is located between the first pixel circuit and the third pixel circuit; The light-emitting unit includes a first light-emitting element, two second light-emitting elements and a third light-emitting element; The first light-emitting element is connected to the first pixel circuit, and an orthographic projection of an anode of the first light-emitting element on the substrate at least partially overlaps with an orthographic projection of a pixel circuit group where the first pixel circuit is located on the substrate; The two second light-emitting elements are both connected to the second pixel circuit, and the orthographic projections of the anodes of the two second light-emitting elements on the base substrate are respectively located on two opposite sides of the orthographic projection of the second pixel circuit on the base substrate; The third light emitting element is connected to the third pixel circuit, and the orthographic projection of the anode of the third light emitting element on the substrate at least partially overlaps with the orthographic projection of the pixel circuit group where the third pixel circuit is located on the substrate.

28. The display panel according to claim 27, characterized in that: The first signal line includes a first reset power line, the connection line includes a second connection line, each pixel circuit unit in the pixel circuit group is respectively connected to two first reset power lines, and the two first reset power lines are electrically connected through the second connection line; For each pixel circuit unit, the orthographic projections of the two first reset power lines on the substrate at least partially overlap with the orthographic projections of the first pixel circuit on the substrate and the orthographic projections of the third pixel circuit on the substrate, respectively, and the two first reset power lines are connected to the first pixel circuit and the third pixel circuit, respectively; The second connecting line is connected to the second pixel circuit.

29. The display panel according to claim 27, characterized in that: The first signal line includes a second reset power line, the connection line includes a fourth connection line, each pixel circuit unit in the pixel circuit group is respectively connected to three second reset power lines, and the three second reset power lines are electrically connected through the fourth connection line; For each pixel circuit unit, the orthographic projections of the three second reset power lines on the substrate at least partially overlap with the orthographic projections of the first pixel circuit on the substrate, the orthographic projections of the second pixel circuit on the substrate, and the orthographic projections of the third pixel circuit on the substrate, and the three second reset power lines are respectively connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit.

30. The display panel according to claim 27, characterized in that: The first signal line includes a third reset power line, the connection line includes a third connection line, each pixel circuit unit in the pixel circuit group is connected to a third reset power line respectively, and the third reset power line is connected to the third connection line; For each pixel circuit unit, an orthographic projection of the third reset power line on the base substrate at least partially overlaps with an orthographic projection of the second pixel circuit on the base substrate, and the third reset power line is connected to the second pixel circuit; The third connecting line is connected to the first pixel circuit and the third pixel circuit.

31. The display panel according to claim 27, characterized in that: The first signal line includes a driving power line, the connecting line includes a fifth connecting line, each pixel circuit unit in the pixel circuit group is respectively connected to two driving power lines, and the two driving power lines are electrically connected through the fifth connecting line; For each pixel circuit unit, the orthographic projection of a driving power line on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit on the substrate and the orthographic projection of the second pixel circuit on the substrate, and is connected to the first pixel circuit and the second pixel circuit; the orthographic projection of another driving power line on the substrate at least partially overlaps with the orthographic projection of the third pixel circuit on the substrate, and is connected to the third pixel circuit.

32. A display device, characterized in that: The display device comprises an optical sensor and the display panel according to any one of claims 1 to 31, wherein an orthographic projection of the optical sensor on the display panel at least partially overlaps with a first display area in the display panel.

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