A method for separating aging of power semiconductor devices at converter level

Abstract

The present invention discloses a method for separating aging of converter-level power semiconductor devices. Obtain a secondary I-V characteristic curve obtained by adding the I-V characteristic curve of the converter-level power semiconductor device and the I-V characteristic curve of the anti-parallel freewheeling diode; determine the intersection point and any point other than the intersection point on the secondary I-V characteristic curve; when the converter-level power semiconductor device works normally, measure the conduction voltage drop at the intersection point and the conduction voltage drop at any point; when the converter-level power semiconductor device ages, measure the conduction voltage drop at the intersection point and the conduction voltage drop at any point; based on the four conduction voltage drops, determine the increment caused by the fall of the bonding wire and the increment caused by the aging of the solder layer, so as to separate the two aging models of the fall of the bonding wire and the aging of the solder layer. The scheme of the present invention realizes the separation of the aging modes of various types of power devices at the converter level, breaking the limitation that the existing methods are all at the component level and can only be implemented on a single power device.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor device reliability, and in particular to a method for separating aging of converter-level power semiconductor devices. Background Art

[0002] With the large-scale application of power semiconductor devices in daily life and industrial production, their reliability performance has become a key factor in packaging design and operation. Research on the reliability of power semiconductor devices can not only greatly increase the service life of the devices, but also provide a reference for product replacement and upgrading. Power devices are mainly divided into bonding lead type and press-fit type according to different packaging technologies. Among them, the bonding lead type is still the mainstream packaging technology for power devices on the market due to its low cost and mature technology, whether for traditional silicon devices or new silicon carbide devices. The aging modes of power devices in bonded lead packages can be divided into two types: bonding wire shedding and solder joint aging. The occurrence of these two forms of aging is related to the change of converter load and the mismatch of thermal expansion coefficient of the material.

[0003] In power devices, bonding wires can be considered as parallel connections, and each bonding wire can be considered as a resistor. Therefore, when a bonding wire falls off, the total equivalent resistance will increase. At this time, the on-state voltage drop of the power device will increase, and the junction temperature of the power device will increase. For another form of aging, solder joint aging, when solder joint aging occurs, the thermal resistance of the power device will increase, and the heat dissipation effect of the entire power device will be reduced, which will also cause the junction temperature to rise. Increase. The on-state voltage drop of power devices is related to temperature, and the occurrence of solder joint aging will also cause the on-state voltage drop of power devices to change. Therefore, in the field of power semiconductor device reliability, on-state voltage drop is often used to describe its health status. In short, aging will increase the temperature of power devices, and the increase in temperature will further accelerate aging, forming a bad positive feedback effect, and ultimately leading to thermal runaway of power devices. Therefore, monitoring the two aging modes is particularly important. The two common aging modes will cause the on-state voltage drop of power devices to change, that is, there is a coupling relationship between the two aging forms. How to separate the two aging modes is a problem that needs to be urgently solved.

[0004] There are several methods to separate the two aging modes, such as Figure 1As shown in (a), for some special metal oxide semiconductor field effect transistors (MOSFETs), there is an auxiliary source terminal AS between the gate G and the source S. AS is connected to the S pole through a bonding wire. Therefore, it is possible to directly measure the voltage between AS and S to determine whether the bonding wire has fallen off. In this way, the total on-state voltage drop caused by the bonding wire falling off can be eliminated. This method has great limitations. Not all power semiconductor devices have such a package. For most insulated gate bipolar transistors (IGBTs), their package forms are as follows: Figure 1 As shown in (b), the auxiliary emitter terminal AE and the emitter E are connected at the same point. In this case, the increase in the on-state voltage drop caused by the bond wire falling off cannot be measured separately.

[0005] For the second existing separation method, such as Figure 2 As shown in the figure, this is the IV characteristic curve of a certain model of IGBT module, which utilizes the characteristic that the current and on-state voltage drop at the intersection of the figure are not affected by temperature. Due to its temperature-independent characteristics, this intersection is only used to detect the detachment of the bonding wire and is not affected by the aging of the solder joint. Then, any other point on the graph is taken as a reference point to separate the two aging modes. There are three disadvantages of this separation method: 1. Not all IGBTs have this intersection; 2. For MOSFETs, all MOSFETs do not have this intersection; 3. This implementation method is limited to a single IGBT tube at the component level, and cannot achieve the aging separation of power semiconductor devices at the converter level.

[0006] In summary, the prior art has technical problems that it cannot be applied to all types of power semiconductors and cannot be implemented at the converter level. Summary of the invention

[0007] In order to solve the technical problems that the prior art is not applicable to all types of power semiconductors and cannot be implemented at the converter level, an embodiment of the present invention provides a converter-level power semiconductor device aging separation method.

[0008] The technical solution of the embodiment of the present invention is achieved as follows:

[0009] An embodiment of the present invention provides a method for separating aging of a converter-level power semiconductor device, the method comprising: obtaining a secondary IV characteristic curve obtained by adding an IV characteristic curve of a converter-level power semiconductor device and an IV characteristic curve of an anti-parallel freewheeling diode; determining an intersection point on the secondary IV characteristic curve and any point other than the intersection point; when the converter-level power semiconductor device is working normally, measuring a first conduction voltage drop at the intersection point and a second conduction voltage drop at any point; when the converter-level power semiconductor device is aged, measuring a third conduction voltage drop at the intersection point and a fourth conduction voltage drop at any point; and determining an increment caused by bonding wire detachment and an increment caused by solder layer aging based on the first conduction voltage drop, the second conduction voltage drop, the third conduction voltage drop and the fourth conduction voltage drop, thereby separating the two aging models of bonding wire detachment and solder layer aging.

[0010] In one embodiment, the increment caused by the bonding wire falling off and the increment caused by the aging of the solder layer are determined according to the first conduction voltage drop, the second conduction voltage drop, the third conduction voltage drop and the fourth conduction voltage drop, including: determining the increase in equivalent resistance caused by the bonding wire falling off according to the first conduction voltage drop and the third conduction voltage drop; determining the increment caused by the bonding wire falling off by using the increase in equivalent resistance caused by the bonding wire falling off and the collector current at any point; determining the increment caused by aging according to the second conduction voltage drop and the fourth conduction voltage drop; determining the increment caused by aging of the solder layer by using the increment caused by aging and the increment caused by the bonding wire falling off.

[0011] In one embodiment, determining the equivalent resistance increase value caused by the bonding wire falling off according to the first conduction voltage drop and the third conduction voltage drop includes:

[0012] According to the first on-state voltage drop and the third on-state voltage drop, the equivalent resistance increase value caused by the bonding wire falling off is determined by using the following calculation formula:

[0013]

[0014] in, Indicates the increase in equivalent resistance caused by the bond wire falling off. represents the third conduction voltage drop, represents the first conduction voltage drop, represents the collector current at the intersection.

[0015] In one embodiment, determining the increment caused by the bonding wire falling off by using the equivalent resistance increase value caused by the bonding wire falling off and the collector current at any point includes:

[0016] The increase in equivalent resistance caused by the falling of the bonding wire and the collector current at any point are used to determine the increment caused by the falling of the bonding wire using the following calculation formula:

[0017]

[0018] in, Indicates the increase caused by the bond wire falling off, Indicates the increase in equivalent resistance caused by the bond wire falling off. Represents the collector current at any point.

[0019] In one embodiment, determining the increment caused by aging according to the second conduction voltage drop and the fourth conduction voltage drop includes:

[0020] According to the second conduction voltage drop and the fourth conduction voltage drop, the increment caused by aging is determined using the following calculation formula:

[0021]

[0022] in, Indicates the increase in on-state voltage drop after aging. represents the fourth conduction voltage drop, Represents the second conduction voltage drop.

[0023] In one embodiment, determining the increment caused by aging of the solder layer by using the increment caused by aging and the increment caused by the bonding wire falling off includes:

[0024] The increment caused by aging and the increment caused by the bonding wire falling off are used to determine the increment caused by aging of the solder layer using the following calculation formula:

[0025]

[0026] in, Indicates the increase caused by aging of the solder layer, Indicates the increase in on-state voltage drop after aging. Indicates the increase caused by bond wire detachment.

[0027] The converter-level power semiconductor device aging separation method provided in the embodiment of the present invention obtains a secondary IV characteristic curve obtained by adding the IV characteristic curve of the converter-level power semiconductor device and the IV characteristic curve of the anti-parallel freewheeling diode;

[0028] Determine the intersection point on the secondary IV characteristic curve and any point other than the intersection point; when the converter-level power semiconductor device is working normally, measure the first conduction voltage drop at the intersection point and the second conduction voltage drop at any point; when the converter-level power semiconductor device is aging, measure the third conduction voltage drop at the intersection point and the fourth conduction voltage drop at any point; determine the increment caused by the fall of the bonding wire and the increment caused by the aging of the solder layer based on the first conduction voltage drop, the second conduction voltage drop, the third conduction voltage drop and the fourth conduction voltage drop, so as to separate the two aging models of the fall of the bonding wire and the aging of the solder layer. The solution provided by the present invention can realize the separation of the aging modes of various types of power devices at the converter level, breaking the limitation that the existing methods are all at the component level and can only be implemented on a single power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is the equivalent circuit diagram of common power semiconductor devices; among them, Figure 1 (a) is the equivalent circuit diagram of metal oxide semiconductor field effect transistor; Figure 1 (b) is the equivalent circuit diagram of the insulated gate bipolar transistor;

[0030] Figure 2 This is the IV characteristic curve of a certain model of IGBT at different temperatures;

[0031] Figure 3 It is a schematic flow chart of a method for separating aging of a converter-level power semiconductor device according to an embodiment of the present invention;

[0032] Figure 4 The IV characteristic curve diagram in the power device manual of the embodiment of the present invention and the secondary IV characteristic curve diagram obtained by adding them; Figure 4 (a) is a schematic diagram of the secondary IV characteristic curve obtained by adding the IV characteristic curve of the power device without intersection and the IV characteristic curve of the freewheeling diode with intersection. Figure 4 (b) is a schematic diagram of a secondary IV characteristic curve obtained by adding the IV characteristic curve of a power device without an intersection point and the IV characteristic curve of a freewheeling diode without an intersection point. Figure 4 (c) is a schematic diagram of a secondary IV characteristic curve obtained by adding the IV characteristic curve of a power device with an intersection point and the IV characteristic curve of a freewheeling diode without an intersection point;

[0033] Figure 5 This is a topological diagram of a single-phase inverter circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0035] The embodiment of the present invention provides a method for separating aging of power semiconductor devices at a converter level, such as Figure 3 As shown, the method includes:

[0036] Step 101: obtaining a secondary IV characteristic curve obtained by adding an IV characteristic curve of a converter-level power semiconductor device and an IV characteristic curve of an anti-parallel freewheeling diode;

[0037] Step 102: Determine an intersection point on the quadratic IV characteristic curve and any point other than the intersection point;

[0038] Step 103: When the converter-level power semiconductor device operates normally, measuring a first conduction voltage drop at the intersection and a second conduction voltage drop at any point;

[0039] Step 104: When the converter-level power semiconductor device is aged, measuring the third conduction voltage drop at the intersection and the fourth conduction voltage drop at any point;

[0040] Step 105: Determine the increment caused by the bonding wire falling off and the increment caused by the aging of the solder layer according to the first conduction voltage drop, the second conduction voltage drop, the third conduction voltage drop and the fourth conduction voltage drop, so as to separate the two aging models of the bonding wire falling off and the solder layer aging.

[0041] The converter-level power semiconductor device aging separation method proposed in this embodiment has the following advantages over the traditional method: 1. It is applicable to different types of power semiconductors, including IGBTs, MOSFETs and diodes. 2. It is a converter-level separation method that can simultaneously separate the aging modes of all power devices in the converter.

[0042] Specifically, this embodiment adds the IV characteristic curve of the converter-level power semiconductor device to the IV characteristic curve of the anti-parallel freewheeling diode to obtain a secondary IV characteristic curve.

[0043] It is known from the prior art that there is no intersection point in the IV characteristic curve of MOSFETs that is independent of temperature, and there is no such intersection point in the IV characteristic curve of some IGBTs. It can be found from the manual of each power device that if the IV characteristic curve of the power device and the IV characteristic curve of the freewheeling diode connected in anti-parallel with it are added, an IV characteristic curve will be obtained again, that is, the secondary IV characteristic curve. This embodiment uses the coordinate extraction tool to add the two power device IV characteristic curves and the freewheeling diode IV characteristic curve in the device manual. The result is as follows Figure 4 As shown. Figure 4It is not difficult to find that no matter whether the two initial IV characteristic curves have an intersection or not, a new intersection will be generated in the secondary IV characteristic curve after adding the two. The on-state voltage drop at this point is independent of temperature. By using this characteristic, the aging condition of the bond wire falling off can be independently detected, thereby separating the two aging modes.

[0044] In order to realize the aging separation method mentioned in this embodiment, the Figure 4 The IGBT module in (b) is a general representative IGBT. Similarly, this method can be verified by selecting other types of power devices. First, take two points from the secondary IV characteristic curve, one is the intersection point , the other is any reference point except the intersection point .according to Figure 1 From the IGBT equivalent circuit in (b), we can see that in the healthy state of the power device, the intersection It can be expressed as:

[0045] Formula (1)

[0046] in, is the on-state voltage drop of the IGBT chip, is the forward conduction voltage of the freewheeling diode itself, and They are the equivalent resistance of the bonding wires connected to the IGBT chip and the freewheeling diode itself. is the collector current at the intersection. When the bonding wire of the IGBT falls off, its equivalent resistance will increase. At this time, equation (1) can be rewritten as:

[0047] Formula (2)

[0048] The equivalent resistance increase due to bond wire detachment can be expressed as:

[0049] Formula (3)

[0050] For the selected reference point , before and after the power device ages, The measured pressure drops are respectively and After aging occurs, The increment can be expressed as:

[0051] Formula (4)

[0052] It is the increment of on-state voltage drop after aging, which includes two parts: the increment caused by the falling of bonding wire and the increment caused by the aging of solder layer. Among them, the increment caused by the falling of bonding wire can be calculated:

[0053] Formula (5)

[0054] According to the result calculated by formula (5), the increment caused by the aging of the solder layer can be calculated:

[0055] Formula (6)

[0056] From the above analysis, it can be seen that the aging modes of the two power semiconductor devices can be separated by equations (5) and (6).

[0057] A specific application example will be used for illustration below.

[0058] This article takes a single-phase inverter as an example for analysis. The topology diagram is as follows: Figure 5 As shown in the previous analysis, Figure 5 The measurement circuit shown measures the sum of the conduction voltage drops of the IGBT chip and the freewheeling diode. This measurement circuit can measure the sum of the conduction voltage drops of the IGBT chip and the freewheeling diode at different current levels when the inverter is working. Then, according to the principle analysis in the previous article, the secondary IV characteristic curve obtained by addition can be used to separate the two aging modes of the power semiconductor device. At different current levels, the conduction voltage drops measured by the measurement circuit are shown in Table 1.

[0059] Table 1

[0060]

[0061] Among them, Ti and Di represent IGBT and freewheeling diode respectively, and VCE-ONi+VFi represents the conduction voltage drop of IGBT and the conduction voltage drop of freewheeling diode respectively. Ⅱ It can be seen that this physical quantity includes all the power devices in the single-phase inverter, indicating that the measurement scheme can be implemented at the converter level. Similarly, the scheme is also applicable to three-phase converters.

[0062] The converter-level power semiconductor device aging separation method provided in this embodiment breaks the limitations of the original separation method, such as high cost, non-universality, and inability to be implemented at the converter level. It can not only greatly increase the service life of the device, but also provide a reference for product replacement and upgrading.

[0063] In addition, the process of this embodiment may be as follows:

[0064] The first step is to obtain the secondary IV characteristic curve. This step is to use When the power device is normal, measure the conduction voltage drop at the intersection (i.e. the first conduction voltage drop) and the conduction voltage drop at the reference point (ie the second conduction voltage drop).

[0065] Then measure the conduction voltage drop at the intersection after aging (i.e. the third conduction voltage drop) and the conduction voltage drop at the reference point (i.e. the fourth conduction voltage drop), calculated using formula (3) .

[0066] At the reference voltage, the increase in the on-state voltage drop caused by the bond wire falling off is calculated according to formula (5).

[0067] Finally, the increase in the on-state voltage drop due to the aging of the solder layer is calculated according to formula (6).

[0068] So far, the separation of the two aging modes has been successfully achieved. An example is shown in Table 2.

[0069] Table 2

[0070]

[0071] The converter-level power semiconductor device aging separation method proposed in this embodiment breaks the limitations of the existing methods and cleverly utilizes the aging of semiconductor devices. The secondary IV characteristic curve is redrawn by the addition method, such as Figure 4 This method is applicable to all power semiconductor devices with freewheeling diodes and is universal. At the same time, using the measurement circuit, the physical quantity measured at different current levels when the converter is working is Contains information on all power devices, greatly saving costs.

[0072] The beneficial effects of the method of this embodiment are as follows: Figure 4 As shown, for different power devices, no matter whether the original IV characteristic curve has an intersection or not, the secondary IV characteristic curve obtained by adding them together will have a new intersection. The on-state voltage drop at the intersection is also not affected by temperature. Using equations (3), (4), (5), and (6) in the principle analysis part, aging separation at the converter level can be achieved.

[0073] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0074] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A method for separating aging of converter-level power semiconductor devices, characterized in that: The method comprises: Obtaining a secondary IV characteristic curve obtained by adding an IV characteristic curve of a converter-level power semiconductor device to an IV characteristic curve of an anti-parallel freewheeling diode; Determine an intersection point and any point other than the intersection point on the quadratic IV characteristic curve; When the converter-level power semiconductor device operates normally, measuring a first conduction voltage drop at the intersection and a second conduction voltage drop at any point; When the converter-level power semiconductor device is aged, measuring the third conduction voltage drop at the intersection and the fourth conduction voltage drop at any point; The increment caused by the bonding wire falling off and the increment caused by the aging of the solder layer are determined according to the first conduction voltage drop, the second conduction voltage drop, the third conduction voltage drop and the fourth conduction voltage drop, so as to separate the two aging models of the bonding wire falling off and the solder layer aging.

2. The method for separating aging of converter-level power semiconductor devices according to claim 1, characterized in that: Determining an increment caused by bonding wire shedding and an increment caused by solder layer aging according to the first conduction voltage drop, the second conduction voltage drop, the third conduction voltage drop, and the fourth conduction voltage drop, including: Determine an increase in equivalent resistance caused by bonding wire detachment according to the first conduction voltage drop and the third conduction voltage drop; Determine the increment caused by the falling off of the bonding wire by using the equivalent resistance increase value caused by the falling off of the bonding wire and the collector current at any point; determining an increment caused by aging according to the second conduction voltage drop and the fourth conduction voltage drop; The increment caused by aging of the solder layer is determined by using the increment caused by aging and the increment caused by the bonding wire falling off.

3. The method for separating aging of converter-level power semiconductor devices according to claim 2, characterized in that: Determining an increase in equivalent resistance caused by a bonding wire falling off according to the first on-state voltage drop and the third on-state voltage drop includes: According to the first on-state voltage drop and the third on-state voltage drop, the equivalent resistance increase value caused by the bonding wire falling off is determined by using the following calculation formula: in, Indicates the increase in equivalent resistance caused by the bond wire falling off. represents the third conduction voltage drop, represents the first conduction voltage drop, represents the collector current at the intersection.

4. The method for separating aging of converter-level power semiconductor devices according to claim 2, characterized in that: Determining the increment caused by the bonding wire falling off by using the equivalent resistance increase value caused by the bonding wire falling off and the collector current at any point, including: The increase in equivalent resistance caused by the falling of the bonding wire and the collector current at any point are used to determine the increment caused by the falling of the bonding wire using the following calculation formula: in, Indicates the increase caused by the bond wire falling off, Indicates the increase in equivalent resistance caused by the bond wire falling off. Represents the collector current at any point.

5. The method according to claim 2, characterized in that: Determining the increment caused by aging according to the second conduction voltage drop and the fourth conduction voltage drop includes: According to the second conduction voltage drop and the fourth conduction voltage drop, the increment caused by aging is determined using the following calculation formula: in, Indicates the increase in on-state voltage drop after aging. represents the fourth conduction voltage drop, Represents the second conduction voltage drop.

6. The method according to claim 2, characterized in that Determining the increment caused by aging of the solder layer by using the increment caused by aging and the increment caused by the bonding wire falling off includes: The increment caused by aging and the increment caused by the bonding wire falling off are used to determine the increment caused by aging of the solder layer using the following calculation formula: in, Indicates the increase caused by aging of the solder layer, Indicates the increase in on-state voltage drop after aging. Indicates the increase caused by bond wire detachment.

Images