Die-to-die dynamic clock and power gating

Abstract

The invention relates to die-to-die dynamic clock and power gating. A system includes a plurality of systems on chip (SoC) connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on respective portions of the network of the plurality of SoCs. A given SoC of the plurality of SoCs may be configured to determine that a local condition has been satisfied to place the respective portion of the network corresponding to the given SoC in a reduced power mode. The given SoC may be further configured to place the respective portion of the network in the reduced power mode in response to determining that global conditions of the reduced power mode are satisfied. The global condition may be evaluated based on current local power information for the remaining SoCs of the plurality of SoCs.

Description

[0001] This application is a divisional application of the invention patent application with application date of May 2, 2022, application number 202280034262.2, and titled "Die-to-Die Dynamic Clock and Power Gating". Technical Field

[0002] Embodiments described herein relate to systems on a chip (SoCs), and more particularly, to parallel communication interfaces for coupling SoCs. Background Art

[0003] A system-on-chip (SoC) integrated circuit (IC) typically includes one or more processors that serve as the central processing unit (CPU) of the system, as well as various other components, such as a memory controller and peripheral components. Additional components may be included on a particular SoC IC to act as the main processor for a given device. For example, a SoC may include any suitable combination of one or more general-purpose processors, a graphics processor, an audio processor, networking circuits (e.g., Ethernet, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe)), a memory controller, a display controller, etc. The combination of processors and components may be coupled to enable communication using one or more networks within the SoC.

[0004] Increasing the number of processors and / or other discrete components included on a SoC IC may be desirable for increased capabilities for performance-oriented applications, while a reduced set of capabilities may be acceptable for cost-sensitive applications. Increasing the number of processors on an IC may increase costs, which is disadvantageous for cost-sensitive applications. In addition, ICs may have physical limitations on die size. Increasing the number of processors and / or other circuits on a SoC may reach physical limits before the desired performance capabilities are achieved. Another technique for scaling SoC capabilities is to use multiple SoCs in a single design. A base SoC may be used for cost-sensitive applications, while two or more instances of a base SoC may be included in performance-oriented applications. Summary of the invention

[0005] In an embodiment, a system includes multiple systems on chip (SoC) connected by a network. Multiple SoCs and networks are configured to operate as a single logical computing system. Multiple SoCs may be configured to exchange local power information indicating network activities occurring on corresponding parts of the networks of multiple SoCs. A given SoC in multiple SoCs may be configured to determine that a local condition has been met for placing a corresponding part of the network corresponding to a given SoC in a reduced power mode. A given SoC may be further configured to place a corresponding part of the network in a reduced power mode in response to determining that a global condition for a reduced power mode is met. Global conditions may be evaluated based on the current local power information of the remaining SoCs in multiple SoCs.

[0006] In another example, to exchange local power information, multiple SoCs may be configured to send their corresponding local power information to at least one other SoC in the multiple SoCs at a specific time interval. In another example, to exchange local power information, a given SoC is configured to send a request to the remaining SoCs to enter a reduced power mode. The given SoC may also be configured to receive the corresponding local power information of the corresponding SoC from the remaining SoCs, and determine whether the received local power information satisfies the global condition.

[0007] In an example, a given SoC may be a primary SoC configured to initiate entry into a reduced power mode. The remaining SoCs may be secondary SoCs configured to wait for an indication from the primary SoC to enter a reduced power mode. In an embodiment, in order to place a corresponding portion of the network into a reduced power mode, the given SoC may be configured to send a request to the remaining SoCs to enter a reduced power mode, and wait for a corresponding reply from the remaining SoCs, wherein the corresponding reply approves or denies the request.

[0008] In other embodiments, a particular SoC among the remaining SoCs may be further configured to delay sending a reply to the request in response to a determination that the corresponding portion of the network in the particular SoC is waiting for the transaction to complete, and to send a reply in response to a determination that the transaction has completed. The reply may include approval to enter a reduced power mode.

[0009] In another embodiment, a particular SoC among the remaining SoCs is further configured to send a reply to the request in response to a determination that the corresponding portion of the network in the particular SoC is waiting for the transaction to complete. The reply may include a rejection of entering a reduced power mode. The given SoC may be further configured to cancel the request to enter a reduced power mode in response to receiving a rejection reply. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0011] Figure 1 A block diagram of an embodiment of a system including multiple systems-on-chips coupled via a shared network is shown.

[0012] Figure 2 A block diagram of another system embodiment including multiple systems on a chip (SoCs) coupled via two shared networks is shown.

[0013] Figure 3 Describes the Figure 1 and Figure 2 A block diagram of an embodiment of a SoC used in a system.

[0014] Figure 4 A depiction of tasks performed by two SoCs in a system coupled by a shared network to place network circuitry in a reduced power mode is shown.

[0015] Figure 5 Another depiction of tasks performed by two SoCs in a system coupled by a shared network to place network circuitry in a reduced power mode is shown.

[0016] Figure 6 Depicted are tasks performed by two SoCs in a system coupled by a shared network to wake up network circuitry that is in a reduced power mode.

[0017] Figure 7 A flow chart of an embodiment of a method for placing a network circuit into a reduced power mode is shown.

[0018] Figure 8 A flow chart illustrating an embodiment of a method for waking up network circuitry that is in a reduced power mode is shown.

[0019] Fig. 9 Various embodiments of systems including coupled integrated circuits are described.

[0020] Fig.10 A block diagram of an exemplary computer-readable medium is shown according to some embodiments.

[0021] Although the embodiments described in the present disclosure may be subject to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and the specific embodiments thereof are not intended to limit the embodiments to the particular forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims. DETAILED DESCRIPTION

[0022] As described above, a system on chip (SoC) design may include one or more network circuits to enable communication between multiple agents. As used herein, an "agent" refers to a functional circuit that can initiate a transaction on a network or serve as a destination for a transaction on a network. Therefore, a general-purpose processor, a graphics processor, a memory controller, and other similar circuits may be referred to as an agent. The exchange of data between two agents across one of the network circuits is referred to as a "transaction" in this article. In order to manage various data transactions between various agents, multiple network circuits may be implemented.

[0023] Utilizing multiple instances of SoC can bring several challenges. For example, in order to reduce the delay associated with inter-SoC communication, the inter-SoC network interface may include a large number of pins, thereby allowing a large number of bits to be exchanged in parallel between two or more SoCs. The on-chip network for a multi-core SoC can utilize one or more communication buses with hundreds or even a thousand or more signals running in parallel. Coupling two or more such SoCs together may require a network interface that provides access to a significant portion of the communication bus, and may require coupling hundreds of pins across two or more dies. Such an inter-SoC network can enable the internal communication bus on two or more instances of the SoC to be used as a single coherent communication fabric, thereby allowing transactions to be exchanged between agents on different dies in a manner similar to exchanging transactions between two agents on the same die. From a functional perspective, multiple instances of the SoC can be executed as a single integrated circuit.

[0024] In order to match or even approach the internal on-chip communication frequency of the communication bus, the timing characteristics of a large number of pins of the network circuit between SoCs can utilize high-speed circuit elements that may not be power-efficient when idle. Therefore, it may be desirable to place the network circuits between SoCs in a reduced power mode when they are idle. In the reduced power mode, the power consumption of a given network circuit is less than the power consumption when operating in the operating mode. For example, the power can be reduced, or it can be gated to one or more power nodes in a given network circuit. Similarly, the frequency of the clock signal can be reduced, or the clock signal can be gated from one or more clock nodes in a given network circuit. In other embodiments, the reduced power mode may correspond to the removal of an active network circuit so that the removed network circuit does not respond to network traffic between other network circuits that can remain active on a common interface.

[0025] As power is reduced, the capability of a given network circuit while in a reduced power mode may also be less than when operating in an operational mode. Thus, in a multi-SoC system, if a particular SoC autonomously places its corresponding network circuit into a reduced power state, transactions sent from different SoCs to an agent on that particular SoC may be missed or blocked while waiting for that particular SoC to place its network circuit back into an operational mode. Thus, an uncoordinated approach to placing corresponding network circuits into a reduced power mode may result in an unacceptable number of transactions being missed or blocked, thereby reducing the effectiveness of the multi-SoC system.

[0026] To address this problem, a technique is envisioned in which multiple SoCs including respective portions of a multi-SoC network exchange local power information indicating network activities occurring on respective portions of the network of the multiple SoCs. A given SoC in the SoCs may then determine that a local condition has been met to place the respective portion of the network of the given SoC in a reduced power mode. In response, the given SoC may then determine whether a global condition for a reduced power mode is met. Such a global condition may be evaluated based on the current local power information of other SoCs in the multi-SoC system. After determining that the global condition has been met, the respective portion of the network may then be placed in a reduced power mode.

[0027] Figure 1 A block diagram of an embodiment of a logical computing system including four SoCs coupled by a shared network is shown. As shown, system 100 includes SoCs 101a to SoC 101d (collectively referred to as SoCs 101). Each SoC 101 includes a corresponding power management circuit in power management circuits 120a to 120d (collectively referred to as power management circuits 120). SoC 101 also includes a corresponding portion of network 105, including a corresponding network circuit in network circuits 110a to 110d (collectively referred to as network circuits 110). Using network 105, SoCs 101 can exchange respective power information (power info) 130a to 130d (collectively referred to as power information 130).

[0028] As shown, SoC 101 is located on the corresponding tube core, and is connected by network 105, and the corresponding part of the network (including corresponding network circuit 110) is located on different tube cores in the corresponding tube core. SoC101 and network 105 are configured to operate as a single logical computing system, for example, as a computing device such as a laptop or desktop computer, a tablet computer, a smart phone, etc. The main application processor operates. As used herein, "logical computing system" refers to a computing system including one or more processor circuits, which are configured to execute program instructions included in a software program, which causes the one or more processor circuits to receive, process and generate data using one or more memory circuits and / or other functional circuits accessed via a common bus protocol. Multiple SoCs that can be arranged on a single integrated circuit (IC) or arranged across two or more ICs can be used to implement a logical computing system. When implemented across multiple ICs, as shown in system 100, a common bus protocol is used in multiple ICs to allow software programs to access agents on each IC without knowing the physical location of the agent. Each SoC 101 includes one or more agents (not shown), such as processor cores, graphics processors, memory systems, wired and / or wireless networking interfaces, etc. Using network 105, an agent on SoC 101a, for example, can communicate with agents on other SoCs 101 in the same manner as it communicates with other agents within SoC 101.

[0029] As shown, the SoC 101 is configured to exchange respective power information 130 indicating network activity occurring on respective portions of the network 105 of the SoC 101. For example, the power management circuit 120b on the SoC 101b maintains power information 130b indicating activity on the network circuit 110b. In some embodiments, the power information 130b is an indication of network activity occurring in the network circuit 110b, including, for example, one or more pieces of information, such as the number of consecutive clock cycles that the network circuit 130b has been idle, an indication of the number of pending transactions in one or more queues included in the network circuit 110b, the destination of the pending transactions in the queue, etc. In other embodiments, additional information such as the current power mode state may be included in the power information 130b. In some embodiments, the power information 130 may include only an indication from the corresponding SoC 101 that the local traffic on the corresponding network circuit 110 meets the conditions for shutting down the network 105, without providing additional network traffic information. The power management circuit 120b may update the power information 130b when a change occurs and / or at specific intervals (including, for example, each cycle of a clock signal associated with the network circuit 110b). In various embodiments, the SoCs 101 may exchange their respective power information 130 at specific time intervals or in response to specific events such as a request from another SoC 101.

[0030] As shown, SoC 101b is configured to determine that the local conditions for placing the network circuit 110b in the reduced power mode have been met. The local conditions may correspond, for example, to the network circuit 110b remaining in an idle state for a continuous number of cycles of clock cycles. As used herein, the "idle state" of a network circuit refers to a network circuit having no transactions to process. Transactions to be sent and / or received via the network circuit may be stored in one or more queues. Transactions may remain queued until resources to process the transaction are available. For example, queued transactions may remain queued until the destination agent has the bandwidth to receive the transaction. A network circuit having queued transactions but no transactions being actively processed cannot be considered idle because once resources are available, the network circuit has transactions to process. If no transactions are queued or being processed, the network circuit may be considered idle. Each clock cycle in which the network circuit is in an idle state is referred to as an "idle cycle."

[0031] As shown, a given one of the network circuits 110 enables the corresponding SoC 101 to communicate with the other three SoCs 101 via the network 105. In some embodiments, the given network circuit 110 may be in an idle state while two or more agents within the corresponding SoC 101 are exchanging transactions. The network circuit 110 is configured to provide a bridge between an on-chip communication bus (not shown) and the network 105, thereby allowing, for example, an agent on SoC 101a to send transactions to an agent on SoC 101d using commands similar to sending transactions to different agents on SoC 101a.

[0032] After SoC 101b determines that power information 130b satisfies local conditions, SoC 101b is further configured to place network circuit 110b in reduced power mode in response to determining that global conditions for reduced power mode are met. As stated, SoCs 101 exchange their respective power information 130 so that each power management circuit 120 may be able to evaluate global conditions for power usage across network 105. In some embodiments, to exchange power information 130, multiple SoCs 101 are configured to send their respective power information 130 to other SoCs 101 at specific time intervals. In other embodiments, SoC 101b may send a request to enter reduced power mode to SoC 101a, SoC 101c, and SoC 101d, and then receive the respective power information 130 of the corresponding SoCs from SoC 101a, SoC 101c, and SoC 101d. SoC 101b is further configured to determine that the received power information 130a, 130c, and 130d satisfies the global conditions.

[0033] As shown, the global condition is evaluated based on the current power information 130 of the remaining SoCs 101a, SoC 101c, and SoC 101d. For example, the power information 130 received from the other SoCs 101 may include the destination of the queued transaction. An example of a global condition for SoC 101b includes that network circuits 110a, 110c, and 110d have no queued transactions with a destination on SoC 101b. In some embodiments, the shared power information 130 includes a current idle cycle count. The power management circuit 120b may not place the network circuit 110b in a reduced power mode unless all four network circuits have been idle for a threshold amount of time.

[0034] In some embodiments, rather than allowing any one of the SoCs 101 to initiate a request to enter a reduced power mode, a given SoC in the SoCs 101 is designated as a master SoC that is configured to initiate a determination of whether network traffic as indicated by the power information 130a to 130d satisfies the conditions for stopping all network traffic. The remaining SoCs 101 are auxiliary SoCs that are configured to wait for a request from the master SoC to provide the corresponding power information 130 of the auxiliary SoCs. The SoCs 101 may each provide an indication of whether the conditions for allowing one or more of the network circuits 110 to enter a reduced power mode are met. If all of the SoCs 101 agree, any particular SoC in the SoCs 101 may place their corresponding network circuits 110 in a reduced power mode.

[0035] For example, SoC 101a may be a designated master SoC, while SoCs 101b through SoC 101d are auxiliary SoCs. In such an example, the exchange of power information 130 includes SoCs 101b through SoC 101d sending corresponding power information in power information 130b through 130d to SoC 101a based on the passage of a specific time interval or in response to a request from SoC 101a. Power management circuitry 120a receives power information 130b through 130d and, in conjunction with local power information 130a, determines whether conditions are met to shut down network 105 and allow one or more SoCs 101 to enter a reduced power mode. In some embodiments, power information 130a through 130d is shared among all SoCs 101, thereby allowing each SoC 101 to have an opportunity to reject shutdown of network 105, in which case no network circuit 110 may be placed in a reduced power mode.

[0036] In some embodiments, the master SoC 101a may determine a global condition for all SoCs 101 to place their respective network circuits 110 in a low power mode. For example, the power information 130 may indicate that no transactions are queued and no transactions are pending completion in any of the network circuits 110. The power management circuit 120a may then send a notification to the power management circuits 120b to 120d that the network 105 is being shut down, and if the respective local conditions of these power management circuits are met, they may place their respective network circuits 110b to 110d in a reduced power mode. In some cases, a particular power management circuit in the power management circuits 120b to 120d may respond with a veto indication. Such a veto indication may cancel the shutdown of the network 105.

[0037] In other embodiments, the master SoC 101a determines, individually for each SoC in the SoC 101, local and global conditions for whether a given one or more SoCs 101 place their corresponding network circuits 110 in a low power mode. For example, based on the power information 130, the power management circuit 120a may determine that the network circuit 110a and the network circuit 110d meet the conditions for entering a reduced power mode, while the network circuits 110b and 110c have active and / or queued transactions to be exchanged between the SoC 101b and the SoC 101c and therefore must remain active. In such an embodiment, the SoC 101a may pass the master designation to either the SoC 101b or the SoC 101c, so that the SoC 101 with the active network circuit 110 is the designated master SoC 101. In other embodiments, the SoC 101a may maintain the master designation despite the network circuit 110a entering a reduced power mode.

[0038] Such a power management system for network circuits may allow a multi-SoC system such as system 100 to reduce power consumption of network circuits while maintaining proper operation of the distributed network system. The disclosed power management techniques may allow the distributed network system to support software running on any particular SoC in the SoC to address an agent in other SoCs in the SoC without knowing that the agent is on a different SoC die.

[0039] Please note that Figure 1 The system 100 shown in FIG. 1 is only an example. Figure 1The illustrations are simplified to highlight the feature structures related to the present disclosure. Various embodiments may include different configurations of circuit elements. For example, system 100 is shown as having four SoCs. In other embodiments, any suitable number of SoCs may be included. For clarity, each SoC is shown as having only corresponding network circuits and power management circuits. In other embodiments, the SoC may have any suitable number of additional circuits, including, for example, one or more processor cores, a graphics processor, a security processor, memory circuits and / or interfaces, image and / or audio capture circuits, etc.

[0040] Figure 1 A system with a signal network distributed among multiple SoCs is depicted. In other embodiments, various numbers of networks may be included, and the networks may have more than one topology. Figure 2 An example of a system including two networks with different topologies is shown in FIG.

[0041] Move to Figure 2 , a block diagram of an embodiment of a system including four SoCs coupled by two shared networks. As shown, system 100 includes SoC 101, and as previously described, each SoC in SoC 101 includes a corresponding power management circuit in power management circuit 120 and a corresponding network circuit in network circuit 110. Network circuit 110 supports two networks in system 200, namely network 105 and network 205, each network having a different topology.

[0042] As shown, networks 105 and 205 allow communication between agents on different SoCs in SoC 101. Each of networks 105 and 205 can be assigned to a corresponding type of transaction. For example, network 105 can be assigned to a memory type transaction, where at least one of the source and / or destination agents includes a memory circuit, thereby allowing agents on various SoCs 101 to access memory circuits on other SoCs in SoC 101. Network 205 can be assigned, for example, to processor cores on each SoC 101, thereby allowing one or more processor cores on each SoC 101 to share information with cores on other SoCs 101.

[0043] In order to perform their respective types of transactions, networks 105 and 205 are arranged in different topologies (mesh topology and ring topology). Network 105 is arranged in a mesh topology, where each network node (e.g., a corresponding circuit within each network circuit in network circuit 110) can be coupled to one or more other network nodes. In general, mesh networks do not have a fixed structure. In network 105, for example, SoC 101a can be directly coupled to each of SoC 101b to SoC 101d, and SoC 101b and SoC 101d also share a direct connection. SoC 101c can only be directly coupled to SoC 101a. Therefore, transactions to / from SoC 101c on network 105 can always pass through network circuit 110a of SoC 101a.

[0044] On the other hand, network 205 is a ring network, in which each network node is directly coupled to two other network nodes. As shown, network 205 directly couples SoC 101a to SoC 101b and SoC 101c, SoC 101b to SoC101a and SoC 101d, SoC 101d to SoC 101b and SoC 101c, and SoC 101c to SoC101a and SoC 101d. In a ring network, transactions are sent "around the ring" until the transactions reach their destination. In some ring networks, transactions can be sent in a single direction. For example, if network 205 has a clockwise direction, a transaction from SoC 101a to SoC 101c will travel through SoC 101b, and then through SoC 101d, and then arrive at SoC101c. However, transactions from SoC 101c to SoC 101a will be direct, without passing through SoC 101b or SoC 101d. In other embodiments, network 205 may be bidirectional, allowing, for example, SoC 101a and SoC 101c to exchange transactions directly.

[0045] The system designer may select the topology of each network for a variety of reasons. Ring networks may be used with processor cores to establish a more predictable network structure, while mesh networks may allow for faster, more direct transmission of transactions when network traffic is low, but may also result in longer paths between two network nodes when traffic on the network is high. Additional factors for selecting the network topology between SoC 101 include what topology the corresponding network in the SoC uses. As shown, network 105 is an extension of the memory network in each SoC in SoC 101. If SoC 101 uses a mesh network for internal memory transactions, using a mesh network to form network 105 allows the processor core coupled to network circuit 110a to access the memory circuits coupled to network circuits 110b to 110d by using the same network protocol as used to access the memory circuits in SoC 101a.

[0046] Several techniques may be utilized to place a given one of the network circuits 110 into a reduced power mode. In some embodiments, placing a given one of the network circuits 110 into a reduced power mode blocks communications on both the network 105 and the network 205. In other embodiments, the network circuits 110 may be partitioned so that subcircuits of the network 105 or the network 205 may be placed into a reduced power mode independently, thereby allowing one network to remain operational while another network enters a reduced power mode.

[0047] In addition, the network topology may determine whether individual network circuits 110 may enter a reduced power mode individually or whether all network circuits 110 in the system 200 must meet the conditions to enter a reduced power mode simultaneously. For example, a mesh network such as network 105 may enable a single network circuit (e.g., network circuit 110c) in the network circuits 110 to enter a reduced power mode as long as network circuits 110a, 110b, and 110d have active network paths between them so that communication between any combination of the three active network circuits is possible. In contrast, a ring network such as network 205 may block communication between one or more active network circuits if a given network circuit 110 enters a reduced power mode. For example, if network 205 is unidirectional (e.g., clockwise transmission only), then if any single network circuit such as network circuit 110b enters a reduced power state, network circuit 110c cannot send transactions to network circuit 110d, and network circuit 110a cannot send transactions to network circuits 110d or 110c. In such an embodiment, all four network circuits 110 would need to enter the reduced power mode simultaneously.

[0048] Therefore, in order to place the network circuit 110a in a reduced power mode, the SoC 101a is configured to send a request 240 to enter the reduced power mode to the SoCs 101b to 101d. The SoC 101a is further configured to wait for corresponding replies 245b to 245d from the SoCs 101b to 101d, wherein the corresponding replies 245b to 245d approve (245c) or deny (245b and 245d) the request 240. If the request 240 is a request to place the portion of the network circuit 110a supporting the ring network 205 in a reduced power mode, or if the network circuit 110 is not partitioned to independently support the networks 105 and 205, the network circuit 110a is not allowed to enter the reduced power state unless the global conditions of the network circuits 110b to 110d are also met. As shown, a transaction 235 between the network circuits 110b and 110d is active or queued to be processed using the network 205. As such, network circuits 110b and 110d must remain active until transaction 235 is completed or otherwise terminated in some embodiments. If network 205 is a unidirectional ring network as described above, network circuit 110d requires network circuit 110a to remain active in order to send network circuit 110d's portion of transaction 235 to network circuit 110b. Therefore, SoC 101b and SoC 101d may send replies 245b and 245d, respectively, to SoC 101a denying request 240 to enter reduced power mode. In other embodiments, SoCs 101b and 101d may delay responding to request 240 until transaction 235 is completed / terminated, and may send an approval reply instead of a rejection if local conditions are met.

[0049] Therefore, by using the disclosed technology, power modes can be managed in a system of SoCs coupled by multiple networks. The disclosed technology can allow some or all parts of the network to be placed in a reduced power mode when conditions are met, thereby achieving a reduction in power consumption of the system.

[0050] Please note that Figure 2 The embodiment of is an example. In other embodiments, different combinations of components may be included. For example, different numbers of SoCs and / or networks may be included. Although a ring network and a mesh network are shown, other types of known network topologies may be included, such as a star topology and / or a tree topology.

[0051] exist Figure 1 and Figure 2 In the description of , the system is shown as having multiple SoCs coupled by one or more shared networks. The SoCs include corresponding power management circuits that track activity on the networks and can initiate requests to place network circuits in a reduced power mode. Such power management circuits can be implemented in various ways. Figure 3 A more detailed example of a SoC with power management circuitry is shown in .

[0052] Steering Figure 3 , depicting a SoC used in a multi-SoC system. As shown in the figure, SoC 101 may correspond to Figure 1 and Figure 2 SoC 101 includes the aforementioned network circuit 110 and power management circuit 120. SoC 101 also includes a plurality of functional circuits 370a to 370c (collectively referred to as 370) and one or more communication buses 360 for implementing a network within SoC 101. Network circuit 110 includes interface circuit 310. Power management circuit 120 includes timer circuit 320 for generating timing value 325 and a plurality of status and control registers 330.

[0053] As shown, the network circuit 110 is configured to be coupled to other compatible network circuits such as Figure 1 and Figure 2 The network circuits 110b to 110d in the SoC 101 form part of the network 105. The network circuit 110 is further configured to exchange multiple transactions with other compatible network circuits. The network circuit 110 includes an interface circuit 310 that is configured to drive and receive various signals associated with the network 105. In some embodiments, multiple instances of the interface circuit 310 may be included to couple the SoC 101 to multiple different networks, such as Figure 2 Networks 105 and 205 in.

[0054] The network circuit 110 bridges communications between functional circuits in the functional circuit 370 and functional circuits included in other SoCs coupled via the network 105. The communication bus 360 may in combination form part of the network 105 within the SoC 101. The functional circuit 370 may act as a proxy for initiating and receiving transactions via the network 105. Thus, the functional circuit 370a, for example, may be configured to send transactions to the functional circuit 370b using the same network protocol used to send transactions to functional circuits on different SoCs coupled via the network 105. This configuration may allow software executing on the SoC 101 to address the functional circuit 370 as well as address functional circuits on other SoCs without knowing the specific SoC in which the given functional circuit is located.

[0055] As shown, the power management circuit 120 is configured to track local power information 130 associated with the network circuit 110 and use the power information 130 to determine that the local condition for entering the reduced power mode is met. For example, the power information 130 may include the number of consecutive cycles during which the network circuit 110 has been idle. The timer circuit 320 is configured to increment (or decrement in other embodiments) a timing value 325, for example, based on a network clock signal 365. The network circuit 110 may use the network clock signal 365 to synchronize the transmission of transactions on the network 105. When the timing value 325 reaches a certain value, the power management circuit 120 may compare the power information 130 with a threshold 335. If the value of the power information 130 meets the threshold 335 (e.g., the idle cycle count in the power information 130 meets or exceeds the threshold 335), the local condition for the network circuit 110 to enter the reduced power mode may be met.

[0056] In some embodiments, the power management circuit 120 is further configured to receive other local power information associated with compatible network circuits in other compatible network circuits. In some embodiments, all power management circuits on all SoCs coupled to the network 105 can exchange the corresponding power information of all SoCs with each other on a periodic basis or in response to a request from a specific SoC. As previously disclosed, in some embodiments, a specific SoC in the SoCs of the network 105 can be designated as the main SoC, while the remaining SoCs play a secondary role. In such an embodiment, the master power management circuit 120 of the master SoC 101 is a power management circuit that can initiate any network circuit in the network circuit 110 of the network 105 to enter a reduced power mode. For example, the SoC 101 can be designated as the master SoC in the network 105 by setting the master enable 333 to a specific value. After determining that the local conditions have been met, the power management circuit 120 that plays the main role can use the value of the power information 130 recently received from other SoCs, or can request the current value of the power information 130 from other SoCs. The power management circuit 120 may then determine whether the network circuit 110 and / or other network circuits in the network 105 may be placed in a reduced power mode. In various embodiments, the idle cycle counts from the other network circuits may be compared to the same threshold 335, or corresponding thresholds may be used for other idle cycle counts. In some embodiments, the power information from the other SoCs may include different information from the local power information 130. For example, the power management circuits on the other SoCs may perform a corresponding determination if the local conditions of the other SoCs are met, and the received power information includes an indication of whether the local conditions of the other SoCs are met for each of the other SoCs.

[0057] In some embodiments where SoC 101 is the designated master SoC, the power management circuit 120 is further configured to receive a request to enter a reduced power mode from a different compatible network circuit in the other compatible network circuits. Using the received other local power information, the power management circuit 120 is configured to determine whether to approve or deny the request. For example, the network circuit of the specific SoC may meet the local conditions for entering the reduced power mode, and in response, send a request to SoC 101 to approve the placement of the specific network circuit in the reduced power mode. After receiving the request from the specific SoC, the power management circuit 120 sends a reply 145 to the specific SoC in response to a determination that the other local power information meets the global conditions for entering the reduced power mode, thereby causing the network circuit of the specific SoC to enter the reduced power mode. In some embodiments, if no additional replies are to be sent to other SoCs of the network 105, the power management circuit 120 may further determine that the network circuit 110 can be placed in a reduced power mode.

[0058] In an embodiment where the SoC 101 is designated as a secondary SoC (e.g., the primary enable 333 is set to a different value to indicate the secondary SoC designation), in order to determine that other local power information satisfies the global condition for entering the reduced power mode, the power management circuit 120 is configured to send a request 240 to enter the reduced power mode to a specific compatible network circuit among other compatible network circuits via the network circuit 110. For example, the power management circuit 120 first determines that the local condition is met. The power management circuit 120 then sends a request 240 to the designated primary SoC to place the network circuit 110 in the reduced power mode. The power management circuit 120 is further configured to wait for a reply from the specific compatible network circuit (e.g., the network circuit of the primary SoC), wherein the reply approves or denies the request.

[0059] To place the network circuit 110 in a reduced power mode, the power management circuit 120 may reduce the voltage of the network circuit 110 or gate one or more power signals to the network circuit. Additionally or alternatively, the power management circuit 120 may reduce the frequency of the network clock signal 365 or gate the network clock signal 365 from the network circuit 110.

[0060] After the network circuit 110 has entered the reduced power mode, regardless of whether the SoC 101 is designated as the primary SoC or the secondary SoC, the power management circuit 120 is further configured to cause the network circuit 110 to exit the reduced power mode in response to receiving an indication that a specific transaction is to be sent to one of the other compatible network circuits via the network circuit 110. After the network circuit 110 wakes up from the reduced power mode, the power management circuit 120 is configured to cause the network circuit 110 to send a wake-up signal 350 to the other compatible network circuits. In some embodiments, the wake-up signal 350 is an asynchronous signal that is not dependent on the network clock signal 365 so as to be detected by the other compatible network circuits.

[0061] In a similar manner, if the network circuit 110 is in a reduced power mode and receives a wake-up signal from one of the other network circuits of the network 105, the power management circuit 120 may be able to detect the receipt of the wake-up signal when the network clock signal 365 is gated from the network circuit 110. For example, the wake-up signal may be a transition from a logic low voltage to a logic high voltage, or vice versa. The transition on a particular pin of the interface circuit 310 may be detected by the power management circuit 120, allowing the power management circuit 120 to restore the power signal, clock signal, and / or any other state of the network circuit 110 back to the operating mode. After the network circuit 110 is in the operating mode, an acknowledgement 355 may then be sent to the other network circuits on the network 105.

[0062] Please note that Figure 3 The SoC is only used to demonstrate the disclosed concepts. In other embodiments, the SoC may have a different configuration. For example, although three functional circuits are shown, the SoC may include any suitable number of functional circuits. The number of pin connections from the interface circuit shown is only an example. In other embodiments, the interface circuit may include any number of pins, including, for example, hundreds or even thousands of pins.

[0063] Figures 1 to 3 Various embodiments of a system having multiple SoCs linked by a shared network and embodiments of SoCs included in such a system are described. The disclosed system describes techniques for managing power to network circuits used to implement the shared network. A variety of techniques can be used to manage power to these network circuits. Figures 4 to 6 Several techniques for managing power modes of network circuits used to implement a multi-SoC network are shown.

[0064] Continue to Figure 4 , depicting the Figure 1Flowchart of tasks performed by SoC 101a and SoC 101b to enter a reduced power mode in an embodiment of system 100. As shown, SoC 101a is designated as the primary SoC, while SoC 101b is the secondary SoC. The two columns indicate which SoC performs which task. Figure 4 Depicted is a situation where entry into a reduced power mode is requested before an active transaction is completed.

[0065] In the illustrated example, the power management circuit 120a in the SoC 101a tracks the idle time of the network circuit 110a (task 402). While the SoC 101a is tracking the idle time, the SoC 101b sends a packet to the SoC 101a via the network circuit 110b as part of a specific transaction (task 405). The packet includes a specific request for which a response (e.g., a flow control message acknowledging receipt of the packet) is expected from the SoC 101a. Before the SoC 101a can respond, the power management circuit 120a determines that the idle time of the network circuit 110a meets a threshold amount of time (task 410). For example, the number of clock cycles during which the network circuit 110a has been idle meets or exceeds a threshold number of cycles. In response to this determination, the power management circuit 120a sends a request to enter a reduced power mode to the SoC 101b, SoC 101c, and SoC 101d using the network circuit 110a (task 415). SoC 101c and SoC 101d may respond with approval to enter the reduced power mode. However, SoC 101b delays sending a reply to the request in response to a determination that network circuitry 110b in SoC 101b is waiting for a particular transaction to complete (task 420).

[0066] At a later point in time, the particular transaction is completed within SoC 101a, and therefore, SoC 101a is ready to respond to the received packet. The packet response is sent to network circuit 110b via network circuit 110a (task 422). After receiving the packet response, SoC 101b determines that the particular transaction has been completed. In response to this determination that the particular transaction has been completed, SoC 101b may send a reply to the request from SoC 101a to enter a reduced power mode (task 425). The reply includes approval to enter the reduced power mode, resulting in permission for power management circuit 120b to place network circuit 110b in a reduced power mode (task 430). In a similar manner, in response to receiving the approval response, power management circuit 120b is allowed to place network circuit 110b in a reduced power mode (task 435).

[0067] exist Figure 5 In Figure 4 Different implementation plans for different scenarios. Figure 4In a similar manner, SoC 101a is designated as the primary SoC, while SoC 101b is the secondary SoC, and depicts a situation where entry into a reduced power mode is requested prior to completion of an active transaction. Figure 5 Different ways of processing a request in response to determining that a transaction remains active are shown.

[0068] As depicted, SoC 101a uses power management circuit 120a to track idle time of network circuit 110a (task 502). While SoC 101a tracks idle time, SoC 101b sends a packet to SoC 101a via network circuit 110b as part of a specific transaction (task 505), which requires a response from SoC 101a. While processing the response to the specific transaction, power management circuit 120a continues to track idle time of network circuit 110a. Power management circuit 120a determines that network 110a has been idle for a threshold amount of time (task 510). In response, power management circuit 120a sends a request to enter a reduced power mode to SoC 101b, SoC 101c, and SoC 101d via network circuit 110a (task 515), and receives replies from SoC 101c and SoC 101d with approval of the reduced power mode. Note that Figure 5 Tasks 502 to 515 correspond to Figure 4 Tasks 402 to 415.

[0069] SoC 101b determines that a response to the particular transaction is still expected (task 520). Network circuit 110b, for example, includes a transaction queue in which pending and / or active transactions are tracked until completion. Therefore, in response to the determination that network circuit 110b is waiting for the particular transaction to complete, SoC 101b sends a reply to the reduced power mode request that includes a rejection of entering the reduced power mode (task 525). SoC 101a is further configured to cancel the request to enter the reduced power mode in response to receiving the rejection reply from SoC 101b (task 535). SoC 101a may also send a notification to SoC 101c and SoC 101d indicating the cancellation of the reduced power mode request.

[0070] In addition, as shown, SoC 101a reinitializes the idle count, and power management circuit 120a may resume tracking the new idle time (task 540). If network circuit 110a remains idle for another threshold amount of time, another request to enter a reduced power mode may be sent. If the particular transaction has been completed and network circuit 110b also satisfies local conditions, SoC 101b may respond with approval for the reduced power mode.

[0071] Figure 4 and Figure 5 Corresponding to different techniques for managing the situation in which a request to enter a reduced power mode is sent. Figure 6 1 depicts a situation where a SoC 101 is in a reduced power mode when a transaction is ready to be sent from one SoC 101 to a different SoC 101. Figure 4 and Figure 5 In that case, SoC 101a is designated as the primary SoC, while SoC 101b is the secondary SoC. Figure 6 Techniques are shown for waking network circuitry from a reduced power mode in response to determining that a transaction is ready to be sent.

[0072] for Figure 1 At least SoC 101a and SoC 101b in system 100 of the present example begin with network circuit 110 in a reduced power mode. Power management circuit 102b on SoC 101b receives an indication that a specific transaction is to be sent to network circuit 110a of SoC 101a via network circuit 110b (task 605). In some embodiments, a portion of network circuit 110b may remain active while other portions are in a reduced power mode, the active portion being configured to detect an internal bus (e.g., Figure 3 In other embodiments, circuitry within or coupled to an internal bus, such as a network switch circuit, sends an indication in response to determining that a particular transaction is to be sent via network circuitry 110b.

[0073] As shown, the power management circuit 120b is further configured to, in response to the indication, cause the network circuit 110b to exit the reduced power mode (task 610). For example, the power management circuit 120b opens one or more gates to the power signal and / or the clock signal to cause the network circuit 110b to wake up from the reduced power mode. After the network circuit 110b is in the operating mode, the power management circuit 120b causes the network circuit 110b to send a wake-up signal to the network circuit 110a and, if applicable, to the network circuits 110c and 110d (task 615).

[0074] The wake-up signal can be implemented in various ways. For example, each network circuit in the network circuit 110 may include a dedicated pin for an asynchronous wake-up signal that can be coupled by a common connection so that all wake-up signal pins are connected to each other. In the reduced power mode, the voltage level on the common connection is maintained at a first logic level (e.g., a low logic level). When a given network circuit in the network circuit 110 wants to wake up other network circuits, the given network circuit asserts an opposite logic level (e.g., a high logic level) on a common connection via its corresponding wake-up signal pin. The transition from the first logic level to the second logic level can cause all network circuits coupled to the common connection to wake up from the reduced power mode. If a specific network circuit 110 has been awakened, it can ignore the wake-up signal. In other embodiments, other methods can be used, such as generating one or more transitions on any given pin of the network interface such as an address or data pin.

[0075] In response to the assertion of the wake-up signal by the network circuit 110b, the power management circuit 120a causes the network circuit 110a to exit the reduced power mode in a manner similar to that described above by the power management circuit 120b waking up the network circuit 110b (task 620). After the network circuit 110a has exited the reduced power mode and is in the operating mode, the network circuit 110a sends a confirmation to the network circuit 110b to indicate that the network circuit 110a is now able to receive transactions (task 625). The confirmation can be performed in any suitable manner. For example, the network circuit 110 may have an additional pin for asserting confirmation similar to the wake-up signal pin. In other embodiments, the awakened network circuit 110 may send a specific packet via the network 105 to indicate that they have returned to the operating mode. As shown, the network circuit 110b is further configured to send a specific transaction to the network circuit 110a (task 630) in response to receiving a confirmation from the network circuit 110a.

[0076] In the illustrated embodiment, network circuit 110b waits for an acknowledgment from destination network circuit 110a before sending a particular transaction. In other embodiments, network circuit 110b may wait until an acknowledgment is received from all network circuits in network 105 before sending any transaction. This technique may avoid causing a late-awakening network circuit to miss a portion of a transaction, which in some embodiments may cause the late-awakening network circuit to perform incorrect or unknown operations.

[0077] Please note that Figure 4 and Figure 5 In the technique, a designated master SoC initiates a request to enter a reduced power mode. Figure 6 In the techniques depicted in , any of the SoCs can initiate a wakeup from a reduced power mode.

[0078] Also note that Figures 4 to 6 The techniques are merely examples that demonstrate the disclosed concepts. In other embodiments, additional tasks may be included, and / or some tasks may be performed in a different order or concurrently. For example, in Figure 4 In the process, network circuits 110a and 110b may be simultaneously placed in their respective reduced power modes (tasks 430 and 435).

[0079] You can use the above information about Figures 1 to 6 The present invention describes circuits and techniques for managing the power modes of network circuits included in a shared network. Figure 7 and Figure 8 Two methods associated with entering and exiting a reduced power mode are described.

[0080] Now move to Figure 7 , a flow chart of an embodiment of a method for placing a network circuit in a reduced power mode is shown. The method 700 may be implemented by a system including two or more SoCs coupled together to form a shared network, such as Figure 1 and Figure 2 The systems 100 and 200 are implemented in the same manner. Figure 1 and Figure 7 , method 700 starts in box 710.

[0081] At block 710, the method 700 includes exchanging power information 130 of the respective individual SoCs 101 in the plurality of SoCs 101 located on the respective dies. Figure 1 As shown, the SoCs 101 are connected by a network 105 implemented across respective dies of the SoCs 101. As disclosed above, the network 105 may extend within each SoC in the SoCs 101 so that software executing on a particular SoC in the SoCs 101 uses the same network protocol for on-chip communications and for communications with other SoCs in the SoCs 101. For example, software executing on SoC 101a accesses functional circuits on SoCs 101b to 101d in the same manner as accessing functional circuits on SoC 101a. In some embodiments, exchanging power information 130 includes sending respective power information 130 by individual SoCs 101 to other SoCs 101 at specific time intervals. For example, the power information 130 may be sent every second, or after a specific number of clock cycles (e.g., cycles of the network clock signal 365). In other embodiments, exchanging power information 130 includes a first SoC 101 (e.g., a SoC in the SoCs 101 designated as a master SoC) sending a request for power information 130 from the remaining SoCs 101.

[0082] At block 720, the method 700 also includes determining, by the SoC 101a, that the power information 130a of the SoC 101a satisfies the local conditions for entering a reduced power mode. As shown, the power information 130a may include any suitable information that can be used to determine an activity level of the network circuit 110a and, therefore, an indication of power usage. The power information 130a may be compared to a threshold value (e.g., Figure 3 The current value of the power information 130a is compared to a threshold value 335 in FIG. 1 to determine that the current value of the power information 130a satisfies the threshold value, thereby indicating that the activity level of the network circuit 110a is low enough to place the network circuit in a reduced power mode.

[0083] At block 730, method 700 also includes entering reduced power mode by SoC 101a in response to determining that power information 130b, 130c, and 130d of SoC 101b, SoC 101c, and SoC 101d meet the global conditions for entering reduced power mode, respectively. As shown, SoC 101a determines whether the power information 130b to 130d received in block 710 meets the global conditions for entering reduced power mode. In various embodiments, power information 130b to 130d may include the same information as power information 130a, more or less information than power information 130a, or different information from power information 130a. Global conditions may correspond to the same threshold as local conditions or may have different dependencies. In some embodiments, power information 130b to 130d may include an indication of whether the corresponding SoC 101b to SoC 101d meets its local conditions for entering reduced power mode.

[0084] In some embodiments, exchanging power information 130 is performed after SoC 101a determines that the local condition is met. In response to the determination, method 700 may include SoC 101a sending a request to SoC 101b to SoC 101d to enter a reduced power mode. SoC 101a may then receive corresponding power information 130b to 130d from SoC 101b to SoC 101d, and determine whether the received power information 130b to 130d meets the global condition. In such an embodiment, the power information 130b to 130d received from SoC 101b to SoC 101d may include approval or rejection of SoC 101a entering the reduced power mode.

[0085] In some embodiments, method 700 may end at block 730, where SoC 101a places network circuit 110a in reduced power mode in response to determining that other SoCs 101 also meet the conditions for entering reduced power mode. In response to determining that network circuit 110a cannot be placed in reduced power mode, method 700 may return to block 710 to repeat. Note that Figure 7The methods of are merely examples for placing network circuits into a reduced power mode.

[0086] Now go to Figure 8 , a flow chart showing an embodiment of a method for waking up a network circuit that has been placed in a reduced power mode. In a manner similar to method 700 above, method 800 may be implemented by a system including a network implemented on multiple SoCs, such as Figure 1 and Figure 2 The method 800 may be performed after performing the method 700 of causing some or all network circuits in the network circuit to enter a reduced power mode. Figure 1 and Figure 8 , the method 800 begins in block 810 after block 730 of the method 700 has been performed and the network circuit 110 of the system 100 has been placed in a reduced power mode.

[0087] At block 810, method 800 includes determining, by SoC 101d, that a particular transaction to be sent has a destination within SoC 101a. As shown, power management circuit 120d receives an indication that a particular transaction is ready to be sent from SoC 101d to an agent in SoC 101a. In various embodiments, the indication may be received from a source agent, from a portion of network circuit 110d that remains active in a reduced power mode, a local network switch in SoC 101d, and the like.

[0088] At block 820, method 800 further includes causing, by SoC 101d, network circuit 110d of network 105 to exit the reduced power mode. In response to the indication of the specific transaction, power management circuit 120d restores power signals and / or clock signals in network circuit 110d, thereby causing network circuit 110d to wake up from the reduced power mode.

[0089] At block 830, the method 800 further includes asserting, by the SoC 101d, a wake-up signal via the network 105. The network circuit 110d may send an indication to the power management circuit 1120d that the network circuit has entered the operational mode. In response, the power management circuit 120d may cause the network circuit 110d to send a wake-up signal (e.g., Figure 3 The network circuit 110d may utilize any suitable method for sending a wake-up signal, including the method described above with respect to Figure 6 The method described.

[0090] At block 840, the method 800 further includes sending, by the SoC 101d, a specific transaction to the SoC 101a in response to receiving the confirmation from the SoC 101a. In response to the wake-up signal from the network circuit 110d, the network circuit 110a wakes up from the reduced power mode. After the power signal and / or the clock signal have recovered to their operating levels, the network circuit 110a sends a confirmation to the network circuit 110d, indicating that the network circuit 110a is operational and able to receive transactions. In response to the confirmation, the specific transaction is sent from the network circuit 110d to the network circuit 110a.

[0091] In some embodiments, method 800 may end in block 840, and operation of the system may return to method 700. Network circuits 110a and 110d may continue to remain active, exchanging packets associated with the particular transaction, until the transaction is completed.

[0092] The use of such power management techniques as described in methods 700 and 800 and shown in the remainder of this disclosure can implement power reduction techniques in multi-SoC systems with complex distributed network fabrics. Such complex network fabrics can consume a lot of power when enabled. Power reduction techniques such as described can reduce power consumption, thereby extending battery life and / or reducing heat levels within the system.

[0093] Please note that Figure 7 and Figure 8 The method is merely an example for managing the power mode of network circuits in a shared network. Variations of the disclosed method are contemplated, including combinations of the operations of methods 700 and 800, such as in Figure 2 The methods are shown to be performed simultaneously in the case where more than one network is used to couple the SoCs.

[0094] Figures 1 to 8 Apparatus and methods for systems including encoding and decoding data packets sent between two or more interface circuits are shown. Any embodiments of the disclosed logic computing system may be included in one or more of a variety of computer systems, such as desktop computers, laptop computers, smart phones, tablet computers, wearable devices, etc. In some embodiments, the above circuits (e.g., SoC 101) may be implemented on one or more integrated circuits. Fig. 9 A block diagram illustrating an embodiment of computer system 900 is shown in . In some embodiments, computer system 900 may include any of the disclosed embodiments of systems 100 and 200 .

[0095] In the illustrated embodiment, system 900 includes two or more instances of SoC 906 (corresponding to, for example, any or all SoCs in SoC 101), which may include various types of processing circuits, such as a central processing unit (CPU), a graphics processing unit (GPU), or other communication fabrics, as well as interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 906 include multiple execution lanes and instruction issue queues. In various embodiments, SoC 906 is coupled to external memory 902, peripherals 904, and power source 908. In an embodiment, SoC 906 can be implemented using a combination of SoCs 101 coupled together through networks 105 and / or 205 to operate as a single SoC.

[0096] A power source 908 is also provided that supplies a supply voltage to the SoC 906 and one or more supply voltages to the memory 902 and / or peripherals 904. In various embodiments, the power source 908 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet computer, or other device). In some embodiments, more than one instance of the SoC 906 is included (and more than one external memory 902 is also included).

[0097] The memory 902 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to the circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the device is mounted with the SoC or integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

[0098] Peripheral devices 904 include any desired circuitry, depending on the type of system 900. For example, in one embodiment, peripheral devices 904 include devices for various types of wireless communications such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, peripheral devices 904 also include additional storage, including RAM storage, solid-state storage, or disk storage. Peripheral devices 904 include user interface devices such as display screens, including touch screens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc.

[0099] As shown, system 900 is shown to be applicable to a wide range of fields. For example, system 900 can be used as a part of a chip, circuit, component, etc. of a desktop computer 910, a laptop computer 920, a tablet computer 930, a cellular or mobile phone 940, or a TV 950 (or a set-top box coupled to a TV). A smart watch and a health monitoring device 960 are also shown. In some embodiments, the smart watch may include various general computing related functions. For example, the smart watch may provide access to email, mobile phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the vital signs of the user, track the proximity of the user to other users for the purpose of epidemiological social distance, contact tracking, provide communications to emergency services in the event of a health crisis, etc. In various embodiments, the above-mentioned smart watch may include or may not include some or any health monitoring related functions. Other wearable devices 960 are also envisioned, such as devices worn around the neck, devices attached to a hat or helmet, devices implantable in the human body, glasses designed to provide enhanced and / or virtual reality experience, and the like.

[0100] The system 900 may also be used as part of a cloud-based service 970. For example, the previously mentioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Still further, the system 900 may be used in one or more devices in a home 980 other than those previously mentioned. For example, a home appliance may monitor and detect noteworthy situations. For example, various devices in a home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device and provide an alert to the homeowner (or, for example, a maintenance agency) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in a home and may automatically adjust the heating / cooling system based on a history of responses by the homeowner to various situations. Fig. 9 Also shown are applications of the system 900 to various modes of transportation 990. For example, the system 900 may be used for control and / or entertainment systems for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), etc. In various cases, the system 900 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc.

[0101] Note that various potential applications of system 900 may include various performance, cost, and power consumption requirements. Therefore, it may be beneficial to enable a scalable solution that can use one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption. These and many other embodiments are possible and contemplated. Note that Fig. 9The devices and applications shown are exemplary only and are not intended to be limiting. Other devices are possible and contemplated.

[0102] As about Fig. 9 As disclosed, computer system 900 may include two or more integrated circuits coupled together and included within a personal computer, smart phone, tablet computer, or other type of computing device. Fig.10 The process for designing and producing integrated circuits using design information is shown in .

[0103] Fig.10 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. Fig.10 Embodiments of the present invention may be used in designing and manufacturing integrated circuits such as Figures 1 to 3 The semiconductor manufacturing system 1020 is used in the process of manufacturing the SoC 101 shown. In the illustrated embodiment, the semiconductor manufacturing system 1020 is configured to process the design information 1015 stored on the non-transitory computer-readable storage medium 1010 and manufacture the integrated circuit 1030 (eg, the SoC 101) based on the design information 1015.

[0104] The non-transitory computer-readable storage medium 1010 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1010 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1010 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1010 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0105] The design information 1015 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1015 may be used by the semiconductor manufacturing system 1020 to manufacture at least a portion of the integrated circuit 1030. The format of the design information 1015 may be recognizable by at least one semiconductor manufacturing system, such as, for example, the semiconductor manufacturing system 1020. In some embodiments, the design information 1015 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in the integrated circuit 1030 may also be included in the design information 1015. Such cell libraries may include information indicating a device or transistor level netlist, mask design data, characterization data, etc. of the cells included in the cell library.

[0106] In various embodiments, integrated circuit 1030 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, design information 1015 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDS) or any other suitable format.

[0107] Semiconductor manufacturing system 1020 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1020 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0108] In various embodiments, integrated circuit 1030 is configured to operate according to the circuit design specified by design information 1015, which may include performing any of the functions described herein. For example, integrated circuit 1030 may include any of the various elements shown or described herein. In addition, integrated circuit 1030 may be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein may be provided by multiple connected integrated circuits (e.g., Figure 4 The integrated circuits 405a and 405b in FIG. 4 are used to perform the above operation.

[0109] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0110] ***

[0111] The present disclosure includes references to "embodiments," which are non-limiting, specific implementations of the disclosed concepts. References to "an embodiment," "one embodiment," "a specific embodiment," "some embodiments," "various embodiments," etc., do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including the specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure. Not all of these embodiments will necessarily exhibit any or all of the potential advantages described herein.

[0112] Unless otherwise stated, the specific embodiments are not intended to limit the scope of the claims drafted based on the disclosure of the disclosed form, even if only a single example is described for a particular feature. Therefore, the embodiments disclosed by the present invention are intended to be illustrative rather than restrictive, without any contrary statement. This patent application is intended to cover such alternatives, modifications and equivalent forms, which will be obvious to those skilled in the art who benefit from this disclosure.

[0113] The particular features, structures or characteristics may be combined in any suitable manner consistent with the present disclosure. Accordingly, the present disclosure is intended to include any feature or combination of such features disclosed herein (explicitly or implicitly), or any generalization thereof. Accordingly, new claims may be made during the prosecution of this patent application (or a patent application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of the dependent claims may be combined with features of the independent claims, and features from the corresponding independent claims may be combined in any suitable manner rather than merely by the specific combinations listed in the appended claims.

[0114] For example, while the appended dependent claims are drafted such that each dependent claim is dependent on a single other claim, additional dependent claims are also contemplated, including the following dependent claims: claim 3 (dependable on any of claims 1-2); claim 4 (any of the preceding claims); claim 5 (claim 4), etc. It is also contemplated that claims drafted in one statutory type (e.g., apparatus) may inspire corresponding claims of another statutory type (e.g., method), where appropriate.

[0115] ***

[0116] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0117] Unless the context clearly dictates otherwise, references to singular forms such as “a,” “an,” and “the” are intended to mean “one or more.” Thus, reference to “an item” in a claim does not exclude additional instances of that item.

[0118] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0119] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0120] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," covering x but not y, y but not x, and both x and y. On the one hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0121] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to encompass all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases encompass any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "... at least one of w, x, y, and z" refers to at least one element of the elements in the set [w, x, y, z], thereby encompassing all possible combinations in the list of options. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0122] In this disclosure, various "labels" may precede a noun. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to a particular feature.

[0123] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a memory storing executable program instructions, and the like. The phrase is not used herein to refer to an intangible thing.

[0124] Hardware circuits may include any combination of the following: combinatorial logic circuits, clock storage devices (such as flip-flops, registers, latches, etc.), finite state machines, memories (such as static random access memory or embedded dynamic random access memory), custom designed circuits, analog circuits, programmable logic arrays, etc. Similarly, for ease of description, various units / circuits / components may be described as performing one or more tasks. Such descriptions should be interpreted as including the phrase "configured to".

[0125] In one embodiment, a hardware circuit according to the present disclosure may be implemented by encoding a description of the circuit in a hardware description language (HDL) such as Verilog or VHDL. The HDL description may be synthesized for a cell library designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that can be transmitted to a factory to generate a mask and ultimately produce an integrated circuit. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design together with a synthesized circuit system. The integrated circuit may include transistors and may also include other circuit elements (e.g., passive elements, such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA.

[0126] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function.

[0127] The phrase "configured to" perform one or more tasks in the appended claims is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution, it will use the phrase "means for [performing the function]" to describe the claim element.

[0128] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, the determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0129] The phrase "in response to" describes one or more factors that trigger an effect. The phrase does not exclude the possibility that other factors may influence or otherwise trigger the effect. That is, the effect may be responsive only to those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." The phrase specifies that B is the factor that triggers the performance of A. The phrase does not exclude that the performance of A may also be responsive to some other factor, such as C. The phrase is also intended to cover embodiments in which A is performed only in response to B.

Claims

1. A system comprising: a plurality of integrated circuits located on respective dies, wherein the plurality of integrated circuits are connected by a network, respective portions of the network being located on different portions of the respective dies, and wherein the plurality of integrated circuits and the network are configured to operate as a single logical computing system; wherein a given integrated circuit of the plurality of integrated circuits comprises a processor circuit configured to access circuit blocks on another integrated circuit of the plurality of integrated circuits using a common bus protocol and to access circuit blocks on the given integrated circuit using the common bus protocol; wherein the plurality of integrated circuits are configured to enter a reduced power mode; wherein a specific integrated circuit among the plurality of integrated circuits is configured as: determining that a particular circuit block in the particular integrated circuit has requested to send a transaction to a different circuit block in a different integrated circuit in the plurality of integrated circuits; waking up a network circuit in the specific integrated circuit from a reduced power mode; as well as A wake-up signal is asserted using the network circuit to a node coupled to the different integrated circuit.

2. The system of claim 1 , wherein to enter the reduced power mode, a master integrated circuit of the plurality of integrated circuits is configured to: determining whether conditions for entering a reduced power mode are met across the plurality of integrated circuits; and In response to determining that the condition is satisfied, a request is sent to remaining integrated circuits of the plurality of integrated circuits to enter a reduced power mode. 3 . The system of claim 1 , wherein a corresponding integrated circuit of the plurality of integrated circuits is a corresponding system-on-chip of a plurality of systems-on-chips.

4. The system of claim 1, wherein the specific integrated circuit is further configured to: receiving an acknowledgement of the wake-up signal from the different integrated circuit; and In response to the acknowledgement, a transaction is sent to the different circuit block.

5. The system of claim 1 , wherein the node is coupled to each integrated circuit of the plurality of integrated circuits; and Wherein asserting the wake-up signal causes an integrated circuit among the plurality of integrated circuits that is currently in a reduced power mode to exit the reduced power mode.

6. The system of claim 5, wherein the specific integrated circuit is further configured to: receiving corresponding acknowledgements of the wake-up signal from other integrated circuits of the plurality of integrated circuits; and In response to receiving an acknowledgement from each of the other integrated circuits, the transaction is sent to the other integrated circuits via the network. 7 . The system of claim 5 , wherein to assert the wake-up signal, the particular integrated circuit is configured to use the network circuit to generate a transition on one or more address lines included in the network.

8. A method comprising: entering a reduced power mode by a plurality of integrated circuits located on a respective die, wherein the plurality of integrated circuits are connected by a network implemented across the respective die; accessing, by a processor circuit in a given integrated circuit in the plurality of integrated circuits, a circuit block on another integrated circuit in the plurality of integrated circuits using the same bus protocol as used to access a circuit block on the given integrated circuit; determining, by power management circuitry of a particular integrated circuit of the plurality of integrated circuits, that a destination of a transaction to be sent from within the particular integrated circuit is within a different integrated circuit of the plurality of integrated circuits, wherein the power management circuitry is active in a reduced power mode; waking up the specific integrated circuit from a reduced power mode by the power management circuit; as well as A wake-up signal is asserted by the particular integrated circuit via the network at a node coupled to a wake-up signal pin of the different integrated circuit.

9. The method of claim 8, further comprising accessing, by software executed on a first integrated circuit of the plurality of integrated circuits, a circuit block on a second integrated circuit of the plurality of integrated circuits in the same manner as the circuit block on the first integrated circuit is accessed.

10. The method of claim 8, wherein determining the destination of the transaction is within the different integrated circuit comprises: determining, by a network switch circuit coupled to an internal bus of the particular integrated circuit, that the destination address of the transaction indicates the use of a network circuit in the particular integrated circuit, wherein the network circuit is coupled to the network; and An indication that the network circuit needs to be used is sent to the power management circuit.

11. The method of claim 8, wherein asserting the wake-up signal comprises transitioning a logic level on a dedicated wake-up pin of the particular integrated circuit, wherein the dedicated wake-up pin is coupled to a corresponding wake-up pin of at least the different one of the plurality of integrated circuits.

12. The method of claim 8, wherein entering a reduced power mode comprises: determining, by a master integrated circuit among the plurality of integrated circuits, whether a condition for entering a reduced power mode is satisfied across the plurality of integrated circuits; as well as In response to determining that the condition is satisfied, a request is sent by the master integrated circuit to the remaining integrated circuits of the plurality of integrated circuits to enter a reduced power mode.

13. The method according to claim 8, further comprising: In response to asserting the wake-up signal, causing one or more circuit blocks of the different integrated circuit to exit a reduced power mode via power management circuitry in the different integrated circuit; as well as In response to determining that the different integrated circuit is ready to receive the transaction, an acknowledgement is sent to the particular integrated circuit.

14. The method of claim 13, further comprising sending the transaction to the different integrated circuit by the particular integrated circuit in response to receiving the acknowledgement from the different integrated circuit.

15. An integrated circuit comprising: a specific circuit block, the specific circuit block being configured to generate transactions to be sent to other circuit blocks; A network circuit, wherein the network circuit is configured to: forming part of a network when coupled with other compatible network circuits located on different integrated circuits; and circuit-switching a plurality of transactions with said other compatible network; A power management circuit, the power management circuit being configured to: In response to determining that the condition is satisfied, causing the network circuit to enter a reduced power mode; receiving, via the network, from the specific circuit block a request to send a specific transaction to a different circuit block; and waking up the network circuitry from a reduced power mode; and The network circuit is further configured to assert a wake-up signal on a node coupled to a different network circuit coupled to the different circuit block in response to the wake-up.

16. The integrated circuit of claim 15, wherein the network circuit is further configured to: receiving an acknowledgement of the wake-up signal from the different network circuit; and In response to the confirmation, the particular transaction is sent to the different circuit block via the different network circuit.

17. The integrated circuit of claim 15, wherein the network circuit is further configured to: in response to assertion of the wake-up signal, receiving from the subset of the other compatible network circuits a respective acknowledgement of the wake-up signal; and In response to determining that acknowledgements have been received from a threshold number of the other compatible network circuits, the particular transaction is sent to the different circuit block via the different network circuit.

18. The integrated circuit of claim 15, further comprising a network switch circuit coupled to the specific circuit block and configured to: Remain active in reduced power modes; detecting the request from the specific circuit block via an internal bus of the integrated circuit; and An indication of the request from the particular circuit block is provided to the power management circuitry.

19. The integrated circuit of claim 15, wherein to assert the wake-up signal, the network circuit is configured to generate a transition on one or more address lines included in the network.

20. The integrated circuit of claim 15, further comprising a processor circuit configured to access a different circuit block coupled to the other compatible network circuit using the same network protocol as used to access the particular circuit block.

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