Data storage device, data storage system, and controller

Abstract

The present disclosure relates to a data storage device, a data storage system, and a controller that detect a defective memory region based on operation information of a memory region included in a memory system and allocated to a host device, and transmit a warning signal to the host device to which the defective memory region is allocated, and excluding the defective memory region from the pool of distributable memory regions to reduce or prevent data loss that may occur due to the defective memory region by a host device using the memory region of the memory system.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0089489, filed on Jul. 11, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology generally relate to a data storage system (eg, a memory system) and a controller (eg, a memory controller). Background Art

[0004] A memory system (or data storage system) may include one or more memory devices, each of which includes a plurality of memory cells configured to store data. In some embodiments, the memory system may also include a memory controller configured to control the operation of the one or more memory devices.

[0005] The memory system may allocate or unallocate one or more memory regions included in one or more memory devices according to a request of a host device. The memory system may perform a memory operation such as a write operation, a read operation, or an erase operation on one or more memory regions allocated to the host device according to a request of the host device.

[0006] Because errors occurring in a memory region allocated to a host device may result in data loss to the host device, error handling is an important component of the overall reliability of the memory system. Summary of the invention

[0007] Various embodiments of the disclosed technology are directed to providing measures capable of predicting the occurrence of an error in a memory area included in a memory and preventing loss of data stored in the memory area.

[0008] In an embodiment, a memory system may include: a plurality of memory devices, each memory device including a plurality of memory areas configured to store data; at least one memory controller communicating with the plurality of memory devices and a plurality of host devices and configured to control the operation of each of the plurality of memory devices in response to requests for memory operations from the plurality of host devices; and a memory management module configured to communicate with at least one of the plurality of memory devices, the plurality of host devices, or the at least one memory controller and configured to allocate one or more memory areas of a plurality of memory areas of one or more memory devices of the plurality of memory devices to the one or more host devices in response to allocation requests from one or more host devices of the plurality of host devices, and to send a warning signal to a first host device of the one or more host devices when identifying that a memory area allocated to a first host device of the one or more host devices is a defective memory area predicted to have an error.

[0009] In an embodiment, a data storage system may include: a plurality of storage devices, including a plurality of memory devices, each memory device including a plurality of memory areas configured to store data; and a memory management device, located outside the plurality of storage devices and configured to allocate one or more of the plurality of memory areas in response to an allocation request from one or more of a plurality of host devices, and, when a defective memory area predicted to have an error is identified, send a warning signal to a first host device among the plurality of host devices to which the defective memory area is allocated.

[0010] In an embodiment, a control unit may include: at least one memory controller configured to control the operation of multiple memory devices, each memory device including multiple memory areas configured to store data; and a memory management module configured to allocate one or more memory areas of the multiple memory areas to one or more host devices in response to an allocation request from one or more host devices among a plurality of host devices, and when a memory area allocated to a first host device among the one or more host devices is identified as a defective memory area predicted to have an error, send a warning signal to a host device among the multiple host devices to which the defective memory area is allocated.

[0011] In an embodiment, a memory system may include: a plurality of memory devices, each memory device including a plurality of memory areas; at least one memory controller configured to control the operation of each of the plurality of memory devices; and a memory management module configured to allocate some memory areas among the plurality of memory areas corresponding to a host device among the plurality of host devices that has sent the allocation request in response to an allocation request from each of the plurality of host devices, and when a defective memory area predicted to have an error is identified among the plurality of memory areas, send a warning signal to a first host device among the plurality of host devices to which the defective memory area is allocated.

[0012] In an embodiment, a memory system may include: a plurality of memory devices, each memory device including a plurality of memory areas; at least one memory controller configured to control the operation of each of the plurality of memory devices; and a memory management module configured to allocate memory areas in response to an allocation request from each of a plurality of host devices, identify defective memory areas based on error occurrence prediction information received from at least one of the plurality of host devices, and allocate memory areas other than the defective memory areas as memory areas corresponding to the host devices that sent the allocation requests according to the allocation requests of the plurality of host devices.

[0013] In an embodiment, a data storage system may include: a plurality of storage devices, including a memory device, each memory device including a plurality of memory areas; and a memory management device, located outside the plurality of storage devices and configured to allocate memory areas according to an allocation request of each of a plurality of host devices, and when a defective memory area predicted to have an error is identified among the memory areas, send a warning signal to a first host device among the plurality of host devices to which the defective memory area is allocated.

[0014] In an embodiment, a data storage device may include: a plurality of memory devices, each memory device including a plurality of memory areas; and a memory controller configured to control the operation of each of the plurality of memory devices and migrate data stored in a defective memory area among the plurality of memory areas, where an error is predicted to occur, to a new memory area according to a command received from the outside.

[0015] In an embodiment, a control unit may include: at least one memory controller configured to control the operation of each of a plurality of memory devices, each memory device including a plurality of memory areas; and a memory management module configured to allocate memory areas according to an allocation request of each of a plurality of host devices, and when a defective memory area predicted to have an error is identified among the memory areas, send a warning signal to a host device among the plurality of host devices to which the defective memory area is allocated.

[0016] According to an embodiment of the disclosed technology, since the occurrence of errors in a memory area included in a memory is predicted, and allocation information of the memory area where the error is predicted to occur and data stored in the corresponding memory area are managed in advance, defects caused by errors in the memory area can be prevented or reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a diagram showing an example of a configuration of a memory system based on an embodiment of the disclosed technology.

[0018] Figures 2 to 4 An example is shown of how a memory system based on an embodiment of the disclosed technology allocates and de-allocates a memory area according to a request of a host device.

[0019] Figure 5 is a diagram showing an example in which a memory system according to an embodiment of the disclosed technology allocates a memory area to a host device.

[0020] Figure 6 is a diagram illustrating example operations performed when a memory system based on an embodiment of the disclosed technology predicts that an error occurs in a memory area.

[0021] Figure 7 is a diagram illustrating example operations performed when a memory system based on an embodiment of the disclosed technology performs prediction of occurrence of an error in a memory region.

[0022] Figure 8 is a diagram illustrating an example operation performed according to a command of a host device after a memory system based on an embodiment of the disclosed technology predicts that an error occurs in a memory area.

[0023] Fig. 9 is a diagram illustrating an example of memory area management performed when a memory system based on an embodiment of the disclosed technology predicts that an error occurs in a memory area.

[0024] Fig.10 is a diagram illustrating an example in which a memory system according to an embodiment of the disclosed technology allocates and de-allocates a memory area according to a request of a host device.

[0025] Fig.11 is a diagram showing an example configuration of a memory system based on an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0026] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings in which is shown by way of illustration specific examples or implementations that may be practiced.

[0027] Figure 1 is a diagram showing an example of a configuration of a memory system 200 based on an embodiment of the disclosed technology.

[0028] Reference Figure 1 , a memory system 200 based on an embodiment of the disclosed technology may include, for example, a control unit 210 and a plurality of memory devices 220 .

[0029] Each of the plurality of memory devices 220 may be, for example, a volatile memory, such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, but the disclosed technology is not limited thereto. In some implementations, each of the plurality of memory devices 220 may be a non-volatile memory. In addition, in some embodiments, the disclosed technology may be implemented as only one memory device 220 is included in the memory system 200.

[0030] The memory system 200 may allocate or unallocate memory areas included in the plurality of memory devices 220 according to a request of the externally located host device 100. The memory system 200 may perform an operation of writing data into a memory area allocated to the host device 100 or erasing data in a memory area allocated to the host device 100, or perform an operation of reading data from a memory area allocated to the host device 100, according to a request of the host device 100.

[0031] For example, the memory system 200 may allocate memory areas included in the plurality of memory devices 220 when communicating with one host device 100. Alternatively, the memory system 200 may allocate memory areas included in the plurality of memory devices 220 when communicating with at least two host devices 100. Figure 1 The example shown in shows a case where the memory system 200 allocates memory areas included in the plurality of memory devices 220 when communicating with N host devices 100_1 (Host_1), 100_2 (Host_2), 100_3 (Host_3), . . . , 100_N (Host_N) (N is a positive integer).

[0032] For example, the host device 100 may be a computer, an ultra mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage constituting a data center, one of various electronic devices constituting a home network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, a motorized device capable of driving under human control or automatically driving (e.g., a vehicle, a robot, or a drone), etc. Optionally, the host device 100 may be a virtual / augmented reality device that provides a 2D or 3D virtual reality image or an augmented reality image. The host device 100 is not limited to the above examples, and may also be any of various electronic devices that require a memory system 200 capable of storing data.

[0033] The host device 100 may include at least one operating system. The operating system may manage and control all functions and operations of the host device 100. The operating system may control the interoperation between the host device 100 and the memory system 200. According to the portability of the host device 100, the operating system may be classified into a general operating system and a mobile operating system.

[0034] The host device 100 and the memory system 200 may be collectively referred to as a computing system.

[0035] The host device 100 may perform communication with the memory system 200 through a preset interface.

[0036] For example, the host device 100 may communicate with the memory system 200 via a high-speed computing link (Compute Express Link, CXL) interface. Compute Express Link (CXL) is an open standard interconnect that maintains a unified memory space and high-speed communication between a host processor and attached devices and systems (e.g., memory devices and systems). Since the host device 100 communicates with the memory system 200 via the CXL interface, a low-latency high-bandwidth access environment can be implemented in a structure that communicates with the memory system 200 including a plurality of large-capacity memory devices 220.

[0037] Alternatively, in some embodiments, the host device 100 may communicate with the memory system 200 via an interface other than the CXL interface.

[0038] For example, the host device 100 and the memory system 200 can communicate through at least one of various interface protocols such as: USB (Universal Serial Bus) protocol, MMC (MultiMedia Card) protocol, PCI (Peripheral Component Interconnect) protocol, PCI-E (PCI-Express) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol and IDE (Integrated Drive Electronics) protocol, but not limited to these.

[0039] As described above, the type and number of host devices 100 that perform communication with the memory system 200 and the communication interface between the host device 100 and the memory system 200 based on the embodiments of the disclosed technology can be various, but hereinafter, as an example, a case where two or more host devices 100 communicate with the memory system 200 through a CXL interface will be described.

[0040] The control unit 210 included in the memory system 200 may perform a required operation according to a request or command received from a plurality of host devices 100 .

[0041] The control unit 210 may include, for example, at least one memory controller 211 and a memory management module (PMM) 212. The control unit 210 may include a supplementary memory (SubM) 213, and communication within the control unit 210 may be performed through a bus 214.

[0042] At least one memory controller 211 may control operations of the plurality of memory devices 220 .

[0043] For example, the memory controller 211 may write data into or erase data from memory areas of the plurality of memory devices 220 or read data from memory areas of the plurality of memory devices 220 according to a command input from the outside.

[0044] The memory controller 211 may provide a channel through which commands and data input from the outside and data stored in the memory device 220 are transmitted and received. One memory controller 211 may control two or more memory devices 220, or memory controllers 211 respectively corresponding to two or more memory devices 220 may control the corresponding memory devices 220.

[0045] Figure 1The example shown in FIG. 2 shows a case where the memory system 200 includes two or more M memory devices 220_1, 220_2, 220_3, ..., 220_M and M memory controllers 211_1 (MC_1), 211_2 (MC_2), 211_3 (MC_3), ..., 211_M (MC_M) respectively corresponding to the M memory devices 220_1, 220_2, 220_3, ..., 220_M are included in the control unit 210 (M is a positive integer). Since the M memory controllers 211_1, 211_2, 211_3, ..., 211_M respectively corresponding to the M memory devices 220_1, 220_2, 220_3, ..., 220_M control the respective operations of the M memory devices 220_1, 220_2, 220_3, ..., 220_M, the data processing speed of the memory system 200 can be improved. In some embodiments, M memory devices 220_1, 220_2, 220_3, ..., 220_M may be included in a memory pool. In some embodiments, the disclosed technology may be implemented using a memory pool technology that allows multiple computing nodes (e.g., processors and memory controllers) to access multiple memory devices in an on-demand manner, thereby providing flexible and efficient access to greater memory bandwidth and capacity.

[0046] For example, the memory controller 211 may perform a read operation to read data from the memory device 220 , and may detect and correct errors in the read data using, for example, error correction techniques.

[0047] In some embodiments, the memory controller 211 may include an error detection and correction circuit. When reading data stored in the memory device 220, a read operation may be performed using a preset read voltage. When the read operation fails, the error detection and correction circuit may perform an error correction operation.

[0048] For example, the error detection and correction circuit may detect error bits in the target data and correct the detected error bits by using an error correction code. The target data may be data read from the memory device 220 or data stored in a working memory different from the memory device 220 .

[0049] The error detection and correction circuit can detect error bits in units of sectors for each read data. Sectors constituting each read data can be mapped to each other by addresses.

[0050] The error detection and correction circuit can calculate the bit error rate in units of sectors and can determine whether the error is correctable. For example, when the bit error rate is lower than a reference value, the error detection and correction circuit can determine that the corresponding sector is correctable and can mark the corresponding sector with "pass". When the read data is recovered by performing an error correction operation using the error detection and correction circuit, the recovered data can be sent to the outside.

[0051] When the bit error rate is higher than a reference value, the error detection and correction circuit may determine that the corresponding sector is uncorrectable and may mark the corresponding sector with “failure”.

[0052] In some implementations, the error detection and correction circuitry can detect one or more uncorrectable or "failed" sectors by performing error detection and correction operations on all read data. The error detection and correction circuitry can output information (eg, address information) regarding the one or more uncorrectable sectors.

[0053] Information regarding error correction operations performed by the error detection and correction circuitry may be maintained, managed, and / or sent externally by the memory controller 211 .

[0054] The memory management module 212 may control the operation of the memory controller 211 .

[0055] The memory management module 212 may control allocation or de-allocation of a memory area included in the memory device 220 according to a command received from the host device 100 .

[0056] The memory management module 212 may transfer commands and data received from the host device 100 to the memory controller 211 that controls the corresponding memory device 220. In some embodiments, the memory management module 212 may be a switching module configured to transfer commands received from the host device 100 to the memory controller 211 or the memory device 220, or may be a part of the switching module.

[0057] The control unit 210 may include an auxiliary memory 213. The memory management module 212 may store information in the auxiliary memory 213 that may be used by the memory controller 211 or the memory device 220 for memory management purposes. The auxiliary memory 213 may be, for example, an SRAM, but the disclosed technology is not limited thereto.

[0058] The memory management module 212 may allocate or unallocate a memory area according to a request of the host device 100. In addition, the memory management module 212 may detect a memory area where an error is predicted to occur by using information about an error detection and correction operation performed by the memory controller 211.

[0059] In various implementations, at least one of the memory management module 212 or the memory controller 211 may be coupled to communicate with one or more host devices, including receiving requests from a host device.

[0060] Figures 2 to 4 An example is shown of how the memory system 200 according to an embodiment of the disclosed technology allocates and de-allocates a memory area according to a request of the host device 100 .

[0061] Reference Figures 2 to 4 In some embodiments, the memory system 200 allocates or de-allocates a memory region included in the memory device 220 according to a request received from a first host device 100_1 and a second host device 100_2 among the plurality of host devices 100 .

[0062] Figures 2 to 4 The term "memory section" used in the specification may indicate a memory area and may include two or more memory cells or two or more memory blocks. Figures 2 to 4 An example is shown where the size of the memory segment is 128 MB, but the disclosed technology is not limited thereto.

[0063] For example, the memory system 200 may allocate or de-allocate memory regions by treating memory regions of a plurality of memory devices 220 included in the memory system 200 as being included in one memory device 220 .

[0064] Reference Figure 2 In operation (1), the memory system 200 may receive an allocation request for two memory regions from the first host device 100_1. In operation (2), the memory system 200, for example, the memory management module 212 included in the memory system 200, may allocate memory region 0 and memory region 1 among the memory regions included in the plurality of memory devices 220 to the first host device 100_1. In one example, the memory region 0 and the memory region 1 may be from the same memory device. In another example, the memory region 0 and the memory region 1 may be from different memory devices.

[0065] The memory management module 212 may store occupation information that the memory area 0 and the memory area 1 are allocated to the first host device 100_1 in the auxiliary memory 213. For example, as the occupation information about the memory area 0 and the memory area 1, the identification number of the first host device 100_1 may be stored.

[0066] When memory area 0 and memory area 1 are allocated to the first host device 100_1, the first host device 100_1 may send a command for writing data into memory area 0 and memory area 1, erasing data from memory area 0 and memory area 1, or reading data from memory area 0 and memory area 1 to the memory system 200.

[0067] The memory management module 212 may transmit corresponding commands or data to the memory controller 211 , and the memory controller 211 controls the operation of the memory device 220 including the memory area 0 and the memory area 1 .

[0068] In some embodiments, the memory system 200 may de-allocate a memory region allocated to the first host device 100_1 in response to a de-allocation request received from the first host device 100_1.

[0069] Reference Figure 3 In operation (3), the memory system 200 may receive a deallocation request for a memory region from the first host device 100_1.

[0070] The memory management module 212 may perform deallocation of the memory region 1 according to the deallocation request received from the first host device 100_1. The memory management module 212 may update the occupancy information to mark the memory region 1 with an unallocated memory region.

[0071] The memory system 200 may perform an operation according to a request or a command received from a second host device 100_2 different from the first host device 100_1.

[0072] Reference Figure 4 , in operation (4), the memory system 200 may receive an allocation request for three memory regions from the second host device 100_2.

[0073] When receiving an allocation request from the second host device 100_2 , the memory management module 212 may allocate a memory area based on occupancy information about a memory area included in the memory device 220 .

[0074] Reference Figure 4 In operation (5), according to the allocation request of the second host device 100_2, the memory management module 212 may allocate the memory area 1, the memory area 2, and the memory area 3 to the second host device 100_2. The memory management module 212 may update the occupation information about the memory area 1, the memory area 2, and the memory area 3 to indicate that the memory area 1, the memory area 2, and the memory area 3 are allocated to the second host device 100_2.

[0075] In some embodiments, data is written to memory area 1, memory area 2, and memory area 3, or data is read or erased from memory area 1, memory area 2, and memory area 3 in response to a command of the second host device 100_2.

[0076] A memory area included in the memory device 220 may be allocated by the memory management module 212 , and the allocated memory area may be used by the host device 100 .

[0077] The memory management module 212 can monitor the operation information of the allocated memory area and predict the occurrence of errors in the memory area. In this way, data loss of the host device 100 due to errors in the allocated memory area can be prevented.

[0078] Figure 5 is a diagram showing an example in which the memory system 200 according to the embodiment of the disclosed technology allocates a memory area to the host device 100 . Figure 6 is a diagram illustrating an example operation performed when the memory system 200 based on an embodiment of the disclosed technology predicts an error occurring in a memory region.

[0079] Reference Figure 5 As in the above example, the memory management module 212 of the memory system 200 may allocate memory areas included in the plurality of memory devices 220 according to allocation requests of the plurality of host devices 100 .

[0080] For example, according to an allocation request of the first host device 100_1 , a portion of a memory area included in the first memory device 220_1 among the plurality of memory devices 220 may be allocated to the first host device 100_1 .

[0081] According to the allocation request of the second host device 100_2, a portion of the memory area included in the first memory device 220_1 and a portion of the memory area included in the second memory device 220_2 may be allocated to the second host device 100_2.

[0082] According to the allocation request of the third host device 100_3, a portion of the memory area included in the second memory device 220_2 and the entire memory area included in the third memory device 220_3 may be allocated to the third host device 100_3.

[0083] The memory areas included in the plurality of memory devices 220 may be allocated in sequence or out of sequence, and may be allocated in various ways according to allocation requests and de-allocation requests received from the host device 100 .

[0084] In a state where the memory area is allocated to the first host device 100_1, the second host device 100_2, and the third host device 100_3, data may be written to or erased from the allocated memory area according to a command of each host device 100. In addition, data stored in the allocated memory area may be read according to a command of each host device 100.

[0085] The memory management module 212 may receive operation information from the memory controller 211 that controls the operation of each memory device 220, and may perform analysis of error occurrence prediction associated with a memory area included in the memory device 220 based on the operation information. In some embodiments, the operation information may indicate information obtained according to the operation of the memory device 220, or information obtained according to a control operation of the memory controller 211 for the operation of the memory device 220. The operation information may include error detection information or error detection and correction information indicating an error in the memory device 220, or information that may be used to detect an error of the memory device 220.

[0086] For example, refer to Figure 6 , the memory management module 212 may receive operation information from each of the plurality of memory controllers 211 .

[0087] For example, the memory management module 212 may periodically receive operation information from each of the plurality of memory controllers 211 .

[0088] Optionally, when each of the plurality of memory controllers 211 generates an interrupt signal, the memory management module 212 may receive operation information from the memory controller 211 that generated the interrupt signal. Each of the plurality of memory controllers 211 may generate an interrupt signal when generating operation information about error occurrence analysis, and may send corresponding operation information to the memory management module 212.

[0089] Optionally, the memory management module 212 may send a signal requesting operation information to at least a portion of the plurality of memory controllers 211, and may receive operation information provided by the memory controller 211 in response to the signal requesting operation information. The memory management module 212 may determine a time point at which the operation information is needed based on at least one of the allocation information, the usage frequency, or the usage cycle of each of the plurality of memory devices 220, and may request the operation information at the corresponding time point.

[0090] The memory management module 212 may detect a memory region predicted to have an error among memory regions included in the plurality of memory devices 220 based on operation information received from the plurality of memory controllers 211. The memory region predicted to have an error may be referred to as a defective memory region.

[0091] When performing an operation of reading data stored in a memory region, the memory management module 212 may receive operation information about whether an error has been corrected and the number of error corrections from the memory controller 211 and may detect a defective memory region based on the corresponding operation information.

[0092] For example, when reading data stored in the memory area, the memory controller 211 may transmit information on error correction performed by the above-mentioned error detection and correction circuit to the memory management module 212 .

[0093] For example, the memory management module 212 may detect a defective memory region based on the number of error correction operations. The memory management module 212 may detect a memory region whose number of error correction operations is equal to or greater than a preset threshold as a defective memory region.

[0094] The memory management module 212 may detect a portion of the memory region adjacent to the defective memory region as the defective memory region.

[0095] For example, the memory management module 212 may detect a memory region that is adjacent to a defective memory region and performs an error correction operation a number of times equal to or greater than a preset reference value as a defective memory region. The preset reference value may be a value less than a preset threshold value. When the number of occurrences of the error correction operation of the memory region adjacent to the defective memory region is less than the preset threshold value but equal to or greater than the preset reference value, the corresponding memory region may be detected as a defective memory region.

[0096] The memory management module 212 may detect a memory region where an uncorrectable error occurs or a portion of a memory region adjacent to the memory region as a defective memory region.

[0097] In some embodiments, the memory management module 212 may detect a memory region in which an error is predicted to occur by using information obtained by the memory controller 211 according to the operation of the memory device 220 including the memory region allocated to the host device 100 .

[0098] When a defective memory area is detected, the memory management module 212 may store and manage information about the defective memory area in the auxiliary memory 213 .

[0099] Alternatively, in some embodiments, the memory controller 211 may detect a defective memory area and send information about the detected defective memory area to the memory management module 212. In some embodiments, the memory controller 211 detects the defective memory area in a manner similar to the above-described scheme in which the memory management module 212 detects the defective memory area. The memory management module 212 may receive information about the defective memory area detected by the memory controller 211 from the memory controller 211. The memory management module 212 may perform a control operation based on the information about the defective memory area received from the memory controller 211.

[0100] Alternatively, in some embodiments, the host device 100 may obtain information about error correction in the process of reading data from the memory device 220, and may detect a defective memory area where an error is predicted to occur based on the obtained information about error correction. Since the host device 100 may obtain information about error correction when reading data, the host device 100 may use the corresponding information to detect a defective memory area. Since the host device 100 may detect a defective memory area during a read operation, the host device 100 may check whether a memory area assigned to the host device 100 is a defective memory area. Alternatively, in some embodiments, the host device 100 may perform a read operation on a memory area assigned to another host device 100. In this case, during a read operation on a memory area assigned to another host device 100, the host device 100 may check whether the corresponding memory area is a defective memory area.

[0101] When a defective memory area is detected through analysis by the host device 100 , the host device 100 may transmit information about the defective memory area to the memory system 200 .

[0102] In some embodiments, the memory system 200 may store information about a defective memory region received from the host device 100 in the auxiliary memory 213 .

[0103] When a defective memory region is detected, the memory management module 212 may perform a separate control operation on the defective memory region to preserve or recover data stored in the defective memory region.

[0104] Figure 7 is a diagram illustrating an example operation performed when the memory system 200 based on an embodiment of the disclosed technology predicts an error occurring in a memory region.

[0105] Reference Figure 7The memory management module 212 may detect the defective memory area based on operation information obtained from the memory controller 211 that controls the operation of the memory device 220. Alternatively, the memory management module 212 may receive information about the defective memory area from the memory controller 211 or the host device 100.

[0106] When the memory management module 212 detects a defective memory area, the memory management module 212 may detect the defective memory area where an error is predicted to occur based on the number of error corrections performed when reading data stored in the corresponding memory area.

[0107] Figure 7 An example is shown in which a portion of a memory area included in the first memory device 220_1 is detected as a defective memory area.

[0108] When a portion of the memory area included in the first memory device 220_1 is detected as a defective memory area, the memory management module 212 may identify the host device 100 to which the defective memory area is allocated based on the occupancy information stored in the auxiliary memory 213 .

[0109] Figure 7 An example is shown in which a memory area allocated to the first host device 100_1 among the memory areas included in the first memory device 220_1 is detected as a defective memory area.

[0110] The memory management module 212 may transmit a warning signal regarding detection of the defective memory region to the first host device 100_1 to which the defective memory region is allocated.

[0111] In some embodiments, the disclosed technology may be implemented to send a warning signal about the detection of a defective memory area to a first host device 100_1 to which a defective memory area predicted to have an error is allocated. In this way, the memory management module 212 may provide the first host device 100_1 with an opportunity to identify the state of a defective memory area allocated from the memory system 200 and used by the first host device 100_1, and may process data stored in the defective memory area. In some embodiments, the memory management module 212 may also send a warning signal to at least one host device 100 other than the first host device 100_1. Another host device 100 may recognize that a first memory device 220_1 among the memory devices 220 included in the memory system 200 includes a defective memory area.

[0112] The memory management module 212 may send a warning signal including information about whether there is a defective memory area and the address of the defective memory area to the first host device 100_1. Alternatively, the memory management module 212 may include information about the defective memory area such as the possibility of error occurrence, erase / write (E / W) cycles, and whether and the degree of progress of recovery of erroneous or damaged data in the warning signal, or may send such information to the first host device 100_1 through a separate signal after sending the warning signal.

[0113] For example, the memory management module 212 may send a warning signal including at least one of the level and type of the error in the defective memory area to the first host device 100_1. Alternatively, the memory management module 212 may send information about at least one of the level and type of the error in the defective memory area to the first host device 100_1 through a signal different from the warning signal.

[0114] The error level of data in the defective memory area can be classified according to the severity of the error. The severity of the error can be classified based on, for example, the number of times the error detection and correction circuit performs error correction on each page. In one example, the error level depending on the severity of the error can be as follows.

[0115]

[0116] For example, the memory management module 212 may classify errors in the defective memory area into three levels. In one example, the memory management module 212 may send only information about the error level to the first host device 100_1. In another example, the memory management module 212 may send information (e.g., ECC coverage) to the first host device 100_1 as a reference for the error level.

[0117] The first host device 100_1 may determine a management scheme of the defective memory area based on the error level received from the memory management module 212 .

[0118] The error type in the defective memory area can be defined as, for example, a bit (cell) error, a row error, a bank / rank / device error, and a channel error. Since the severity may vary depending on the error type in the defective memory area, the severity can be classified according to the error type. Information about the severity and type of the error can be classified as follows.

[0119]

[0120] The memory management module 212 may transmit information to the first host device 100_1 by including information about the type such as whether the detected error occurs in a single page or in a plurality of pages and whether the type of the error is a row error or a bank error in the warning signal or through a signal different from the warning signal. Since the severity may vary depending on the type of the error, the first host device 100_1 may determine a processing scheme for the defective memory area based on the type and level of the error included in the warning signal.

[0121] When receiving the warning signal from the memory system 200 , the first host device 100_1 may transmit a command for processing data stored in the defective memory area to the memory system 200 .

[0122] For example, when there is no need to use data stored in a defective memory area, the first host device 100_1 may instruct the memory page to be offline.

[0123] In some embodiments, according to a command of the first host device 100_1 , the memory management module 212 of the memory system 200 may stop the operation of the defective memory area allocated to the first host device 100_1 .

[0124] The memory management module 212 may perform deallocation of the defective memory area allocated to the first host device 100_1 or may perform erasing of data stored in the defective memory area.

[0125] In some embodiments, the first host device 100_1 identifies the defective memory region through the memory management module 212 and performs data processing on the defective memory region. In this way, the first host device 100_1 can avoid data loss due to errors in the defective memory region.

[0126] When data stored in the defective memory area needs to be used, the first host device 100_1 may request the memory system 200 to migrate the corresponding data.

[0127] The first host device 100_1 may determine an operation to be performed on the defective memory area based on information about the level or type of the error received through the warning signal. For example, the first host device 100_1 may classify the operations to be performed according to the error level as follows.

[0128]

[0129] Since the first host device 100_1 can determine an operation to be performed on the defective memory area based on the error level or type of the defective memory area received from the memory management module 212, the first host device 100_1 can control an operation conforming to the state of the defective memory area.

[0130] Figure 8 is a diagram illustrating an example operation performed according to a command of the host device 100 after the memory system 200 based on the embodiment of the disclosed technology predicts that an error occurs in a memory area.

[0131] Reference Figure 8 , the memory management module 212 may un-allocate the defective memory area according to a command received from the first host device 100_1 that receives the warning signal, and may stop the operation of the defective memory area.

[0132] Optionally, the memory management module 212 may control an operation of migrating data stored in the defective memory area to other memory areas according to a command received from the first host device 100_1 .

[0133] For example, the first host device 100_1 may request the memory system 200 to migrate data stored in a defective memory area to other memory areas included in the memory system 200 (option 1).

[0134] When receiving a request for data migration within the memory system 200 from the first host device 100_1 , the memory management module 212 may allocate a new memory area included in the memory device 220 to the first host device 100_1 .

[0135] For example, Figure 8 As shown, the memory management module 212 may allocate a portion of the memory area included in the Mth memory device 220_M to the first host device 100_1. According to the allocation of the new memory area, the memory management module 212 may update the occupancy information stored in the auxiliary memory 213.

[0136] When allocating a new memory area, the memory management module 212 may migrate data stored in some memory areas included in the first memory device 220_1 as defective memory areas to some memory areas included in the Mth memory device 220_M.

[0137] When the migration of the data stored in the defective memory area is completed, the memory management module 212 may stop the operation of the defective memory area or erase the data stored in the defective memory area.

[0138] The memory management module 212 may provide information about the newly allocated memory area to the first host device 100_1. The first host device 100_1 may use the newly allocated memory area included in the Mth memory device 220_M.

[0139] As another example, the first host device 100_1 may request the memory system 200 to migrate data stored in the defective memory area to a memory located outside the memory system 200 (Option 2).

[0140] The first host device 100_1 may request to migrate data stored in a defective memory area to a local memory (LocM) 110 adjacent to the first host device 100_1.

[0141] The local memory 110 may be, for example, a volatile memory such as SRAM, DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, but the disclosed technology is not limited thereto.

[0142] The local memory 110 may be provided to each of the plurality of host devices 100. Each of the plurality of host devices 100 may store data using the local memory 110 and a memory area allocated by the memory system 200.

[0143] In some embodiments, according to the migration request of the first host device 100_1, the memory management module 212 may send the data stored in the defective memory area to the local memory 110 adjacent to and controlled by the first host device 100_1.

[0144] When the migration operation of data to the local memory 110 is completed, the memory management module 212 may stop the operation of the defective memory area or erase the data stored in the defective memory area.

[0145] In some embodiments, according to a request of the first host device 100_1 , a portion of data stored in the defective memory area may be migrated to a new memory area in the memory system 200 , and the remaining data may be migrated to the local memory 110 .

[0146] In some embodiments, the memory management module 212 may perform processing on the defective memory region without receiving a request from the first host device 100_1 to which the defective memory region is allocated.

[0147] For example, when sending a warning signal about a defective memory area to the first host device 100_1, the memory management module 212 may migrate data stored in the defective memory area to a new memory area. The memory management module 212 may allocate a new memory area to the first host device 100_1.

[0148] The memory management module 212 may send information about the allocation of the new memory area to the first host device 100_1. For example, the memory management module 212 may modify the mapping information about the defective memory area to the mapping information about the new memory area, and may send the modified mapping information to the first host device 100_1.

[0149] Alternatively, the memory management module 212 may perform processing on the defective memory area after receiving an instruction on whether to use data of the defective memory area from the first host device 100_1.

[0150] For example, when receiving an instruction from the first host device 100_1 not to use data of a defective memory area (eg, an offline memory page), the memory management module 212 may unassign the defective memory area. The memory management module 212 may not perform separate processing on the data stored in the defective memory area.

[0151] As described above, upon receiving an instruction from the first host device 100_1 to use data stored in a defective memory area, the memory management module 212 may migrate the data of the defective memory area to a new memory area. The memory management module 212 may allocate the new memory area to the first host device 100_1, and may send allocation information of the new memory area to the first host device 100_1.

[0152] Since a warning signal is sent to the first host device 100_1 to which the defective memory area is allocated, and according to the request of the first host device 100_1, the operation of the defective memory area is interrupted or the data stored in the defective memory area is migrated, a failure can be prevented from occurring during data processing using the defective memory area by the first host device 100_1.

[0153] When data processing according to the request of the first host device 100_1 to which the defective memory area is allocated is completed, the memory management module 212 may separately manage the defective memory area.

[0154] Fig. 9 is a diagram showing an example of memory area management performed when the memory system 200 based on the embodiment of the disclosed technology predicts the occurrence of an error in the memory area.

[0155] Reference Fig. 9 Through the error occurrence prediction analysis of the memory management module 212, some memory areas of the first memory device 220_1 can be detected as defective memory areas.

[0156] In some embodiments, according to a request of the first host device 100_1 to which the defective memory area is allocated, processing may be performed on data stored in the defective memory area. Alternatively, without a request from the first host device 100_1, processing may be performed by the memory management module 212 on data stored in the defective memory area.

[0157] When processing of data stored in the defective memory area is completed, the memory management module 212 may store and manage information about the defective memory area, for example, in the auxiliary memory 213 .

[0158] When receiving an allocation request from the first host device 100_1, the memory management module 212 may allocate a portion of memory areas among the remaining memory areas except the defective memory area to the first host device 100_1.

[0159] After the memory area allocated to the first host device 100_1 is detected as a defective memory area, the memory management module 212 may allocate a portion of the remaining memory areas except the defective memory area to the second host device 100_2 according to an allocation request of the second host device 100_2.

[0160] The memory management module 212 may exclude the memory region detected as a defective memory region from the pool of allocatable memory regions.

[0161] When allocation requests from a plurality of host devices 100 are received after a defective memory area is detected, the memory management module 212 may allocate a portion of memory areas among the remaining memory areas except the defective memory area to the host device 100 that has sent the allocation request.

[0162] Since a memory area allocated to any host device 100 and detected as a defective memory area is not used by other host devices 100, it is possible to prevent a malfunction from occurring during data processing by other host devices due to allocation of the defective memory area.

[0163] Similar to the case when the memory management module 212 of the memory system 200 detects a defective memory area, even when the host device 100 detects a defective memory area, the defective memory area may be excluded from the allocatable memory area pool.

[0164] For example, when the first host device 100_1 reads data from a memory area allocated by the memory system 200 , the first host device 100_1 may detect a defective memory area based on the number of error corrections, etc. The first host device 100_1 may provide information about the defective memory area to the memory management module 212 of the memory system 200 .

[0165] The memory management module 212 may store and manage information about a defective memory area received from the first host device 100_1 , for example, in the auxiliary memory 213 .

[0166] When receiving an allocation request from the first host device 100_1 or a host device 100 other than the first host device 100_1 , the memory management module 212 may allocate a memory area other than the defective memory area to the host device that sent the allocation request based on information stored in the auxiliary memory 213 .

[0167] Even when any host device 100 outside the memory system 200 performs error occurrence prediction analysis, it is possible to prevent a failure from occurring due to a defective memory area during data processing when the remaining host devices 100 use the memory system 200 .

[0168] In this manner, when a defective memory region is detected, since the memory management module 212 excludes the defective memory region from the pool of allocatable memory regions, data processing can be improved regardless of whether the defective memory region exists.

[0169] Fig.10 is a diagram illustrating an example in which the memory system 200 according to an embodiment of the disclosed technology allocates and de-allocates a memory area according to a request of the host device 100 .

[0170] Reference Fig.10 In some embodiments, the memory area is allocated after a defective memory area is detected in a state where the memory area is allocated to the first host device 100_1 and the second host device 100_2.

[0171] For example, the memory management module 212 may allocate the memory area 0 included in the memory system 200 to the first host device 100_1. The memory management module 212 may allocate the memory area 1, the memory area 2, and the memory area 3 to the second host device 100_2.

[0172] In some embodiments, the memory management module 212 performs error occurrence prediction analysis, and the memory region 0 allocated to the first host device 100_1 may be detected as a defective memory region. Alternatively, the first host device 100_1 allocated with the memory region 0 performs error occurrence prediction analysis, and thus the memory region 0 may be detected as a defective memory region.

[0173] When the memory region 0 is detected as a defective memory region, the memory management module 212 may exclude the memory region 0 from the allocatable memory region pool.

[0174] Reference Fig.10 , in operation (6), a request for allocating two memory regions may be sent by the first host device 100_1 to the memory system 200 .

[0175] For example, in operation (7), the memory management module 212 of the memory system 200 may allocate the memory area 4 and the memory area 5 to the first host device 100_1 by excluding the defective memory area and the memory area allocated to the second host device 100_2.

[0176] Even when receiving an allocation request of the second host device 100_2 or another host device 100 , the memory management module 212 may allocate a memory area other than the memory area 0 and the memory area allocated to the second host device 100_2 to the corresponding host device 100 .

[0177] As described above, in some embodiments, the disclosed technology can be implemented to prevent data loss caused by a defective memory area through error occurrence prediction analysis of the memory management module 212, thereby preventing data loss caused by another host device 100 using the defective memory area after the defective memory area is detected.

[0178] In some embodiments discussed above, multiple host devices 100 use a memory system 200 including multiple memory devices 220. In other embodiments, one host device 100 uses a memory system 200 including one memory device 220. In other embodiments, two or more host devices 100 use a memory system 200 including one memory device 220. In other embodiments, one host device 100 uses a memory system 200 including two or more memory devices 220.

[0179] In some implementations, detection, processing, and management of defective memory regions may be performed by components external to the memory system 200 .

[0180] Fig.11is a diagram showing an example configuration of a memory system 200 based on an embodiment of the disclosed technology.

[0181] Reference Fig.11 , a memory system 200 based on an embodiment of the disclosed technology may include at least one memory device 220, the memory device 220 including two or more memory areas. The memory system 200 may include at least one memory controller 211, the memory controller 211 being configured to control the operation of the memory device 220. The memory system 200 including the memory device 220 or the memory system 200 including the memory device 200 and the memory controller 211 may be referred to as a storage device or a data storage device.

[0182] The memory management device 300 may be located outside the memory system 200. The memory management device 300 and the above-mentioned memory system 200 (or storage device or data storage device) may be collectively referred to as a data storage system.

[0183] The memory management device 300 can execute at least a portion of the functions of the above-mentioned memory management module 212 .

[0184] For example, the memory management device 300 may allocate or de-allocate a memory region of the memory device 220 included in the memory system 200 according to requests of a plurality of host devices 100 .

[0185] The host device 100 may allocate a memory area by the memory management device 300. The host device 100 may send a command for writing data to or reading data from the allocated memory area to the memory system 200 through the memory management device 300 or directly. Fig.11 An example is shown in which the host device 100 can directly communicate with the memory system 200 , but the host device 100 can communicate with the memory system 200 only through the memory management device 300 located outside the memory system 200 .

[0186] The memory management device 300 may detect a defective memory area based on operation information received from the memory controller 211 of the memory system 200. Alternatively, the memory management device 300 may receive information about the defective memory area from the memory controller 211.

[0187] When a defective memory area is detected or information about a defective memory area is received, the memory management device 300 may transmit a warning signal to the host device 100 to which the defective memory area is allocated.

[0188] In some embodiments, according to a request of the host device 100 that receives the warning signal, the memory management device 300 may un-allocate the defective memory area or migrate data stored in the defective memory area to a new memory area.

[0189] When receiving an allocation request for a memory area from the host device 100, the memory management device 300 may allocate a portion of the memory area except the defective memory area in response to the allocation request. The memory management device 300 may exclude the defective memory area from the allocatable memory area.

[0190] In some embodiments, the memory management device 300 may send a warning signal and then migrate data stored in the defective memory area to a new memory area regardless of a request of the host device 100. The memory management device 300 may allocate the new memory area to the host device 100 that has received the warning signal. The memory management device 300 may send mapping information about the new memory area to the host device 100 that has received the warning signal.

[0191] In some embodiments, the host device 100 may detect the defective memory area. The host device 100 may detect the defective memory area according to whether an error is detected in the process of reading data of the allocated memory area.

[0192] The memory management device 300 may perform processing (eg, data migration, de-allocation, etc.) on the defective memory area based on the information on the defective memory area received from the host device 100 .

[0193] For example, the memory management device 300 may communicate with the memory system 200 through the same interface as the communication interface between the host device 100 and the memory system 200. In addition, the memory management device 300 may communicate with the host device 100 through the same interface.

[0194] although Fig.11 The example shown in illustrates the memory management device 300 as being located outside the memory system 200 and the host device 100 , but the memory management device 300 may be included in the host device 100 , or at least a portion of the functions of the memory management device 300 may be incorporated into the host device 100 .

[0195] For example, the memory management device 300 may be included in the host device 100. The memory management device 300 may be implemented in the form of a module included in the host device 100, or may be implemented in the form of communicating with the host device 100 as a separate device adjacent to the host device 100.

[0196] When at least a part of the function of the memory management device 300 is included in the host device 100 , the memory management device 300 may perform direct communication with the memory system 200 , or may perform communication with the memory system 200 through the host device 100 .

[0197] Alternatively, the memory management device 300 may directly communicate with the memory system 200 , and the host device 100 may be implemented in a form of performing communication with the memory system 200 through the memory management device 300 .

[0198] Therefore, the memory management module 212 or the memory management device 300 that manages the defective memory area of ​​the memory system 200 or the data storage device can be implemented in various forms. Since the defective memory area is managed by the memory management module 212 or the memory management device 300, the operation performance of the memory system 200 or the data storage device including the memory area allocated to the plurality of host devices 100 can be improved.

[0199] The above-mentioned embodiments are briefly described below.

[0200] A memory system according to an embodiment of the present disclosure may include: a plurality of memory devices, each memory device including a plurality of memory areas configured to store data; at least one memory controller communicating with the plurality of memory devices and a plurality of host devices, and configured to control the operation of each of the plurality of memory devices in response to requests for memory operations from the plurality of host devices; and a memory management module configured to communicate with the plurality of memory devices, the plurality of host devices, and the at least one memory controller, and configured to allocate one or more memory areas of the plurality of memory areas of one or more memory devices in the plurality of memory devices to the one or more host devices in response to allocation requests from one or more host devices in the plurality of host devices, and to send a warning signal to a first host device in the one or more host devices when identifying that the memory area allocated to the first host device is a defective memory area predicted to have an error.

[0201] The memory management module may obtain operation information for controlling each of the plurality of memory devices from at least one memory controller, and may identify a defective memory region based on the operation information.

[0202] During a read operation on the plurality of memory regions, when at least one memory controller performs a plurality of error corrections such that the number of error corrections is equal to or greater than a preset threshold, the memory management module may identify the memory region as a defective memory region.

[0203] During a read operation on multiple memory regions, when at least one memory controller performs multiple error corrections so that the number of error corrections is equal to or greater than a preset reference value, the memory management module may identify a memory region adjacent to a known defective memory region as a defective memory region.

[0204] The memory management module may periodically receive operating information from at least one memory controller.

[0205] The memory management module may receive the operation information in response to an interrupt request generated by at least one memory controller.

[0206] The memory management module may send an operation information request command to at least one memory controller, and may receive operation information.

[0207] The memory management module may identify the defective memory region by receiving, from the at least one memory controller, information regarding the defective memory region detected by the at least one memory controller.

[0208] The memory management module may de-allocate the defective memory area according to a de-allocation request of the first host device that receives the warning signal.

[0209] The memory management module may reallocate a new memory area among the plurality of memory areas to the first host device according to a migration request of the first host device that receives the warning signal, and may migrate data stored in the defective memory area to the new memory area.

[0210] The memory management module may migrate the data stored in the defective memory area to a local memory adjacent to the first host device according to a migration request of the first host device that receives the warning signal.

[0211] The memory management module may be configured to migrate data stored in the defective memory area to a new memory area among the plurality of memory areas, reallocate the new memory area to the first host device, and transmit allocation information of the reallocated new memory area to the first host device.

[0212] When receiving a new allocation request from the first host device, the memory management module may reallocate a memory area other than the defective memory area among the plurality of memory areas as a memory area corresponding to the first host device.

[0213] In response to an allocation request of a second host device different from the first host device among the plurality of host devices, the memory management module may allocate a memory area other than the defective memory area among the plurality of memory areas as a memory area corresponding to the second host device.

[0214] The memory management module may identify a first host device among the plurality of host devices as being allocated a defective memory region based on occupancy information from an auxiliary memory configured to store occupancy information about a plurality of memory regions allocated to the plurality of host devices.

[0215] The memory management module may store information about defective memory regions in the auxiliary memory.

[0216] The memory management module may further send a warning signal to host devices other than the first host device.

[0217] The memory management module may transmit a warning signal including at least one of an error level and an error type of an error in the defective memory area to the first host device.

[0218] A memory system according to an embodiment of the present disclosure may include: a plurality of memory devices, each memory device including a plurality of memory areas configured to store data; at least one memory controller communicating with the plurality of memory devices and a plurality of host devices, and configured to control the operation of each of the plurality of memory devices in response to requests from the plurality of host devices; and a memory management module configured to: allocate one or more memory areas of the plurality of memory areas in response to allocation requests from one or more of the plurality of host devices, identify defective memory areas based on error occurrence prediction information received from at least one of the plurality of host devices, and upon receiving allocation requests from one or more of the plurality of host devices, allocate memory areas other than the defective memory areas to the one or more host devices that sent the allocation requests.

[0219] The memory management module may identify a defective memory area by receiving error occurrence prediction information from a first host device among the plurality of host devices, and may allocate a memory area other than the defective memory area to a second host device among the plurality of host devices upon receiving an allocation request from the second host device.

[0220] The memory management module may reallocate a new memory area among the plurality of memory areas to the first host device according to a migration request of the first host device, and may migrate data stored in the defective memory area to the new memory area.

[0221] The memory management module may migrate the data stored in the defective memory area to a local memory adjacent to the first host device according to a migration request of the first host device.

[0222] The memory management module may migrate data stored in the defective memory area to a new memory area among the plurality of memory areas, may reallocate the new memory area to the first host device, and may send allocation information of the reallocated new memory area to the first host device.

[0223] At least one of the plurality of host devices may generate error occurrence prediction information based on the number of error corrections performed by at least one memory controller during a read operation on the memory region.

[0224] According to an embodiment of the present disclosure, a data storage system may include: multiple storage devices, including multiple memory devices, each memory device including multiple memory areas configured to store data; and a memory management device, located outside the multiple storage devices and configured to: allocate one or more memory areas among the multiple memory areas in response to an allocation request from one or more host devices among a plurality of host devices, and when a defective memory area predicted to have an error is identified, send a warning signal to a first host device among the multiple host devices to which the defective memory area is allocated.

[0225] Each of the plurality of memory devices may further include a memory controller configured to control operations of the memory device, and wherein the memory management device receives information about the defective memory region detected by the memory controller from the memory controller.

[0226] The memory management device may obtain operation information for controlling the memory devices from the plurality of memory devices, and may identify a defective memory area based on the operation information.

[0227] The memory management device may directly control operations of a memory device included in each of the plurality of memory devices, and may identify a defective memory area based on operation information for controlling the memory device.

[0228] The memory management device may transmit the warning signal to at least one host device other than the first host device among the plurality of host devices.

[0229] The memory management device may transmit a warning signal including at least one of an error level and an error type of an error in the defective memory area to the first host device.

[0230] The memory management device may communicate with the plurality of storage devices using the same communication interface as that between the plurality of host devices and the plurality of storage devices.

[0231] A data storage device according to an embodiment of the present disclosure may include: a plurality of memory devices, each memory device including a plurality of memory areas configured to store data; and a memory controller that communicates with the plurality of memory devices and is configured to control the operation of each of the plurality of memory devices, and migrate data stored in a defective memory area where an error is predicted to occur to a new memory area according to a command received from outside the memory controller.

[0232] The memory controller may identify a defective memory area based on operation information for controlling at least one of the plurality of memory devices, may transmit information about the defective memory area to a memory management device located outside the memory controller, and may receive a command from the memory management device.

[0233] The memory controller may identify a memory region, for which error correction is performed a plurality of times in a read operation on the plurality of memory regions so that the number of error corrections is equal to or greater than a preset threshold, as a defective memory region.

[0234] The memory controller may transmit operation information for controlling at least one of the plurality of memory devices to a memory management device located outside the memory controller, and may receive information about a defective memory area and a command from the memory management device.

[0235] The memory controller may receive information about the defective memory region and a command from a first host device to which the defective memory region is allocated among a plurality of host devices to which the plurality of memory regions are allocated.

[0236] A control unit according to an embodiment of the present disclosure may include: at least one memory controller configured to control the operation of multiple memory devices, each memory device including multiple memory areas configured to store data; and a memory management module configured to: allocate one or more memory areas of the multiple memory areas to one or more host devices in response to an allocation request from one or more host devices among a plurality of host devices, and when identifying that a memory area allocated to a first host device among the one or more host devices is a defective memory area predicted to have an error, send a warning signal to a host device among the multiple host devices to which the defective memory area is allocated.

[0237] The memory management module may receive, from at least one memory controller, information regarding a defective memory region detected by the at least one memory controller.

[0238] The memory management module may obtain operation information for controlling at least one of the plurality of memory devices from at least one memory controller, and may identify a defective memory region based on the operation information.

[0239] The memory management module may transmit a warning signal including at least one of an error level and an error type of an error in the defective memory area to the host device to which the defective memory area is allocated.

[0240] Upon identifying a defective memory area and receiving an allocation request from each of the plurality of host devices, the memory management module may allocate at least a portion of the plurality of memory areas except for the defective memory area.

[0241] The control unit may further include an auxiliary memory configured to store occupancy information about one or more of the plurality of memory areas allocated to one or more of the plurality of host devices.

[0242] Information about defective memory areas may be stored in the auxiliary memory.

[0243] Only a few embodiments and examples are described herein. Based on what is described and shown in this patent application document, improvements and changes may be made to the disclosed embodiments and other embodiments.

Claims

1. A memory system, comprising: a plurality of memory devices, each memory device comprising a plurality of memory areas for storing data; at least one memory controller that communicates with the plurality of memory devices and a plurality of host devices and controls an operation of each of the plurality of memory devices in response to requests for memory operations from the plurality of host devices; as well as A memory management module that communicates with at least one of the plurality of memory devices, the plurality of host devices, or the at least one memory controller, and allocates one or more memory areas of the plurality of memory areas of one or more memory devices of the plurality of memory devices to the one or more host devices in response to allocation requests from the one or more host devices of the plurality of host devices, and sends a warning signal to a first host device of the one or more host devices when identifying that a memory area allocated to the first host device is a defective memory area predicted to cause an error.

2. The memory system according to claim 1, wherein: The memory management module obtains operation information for controlling each of the plurality of memory devices from the at least one memory controller, and identifies the defective memory region based on the operation information.

3. The memory system according to claim 2, wherein: During a read operation on the plurality of memory regions, the memory management module identifies a memory region as the defective memory region when the at least one memory controller performs a plurality of error corrections such that the number of error corrections is equal to or greater than a preset threshold.

4. The memory system according to claim 2, wherein: During a read operation on the multiple memory areas, the memory management module identifies a memory area adjacent to a known defective memory area as the defective memory area when the at least one memory controller performs multiple error corrections so that the number of error corrections is equal to or greater than a preset reference value.

5. The memory system according to claim 2, wherein: The memory management module periodically receives the operating information from the at least one memory controller.

6. The memory system according to claim 2, wherein: The memory management module receives the operating information in response to an interrupt request generated by the at least one memory controller.

7. The memory system according to claim 2, wherein: The memory management module sends an operation information request command to the at least one memory controller and receives the operation information.

8. The memory system according to claim 1, wherein: The memory management module identifies the defective memory region by receiving information about the defective memory region detected by the at least one memory controller from the at least one memory controller.

9. The memory system according to claim 1, wherein: The memory management module de-allocates the defective memory area according to a de-allocation request of the first host device that receives the warning signal.

10. The memory system according to claim 1, wherein: The memory management module reallocates a new memory area among the plurality of memory areas to the first host device according to a migration request of the first host device that receives the warning signal, and migrates data stored in the defective memory area to the new memory area.

11. The memory system according to claim 1, wherein: The memory management module migrates the data stored in the defective memory area to a local memory adjacent to the first host device according to a migration request of the first host device that receives the warning signal.

12. The memory system according to claim 1, wherein: The memory management module migrates data stored in the defective memory area to a new memory area among the plurality of memory areas, reallocates the new memory area to the first host device, and sends allocation information of the reallocated new memory area to the first host device.

13. The memory system according to claim 1, wherein: Upon receiving a new allocation request from the first host device, the memory management module reallocates a memory area other than the defective memory area among the plurality of memory areas as a memory area corresponding to the first host device.

14. The memory system according to claim 1, wherein: In response to an allocation request from a second host device different from the first host device among the plurality of host devices, the memory management module allocates a memory area different from the defective memory area among the plurality of memory areas as a memory area corresponding to the second host device.

15. The memory system according to claim 1, wherein: The memory management module identifies a first host device among the plurality of host devices as being allocated with the defective memory region based on occupancy information from an auxiliary memory storing occupancy information about a plurality of memory regions allocated to the plurality of host devices.

16. The memory system according to claim 1, wherein: The memory management module stores information about the defective memory region in an auxiliary memory.

17. The memory system according to claim 1, wherein: The memory management module further sends the warning signal to a host device other than the first host device.

18. The memory system according to claim 1, wherein: The memory management module transmits a warning signal including at least one of an error level and an error type of an error in the defective memory area to the first host device.

19. A data storage system comprising: a plurality of storage devices, including a plurality of memory devices, each memory device including a plurality of memory areas for storing data; as well as A memory management device is located outside the multiple storage devices and allocates one or more memory areas among the multiple memory areas in response to allocation requests from one or more host devices among the multiple host devices, and when a defective memory area predicted to have an error is identified, sends a warning signal to a first host device among the multiple host devices to which the defective memory area is allocated.

20. A control unit, comprising: at least one memory controller that controls operation of a plurality of memory devices, each memory device including a plurality of memory regions storing data; as well as A memory management module allocates one or more memory areas among the multiple memory areas to the one or more host devices in response to an allocation request from the one or more host devices, and when identifying that the memory area allocated to a first host device among the one or more host devices is a defective memory area predicted to have an error, sends a warning signal to the host device among the multiple host devices to which the defective memory area is allocated.

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