Peripheral device interconnection to expand device resource management systems, devices and clusters

Abstract

The present application provides a peripheral device interconnection expansion device resource management system, device and cluster. The system includes: a first peripheral device interconnection expansion device card, including a first physical function and a second physical function; a host receives a first resource application request sent by the first physical function, and allocates a first resource based on the first resource application request and the number of resources in the first resource pool to implement the business deployment of the first physical function and the first virtual function virtualized by the first physical function; receives a second resource application request sent by the second physical function, and allocates a second resource based on the second resource application request and the first remaining resource number of the first resource pool to implement the business deployment of the second physical function and the second virtual function virtualized by the second physical function, the first remaining resource number is equal to the number of resources in the first resource pool minus the number of the first resource; the first resource pool is created based on the resources of the first peripheral device interconnection expansion device card.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a peripheral device interconnection expansion device resource management system, device and cluster. Background Art

[0002] A Peripheral Component Interconnect Express (PCIE) device is a peripheral that connects to a computer's motherboard via the PCIE bus standard. PCIE is a high-speed serial computer expansion bus standard that is widely used in modern computer architectures to connect various hardware components.

[0003] like Figure 1 As shown in the figure, PCIE devices can virtualize multiple virtual PCIE devices from a single physical PCIE device through Single Root I / O Virtualization (SR-IOV), and then pass the virtual PCIE devices directly to each virtual machine to achieve the application scenario of a single physical PCIE device supporting multiple virtual machines. SR-IOV is implemented on the basis of the PCIE specification. The SR-IOV protocol introduces the concept of two types of functions: physical function (PF) 11 and virtual function (VF) 12. PF11 is used to support PCI functions with SR-IOV functions. As defined in the SR-IOV specification, PF11 contains the SR-IOV function configuration structure for managing SR-IOV functions. PF11 is a full-featured PCIE function that can be discovered, managed, and processed like any other PCIE device. PF11 has full configuration resources and can be used to configure or control PCIE devices; VF12 is a function associated with PF, which is a lightweight PCIE function that can share one or more physical resources with physical function 11 and other VF12 associated with the same physical function 11. VF12 is only allowed to have configuration resources for its own behavior.

[0004] However, currently the resources of the entire hardware are pre-divided according to the strength of PF11, and VF12 can only apply for and release resources from the corresponding PF11. Summary of the invention

[0005] The present application provides a peripheral device interconnection expansion device resource management system, device and cluster, which can flexibly allocate resources within the same PCIE device board.

[0006] In a first aspect, a peripheral device interconnection expansion device resource management system is provided, comprising:

[0007] A first peripheral device interconnection expansion device card, wherein the first peripheral device interconnection expansion device card includes a first physical function and a second physical function;

[0008] A host, configured to run a first driver instance and a second driver instance, wherein the first driver instance is configured to drive a first physical function, and the second driver instance is configured to drive a second physical function;

[0009] receiving a first resource application request sent by a first physical function, and allocating a first resource based on the first resource application request and the number of resources in a first resource pool stored in the host to implement service deployment of the first physical function and a first virtual function virtualized by the first physical function;

[0010] receiving a second resource application request sent by a second physical function, and allocating a second resource based on the second resource application request and a first remaining resource quantity of a first resource pool stored in the host to implement service deployment of a second physical function and a second virtual function virtualized by the second physical function, wherein the first remaining resource quantity is equal to the resource quantity of the first resource pool minus the quantity of the first resource;

[0011] The first resource pool is created based on resources of the first peripheral device interconnect expansion device card.

[0012] In some possible designs, the host is also used to receive a third resource application request sent by the first physical function, and allocate a third resource based on the third resource application request and the second remaining resource quantity of the first resource pool stored in the host to implement business deployment of the first physical function and the third virtual function virtualized by the first physical function, where the second remaining resource quantity is equal to the first remaining resource quantity, which is equal to the resource quantity of the first resource pool minus the quantity of the first resources minus the quantity of the second resources.

[0013] In some possible designs, the system further includes a second peripheral device interconnect expansion device card, wherein the second peripheral device interconnect expansion device card includes a third physical function;

[0014] The host is also used to receive a fourth resource application request sent by the third physical function, and allocate a fourth resource based on the fourth resource application request according to the number of resources in the second resource pool stored in the host to implement business deployment of the third physical function and the fourth virtual function virtualized by the third physical function, wherein the second resource pool is created based on the resources of the second peripheral device interconnect expansion device card.

[0015] In some possible designs, the host is further used to allocate a first board identifier to the first peripheral device interconnect expansion device card when the first peripheral device interconnect expansion device card is online, wherein the first board identifier is a unique identifier of the first peripheral device interconnect expansion device card.

[0016] The host is further configured to send a query instruction to the first peripheral device interconnect expansion device card through a first driver instance, and receive a first resource quantity returned by each physical function in the first peripheral device interconnect expansion device card based on the query instruction.

[0017] The host is further configured to create a first resource pool for the first peripheral device interconnect expansion device card based on the first resource quantity returned by each physical function in the first peripheral device interconnect expansion device card, and associate the first resource pool with the first board identifier.

[0018] In some possible designs, the host is also used to allocate a first reference count for the first peripheral device interconnect expansion device card, and the first reference count is used to indicate the number of physical functions online in the first peripheral device interconnect expansion device card. When the first reference count is zero, the first board identifier is deleted and the resources in the first resource pool are released.

[0019] In some possible designs, the first resource pool is any one of a queue resource pool, a flow table resource pool, and an interrupt resource pool.

[0020] In some possible designs, the host is further used to query the number of remaining resources in the first resource pool according to the first board identifier.

[0021] In some possible designs, the number of resources in the first resource pool is stored in a global variable of the host.

[0022] In a second aspect, a computing device is provided, comprising a peripheral device interconnection extension device resource management system and a storage unit, wherein the peripheral device interconnection extension device resource management system and the storage unit can communicate with each other, and the peripheral device interconnection extension device resource management system is a system as described in any one of the first aspects.

[0023] According to a third aspect, a computing device cluster is provided, comprising a plurality of computing devices, wherein at least one computing device comprises a peripheral device interconnection extension device resource management system and a storage unit, wherein the peripheral device interconnection extension device resource management system and the storage unit are capable of communicating with each other, and the peripheral device interconnection extension device resource management system is a system as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0025] Figure 1 It is a structural schematic diagram of a PCIE device provided by the prior art;

[0026] Figure 2 It is a structural diagram of a peripheral device interconnection expansion device resource management system provided by the present application;

[0027] Figure 3 It is a structural schematic diagram of a host provided by this application;

[0028] Figure 4 It is a structural schematic diagram of a computing device provided by this application. DETAILED DESCRIPTION

[0029] The embodiments of the present invention are described below in conjunction with the accompanying drawings in the embodiments of the present invention. The terms used in the implementation mode of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0030] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of a peripheral device interconnection expansion device resource management system provided by this application. Figure 2 As shown, the peripheral device interconnection expansion device resource management system of the present application includes: a host, a first PCIE device card and a second PCIE device card.

[0031] The host is the computing core and control core, which can handle complex situations. The host can be a very large-scale integrated circuit. The main operating system and other software programs are installed in the host, so that the host can access the memory and various PCIE devices. The host can quickly access the local memory through the on-chip bus. The host may include one or more processor cores. In one implementation, the host may be a multi-core chip, that is, a chip containing multiple processing cores. In another implementation, the host may include one or more processor cores. It can be a chip with one processing core.

[0032] See also Figure 3 , Figure 3 This is a schematic diagram of the structure of a host provided by this application. Figure 3As shown, the host may include a memory address register 101, a memory data register 102, a program counter 103, an instruction register 104, an instruction decoder 105, a microcode read-only memory 106, an operation controller 107, a calculation unit 108, a general register group 109, an accumulator 110, a program status word register 111, a timing circuit 112 and a host bus 120. The host bus 120 may also be a data bus, a power bus, a control bus or a status signal bus.

[0033] The host is used to process instructions and data stored in the memory 113. In some embodiments, the instructions may include one or more instruction formats. The instruction format may indicate various fields (number of bits, position of bits, etc.) to specify the data processing operation to be performed and the operand on which the operation is to be performed. Some instruction formats may be further defined by instruction templates (or sub-formats).

[0034] In the host, the memory address register 101 is used to store the address of the memory currently accessed by the host. The memory data register 102 is used to store the data and read or write instructions read or written by the host from the address, so as to make up for the difference in operating speed between the host and the memory.

[0035] The timing circuit 112 provides a time reference for each component through a fixed clock. The time for the host to execute an instruction is an instruction cycle. The program counter 103 is used to store the address of the next instruction. When the instructions are executed sequentially, the program counter 103 automatically adds the number of bytes of an instruction after each instruction is taken. When a transfer instruction is encountered, the program counter 103 specifies the address of the next instruction through the address code field in the transfer instruction. The instruction register 104 is used to save the instruction currently being executed. The instruction includes two fields, an operation code and an address code. The operation code part is decoded by the instruction decoder 105 to generate the control potential of the operation required by the instruction. The operation controller 107 can generate various operation control signals based on the control potential signal output by the instruction decoder and the timing signal generated by the timing circuit 112, and control the remaining components of the host to complete the operation of fetching and executing instructions.

[0036] A microinstruction is the smallest unit of instructions executed by the host. An instruction can be a single microinstruction or composed of several microinstructions. An instruction composed of multiple microinstructions is called a complex instruction. Various mechanisms can be used to implement the decoding of complex instructions by the instruction decoder 105. Specific decoding mechanisms include but are not limited to lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one embodiment, the steps of the microinstructions corresponding to the complex instructions can be stored in the microcode read-only memory 106. During the decoding process, the instruction decoder 105 can query and obtain the operation code and address code of the microinstructions constituting the complex instructions from the microcode read-only memory 106, and decode the operation code part of the microinstructions in turn to generate the control potential required by the microinstructions.

[0037] The operation controller 107 has multiple buffers, and can send the decoded instructions to their respective reservation stations for storage according to the types of instructions. After analyzing the status of the hardware circuit of the computing unit and the specific situation of whether each instruction can be executed in advance, the instructions that can be executed in advance are scheduled to the corresponding computing unit 108 for execution. During this period, the instruction stream is reordered so that the instruction pipeline can proceed and be smoothly scheduled. Exemplarily, for instructions of integer calculation, the operation controller 107 can use the integer reservation station to save instructions and assign them to the integer computing unit for calculation; for instructions of floating-point calculation, the operation controller 107 can use the floating-point reservation station to save instructions and assign them to the floating-point computing unit for calculation.

[0038] The general register group 109 is used to store the data corresponding to the address code according to the address code of the instruction. The calculation unit 108 is used to receive the operation control signal of the operation controller 107 and perform calculations on the data stored in the general register group 109, including arithmetic operations (including basic operations such as addition, subtraction, multiplication and additional operations) and logical operations (including shifting, logical testing or comparison of two values). The temporary variables generated in the calculation are stored in the accumulator 110, and the information of the generated status is stored in the program status word register 111, such as the operation result carry / borrow flag (C), the operation result overflow flag (O), the operation result zero flag (Z), the operation result negative flag (N), the operation result sign flag (S), etc. The program status word register is also used to save information such as interrupts and the working status of the computing device, so that the host can timely understand the machine operation status and program operation status.

[0039] The calculation unit 108 includes a variety of different circuit modules, which can be used to execute different instructions. For example, the integer calculation unit 1081 and the floating point calculation unit 1082 are used to perform arithmetic operations and logical operations on integers and floating point numbers, respectively.

[0040] It can be understood that the above host is only a specific embodiment. In actual application, it can also have more or fewer components, which will not be described in detail here.

[0041] The first peripheral device interconnection expansion device card includes a first physical function and a second physical function. The first physical function and the second physical function are both concentrated on the same PCIE device card. The PCIE device card can be an expansion card connected to the host through a PCIE interface. They are usually used to add additional functions or improve system performance, including graphics processing, storage control, network connection, etc.

[0042] The first peripheral device interconnect expansion device card includes a third physical function.

[0043] Here, the host is used to run a first driver instance, a second driver instance, and a third driver instance. The first driver instance is used to drive a first physical function, the second driver instance is used to drive a second physical function, and the third driver instance is used to drive a third physical function.

[0044] When the first peripheral device interconnection expansion device card is online, the host allocates a first board identifier to the first peripheral device interconnection expansion device card, wherein the first board identifier is a unique identifier of the first peripheral device interconnection expansion device card. Then, the host sends a query instruction to the first peripheral device interconnection expansion device card through the first driver instance. The first peripheral device interconnection expansion device card queries the resource quantity of each physical function according to the query instruction, and returns the first resource quantity of each physical function in the first peripheral device interconnection expansion device card. The host creates a first resource pool for the first peripheral device interconnection expansion device card based on the first resource quantity returned by each physical function in the first peripheral device interconnection expansion device card, and associates the first resource pool with the first board identifier. The first resource pool is created based on the resources of the first peripheral device interconnection expansion device card. The first resource pool is any one of a first queue resource pool, a first flow table resource pool, and a first interrupt resource pool. The first queue resource pool is used to collect multiple queues in the first peripheral device interconnection expansion device card. The first flow table resource pool is used to collect multiple flow tables in the first peripheral device interconnection expansion device card. The first interrupt resource pool is used to collect multiple interrupts in the first peripheral device interconnection expansion device card. The number of resources in the first resource pool is stored in a global variable of the host. The host allocates a first reference count to the first peripheral device interconnect expansion device card, wherein the first reference count is used to indicate the number of physical functions online in the first peripheral device interconnect expansion device card. In a specific embodiment, when none of the PFs of the first peripheral device interconnect expansion device card are online, the value of the first reference count is 0, when the first PF is online, the value of the first reference count increases to 1, and when the second PF is online, the value of the first reference count increases to 2.

[0045] When the second peripheral device interconnection expansion device card is online, the host allocates a second board identifier to the second peripheral device interconnection expansion device card, wherein the second board identifier is a unique identifier of the second peripheral device interconnection expansion device card. Then, the host sends a query instruction to the second peripheral device interconnection expansion device card through a second driver instance. The second peripheral device interconnection expansion device card queries the resource quantity of each physical function according to the query instruction, and returns the second resource quantity of each physical function in the second peripheral device interconnection expansion device card. The host creates a second resource pool for the second peripheral device interconnection expansion device card based on the second resource quantity returned by each physical function in the second peripheral device interconnection expansion device card, and associates the second resource pool with the second board identifier. The second resource pool is created based on the resources of the second peripheral device interconnection expansion device card. The second resource pool is any one of a second queue resource pool, a second flow table resource pool, and a second interrupt resource pool. The second queue resource pool is used to bring together multiple queues in the second peripheral device interconnection expansion device card. The second flow table resource pool is used to bring together multiple queues in the second peripheral device interconnection expansion device card. The second interrupt resource pool is used to bring together multiple interrupts in the second peripheral device interconnection expansion device card. The number of resources in the second resource pool is stored in a global variable of the host. The host allocates a second reference count to the second peripheral device interconnect expansion device card, wherein the second reference count is used to indicate the number of physical functions online in the second peripheral device interconnect expansion device card. In a specific embodiment, when none of the PFs of the second peripheral device interconnect expansion device card is online, the value of the second reference count is 0, and when the third PF is online, the value of the second reference count increases to 1.

[0046] After the first peripheral device interconnect expansion device card is online, the first physical function sends a first resource application request to the host. Accordingly, the host receives the first resource application request sent by the first physical function. The host allocates the first resource based on the first resource application request and the number of resources in the first resource pool stored in the host to implement the service deployment of the first physical function and the first virtual function virtualized by the first physical function. The second physical function sends a second resource application request to the host. Accordingly, the host receives the second resource application request sent by the second physical function. The host allocates the second resource based on the second resource application request and the first remaining resource number of the first resource pool stored in the host to implement the service deployment of the second physical function and the second virtual function virtualized by the second physical function, and the first remaining resource number is equal to the resource number of the first resource pool minus the first resource number. The first physical function sends a third resource application request to the host. Accordingly, the host receives the third resource application request sent by the first physical function. The host allocates a third resource based on the third resource application request and the second remaining resource quantity of the first resource pool stored in the host to implement the business deployment of the first physical function and the third virtual function virtualized by the first physical function, and the second remaining resource quantity is equal to the first remaining resource quantity, which is equal to the resource quantity of the first resource pool minus the quantity of the first resources minus the quantity of the second resources.

[0047] After the second peripheral device interconnect expansion device card is online, the third physical function sends a fourth resource application request to the host. Correspondingly, the host receives the fourth resource application request sent by the third physical function. The host allocates the fourth resource based on the fourth resource application request and the number of resources in the second resource pool stored in the host to implement the service deployment of the third physical function and the fourth virtual function virtualized by the third physical function.

[0048] When the first PF goes offline, the first reference count will change from 2 to 1, and when the second PF also goes offline, the first reference count will change from 2 to 0. When the first reference counts are all zero, the first board identifier is deleted, and the resources in the first resource pool are released.

[0049] When the third PF goes offline, the second reference count will change from 1 to 0. When the second reference counts are all zero, the second board identifier is deleted, and the resources in the second resource pool are released.

[0050] See also Figure 4 , Figure 4 4 is a schematic diagram of a computing device provided by the present application. The computing device 400 includes: one or more processing units 410 , a communication interface 420 and a storage unit 430 .

[0051] The processing unit 410, the communication interface 420 and the storage unit 430 are interconnected via a bus 440. Optionally, the computing device 400 may also include an input / output interface 450, which is connected to an input / output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processing unit 410 can also be used to implement some or all of the operation steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 400 can refer to the specific details in the above-mentioned embodiment, such as the processing unit 410 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in the embodiment of the present application, the computing device 400 can be used to implement some or all of the functions of one or more components in the above-mentioned device embodiment, and the communication interface 420 can be specifically used for the communication functions necessary to implement the functions of these devices and components, and the processing unit 410 can be specifically used for the processing functions necessary to implement the functions of these devices and components, etc.

[0052] Figure 4 The computing device 400 may include one or more processing units 410, and the multiple processing units 410 may provide processing capabilities in a coordinated manner in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner, or the multiple processing units 410 may constitute a processor sequence or a processor array, or the multiple processing units 410 may be divided into a main processor and an auxiliary processor, or the multiple processing units 410 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 4 The computing device 400 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include Figure 4 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0053] The processing unit 410 may have a variety of specific implementation forms. For example, the processing unit 410 may include a processor (central processing unit, CPU), a graphic processing unit (graphic processing unit, GPU), a neural-network processing unit (neural-network processing unit, NPU), a tensor processing unit (tensor processing unit, TPU) or a data processing unit (data processing unit, DPU) and other combinations thereof, which are not specifically limited in the embodiments of the present application. The processing unit 410 may also be a single-core processor or a multi-core processor. The processing unit 410 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a generic array logic (generic array logic, GAL) or any combination thereof. The processing unit 410 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (digital signal processor, DSP), etc. The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0054] The storage unit 430 may be a non-volatile memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The storage unit 430 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The storage unit 430 may also be used to store program codes and data, so that the processing unit 410 can call the program codes stored in the storage unit 430 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 4 Show more or fewer components, or have different component configurations.

[0055] The bus 440 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 440 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 440 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0056] The present application also provides a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0057] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one network site, computer, server or data center to another network site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or it can be a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape, etc.), an optical medium (e.g., a DVD, etc.), or a semiconductor medium (e.g., a solid-state hard disk), etc. In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Claims

1. A peripheral device interconnection expansion equipment resource management system, characterized in that: include: A first peripheral device interconnection expansion device card, wherein the first peripheral device interconnection expansion device card includes a first physical function and a second physical function; A host, configured to run a first driver instance and a second driver instance, wherein the first driver instance is configured to drive a first physical function, and the second driver instance is configured to drive a second physical function; receiving a first resource application request sent by a first physical function, and allocating a first resource based on the first resource application request and the number of resources in a first resource pool stored in the host to implement service deployment of the first physical function and a first virtual function virtualized by the first physical function; receiving a second resource application request sent by a second physical function, and allocating a second resource based on the second resource application request and a first remaining resource quantity of a first resource pool stored in the host to implement service deployment of a second physical function and a second virtual function virtualized by the second physical function, wherein the first remaining resource quantity is equal to the resource quantity of the first resource pool minus the quantity of the first resource; Among them, the first resource pool is created based on the resources of the first peripheral device interconnect expansion device card, the first resource pool is any one of a queue resource pool, a flow table resource pool and an interrupt resource pool, and the number of resources in the first resource pool is stored in the global variable of the host.

2. The system according to claim 1, characterized in that The host is also used to receive a third resource application request sent by the first physical function, and allocate a third resource based on the third resource application request and the second remaining resource quantity of the first resource pool stored in the host to realize the business deployment of the first physical function and the third virtual function virtualized by the first physical function, wherein the second remaining resource quantity is equal to the first remaining resource quantity, which is equal to the resource quantity of the first resource pool minus the quantity of the first resources minus the quantity of the second resources.

3. The system according to claim 1 or 2, characterized in that: The system further includes a second peripheral device interconnect expansion device card, wherein the second peripheral device interconnect expansion device card includes a third physical function; The host is also used to run a third driver instance, which is used to drive a third physical function, receive a fourth resource application request sent by the third physical function, and allocate a fourth resource based on the fourth resource application request according to the number of resources in the second resource pool stored in the host to implement the business deployment of the third physical function and the fourth virtual function virtualized by the third physical function, wherein the second resource pool is created based on the resources of the second peripheral device interconnect expansion device card.

4. The system according to claim 1 or 2, characterized in that: The host is further used to allocate a first board identifier to the first peripheral device interconnection expansion device card when the first peripheral device interconnection expansion device card is online, wherein the first board identifier is a unique identifier of the first peripheral device interconnection expansion device card, The host is further configured to send a query instruction to the first peripheral device interconnect expansion device card through a first driver instance, and receive a first resource quantity returned by each physical function in the first peripheral device interconnect expansion device card based on the query instruction. The host is further configured to create a first resource pool for the first peripheral device interconnect expansion device card based on the first resource quantity returned by each physical function in the first peripheral device interconnect expansion device card, and associate the first resource pool with the first board identifier.

5. The system according to claim 4, characterized in that The host is also used to allocate a first reference count for the first peripheral device interconnect expansion device card, and the first reference count is used to indicate the number of physical functions online in the first peripheral device interconnect expansion device card. When the first reference counts are all zero, the first board identifier is deleted and the resources in the first resource pool are released.

6. The system according to claim 4, characterized in that The host is further configured to query the quantity of remaining resources in the first resource pool according to the first board identifier.

7. A computing device, characterized in that It comprises a peripheral device interconnection extension device resource management system and a storage unit, the peripheral device interconnection extension device resource management system and the storage unit can communicate with each other, and the peripheral device interconnection extension device resource management system is a system as claimed in any one of claims 1-6.

8. A computing device cluster, characterized in that: It includes multiple computing devices, at least one computing device includes a peripheral device interconnection extension device resource management system and a storage unit, the peripheral device interconnection extension device resource management system and the storage unit can communicate with each other, and the peripheral device interconnection extension device resource management system is a system as described in any one of claims 1-6.

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