Method for controlling display screen and display driving circuit and scanning control circuit thereof

Abstract

The invention discloses a method for controlling a display screen, the display screen is provided with a plurality of pixels, and one row of pixels are divided into a plurality of groups of pixels. The method comprises the following steps of: when the row of pixels are scanned, generating a scanning control signal for the row of pixels; outputting a plurality of enabling signals, wherein each enabling signal is used for controlling one of the plurality of groups of pixels; and when the row of pixels are scanned, determining whether to output a scanning signal to each group of the plurality of groups of pixels according to the scanning control signal and each of the plurality of enabling signals.

Description

Technical Field

[0001] The present invention relates to a method for controlling a display screen, and more particularly to a method for controlling a display screen under a multi-frequency display (MFD) and a related display driving circuit and scanning control circuit. Background Art

[0002] Multi-Frequency Display (MFD) is a new display technology that can generate images at different frame rates in different areas of the display screen. Under multi-frequency display, an image frame can be dynamically divided into one or more high frame rate areas and one or more low frame rate areas. For example, the area used to display video should preferably be allocated to the high frame rate area, and other areas used to display text content should preferably be allocated to the low frame rate area. Multi-frequency display operation can save power by reducing the number of refresh times in the low frame rate area, while maintaining the refresh rate in the high frame rate area to achieve ideal image quality, wherein each image frame can dynamically configure the refresh rate according to its image content.

[0003] Generally speaking, a display screen may include a plurality of pixels arranged in an array form. A plurality of data lines (or source lines) and a plurality of scan lines (or gate lines) for controlling the pixels are provided on the display screen, wherein each data line may be arranged along the y direction and coupled to a column of pixels in a vertical direction; each scan line may be arranged along the x direction and coupled to a row of pixels in a horizontal direction. In other words, the direction in which the scan line connects the pixels is the x direction, and the direction in which the data line connects the pixels is the y direction. Under such a panel structure, the pixels on the display screen may be scanned row by row from top to bottom, that is, the scanning operation is performed along the y direction.

[0004] Based on the above display characteristics, the existing multi-frequency display operation needs to split the active area of ​​the display screen along the y direction. However, the x-direction splitting for different frame rate configurations cannot be implemented in the existing multi-frequency display operation. Summary of the invention

[0005] Therefore, the main purpose of the present invention is to provide a method for controlling a display screen under a multi-frequency display (MFD) and its related display driving circuit and scanning control circuit, which can support x-direction segmentation for multi-frequency display applications to solve the above-mentioned problems.

[0006] An embodiment of the present invention discloses a method for controlling a display screen, wherein the display screen has a plurality of pixels, wherein a row of pixels is divided into a plurality of groups of pixels. The method comprises the following steps: when scanning the row of pixels, generating a scanning control signal for the row of pixels; outputting a plurality of enabling signals, wherein each enabling signal is used to control one of the plurality of groups of pixels; and when scanning the row of pixels, determining whether to output a scanning signal to each of the plurality of groups of pixels according to the scanning control signal and each enabling signal of the plurality of enabling signals.

[0007] Another embodiment of the present invention discloses a display driving circuit for controlling a display screen having a plurality of pixels, wherein a row of pixels is divided into a plurality of groups of pixels. The display driving circuit is used to control a scanning control circuit to generate a scanning control signal for the row of pixels when scanning the row of pixels; output a plurality of enabling signals, wherein each enabling signal is used to control one of the plurality of groups of pixels; and when scanning the row of pixels, determine whether to output a scanning signal to each of the plurality of groups of pixels according to the scanning control signal and each enabling signal of the plurality of enabling signals.

[0008] Another embodiment of the present invention discloses a scanning control circuit of a display screen, the display screen having a plurality of pixels, the scanning control circuit comprising at least one shift circuit and a multiplexing circuit. Each shift circuit in the at least one shift circuit is used to generate a plurality of scanning control signals, each of the plurality of scanning control signals is used for a row of pixels in the plurality of pixels. The multiplexing circuit is coupled to the at least one shift circuit, and is used to receive the plurality of scanning control signals and a plurality of enabling signals to generate and output a plurality of scanning signals to the plurality of pixels. A row of pixels in the plurality of pixels is divided into a plurality of groups of pixels, and each of the plurality of scanning signals for the row of pixels corresponds to one of the plurality of groups of pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 The scanning operation of 4 consecutive image frames is shown to achieve different frame rates for each region.

[0010] Figure 2 A schematic diagram of partially updating image data in a display system.

[0011] Figure 3 The display driver circuit is shown refreshing the display screen to achieve different frame rates in different areas.

[0012] Figure 4 It shows that the conventional y-division may not be effective in achieving power saving when a mobile phone is operated in landscape mode.

[0013] Figure 5An application scenario in which an image screen is displayed in a landscape mode of a mobile phone is shown.

[0014] Figure 6 Another application of x-direction segmentation is shown.

[0015] Fig. 7A and Figure 7B A schematic diagram of implementing x-direction segmentation on a display screen.

[0016] Figure 8 A target refresh rate configuration method achieved with x-direction segmentation is shown.

[0017] Fig. 9 The figure is a flow chart of a scanning process according to an embodiment of the present invention.

[0018] Fig.10 Shows Fig. 7A part of the display or Figure 7B A detailed implementation of a portion of a display screen in FIG.

[0019] Fig.11 for Fig.10 Waveform diagram of the scan control circuit in .

[0020] Fig.12 A schematic diagram of a detailed implementation of a pixel located in an active area of ​​a display screen.

[0021] Fig.13 FIG. 4 is a schematic diagram of another display screen according to an embodiment of the present invention.

[0022] Fig.14 Shows Fig.13 A detailed implementation of coupling a scan line to a pixel.

[0023] Fig.15 An exemplary implementation of a logic operation circuit according to the first embodiment of the present invention is shown.

[0024] Fig.16 Another frame rate configuration on the display screen is shown.

[0025] Fig.17 The operation of the scan control circuit to implement this frame rate configuration is shown.

[0026] Fig.18 for Fig.17 Waveform diagram of the scan control circuit in .

[0027] Fig.19 Another frame rate configuration mode on the display screen is shown.

[0028] Fig. 20The operation of the scan control circuit to implement this frame rate configuration is shown.

[0029] Fig.21 for Fig. 20 Waveform diagram of the scan control circuit in .

[0030] Fig. 22 Several possible high frame rate and low frame rate configurations on the display are shown.

[0031] Fig.23 The power saving effect achieved on the data line when the x-direction segmentation is adopted is shown.

[0032] Fig.24 The power saving effect that can be achieved by scanning control is shown.

[0033] Fig.25 An application scenario of performing x-direction segmentation on a display screen of a display system is shown.

[0034] Fig.26A and Fig.26B FIG. 1 is a schematic diagram of partially updating image data in a display system using compressed blocks corresponding to a group size.

[0035] Fig. 27 An exemplary frame rate configuration method for a series of image frames according to an embodiment of the present invention is shown.

[0036] The reference numerals are described as follows:

[0037] F1~F4、F_1~F_120 Image frame

[0038] Area A1 to A4

[0039] 20, 250, 260 display system

[0040] 202, 2502, 2602 Application Processors

[0041] 204, 404, 604_1, 604_2, 720, 770, display driving circuit 2504, 2604

[0043] 206、400、600、700、750、2506、 Display screen 2606

[0045] 40 Mobile Phone

[0046] 402_1, 402_2, 602_1, 602_2 gate drive array circuit

[0047] HFR High Frame Rate Area

[0048] LFR Low Frame Rate Area

[0049] 60 Folding Phone

[0050] 702, 752 Active Zone

[0051] 710_1, 710_2, 760_1, 760_2, 1000 Scan control circuit

[0052] 712_1, 712_2, 762_1, 762_2, 1002, shift circuit

[0053] 1302_1, 1302_2

[0054] 714_1, 714_2, 764_1, 764_2, 1004, multiplexer circuit 1304

[0055] EN_L, EN_R, EN enable signal

[0056] 90 Scanning Process

[0057] Steps 902-906

[0058] SC_N~SC_(N+3), SC2_N Scan control signal

[0059] G[1]_L1~G[1]_L5、G[N]_L1~ Scan line

[0060] G[N]_L5, G[R-1]_L1~G[R-1]_L5,

[0061] G[R]_L1~G[R]_L5, G[M-1]_L1~

[0062] G[M-1]_L5, G[M]_L1~G[M]_L5,

[0063] G[N-1]_L1, G[N-1]_L2, G[N+1]_L1,

[0064] G[N+1]_L2, G2[N]_L1~G2[N]_L5

[0065] M_N~M_(N+3), M2_N, 150 logic operation circuit

[0066] EN_L1~EN_L5, EN2_L1~EN2_L5 enable signal

[0067] CLK, CLKB clock signals

[0068] STV, STV1, STV2 start pulse

[0069] NSCAN[N] Current scan signal

[0070] NSCAN[N-1] Previous scan signal

[0071] G1, G2 Group

[0072] NSCAN1[N], NSCAN2[N] scanning signal

[0073] SR_NODEA node

[0074] VGH, VGL supply voltage

[0075] DL_1~DL_3 data lines

[0076] DEC1, DEC2 decoders DETAILED DESCRIPTION

[0077] Figure 1 The scanning operation of four consecutive image frames F1 to F4 is shown to achieve different frame rates for each area A1 to A4. Based on the frame rate configuration on the display screen, image frame F1 is fully refreshed and image frames F2 to F4 are partially refreshed. More specifically, in image frames F2 and F4, areas A2 and A3 are assigned to the low frame rate area, and their scanning signals are gated, so the corresponding pixels are not refreshed; at the same time, the panel is refreshed in areas A1 and A4 assigned to the high frame rate area. In image frame F3, area A3 is assigned to the low frame rate area, and its scanning signal is gated, so the corresponding pixels are not refreshed; at the same time, the panel is refreshed in areas A1, A2 and A4 assigned to the high frame rate area. Assuming that the basic frame rate of the panel is 120Hz, the refresh operation can be performed within a series of consecutive image frames. Figure 1 The allocation method shown is repeated to achieve lower frame rates, such as 60 Hz and 30 Hz. The display driver circuit can trigger a multi-frequency display (Multi-FrequencyDisplay, MFD) in any and suitable manner. In one embodiment, the display driver circuit receives only part of the display data of an image frame from the video source, and determines the position allocated to the high frame rate area and / or the low frame rate area according to the image content. Alternatively, the display driver circuit may receive a notification from the video source, which indicates which areas need to be refreshed and which areas do not need to be refreshed, thereby determining the position allocated to the high frame rate area and / or the low frame rate area.

[0078] like Figure 1As shown, the display screen is divided into four areas A1 to A4 with separate frame rates. In the area where refresh is not required on a portion of the image frame, the corresponding scan line is locked to a specific level to stop the refresh operation of the pixels connected to it. Therefore, a row of pixels connected to the same scan line should be refreshed or not refreshed at the same time, and a frame rate can be allocated to each row of pixels, thereby achieving segmentation in the y direction.

[0079] It is worth noting that the above operation can only support the segmentation in the y direction, which limits the application of general mobile phones, where the video may be displayed in the middle row, the system status bar is above the video area and the text area (such as a chat room) is below, and in most image frames, the refresh area should completely cover one or more complete rows of pixels of the displayed video. However, the existing method cannot support the segmentation in the x direction in multi-frequency display applications.

[0080] Figure 2 A schematic diagram of partially updating image data in a display system 20. The display system 20 includes an application processor (AP) 202, a display driver circuit 204, and a display screen 206. The application processor 202 may be a core processor of the display system 20, and may be used as a video source or a video providing unit to provide display data for display on the display screen 206. The display driver circuit 204 may process the display data and convert the display data into data voltages to be output to pixels on the display screen 206. In one embodiment, the display driver circuit 204 may be implemented in an integrated circuit (IC) to realize a display driver integrated circuit (DDIC). Figure 2 In the following figures, the display driver circuit is abbreviated as DDIC, and those skilled in the art should understand that the DDIC referred to in the figures and the text represents a driver circuit that can be implemented in any way and used to drive the display screen. The display screen 206 can be any type of display device, such as an organic light emitting diode (OLED) panel, a liquid crystal display (LCD) panel, or any other panel that can be controlled by a scanning signal to display, but is not limited thereto.

[0081] Partial update of image data may be performed in the display system 20. Partial update means that the application processor 202 sends only part of the image data in an image frame to the display driver circuit 204. The image data sent is usually video data. The display driver circuit 204 may write the latest received image data into a memory (such as a random access memory (RAM)) to replace the previous image data of the same area, and the other unupdated image data is retained in the memory.

[0082] Next, the display driving circuit 204 outputs all image data in one frame to the display screen 206 to refresh the display screen 206. Since all pixels on the display screen 206 are refreshed, the power saving effect cannot be obtained on the display screen 206. Figure 2 FIG. 2 shows a series of image frame refresh operations (i.e., from F_1 to F_120), which are represented by Figure 2 It can be observed that all image data on these image frames are output to the display screen 206 .

[0083] In one embodiment, based on the way of dividing the display screen 206 in the x-direction and the y-direction, the display screen 206 can be refreshed only in a specific area in conjunction with a partial update implementation. Figure 3 As shown, the application processor 202 can send only the image data in the video area to the display driver circuit 204 in a similar manner. The display driver circuit 204 does not output a complete frame of image data to the display screen 206, but only refreshes part of the pixels in the video area within the image frame, thereby achieving different frame rates in different areas. Figure 3 In the example of , the video area is refreshed at a high frame rate of 120Hz, and other areas showing static images are refreshed at a very low frame rate of 1Hz. In other words, the low frame rate area can be refreshed in one frame out of every 120 image frames, which can achieve a significant reduction in power consumption.

[0084] Therefore, under the partial update implementation, the purpose of power saving can be achieved in the display driver circuit 204 and the display screen 206. On the display screen 206, a partial area on one or more image frames can be refreshed by a multi-frequency display operation. Therefore, in the unrefreshed area, the pixel does not receive any image data, so the corresponding data line will not be charged or discharged by the data voltage. Correspondingly, the scan line output for the unrefreshed area is locked or stopped, that is, the gate driver or the gate driver array (Gate-On-Array, GOA) circuit does not need to output a scan signal to drive the load on the display screen 206, thereby saving the power consumption of the gate / scan control.

[0085] In the display driver circuit 204, since the amount of image data received from the application processor 202 and output to the display screen 206 is reduced, the image data that needs to be processed by the display driver circuit 204 is less. For example, the digital circuit in the display driver circuit 204 may include some signal processing circuits for performing some signal processing operations on the received image data, and these signal processing operations include moire compensation (Mura compensation), subpixel rendering (subpixelrendering), and brightness and contrast adjustment, etc., but are not limited to this. The signal processing circuit only needs to process the image data that needs to be refreshed in the video area of ​​the smaller block, and it only needs to use less processing time. Therefore, during the time when there is no image data to be processed, these signal processing circuits can be turned off, or the clock signal for the signal processing circuit can be stopped to achieve power saving in the display driver circuit 204.

[0086] Figure 4 It shows that when a mobile phone 40 is operated in landscape mode, conventional y-direction splitting may not be effective in achieving power saving. Figure 4 As shown, the mobile phone 40 includes a display screen 400, which receives control of gate drive array (GOA) circuits 402_1 and 402_2 and a display driver circuit (DDIC) 404 to perform display. When the display screen 400 is placed horizontally, the display driver circuit 404 is disposed on the right side of the display screen 400, and the gate drive array circuit is located above and / or below the display screen 400. Figure 4 Two gate driving array circuits 402_1 and 402_2 are shown, which are respectively disposed on the upper and lower sides of the display screen 400. However, in another embodiment, only one gate driving array circuit may be disposed above or below the display screen.

[0087] In this case, the x direction is the vertical direction and the y direction is the horizontal direction. As described above, since a row of pixels coupled to the same scan line should be refreshed or not refreshed at the same time, the existing multi-frequency display operation is to allocate a high frame rate area (HFR) and a low frame rate area (LFR) along the y direction. However, in the prior art, different frame rates cannot be divided in the x direction to be allocated to different areas.

[0088] For example, in some application scenarios, the mobile phone 40 plays the video in a horizontal mode, such as Figure 5 As shown, blank (or text) areas are located above and below the display screen 400, and the video is displayed in the middle. Figure 4 The segmentation of the high frame rate region (HFR) and the low frame rate region (LFR) along the y direction shown cannot be realized in Figure 5In contrast, if the x-direction split is used, the refresh of the upper and lower blank areas can be omitted, thereby achieving a power saving effect of multi-frequency display operation in the horizontal mode.

[0089] Figure 6 FIG. 6 shows another application of x-division, where different frame rates can be allocated to different display areas on a foldable phone 60. The foldable phone 60 also includes a display screen 600, which receives control of gate drive array (GOA) circuits 602_1 and 602_2 and display driver circuits (DDIC) 604_1 and 604_2 to display. Figure 6 As shown, two serially connected display driver circuits 604_1 and 604_2 are disposed on the right side of the display screen 600, and gate driver array circuits 602_1 and 602_2 are respectively located above and below the display screen 600. It should be noted that Figure 6 The implementation is only an example. In another folding mobile phone, it is also possible to include only one display driving circuit or to set more than three display driving circuits to jointly control the display screen, or to set only one gate driving array circuit above or below the display screen, but it is not limited thereto.

[0090] Based on the division of the folding line, the display screen 600 of the folding mobile phone 60 may include three parts. The display operation of the folding mobile phone 60 is equivalent to a mobile phone when folded, and is equivalent to a tablet computer when unfolded. Figure 6 In the embodiment of the present invention, only the left part of the display screen 600 displays the image, and the undisplayed parts in the middle and right sides should preferably not be refreshed to save power consumption. For the display screen 600 in the folded state, the y-direction division can only turn off the refresh of the middle and right parts / areas, but the multi-frequency display operation cannot be performed on the display part / area on the left side of the display screen 600. The multi-frequency display operation on the left display part needs to be implemented by the x-direction division, so that the high frame rate area (HFR) and the low frame rate area (LFR) can be allocated in any appropriate manner. Through the joint operation of the x-direction division and the y-direction division, the frame rate of the display part on the left side of the display screen 600 can be flexibly allocated to achieve a significant improvement in power saving in the application of the folding mobile phone 60.

[0091] Fig. 7A and Figure 7B A schematic diagram of implementing x-direction segmentation on a display screen. Fig. 7A A display screen 700 is shown, which includes an active area 702 and two scan control circuits 710_1 and 710_2 respectively disposed on the left and right sides of the active area 702. The display screen 700 is controlled by a display driver circuit (DDIC) 720, which may be disposed below the display screen 700. Fig. 7AIt is shown that the left scan control circuit 710_1 drives the left half of the display screen 700 and the right scan control circuit 710_2 drives the right half of the display screen 700, that is, the scan line corresponding to the scan control circuit 710_1 is not connected to the scan line corresponding to the scan control circuit 710_2. In this example, a row may include 1080 pixels, which are divided into 10 groups, so each group has 108 pixels. The left scan control circuit 710_1 is responsible for controlling the left half of the panel and is coupled to 5 groups of pixels in each row; the right scan control circuit 710_2 is responsible for controlling the right half of the panel and is coupled to the other 5 groups of pixels in each row. The panel structure in which the left scan control circuit 710_1 and the right scan control circuit 710_2 each drive their corresponding areas can simplify the fanout of the connection lines on the display screen 700, so it has an optimized performance in terms of circuit cost and complexity.

[0092] Figure 7B Another display screen 750 is shown, which includes an active area 752 and two scan control circuits 760_1 and 760_2 respectively disposed on the left and right sides of the active area 752. The display screen 750 is controlled by a display driver circuit (DDIC) 770, which can be disposed below the display screen 750. Figure 7B As shown, the display screen 750 is another embodiment, wherein the left scan control circuit 760_1 and the right scan control circuit 760_2 jointly drive all pixels of the active area 752, that is, each scan line on the display screen 750 is connected between the left and right scan control circuits 760_1 and 760_2. In this example, if a row of pixels is divided into 10 groups, the scan control circuits 760_1 and 760_2 can be commonly coupled to a row of pixels through 10 scan lines, wherein each scan line is coupled to one of the 10 groups of pixels. Since a scan signal can be outputted from the left scan control circuit 760_1 and the right scan control circuit 760_2 at the same time, Figure 7B The illustrated embodiment allows for optimized reliability.

[0093] like Fig. 7A and Figure 7BAs shown, each scan control circuit 710_1, 710_2, 760_1 and 760_2 may include a shift circuit (represented by 712_1, 712_2, 762_1 and 762_2, respectively) and a multiplexer (MUX) circuit (represented by 714_1, 714_2, 764_1 and 764_2, respectively). Each shift circuit 712_1, 712_2, 762_1 and 762_2 may be included in a gate drive array circuit of the display screen 700 or 750. Each multiplexer circuit 714_1, 714_2, 764_1 and 764_2 may be considered to be coupled between the corresponding gate drive array circuit and the active area 702 or 752 of the display screen 700 or 750, or may be considered to be included in the gate drive array circuit of the display screen 700 or 750. The shift circuits 712_1, 712_2, 762_1 and 762_2 may receive gate drive array (GOA) signals (including gate drive array clock, start pulse and / or reset signal, etc., but not limited thereto) from the corresponding display driving circuits 720 and 770, and correspondingly generate scan control signals for each row of pixels. The multiplexer circuits 714_1, 714_2, 764_1 and 764_2 may receive scan control signals from the corresponding shifter circuits 712_1, 712_2, 762_1 and 762_2, wherein each scan control signal may be used to control a row of pixels. The multiplexer circuits 714_1, 714_2, 764_1 and 764_2 may also receive enable signals from the corresponding display driving circuits 720 and 770, and correspondingly output a plurality of scan signals to pixels according to the enable signals and the scan control signals, wherein each scan signal corresponds to a group of pixels.

[0094] For example, in Fig. 7A In the embodiment of FIG. 7 , a row of pixels is divided into 10 groups, the left half of the display screen 700 is controlled by the left scan control circuit 710_1 and the right half of the display screen 700 is controlled by the right scan control circuit 710_2. Therefore, each scan control circuit 710_1 and 710_2 can control 5 groups of pixels in a row, and thus can output 5 scan signals to the 5 groups of pixels respectively. The multiplexer circuits 714_1 and 714_2 can receive 5 enable signals (EN_L, EN_R) respectively to generate 5 scan signals.

[0095] exist Figure 7B In the embodiment of FIG. 1 , a row of pixels is also divided into 10 groups, and the left scan control circuit 760_1 and the right scan control circuit 760_2 jointly control the 10 groups of pixels in each row. Therefore, each scan control circuit 760_1 and 760_2 can output 10 scan signals to the 10 groups of pixels respectively. The multiplexer circuits 764_1 and 764_2 can receive 10 enable signals (EN) respectively to generate 10 scan signals.

[0096] The display driving circuits 720 and 770 can determine whether the scan signal needs to be output to the corresponding group of pixels, and output an enable signal to the scan control circuit accordingly. Each enable signal can be used to control whether to enable or disable the output of the scan signal for the corresponding group of pixels. If it is decided to refresh a group of pixels, the enable signal can be located at a specific level to enable the scan signal to be output to the group of pixels; if it is decided not to refresh a group of pixels, the enable signal can be located at another level to lock the scan signal so that the scan signal is locked at this level to turn off the corresponding transistor in the pixel. Therefore, in each image frame, each group of pixels can be dynamically set to refresh or not refresh, thereby achieving segmentation in the x direction. In addition, segmentation in the y direction can also be achieved by sequentially scanning pixels row by row.

[0097] Different from the existing multi-frequency display operation in which each scan signal is output to a whole row of pixels and refresh or not is determined row by row, in the present invention, by dividing a row of pixels into multiple groups and outputting a scan signal to each group, x-direction division can be achieved, so that refresh can be determined group by group.

[0098] In this case, the grouping method can achieve a combination of x-direction segmentation and y-direction segmentation. Fig. 7A or Figure 7B The pixel structure shown can be configured such that the high frame rate region (HFR) in the middle is surrounded by low frame rate regions (LFR) on all sides. To achieve this configuration, the middle 4 groups of pixels in some middle rows can be assigned to the high frame rate region, and the other groups can be assigned to the low frame rate region, so that the following can be achieved: Figure 8 The target refresh rate configuration is shown, in which the high frame rate area in the middle can be refreshed with a high frame rate of 120 Hz, and the low frame rate area at the periphery can be refreshed with a low frame rate of 1 Hz.

[0099] Fig. 9 FIG. 9 is a flow chart of a scanning process 90 according to an embodiment of the present invention. The scanning process 90 can be implemented in a display driving circuit and a scanning control circuit for controlling a display screen, such as Fig. 7A and Figure 7B The display driving circuits 720 and 770 and the scanning control circuits 710_1, 710_2, 760_1 and 760_2 in the display screen have a plurality of pixels, wherein a row of pixels can be divided into a plurality of groups of pixels. Fig. 9 As shown, the scanning process 90 includes the following steps:

[0100] Step 902: Generate a scanning control signal for the row of pixels when scanning the row of pixels.

[0101] Step 904: Output a plurality of enabling signals, wherein each enabling signal is used to control one of the plurality of groups of pixels.

[0102] Step 906 : When scanning the row of pixels, determine whether to output a scan signal to each of the plurality of groups of pixels according to the scan control signal and each of the plurality of enable signals.

[0103] On the display screen, the row of pixels may represent a row of pixels or a column of pixels. For a general mobile phone, the display driving circuit may be arranged below the display screen, and the scanning control circuit (such as a gate driving array circuit) may be arranged on the left and / or right side of the display screen. Therefore, a data line of the display driving circuit is coupled to a column of pixels, and a scanning line of the scanning control circuit is coupled to a row of pixels, so that each row of pixels can be divided into a plurality of groups to achieve segmentation in the x direction. On the other hand, for a tablet computer or a folding mobile phone, the display driving circuit may be arranged on the left or right side of the display screen, and the scanning control circuit may be arranged above and / or below the display screen. Therefore, a data line of the display driving circuit is coupled to a row of pixels, and a scanning line of the scanning control circuit is coupled to a column of pixels, so that each column of pixels can be divided into a plurality of groups to achieve segmentation in the x direction. It should be noted that in these embodiments, the pixels are scanned sequentially along the y direction, and each row of pixels is arranged and grouped along the x direction.

[0104] According to the scanning process 90, the scanning control circuit can generate a scanning control signal for each row of pixels when scanning each row of pixels. The display driving circuit can output multiple enable signals to the scanning control circuit, wherein each enable signal corresponds to a group of pixels in the row of pixels. According to the enable signal, the scanning control circuit can determine whether to output a scanning signal to each group of pixels when scanning the row of pixels. More specifically, if it is decided to refresh a first group of pixels within an image frame, the scanning signal can be output to the first group of pixels within this image frame; if it is decided not to refresh a second group of pixels within an image frame, the scanning signal can not be output to the second group of pixels within this image frame, wherein the scanning signal or scanning line corresponding to the second group of pixels can be stopped or locked by the corresponding enable signal. In other words, since the first group of pixels is assigned to the high frame rate area, the scanning signal is output to the first group of pixels; since the second group of pixels is assigned to the low frame rate area, the scanning signal is not output to the second group of pixels.

[0105] Fig.10 Shows Fig. 7A A portion of the display screen 700 or Figure 7BDetailed implementation of a portion of the display screen 750 in FIG. 1 shows an exemplary structure of a shift circuit 1002 and a multiplexing circuit 1004 included in a scan control circuit 1000. The scan control circuit 1000 outputs scan signals to the right to the corresponding pixels, so it can be used to implement the scan control circuit 710_1 or 760_1 on the left. The scan control circuits 710_2 and 760_2 on the right can be implemented in a similar manner, and those skilled in the art can refer to Fig.10 The structure and operation method of the right scan control circuits 710_2 and 760_2 can be inferred from the content.

[0106] Fig.10 The figure shows some rows of pixels located in the left half of the panel and the related circuits used to control these pixels in the scan control circuit 1000. In detail, each row of pixels includes 5 groups of pixels, and each group of pixels can receive a scan signal from the multiplexer circuit 1004. The shift circuit 1002 can generate and output a scan control signal SC_N~SC_(N+3) for each row of pixels. For example, for the pixels located in the Nth row, the multiplexer circuit 1004 can output 5 scan signals to the 5 groups of pixels through the scan lines G[N]_L1~G[N]_L5 respectively. The shift circuit 1002 can output a scan control signal SC_N to the multiplexer circuit 1004 to generate these scan signals for the Nth row. In detail, the shift circuit 1002 may include a plurality of shift registers (S / R), each of which is used to output one of the scan control signals SC_N~SC_(N+3).

[0107] If the display screen only supports y-direction segmentation, a scan control signal and an enable signal may be used to generate a scan signal for outputting to a row of pixels. Fig.10In the embodiment of , x-direction division is added, and the structure of the shift circuit 1002 remains the same, but the multiplexing circuit 1004 is implemented by a plurality of logic operation circuits M_N~M_(N+3), wherein each logic operation circuit M_N~M_(N+3) is coupled to a row of pixels to output a scan signal to the row of pixels according to the control of the enable signal EN_L1~EN_L5. The logic operation circuits M_N~M_(N+3) can respectively receive corresponding scan control signals SC_N~SC_(N+3) from the shift circuit 1002, and at the same time receive the enable signal EN_L1~EN_L5 from the display driving circuit to generate a scan signal. For example, for pixels located in the Nth row, the logic operation circuit M_N may include 5 output terminals, wherein each output terminal is coupled to a group of pixels on the Nth row. Each logic operation circuit M_N-M_(N+3) may include five logic gates, wherein each logic gate may perform a logic operation on a corresponding scan control signal SC_N-SC_(N+3) and one of the enable signals EN_L1-EN_L5 to generate a corresponding scan signal.

[0108] In this example, it is assumed that the scan signal output to the display screen is used to control an NMOS transistor, so the scan signal is a high-active signal, which is usually at a low level, and an upward pulse is added during the corresponding horizontal line to turn on the NMOS transistor. Therefore, the logic operation circuit M_N~M_(N+3) can use an "AND" gate to generate a scan signal. In this case, the scan signal can be enabled when the corresponding enable signal is at a "high" level, and disabled (i.e. locked and forced to be at a "low" level) when the corresponding enable signal is at a "low" level.

[0109] like Fig.10 As shown, the enable signals EN_L1 to EN_L5 are first at a "low" level for the unrefreshed low frame rate area (LFR). When the scanning operation enters the high frame rate area (HFR) at the N+2th row, the corresponding enable signal can be switched to a "high" level. In this example, the enable signals EN_L4 and EN_L5 are switched to a "high" level to enable the corresponding scanning signals to refresh the pixel groups located in the high frame rate area, and the enable signals EN_L1, EN_L2 and EN_L3 are maintained at a "low" level to achieve x-direction segmentation. In this way, the x-direction segmentation can be performed by controlling the state of each enable signal separately during each horizontal line period (spatial control); the y-direction segmentation can be performed by controlling the state of the enable signal during different horizontal lines during a frame period (temporal control).

[0110] Fig.11 for Fig.101 is a waveform diagram of the scan control circuit 1000 in FIG. 1 , which shows that the scan operation enters the high frame rate region from the low frame rate region and then returns to the low frame rate region. Fig.11 The clock signals CLK and CLKB, the start pulse STV, the enable signals EN_L1 to EN_L5, and the scan signals on the scan lines G[1]_L1 to G[1]_L5, G[2]_L1 to G[2]_L5 ... G[M]_L1 to G[M]_L5 ... are shown. The clock signals CLK and CLKB and the start pulse STV may be output by the display driver circuit (DDIC) to the shift circuit 1002, and the enable signals EN_L1 to EN_L5 may be output by the display driver circuit to the multiplexing circuit 1004.

[0111] The high frame rate area starts at the Rth row and ends at the Mth row. Based on the x-direction segmentation, the high frame rate area only includes part of the pixel groups in a row. Therefore, the corresponding enable signals EN_L4 and EN_L5 are pulled "high" to enable the scan control of these pixel groups, and the other enable signals EN_L1~EN_L3 are maintained at the "low" level, so that the corresponding scan lines are locked at the "low" level. According to the shift of the shift circuit 1002 in response to the shift of the start pulse STV, the scan signal can be output sequentially on the scan lines G[x]_L4 and G[x]_L5, where x is from R to M-1 (R<(M-1)), to correspond to the high frame rate area and controlled by the enable signals EN_L4 and EN_L5.

[0112] Fig.12 Schematic diagram of a detailed implementation of a pixel located in the active area of ​​a display screen. In this example, each pixel is coupled to two scan lines to receive a current scan signal NSCAN[N] and a previous scan signal NSCAN[N-1]. In each row of pixels, two pixels belonging to different groups can be controlled by different sets of scan signals, wherein each set of scan signals includes a current scan signal NSCAN[N] and a previous scan signal NSCAN[N-1]. For example, pixels located in a first group G1 can receive the current scan signal NSCAN[N] from the scan line G[N]_L1 and the previous scan signal NSCAN[N-1] from the scan line G[N-1]_L1, and pixels located in a second group G2 can receive the current scan signal NSCAN[N] from the scan line G[N]_L2 and the previous scan signal NSCAN[N-1] from the scan line G[N-1]_L2. Each scan line may be coupled to a pixel group in a first row of pixels to transmit a current scan signal NSCAN[N] to the pixel group, and coupled to another pixel group in a second row of pixels to transmit a previous scan signal NSCAN[N-1] to the pixel group.

[0113] In detail, in order to achieve the x-direction segmentation, the pixel circuit structure located in the active area does not need to be changed or modified, and the grouping can be achieved by connecting different scan lines to different pixel groups. These scan lines can be respectively coupled to different output ends of the multiplexing circuit included in the scan control circuit, which can be set at the boundary of the display screen. In another embodiment, for each row of pixels, the scan line used to transmit the current scan signal NSCAN[N] is coupled to a scan control circuit, and the scan line used to transmit the previous scan signal NSCAN[N-1] is coupled to another scan control circuit. In another embodiment, the pixel may have another circuit structure, so it needs to be coupled to a different number of scan lines to receive different numbers of scan signals from the scan control circuit.

[0114] Since a group of pixels in a row may receive more than one scan signal from different scan lines, different enable signals may be used to generate these scan signals. Fig.13 FIG. 1 is a schematic diagram of another display screen according to an embodiment of the present invention. Fig.13 As shown, the scan control circuit includes two shift circuits 1302_1 and 1302_2 and a multiplexer circuit 1304. In this example, although each row of pixels controlled by the scan control circuit has 5 groups, the scan control circuit can output 10 scan signals to the 5 groups of pixels, wherein each group of pixels receives 2 scan signals. The shift circuits 1302_1 and 1302_2 can respectively receive different start pulses STV1 and STV2 and shift the scan pulses to generate scan control signals, and output the scan control signals to the multiplexer circuit 1304. The multiplexer circuit 1304 can receive the scan control signals from the shift circuits 1302_1 and 1302_2 respectively, and simultaneously receive enable signals EN_L1~EN_L5 and EN2_L1~EN2_L5 from the display driving circuit. The multiplexer circuit 1304 may include 2 logic operation circuits for a row of pixels, which are used to perform logic operations to generate corresponding scan signals.

[0115] For example, for the pixels in the Nth row, the shift circuits 1302_1 and 1302_2 may generate scan control signals SC_N and SC2_N, respectively. The multiplexer circuit 1304 receives the scan control signals SC_N and SC2_N from the shift circuits 1302_1 and 1302_2, respectively. In the multiplexer circuit 1304, the logic operation circuit M_N may perform a logic operation on the scan control signal SC_N and each of the enable signals EN_L1 to EN_L5 to generate five scan signals, which are respectively output through the scan lines G[N]_L1 to G[N]_L5; and the logic operation circuit M2_N may perform a logic operation on the scan control signal SC2_N and each of the enable signals EN2_L1 to EN2_L5 to generate another five scan signals, which are respectively output through the scan lines G2[N]_L1 to G2[N]_L5. Correspondingly, each group of pixels is coupled to two scan lines, and the scan signals transmitted on the scan lines can be generated by different scan control signals (such as SC_N and SC2_N). In other words, the scan signal received by a pixel can be generated by different logic operation circuits according to different enabling signals.

[0116] Fig.14 Shows Fig.13 A detailed implementation of coupling the scan lines to the pixels. A pixel located in the Nth row can receive two scan signals NSCAN1[N] and NSCAN2[N] respectively from two different scan lines (such as G[N]_L1 and G2[N]_L1). The two scan signals NSCAN1[N] and NSCAN2[N] can be generated by different shift circuits 1302_1 and 1302_2, which have a shift in the control timing to solve the problem of horizontal lines appearing at the time point when the frame rate changes. In one embodiment, the scan signal NSCAN1[N] may be a previous scan signal NSCAN[N-1] used to control the initialization of each pixel, and the scan signal NSCAN2[N] may be a current scan signal NSCAN[N] used to control the writing of data to each pixel. Fig.13 and Fig.14 As shown, different shift circuits 1302_1 and 1302_2 with different start pulses STV1 and STV2 can be used to generate scan signals NSCAN1[N] and NSCAN2[N] with 1H shift (ie, shift during one horizontal line period) to respectively implement the previous scan signal NSCAN[N-1] and the current scan signal NSCAN[N].

[0117] It is worth noting that Fig.13 and Fig.14It is shown that each group of pixels is controlled by two shift circuits included in a scan control circuit, but the present invention is not limited to this. In fact, a pixel group can be coupled to and receive control (i.e., receive scan signals) of one or more scan control circuits (such as one or more gate drive array circuits), and the number of scan control circuits used for scan control should not be used to limit the scope of the present invention. From one aspect, each pixel group can receive a set of scan signals from the scan control circuit, wherein different pixel groups located in the same row can receive different sets of scan signals. In one embodiment, a row of pixels can be divided into 10 groups, so the scan control circuit can output 10 sets of scan signals to 10 groups of pixels respectively, and each set of scan signals can include any number of scan signals, not limited to the situation described in this specification.

[0118] Fig.15 An exemplary implementation of a logic operation circuit 150 in an embodiment of the present invention is shown. The logic operation circuit 150 can be used to implement any one of the logic operation circuits M_N~M_(N+3), which includes 5 "AND" gates, which are respectively coupled to 5 scan lines G[N]_L1~G[N]_L5. Each "AND" gate can be implemented using two transistors. Node SR_NODEA represents a corresponding output of the shift circuit. Each "AND" gate has two input terminals, one of which is coupled to the node SR_NODEA, and the other is coupled to the display driving circuit to receive an enable signal (such as one of the enable signals EN_L1~EN_L5). The "AND" gate can be used to generate a scan signal and output the scan signal to the corresponding pixel group through the corresponding scan lines G[N]_L1~G[N]_L5. In this example, each "AND" gate is commonly coupled to the input node SR_NODEA and commonly receives the clock signal CLK / CLKB and the supply voltages VGH and VGL through the same endpoint to simplify the circuit structure. Based on Fig.15 In the circuit structure shown, a high-level pulse is generated on the scan lines G[N]_L1 to G[N]_L5 only when the clock signal CLK is at a "high" level, the node SR_NODEA is at a "high" level, and the corresponding enable signal is at a "high" level (i.e., the scan line is not locked).

[0119] In the above embodiment, the high frame rate area is located in the center of the panel and is surrounded by the low frame rate area. This implementation can be achieved by combining x-direction segmentation and y-direction segmentation, wherein the x-direction segmentation can be performed by individually controlling different pixel groups in the same row to refresh, and the y-direction segmentation can be performed by controlling the enable signal during the scanning operation. It should be noted that the high frame rate area (such as the refresh area) and the low frame rate area (such as the non-refresh area) can be allocated in any appropriate manner.

[0120] For example, Fig.16Another frame rate configuration method on the display screen 700 is shown, wherein the configuration method of the pixel group and its related control circuit are the same as Fig. 7A As shown in Figure 1, the same circuit components and signals are represented by the same symbols. Fig.16 As shown, the high frame rate region (HFR) includes all pixels located in a portion of the middle column, and has two low frame rate regions (LFR) on the left and right sides thereof.

[0121] The frame rate configuration in this embodiment can be achieved by performing only x-direction segmentation, and Fig.17 FIG. 2 shows the operation of the scanning control circuit to implement this frame rate configuration mode. Fig.17 As shown, according to whether the corresponding pixel group is located in the high frame rate area or the low frame rate area, each enable signal EN_L1~EN_L5 is maintained at a "high" level or a "low" level in an image frame. More specifically, if a row of pixels are all located in the high frame rate area, the corresponding enable signal is continuously at a "high" level; or if a row of pixels are all located in the low frame rate area, the corresponding enable signal is continuously at a "low" level.

[0122] The detailed waveform of the scanning control circuit of this embodiment is shown in Fig.18 , which shows the scanning signal on the display screen 700 and the signal output by the display driver circuit (DDIC) 720. Fig.18 As shown, during this frame period, the enable signals EN_L1 and EN_L2 are continuously at the "low" level, while the enable signals EN_L3, EN_L4 and EN_L5 are continuously at the "high" level. The scan signal can be output sequentially through the scan lines G[x]_L3, G[x]_L4 and G[x]_L5, where x is from 1 to the total number of rows of the panel, indicating that the entire column of pixels is allocated to the high frame rate area to receive the scan signal.

[0123] In another embodiment, the high frame rate region includes all pixels located in a portion of the middle row, and there are two low frame rate regions (LFR) above and below the middle high frame rate region (HFR), such as Fig.19 shown.

[0124] The frame rate configuration in this embodiment can be achieved by performing only y-direction segmentation, and Fig. 20 FIG. 2 shows the operation of the scanning control circuit to implement this frame rate configuration mode. Fig. 20 As shown, the enable signals EN_L1 to EN_L5 all change state at the same time. Therefore, a row of pixels can be completely located in the high frame rate area or completely located in the low frame rate area. Fig.19 As shown, the pixel rows between the Rth row and the Mth row are located in the high frame rate area, and the other pixel rows are located in the low frame rate area.

[0125] The detailed waveform of the scanning control circuit of this embodiment is shown in Fig.21 , which shows the scanning signal on the display screen 700 and the signal output by the display driver circuit (DDIC) 720. Fig.21 As shown, all enable signals EN_L1 to EN_L5 are switched to a "high" level in row R and switched to a "low" level in row M. Therefore, the scan signals can be sequentially output on all scan lines between row R and row M-1 (R<(M-1)).

[0126] It can be seen that based on the implementation method of grouping each row of pixels in the present invention and the proposed scanning control circuit structure, the refresh area and the non-refresh area can be allocated in any appropriate manner by performing x-direction segmentation, y-direction segmentation, or both, wherein a group of pixels (rather than a complete row of pixels) can be regarded as a unit for frame rate configuration. Fig. 22 Several possible high frame rate and low frame rate configurations on the display screen are shown. It should be noted that the frame rate configuration is not necessarily symmetrical. For example, the high frame rate area (HFR) or the low frame rate area (LFR) does not need to be set in the middle row or middle column, but can be set in any way according to the image content. In other embodiments, there may be multiple high frame rate blocks and / or multiple low frame rate blocks on an image frame. By controlling multiple enable signals from the display driver circuit, each group of pixels can be flexibly and dynamically allocated to the high frame rate area to receive a set of scan signals for refresh, or allocated to the low frame rate area to stop the refresh operation. In fact, the frame rate configuration method is not limited to the implementation method proposed in this specification.

[0127] The implementation of omitting refresh of some pixels on the display helps save power. If most areas on the display display are displaying a static image, these areas can be operated at a very low frame rate and refreshed only on a few image frames. In the unrefreshed areas, in addition to stopping the output of the scan signal, power consumption can be further saved by stopping the transmission of display data through the data line. In other words, the display driver circuit will not output display data to the data line, so the data line will not be charged or discharged, thereby saving power.

[0128] If the x-direction segmentation is combined with the y-direction segmentation, the high frame rate area that needs to be refreshed can be minimized. Therefore, the power saving effect achieved on the data line can also be optimized. Fig.23 shown.

[0129] More specifically, if only the y-direction segmentation is performed (e.g. Fig.23 The high frame rate area must include a complete row of pixels, where data lines DL_1 to DL_3 are required to perform data output. In contrast, when x-direction segmentation is added (e.g. Fig.23), the high frame rate area is configured as a group of pixels. In this case, the high frame rate area may only include pixels that need to be refreshed, so only the data line DL_2 corresponding to the high frame rate area needs to output data, and the other data lines DL_1 and DL_3 can be disabled (such as set to float or locked at a specific level), thereby reducing the charge and discharge operations on the data lines.

[0130] It is worth noting that the display driving circuit can output display data to the data line through a source driving device. The source driving device may include multiple output channels, which are coupled to multiple data lines on the display screen, wherein each output channel includes a source operational amplifier (Source Operational Amplifier, SOP), a digital-to-analog converter (Digital-to-Analog Converter, DAC), a latch circuit (latch circuit), and a shift register. In one embodiment, in order to save power consumption, when a data line does not need to receive image data, the source operational amplifier, digital-to-analog converter and / or any other circuit components on the corresponding output channel can be disabled or turned off. For example, if Fig.23 As shown in the right half of , during this frame period, the output channels corresponding to the data lines DL_1 and DL_3 can be kept constantly off. The output channel corresponding to the data line DL_2 is first turned off, then turned on when the scanning operation enters the high frame rate area, and then turned off when the scanning operation enters the low frame rate area. Therefore, compared with the case of only performing y-direction segmentation, when adding x-direction segmentation, the high frame rate area can be minimized, so that the power saving effect that can be achieved by stopping the image data output is optimized.

[0131] In one embodiment, output channels for different pixel groups can be enabled or disabled by different enable signals. Therefore, circuit components (such as source operational amplifiers and digital-to-analog converters) on different output channels of the source driver can be controlled differently, thereby achieving power saving according to the frame rate configuration of the display screen.

[0132] The above paragraphs illustrate that the display driver circuit can stop data output and shut down its internal circuit blocks to achieve power saving. In addition, power saving can also be achieved in the gate driver device or gate driver array circuit. Fig.24 As shown, in the area marked by the dotted line (ie, the low frame rate area), the scan signal is locked and does not switch, so the scan control circuit does not need to drive the load of the scan line on the display screen, thereby achieving the purpose of power saving.

[0133] Fig.25An application scenario of x-segmentation on a display screen of a display system 250 is shown. The display system 250 may be a mobile phone, which includes an application processor 2502, a display driver circuit (DDIC) 2504, and a display screen 2506. The display screen 2506 may display a wallpaper, in which most images are static images, and only one application icon is included to display a dynamically running clock. In this case, the icon of the clock is required to be displayed at a high refresh rate, and other images are preferably displayed at a low refresh rate to save power.

[0134] In such an application, in order to reduce the amount of data and save the data transmission time between the application processor 2502 and the display driver circuit 2504, the image data transmitted from the application processor 2502 to the display driver circuit 2504 can be compressed data. For example, a frame of image data can be divided into several compressed blocks, and the image data of each block can be compressed and packaged in the application processor 2502 before being output to the display driver circuit 2504. The display driver circuit 2504 is usually provided with two decoders DEC1 and DEC2 for decompressing the received image data, wherein the decoder DEC1 is responsible for processing the image data of the left half panel, and the other decoder DEC2 is responsible for processing the image data of the right half panel. A certain number of pixels in a row of the left half panel can be divided into a compressed block, and the image data in the block can be compressed and transmitted; and the pixels in the same row of the right half panel can be divided into another compressed block, and the image data in the block can be compressed and transmitted.

[0135] In the image frame, the only dynamic part is the diagram of the operating clock, which is much smaller than the size of a compressed block. In the transmission scheme using compression, the application processor 2502 can compress the image data in a block and output the compressed image data to the display driver circuit 2504, and then the display driver circuit 2504 decompresses the received data to restore the original image data. When a partial update implementation is adopted, the application processor 2502 should send at least one complete block of compressed data to ensure that the image data can be successfully decompressed by the decoder (DEC1 and / or DEC2) of the display driver circuit 2504. In other words, a partial update needs to be performed with a compressed block as the transmission unit.

[0136] In order to save power when only a small block of the image of the icon needs to be updated, the application processor 2502 can send the uncompressed raw data of the icon in a partial update mode. In this case, the application processor 2502 does not need to output all the image data of the complete compressed block, and its data volume is usually larger than the icon area; instead, the application processor 2502 only needs to output the image data of the icon. In one embodiment, the application processor 2502 can send the address information of the icon together with the raw data of the icon area to the display driver circuit 2504. Therefore, according to the address information, the display driver circuit 2504 can use the received raw data to refresh the area of ​​the icon on the display screen 2506 without decompression. Through the joint operation of the x-direction segmentation and the y-direction segmentation, the refresh area can be minimized, and it is possible that the refresh area is much smaller than the compressed block. In one embodiment, the application processor 2502 and the display driver circuit 2504 can be set to have a raw data mode, which omits the data compression and decompression operations. If the image frame needs to be completely updated, or the partially updated refresh area is larger than a specific critical value, the application processor 2502 and the display driver circuit 2504 can be in a general compression mode to transmit and receive compressed image data; if the partially updated refresh area is smaller than the critical value, the application processor 2502 and the display driver circuit 2504 will enter the raw data mode to transmit and receive uncompressed raw data.

[0137] In one embodiment, in order to achieve the optimal power saving effect of the x-direction segmentation and the partial update of the interface between the application processor and the display driver circuit, the compression scheme can correspond to the segmentation and grouping in the x-direction. That is, the image data to be transmitted to the display driver circuit can be compressed as a unit of a group size corresponding to one or more groups of pixels, and the display driver circuit can decompress the image data in the same unit.

[0138] Fig.26A 2 shows a related embodiment, which shows a display system 260 having an application processor 2602, a display driver circuit (DDIC) 2604 and a display screen 2606. Fig.26AAs shown, each row of pixels on the display screen 2606 is divided into 10 groups, and each group is assigned to have a frame rate. In this example, a row may include 1080 pixels, so each group includes 108 pixels. Correspondingly, the encoder of the application processor 2602 can compress the image data according to the compression block, wherein each row of pixels is also divided into 10 compression blocks, wherein each compression block corresponds to the group size (such as the number of columns in a group) divided in the x direction. Therefore, since a row includes 1080 pixels, each compression block may include 108 columns and one or more rows of pixels. The display driver circuit 2604 includes one or more decoders, which perform block-based decompression in a corresponding manner. Therefore, the image data of each block after decompression can correspond to one or more groups.

[0139] like Fig.26A As shown, the display driver circuit 2604 can perform a complete update to refresh all pixels on the display screen 2606 within an image frame. Therefore, the application processor 2602 can send a complete frame of image data to the display driver circuit 2604, and all pixels on the display screen 2606 are allocated to the high frame rate area (HFR), and thus refreshed in this image frame.

[0140] When partial updates are performed with multi-frequency display operation, such as Fig.26B As shown, data compression and decompression can still be performed in units of one or more groups of pixels. In detail, the high frame rate area (HFR) for performing refresh can be allocated to several rows of pixels and 4 pixel groups in each row. The application processor 2602 can compress image data in several compression blocks corresponding to the high frame rate area (i.e., 4 blocks in a row), and send the compressed image data in these blocks to the display driver circuit 2604. The display driver circuit 2604 can receive the image data of the high frame rate area and its related address information from the application processor 2602, so as to decompress the received image data according to the address information. Then, the display driver circuit 2604 can use these image data to refresh the high frame rate area of ​​the display screen 2606.

[0141] It is worth noting that the purpose of the present invention is to provide a method for controlling a display screen under a multi-frequency display operation. Those skilled in the art may make modifications or changes accordingly, but are not limited thereto. For example, in the above embodiment, the multiplexing circuit uses an "AND" gate with an enable signal to generate a high-activity pulse on the scan signal to control the output of the scan signal. In another embodiment, the logic operation circuit in the multiplexing circuit may include an "OR" gate to generate and output a low-active scan signal. Preferably, the high-activity scan signal is used to control the N-type metal oxide semiconductor transistor in the pixel, and the low-activity scan signal is used to control the P-type metal oxide semiconductor transistor (PMOS transistor) in the pixel. In addition, the pixels can be grouped in any manner, which is not limited to the manner described in the above specification. For example, a row of pixels can be divided into any number of groups, wherein an implementation in which a row includes 10 pixel groups is only an exemplary embodiment. As long as a row of pixels is divided into multiple groups, and each group independently and individually receives a scan signal to achieve x-direction segmentation, the relevant implementations should all fall within the scope of the present invention.

[0142] In addition, the frame rate configuration can generate one or more high frame rate regions and one or more low frame rate regions on an image frame. A series of image frames with predetermined high frame rate regions and low frame rate regions can be combined to achieve any frame rate combination. For example, Fig. 27 An exemplary frame rate configuration method for a series of image frames F_1 to F_120 according to an embodiment of the present invention is shown. Each pixel group in a row can be dynamically allocated to a high frame rate area or a low frame rate area, wherein the pixels are refreshed in the high frame rate area and not refreshed in the low frame rate area, thereby achieving different frame rates. In this example, most areas are displayed at an extremely low frame rate of 1 Hz, so only 1 frame is refreshed in every 120 image frames (i.e., only refreshed in F_1). The display screen includes a 60 Hz block (which is refreshed in 1 of every 2 image frames), a 30 Hz block (which is refreshed in 1 of every 4 image frames), and a 120 Hz block (which is refreshed in 1 of every 120 image frames F_1 to F_120).

[0143] In summary, the present invention proposes a novel multi-frequency display operation, whose frame rate configuration can be divided not only along the y direction, but also along the x direction, where the x direction is the direction in which the scan line connects a row of pixels. To achieve the x-direction division, each row of pixels can be divided into a plurality of pixel groups, and each pixel group is coupled to a respective scan line group. A scan control circuit is provided on the display screen, which can generate a plurality of scan signals for a row of pixels by receiving a plurality of enable signals, wherein the scan signal can be output to the corresponding pixel group according to whether the pixel group is to be refreshed in each frame. Through different enable signals, each pixel group can be controlled separately and independently, thereby achieving the x-direction division. The display driving circuit can output an enable signal to determine the area on the panel that needs to be refreshed, and correspondingly enable or disable the source data output to achieve the purpose of power saving. For example, when one or more circuit components in the source driving device correspond to the unrefreshed area and do not need to output image data, these circuit components can be turned off. In addition, the display driver circuit can perform a partial update to receive image data of a small video area, so that part of the signal processing circuit only needs to use a short processing time and can be disabled at a time point when image data is not needed to be processed to save power. In this way, the power saving effect under multi-frequency display operation is optimized through x-direction segmentation.

[0144] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for controlling a display screen, characterized in that: The display screen has a plurality of pixels, wherein a row of pixels is divided into a plurality of groups of pixels, and the method comprises: When scanning the row of pixels, generating a scanning control signal for the row of pixels; outputting a plurality of enabling signals, wherein each enabling signal is used to control one of the plurality of groups of pixels; and When scanning the row of pixels, whether to output a scanning signal to each of the plurality of pixel groups is determined according to the scanning control signal and each of the plurality of enabling signals.

2. The method according to claim 1, characterized in that The plurality of pixels are scanned sequentially along a first direction, and the row of pixels is arranged along a second direction different from the first direction.

3. The method according to claim 1, characterized in that The plurality of groups of pixels include a first group of pixels and a second group of pixels, and the method further includes: When scanning the row of pixels in an image frame, outputting the scanning signal to the first group of pixels; and When scanning the row of pixels in the image frame, the output of the scanning signal to the second group of pixels is stopped.

4. The method according to claim 3, characterized in that The first group of pixels is allocated to a high frame rate region, and the second group of pixels is allocated to a low frame rate region, wherein the frame rate of the high frame rate region is greater than the frame rate of the low frame rate region.

5. The method according to claim 3, characterized in that In the image frame, the first group of pixels is refreshed while the second group of pixels is not refreshed.

6. The method according to claim 1, characterized in that The step of determining whether to output the scanning signal to each of the plurality of groups of pixels comprises: A logic operation is performed on the scan control signal and each of the plurality of enable signals to determine whether to output the scan signal to each of the plurality of pixel groups.

7. The method according to claim 1, characterized in that The plurality of pixel groups include a first pixel group and a second pixel group. The first pixel group is controlled by a first scanning signal group, and the second pixel group is controlled by a second scanning signal group different from the first scanning signal group.

8. The method according to claim 7, characterized in that Each of the first group of scan signals and the second group of scan signals includes a first scan signal generated by a first scan control signal and a second scan signal generated by a second scan control signal.

9. The method according to claim 8, characterized in that The first scan signal is generated according to a first enable signal among the plurality of enable signals, and the second scan signal is generated according to a second enable signal among the plurality of enable signals that is different from the first enable signal.

10. The method according to claim 1, characterized in that An image data of the plurality of pixels is compressed or decompressed using a group size corresponding to one or more groups of the plurality of groups of pixels as a unit.

11. The method according to claim 1, characterized in that An image frame has a refresh area, and the method further includes: When the refresh area is smaller than a critical value, receiving uncompressed original data of the image frame; or When the refresh area is larger than the critical value, a compressed image data of the image frame is received.

12. A display driving circuit for controlling a display screen, characterized in that: The display screen has a plurality of pixels, wherein a row of pixels is divided into a plurality of groups of pixels, and the display driving circuit is used to: When scanning the row of pixels, controlling a scanning control circuit to generate a scanning control signal for the row of pixels; outputting a plurality of enabling signals, wherein each enabling signal is used to control one of the plurality of groups of pixels; and When scanning the row of pixels, whether to output a scanning signal to each of the plurality of pixel groups is determined according to the scanning control signal and each of the plurality of enabling signals.

13. The display driving circuit according to claim 12, wherein: The plurality of pixels are scanned sequentially along a first direction, and the row of pixels is arranged along a second direction different from the first direction.

14. The display driving circuit according to claim 12, wherein: The plurality of groups of pixels include a first group of pixels and a second group of pixels, and the display driving circuit is further used for: When scanning the row of pixels in an image frame, outputting the scanning signal to the first group of pixels; and When scanning the row of pixels in the image frame, the output of the scanning signal to the second group of pixels is stopped.

15. The display driving circuit according to claim 14, characterized in that: The first group of pixels is allocated to a high frame rate region, and the second group of pixels is allocated to a low frame rate region, wherein the frame rate of the high frame rate region is greater than the frame rate of the low frame rate region.

16. The display driving circuit according to claim 14, characterized in that: In the image frame, the first group of pixels is refreshed while the second group of pixels is not refreshed.

17. The display driving circuit according to claim 12, wherein: The scanning control circuit is also used to control the scanning control signal and each enabling signal of the plurality of enabling signals to perform a logic operation to determine whether to output the scanning signal to each group of the plurality of pixel groups.

18. The display driving circuit according to claim 12, wherein: The plurality of pixel groups include a first pixel group and a second pixel group. The first pixel group is controlled by a first scanning signal group, and the second pixel group is controlled by a second scanning signal group different from the first scanning signal group.

19. The display driving circuit according to claim 18, characterized in that: Each of the first group of scan signals and the second group of scan signals includes a first scan signal generated by a first scan control signal and a second scan signal generated by a second scan control signal.

20. The display driving circuit according to claim 19, characterized in that: The first scan signal is generated according to a first enable signal among the plurality of enable signals, and the second scan signal is generated according to a second enable signal among the plurality of enable signals that is different from the first enable signal.

21. The display driving circuit according to claim 12, characterized in that: Also includes: A decoder is used for decompressing image data of the plurality of pixels by taking a group size corresponding to one or more groups of the plurality of groups of pixels as a unit.

22. The display driving circuit according to claim 12, characterized in that: An image frame has a refresh area, and the display driving circuit is further used for: When the refresh area is smaller than a critical value, receiving uncompressed original data of the image frame; or When the refresh area is larger than the critical value, a compressed image data of the image frame is received.

23. A scanning control circuit for a display screen, characterized in that: The display screen has a plurality of pixels, and the scanning control circuit includes: at least one shift circuit, wherein each shift circuit is used to generate a plurality of scan control signals, each of the plurality of scan control signals being used for a row of pixels among the plurality of pixels; and a multiplexing circuit, coupled to the at least one shift circuit, for receiving the plurality of scan control signals and the plurality of enable signals to generate and output a plurality of scan signals to the plurality of pixels; A row of pixels among the plurality of pixels is divided into a plurality of groups of pixels, and each of the plurality of scanning signals for the row of pixels corresponds to one of the plurality of groups of pixels.

24. The scanning control circuit according to claim 23, characterized in that: The multiplexing circuit includes a plurality of logic operation circuits, wherein a first logic operation circuit is coupled to the row of pixels.

25. The scanning control circuit according to claim 24, characterized in that: The first logic operation circuit includes a plurality of output terminals, wherein each output terminal is coupled to a group of pixels among the plurality of groups of pixels.

26. The scanning control circuit according to claim 24, characterized in that: The first logic operation circuit receives a first scan control signal among the plurality of scan control signals from the at least one shift circuit and receives the plurality of enable signals to generate a plurality of first scan signals among the plurality of scan signals and output the plurality of first scan signals to the row of pixels.

27. The scanning control circuit according to claim 26, characterized in that: Each of the plurality of first scanning signals is output to a group of pixels in the plurality of groups of pixels.

28. The scanning control circuit according to claim 26, characterized in that: The first logic operation circuit includes a plurality of logic gates, wherein each logic gate performs a logic operation on the first scan control signal and an enable signal among the plurality of enable signals to generate one of the plurality of first scan signals.

29. The scanning control circuit according to claim 28, characterized in that: Each scan signal of the plurality of scan signals is a high active signal, and each logic gate of the plurality of logic gates is an AND gate.

30. The scanning control circuit according to claim 23, characterized in that: Each shift circuit in the at least one shift circuit includes a plurality of shift registers, wherein each shift register is used to output one of the plurality of scan control signals to control a row of pixels in the plurality of pixels.

31. The scanning control circuit according to claim 23, characterized in that: The plurality of pixel groups include a first pixel group and a second pixel group. The first pixel group is controlled by a first scanning signal group, and the second pixel group is controlled by a second scanning signal group different from the first scanning signal group.

32. The scanning control circuit according to claim 31, characterized in that: Each of the first group of scan signals and the second group of scan signals includes a first scan signal corresponding to a first shift circuit of the at least one shift circuit and a second scan signal corresponding to a second shift circuit of the at least one shift circuit.

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