Source driver and control method thereof

Abstract

The invention relates to a source driver and a control method thereof. The source driver includes: a pin to which a first voltage or a second voltage is applied; an output multiplexer configured to select a data voltage of the pixel data and a black gradation voltage; and a controller configured to differently control a voltage level of the black gradation voltage according to a voltage applied to the pin.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0090059, filed on July 11, 2023, and Korean Patent Application No. 10-2024-0050746, filed on April 16, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a source driver and a control method thereof. Background Art

[0004] Known various display devices include electroluminescent displays (ELDs) such as liquid crystal displays (LCDs) and organic light emitting diode displays (OLED displays), field emission displays (FEDs), plasma display panels (PDPs), and electrophoretic displays (EPDs).

[0005] The display device includes a display panel having pixels arranged for displaying an input image and a display panel driving circuit that writes data into the pixels of the display panel. The display panel driving circuit may include a source driver that integrates a data driving circuit for providing data signals to data lines of the display panel.

[0006] The output voltage of the source driver can vary according to the driving characteristics of the display panel (e.g., the semiconductor channel characteristics of the transistor constituting the pixel circuit). For example, the pixel circuit of the OLED display may include a driving transistor that provides current to the OLED. The driving transistor may be implemented as an n-channel transistor or a p-channel transistor. Since the voltage of the same grayscale varies according to the channel type of the driving transistor, the source driver is developed separately according to the transistor type of the display panel. Summary of the invention

[0007] The present disclosure provides a source driver capable of changing an output voltage according to driving characteristics of a display panel and a control method thereof.

[0008] A source driver according to one embodiment of the present disclosure includes: a pin to which a first voltage or a second voltage is applied; an output multiplexer configured to select a data voltage and a black grayscale voltage of pixel data; and a controller configured to differently control a voltage level of the black grayscale voltage according to the voltage applied to the pin.

[0009] When the voltage on the pin is the first voltage, the black gray voltage may be higher than the white gray voltage. When the voltage on the pin is the second voltage, the black gray voltage may be lower than the white gray voltage.

[0010] The source driver may further include: a digital-to-analog converter configured to convert an input digital signal into a gray voltage; a gamma voltage generator configured to provide the gray voltage to the digital-to-analog converter; and an output buffer connected to an output terminal of the digital-to-analog converter.

[0011] The output multiplexer may select one of an output voltage of the output buffer, a high potential voltage, and a low potential voltage lower than the high potential voltage under the control of the controller, and output the selected voltage.

[0012] During a normal driving period in which pixel data of an input image is received, the output multiplexer may select an output voltage of the output buffer and output the output voltage to an output terminal of the source driver.

[0013] In at least one of the power-on period, the power-off period, the abnormal driving period, and the low-power driving period, when the voltage on the pin is the first voltage, the output multiplexer may select the high potential voltage and output the high potential voltage to the output terminal of the source driver. In at least one of the power-on period, the power-off period, the abnormal driving period, and the low-power driving period, when the voltage on the pin is the second voltage, the output multiplexer may select the low potential voltage and output the low potential voltage to the output terminal of the source driver.

[0014] The gamma voltage generator may include: a first buffer configured to output a lowest reference voltage; and a second buffer configured to output a highest reference voltage. During the power-on period, when the voltage on the pin is the first voltage, the second buffer may be turned on and the first buffer may be in an off state. During the power-on period, when the voltage on the pin is the second voltage, the first buffer may be turned on and the second buffer may be in an off state.

[0015] The pin may be connected to any one of: a power line provided on a printed circuit board, a power line provided on a film on which the source driver is mounted, and a power line provided on a display panel electrically connected to the source driver.

[0016] A method of controlling a source driver according to one embodiment of the present disclosure includes: selecting one of a first black gray voltage and a second black gray voltage having different voltage levels according to a voltage level on a pin; and outputting the selected black gray voltage.

[0017] When the voltage on the pin is a first voltage, the selected black gray voltage may be higher than the white gray voltage. When the voltage on the pin is a second voltage, the selected black gray voltage may be lower than the white gray voltage.

[0018] The method may further include: during a normal operation period of receiving pixel data of an input image, outputting a data voltage of the pixel data regardless of a voltage level on the pin; and outputting a selected black grayscale voltage in at least one of a power-on period, a power-off period, an abnormal drive period, and a low-power drive period.

[0019] According to an embodiment of the present disclosure, the source driver can select a grayscale voltage suitable for the driving characteristics of the display panel according to the voltage level or logic value on the pin. Therefore, the source driver of the present disclosure is compatible with display panels with different driving characteristics.

[0020] According to an embodiment of the present disclosure, a source driver can prevent an abnormal image from being visible on a display panel during a power-on / power-off period, an abnormal driving period, and a low-power driving period.

[0021] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0023] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0024] Figure 2A and Figure 2B is a circuit diagram showing an example of a pixel circuit formed in a display panel;

[0025] Figure 3 is a block diagram showing a source driver according to one embodiment of the present disclosure;

[0026] Figure 4 is a diagram schematically showing pins of a source driver;

[0027] Figure 5is a diagram showing power supply lines and pads of a COF according to one embodiment of the present disclosure;

[0028] Figure 6 is a diagram showing a power supply line of a display panel connected to a source driver according to one embodiment of the present disclosure;

[0029] Figure 7 is a flow chart showing a method of controlling a source driver according to one embodiment of the present disclosure;

[0030] Figure 8 and Fig. 9 is a circuit diagram illustrating in detail a gamma voltage generator and an output multiplexer according to one embodiment of the present disclosure;

[0031] Fig.10 is a diagram illustrating the operation of an output multiplexer;

[0032] Fig.11A and Fig. 11B is a diagram illustrating a method of controlling a buffer in a gamma voltage generator according to one embodiment of the present disclosure;

[0033] Fig.12 It shows that the generated Fig.11A and Fig. 11B An example waveform diagram of a method for enabling a buffer signal is shown;

[0034] Fig.13 and Fig.14 2 is a graph showing a constant voltage input to a source driver and an output voltage of the source driver during a power-on period, a normal driving period, and a power-off period. DETAILED DESCRIPTION

[0035] According to the embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for realizing the same will be more clearly understood. However, the present disclosure is not limited to the following embodiments, but can be implemented in various forms. On the contrary, the present embodiment will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0036] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, the same reference numerals generally represent the same elements. In addition, when describing the present disclosure, a detailed description of known related technologies may be omitted to avoid unnecessarily making the subject matter of the present disclosure difficult to understand.

[0037] Terms such as "includes," "comprising," "having," and "containing" used herein are generally intended to allow the addition of other components unless these terms are used with the term "only." Any reference to the singular may include the plural unless explicitly stated otherwise.

[0038] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0039] When describing the position or interconnection relationship between two components, such as "on top of", "above", "below", "next", "connected or coupled to", "crossing", "intersecting", etc., unless "immediately" or "directly" is used, one or more other components may be inserted between them.

[0040] When describing a temporal precedence relationship, such as “after,” “after,” “next,” “before,” etc., unless “immediately” or “directly” is used, it may not be continuous in time.

[0041] The terms “first”, “second”, etc. may be used to distinguish elements from one another, but the function or structure of a component is not limited by an ordinal number preceding the component or the name of the component.

[0042] The following embodiments may be partially or completely combined or combined with each other, and may be connected and operated in various technical ways. The embodiments may be performed independently or in association with each other.

[0043] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is the electrode from which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a current direction that flows from the drain to the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. Note that the source and drain of a transistor are not fixed. In the following description, the source and drain of a transistor are referred to as the first electrode and the second electrode.

[0044] The transistor may be implemented as an oxide TFT (Thin Film Transistor) including an oxide semiconductor, an LTPS (Low Temperature Polysilicon) TFT including polysilicon, or the like.

[0045] In the following, the first type of panel and the second type of panel refer to display panels having different grayscale voltages due to differences in the driving characteristics of the display panels. For example, in an electroluminescent display device, the first type of panel may be a display panel in which a driving transistor for driving a light-emitting element (such as an OLED) is implemented as a p-channel transistor. In another example, in a display panel of a liquid crystal display device, the first type of panel may be a liquid crystal display panel in a normally white mode. In a source driver for driving a data line of the first type of panel, the black grayscale voltage may be a voltage higher than the white grayscale voltage.

[0046] Among the display panels of the electroluminescent display device, the second type of panel may be a display panel in which a driving transistor for driving the light-emitting element is implemented as a p-channel transistor. In another example, among the display panels of the liquid crystal display device, the second type of panel may be a liquid crystal display panel in a normally black mode. In a source driver for driving a data line of the second type of panel, the black grayscale voltage may be a voltage lower than the white grayscale voltage.

[0047] The source driver of the present disclosure includes a pin indicating the driving characteristics of the display panel 100. The pin may be a single pin. The pin may be exposed outside the IC chip of the source driver. The voltage level applied to the pin may determine the logic value indicating the driving characteristics of the display panel 100. The source driver may compatibly drive the data lines of the display panels with different driving characteristics by selecting the grayscale voltage indicated by the logic value on the pin, and may also avoid abnormal images visible on the display panel during the power-on / power-off period, the abnormal driving period, and the low-power driving period.

[0048] The abnormal driving period may include a period in which static electricity, overcurrent, overvoltage, etc. are detected. A low-power driving period may be initiated to reduce power consumption in a period in which at least one of the host system 200, the timing controller 130, and the data driver 110 does not output a signal, for example, in a period in which a still image continues for a predetermined time, in a standby mode, or in a vertical blanking period in which there is no pixel data between an Nth (N is a natural number) frame and an N+1th frame, thereby reducing power consumption of the display device.

[0049] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 is a block diagram illustrating a display device according to one embodiment of the present disclosure.

[0051] refer to Figure 1 , a display device according to an embodiment of the present disclosure includes a display panel 100 and a display panel driving circuit for writing source data into pixels of the display panel 100 .

[0052] The substrate of the display panel 100 may be, but is not limited to, a plastic substrate, a thin glass substrate or a metal substrate. The display panel 100 may be, but is not limited to, a panel having a rectangular structure with a length in a first direction X, a width in a second direction Y, and a thickness in a third direction Z.

[0053] In the case of a liquid crystal display device, a backlight unit (BLU) may be disposed under the display panel 100. In the case of a self-luminous display device such as an electroluminescent display device, a separate light source such as a backlight unit is not required.

[0054] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes a plurality of data lines 102 , a plurality of gate lines 103 crossing the data lines 102 , and pixels 101 connected to the data lines 102 and the gate lines 103 .

[0055] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel and a blue sub-pixel for realizing color. Each pixel can also include a white sub-pixel. In a liquid crystal display device, a pixel includes a liquid crystal cell. In an electroluminescent display device, a pixel can include a light-emitting element such as an OLED. Each sub-pixel includes a pixel circuit for driving a liquid crystal cell or a light-emitting element.

[0056] The display panel driving circuit writes pixel data (or source data) of an input image into pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120 that convert pixel data into data voltages.

[0057] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted in FIG. The data driver 110 and the touch sensor driver may be integrated together into a source driver integrated circuit (IC). Hereinafter, the source driver may be explained as a source driver IC.

[0058] The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may convert the input digital signal into a gray voltage (or a gamma compensation voltage) using a digital-to-analog converter (hereinafter referred to as a DAC) and output the data voltage. The data voltage of the pixel data may be output as a gray voltage corresponding to the gray value of the pixel data. For 8-bit pixel data, the pixel data "0000" may be a black gray or gray 0 (zero), and the pixel data "1111 1111" may be a white gray or gray 255.

[0059] For the first type of panel, the voltage level of the black grayscale may be the maximum voltage within the output voltage range of the data driver 110 or a high potential voltage close to the maximum voltage, and the voltage level of the white grayscale may be the minimum voltage within the output voltage range of the data driver 110 or a low potential voltage close to the minimum voltage. For the second type of panel, the voltage level of the black grayscale may be the minimum voltage within the output voltage range of the data driver 110 or a low potential voltage close to the minimum voltage, and the voltage level of the white grayscale may be the maximum voltage within the output voltage range of the data driver 110 or a high potential voltage close to the maximum voltage.

[0060] The data driver 110 may output a grayscale voltage suitable for the driving characteristics of the display panel 100 in response to the logic value on the pin described below. For example, when driving the data line of the first type of panel, the data driver 110 may output a high potential voltage as a black grayscale voltage in response to the first logic value on the pin. On the other hand, the data driver 110 may output a low potential voltage as a black grayscale voltage in response to the second logic value on the pin. Among them, the first logic value may be, but not limited to, Low or 0 (zero), and the second logic value may be High or 1. Hereinafter, in the first type of panel, the high potential voltage set as the black grayscale voltage may be, for example, but not limited to, VDD. In the second type of panel, the low potential voltage set as the black grayscale voltage may be, for example, but not limited to, VSS.

[0061] The circuit of the data driver 110 may be integrated into the source driver. Figure 3 As shown, the source driver may include a data driver 110 .

[0062] The circuit of the gate driver 120 may be disposed in the non-display area NA outside the display area AA of the display panel 100, or at least a portion of the gate driver 120 may be disposed in the display area AA. The gate driver 120 may be integrated into a separate gate driver IC and electrically connected to the gate lines 103 of the display panel 100.

[0063] The gate driver 120 sequentially outputs gate pulses (or scan pulses) to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate pulses to the gate lines 103 by shifting the gate pulses using a shift register.

[0064] The display device may further include a power supply which is omitted in the drawings. The power supply receives an input voltage applied from the host system 200 and outputs a constant voltage required to drive the pixels 101 of the display panel 100 and the display panel driving circuit. The constant voltage output from the power supply may include a high potential voltage VDD, an IC power supply voltage VCC, a low potential voltage VSS, a first input voltage VREFL, a second input voltage VREFH, an intermediate reference voltage VGC, etc.

[0065] The timing controller 130 receives pixel data of an input image and a timing signal synchronized with the pixel data from an external host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a master clock. The vertical period and the horizontal period may be identified by counting the data enable signal DE, so the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The vertical synchronization signal Vsync has a cycle of a frame period. The horizontal synchronization signal Hsync and the data enable signal DE have a cycle of a horizontal period (1H). The timing controller 130 may control the operation timing of the display panel drive circuits 110 and 120 based on the timing signals Vsync, HSync, and DE received from the host system 200. The timing controller 130 may control the source driver in the power-on period by transmitting a power-on reset signal to the source driver, and may control the source driver in the low-power drive period (or low-power mode) by adding a low-power mode enable signal to the data and transmitting it to the source driver.

[0066] The host system 200 may scale an image signal from a video source to match a resolution of the display panel 100 , and may transmit the image signal to the timing controller 130 together with a timing control signal.

[0067] Figure 2A and Figure 2B is a circuit diagram showing an example of a pixel circuit formed in a display panel.

[0068] refer to Figure 2A and Figure 2B The pixel circuit includes a light emitting element LD, a driving transistor PT1, NT1, one or more switching transistors PT2, NT2 and a storage capacitor Cst.

[0069] The driving transistors PT1 and NT1 and the light emitting element LD may be connected in series between an EVDD node to which a pixel driving voltage EVDD is applied and an EVSS node to which a pixel reference voltage EVSS is applied. The driving transistors PT1 and NT1 may generate a current for driving the light emitting element LD according to their gate-source voltages.

[0070] The switching transistor PT2, NT2 may be connected between the data line 102 and the gate electrode of the driving transistor PT1, NT1, and may be turned on in response to the gate pulse Vg input through the gate line 103. When the switching transistor PT2, NT2 is turned on, the output voltage Yn from the data driver 110 may be applied to the gate electrode of the driving transistor PT1, NT1.

[0071] Although not shown in the figure, a switch transistor may also be connected between the EVDD node and the drive transistor PT1, NT1, and another switch transistor may be connected between the drive transistor PT1, NT1 and the EVSS node. These switch transistors may be turned on in response to another gate signal (e.g., a light emission signal). A compensation circuit for sensing and compensating the threshold voltage of the drive transistor PT1, NT1 may be connected to the drive transistor PT1, NT1.

[0072] constitute Figure 2A The transistors PT1 and PT2 of the pixel circuit shown may be p-channel LTPS (low temperature polysilicon) TFTs (thin film transistors). Figure 2B The transistors NT1, NT2 of the pixel circuit shown may be n-channel oxide TFTs.

[0073] The sub-pixels arranged in the first type of panel may be implemented as follows Figure 2A The sub-pixels arranged in the second type of panel can be implemented as follows Figure 2B The pixel circuit shown.

[0074] Figure 3 is a block diagram illustrating a source driver according to one embodiment of the present disclosure.

[0075] refer to Figure 3 The data driver 110 of the source driver SIC may include a receiver 112 , a logic controller 300 , a shift register 113 , a first latch array 114 , a second latch array 115 , a gamma voltage generator 320 , a DAC 116 , an output buffer 117 , and an output multiplexer OMUX 310 .

[0076] In order to drive the source driver SIC, constant voltages VDD, VCC and VSS are applied to the source driver SIC. The high potential voltage VDD may be a voltage higher than the low potential voltage VSS, and the IC power supply voltage VCC may be a voltage lower than the high potential voltage VDD and higher than the low potential voltage VSS. For example, VDD=9V, VCC=1.8V. VSS may be, but is not limited to, 0V.

[0077] The timing controller 130 may convert the clock and data into low voltage differential signals and transmit the differential signals to the data driver 110 through a high-speed serial interface. The receiver 112 receives the data DATA transmitted in series from the timing controller 130. The receiver 112 recovers the clock from the data DATA, samples the control data and the pixel data of the input image from the data DATA using the recovered clock, and provides them to the logic controller 300.

[0078] The logic controller 300 may transfer the pixel data of the input image provided by the receiver 112 to the shift register 113, and may control the output timing of the first latch array 114 and the second latch array 115 using the recovered clock and control data. The shift register 113, the first latch array 114, and the second latch array 115 convert the serial mode data into the parallel mode data. The shift register 113 sequentially outputs the pixel data of the input image to the latches of the first latch array 114. The first latch array 114 sequentially samples the pixel data of the input image input through the shift register 113 in response to the clock input from the logic controller 300, and when all latches are latched, the latched pixel data is simultaneously output to the latches of the second latch array 115. The second latch array 115 latches the pixel data simultaneously received from the latches of the first latch array 114, and simultaneously outputs the latched pixel data to the DAC 116 in response to the output enable signal from the logic controller 300.

[0079] The logic controller 300 may include a voltage detection circuit for detecting the high potential voltage VDD, an overcurrent protection circuit, and the like.

[0080] The logic controller 300 can control at least one of the output multiplexer 310 and the gamma voltage generator 320 according to the logic value on the pin PN to ensure that a black grayscale voltage suitable for the driving characteristics of the display panel 100 can be output during at least one of the power-on period, the power-off period, the abnormal driving period, and the low-power driving period (or low-power mode). To this end, as shown in FIG. Figure 8 As shown, the logic controller 300 further includes a first controller 302 and a second controller 304 .

[0081] The gamma voltage generator 320 provides gamma reference voltages with different voltage levels to the DAC 116. The gamma voltage generator 320 may be implemented as a programmable gamma voltage generating circuit, which may adjust the voltage level of each gamma reference voltage according to a register setting value. The gamma voltage generator 320 may control the output time of the highest gamma reference voltage and the lowest gamma reference voltage to be different from each other according to the logic value on the pin PN in at least one of a power-on period, a power-off period, an abnormal driving period, and a low-power driving period (or a low-power mode). By utilizing a voltage divider circuit of a plurality of resistors connected in series, the gamma reference voltage output from the gamma voltage generator 320 may be divided into gray voltages for corresponding grayscales and may be provided to the DAC 116. The DAC 116 selects a grayscale voltage corresponding to the grayscale of the pixel data input from the second latch array 115 from the grayscale voltage input from the gamma voltage generator 320, and outputs the selected grayscale voltage as the data voltage of the pixel data. The data voltage may be output through the output buffer 117 and provided to the data line 102 of the display panel 100. A high potential voltage VDD may be applied to a VDD node of the output buffer 117, and a low potential voltage VSS or a ground voltage may be applied to the VSS node.

[0082] During the normal driving period when the pixel data of the input image is input to the receiver of the source driver SIC, the output multiplexer 310 can output the data voltage of the pixel data output by the output buffer 117 regardless of the logic value on the pin PN. Under the control of the logic controller 300, the output multiplexer 310 can output a separate high potential voltage VDD or a separate low potential voltage VSS as a black grayscale voltage separated from the data voltage channel according to the logic value on the pin PN. For example, in any one of the power-on period, the power-off period, the abnormal driving period, and the low power driving period (or low power mode), the output multiplexer 310 can output the high potential voltage VDD when the logic value on the pin PN is Low, and output the low potential voltage VSS when the logic value on the pin PN is High. Therefore, the output multiplexer 310 can select and output any one of the data voltage, the high potential voltage VDD, and the low potential voltage VSS from the output buffer 117 as the output voltage Yn.

[0083] Figure 4 FIG. 1 is a diagram schematically showing a pin PN of a source driver SIC.

[0084] The display device may include a circuit board (PCB) and a chip on film (COF) electrically connected to the display panel 100. A source driver SIC in which a circuit of the data driver 110 is integrated may be mounted on a flexible film of the COF. The source driver SIC may be directly mounted on a substrate of the display panel 100 in a chip on glass (COG) process or a chip on plastic (COP) process.

[0085] The source driver SIC may include a pin PN indicating driving characteristics of the display panel 100. The pin PN may be a single lead protruding outward from any one of four sides of the IC chip package of the source driver SIC, or a single pad or a single bump exposed on the bottom surface of the IC chip package.

[0086] The pin PN of the source driver SIC may be exposed outside the IC chip of the source driver SIC for connecting any one of a power line formed on the circuit board PCB and the flexible film of the COF and a power line formed on the display panel 100. The black grayscale voltage output from the source driver SIC may vary according to the voltage applied to the pin PN (i.e., the logic value on the pin PN). Figure 4 As shown, when a first voltage (e.g., a low potential voltage VSS) is applied to the pin PN of the source driver SIC, the logic value on the pin PN may be Low. When a second voltage (e.g., an IC power supply voltage VCC) is applied to the pin PN of the source driver SIC, the logic value on the pin PN may be High, but is not limited thereto. The IC power supply voltage VCC and the low potential voltage VSS may be connected to the pin PN through a resistor.

[0087] Figure 5 is a diagram showing power supply lines of a COF according to one embodiment of the present disclosure.

[0088] refer to Figure 5 , the COF on which the source driver SIC is mounted includes power lines 61, 62 and 63. The first power line 61 is connected to one or more VDD pads 65. The second power line 62 is connected to the VCC pad 66. The third power line 63 is connected to the VSS pad 67. The COF includes a plurality of input pads for receiving input data, and a plurality of output pads 64 for outputting output voltages Yn. Figure 5 The input pad is omitted. The COF further includes a pin pad 68. The pin pad 68 may be connected to the second power line 62 or the third power line 63. The logic value on the pin PN may be determined by the voltage level applied to the pin pad 68.

[0089] Figure 6 is a diagram illustrating power supply lines of a display panel connected to a source driver according to one embodiment of the present disclosure.

[0090] refer to Figure 6 , the source driver SIC can be directly mounted on the substrate of the display panel 100 in a chip on glass (COG) process or a chip on plastic (COP) process. The source driver SIC includes a plurality of pads 74, 75, 76 and 77 electrically connected to power lines 71, 72 and 73 provided on the substrate of the display panel 100. The first power line 71 is connected to one or more VDD pads 75 formed on the bottom surface of the source driver SIC. The second power line 72 is connected to a VCC pad 76 formed on the bottom surface of the source driver SIC. The third power line 73 is connected to a VSS pad 77 formed on the bottom surface of the source driver SIC. The output pad 74 of the source driver SIC can be electrically connected to the data line of the display panel 100. Figure 6 , the input pad is omitted. The source driver SIC also includes a pin pad 78. The pin PN can be connected to the second power line 72 or the third power line 73 to determine its logic value. The pin pad 78 can be connected to the second power line 72 or the third power line 73. The logic value of the pin PN can be determined by the voltage level applied to the pin pad 78.

[0091] Figure 7 2 is a flow chart showing a method of controlling a source driver according to an embodiment of the present disclosure. The control method may be controlled by a logic controller 300 electrically connected to a pin PN.

[0092] refer to Figure 7 , the source driver SIC may determine whether each of the IC power supply voltage VCC and the high potential voltage VDD is at a voltage level of a normal power supply voltage during a power-on period when the power supply voltages VCC and VDD are initially input (S01 and S02). The source driver SIC may determine a period from a time when the high potential voltage VDD rises to a value higher than the reference value to a time when a predetermined amount of time is delayed as the power-on period by comparing the voltage level of the high potential voltage VDD with a reference value, or may determine the power-on state by reading a data code indicating the power-on period from data received from the self-timing controller 130.

[0093] Since data received by the source driver SIC during the power-on period is useless data, the source driver SIC ignores the data received during the power-on period without sampling it.

[0094] During the power-on period, the source driver SIC outputs a black gray voltage indicated by a logic value on the pin PN to prevent an abnormal image from being visible on the display panel 100 (S03). For example, as described above, the source driver SIC may output a black gray voltage as a high potential voltage VDD indicated by a first logic value on the pin PN. On the other hand, the source driver SIC may output a black gray voltage as a low potential voltage VSS indicated by a second logic value on the pin PN.

[0095] After the power-on period, when the power supply voltages VCC and VDD stabilize to the voltage level of the normal power supply, the normal driving period begins. The data received by the source driver SIC during the normal driving period includes valid pixel data to be written to the pixels of the display panel 100 and visually reproduced. The source driver SIC converts the pixel data of the received input video into a grayscale voltage and outputs a data voltage during the normal driving period (S04).

[0096] When at least one of static electricity, overcurrent, and overvoltage is detected by real-time detection of the power supply voltage (e.g., the high potential voltage VDD), or when the IC power supply voltage VCC is discharged earlier than the high potential voltage VDD in the power-off period, the source driver SIC may be driven in an abnormal driving period. The source driver SIC may output a black grayscale voltage indicated by a logic value on the pin PN during the abnormal driving period to prevent an abnormal image from being visible on the display panel 100 (S05 and S06).

[0097] The source driver SIC may output a black gray voltage indicated by a logic value on the pin PN during a power-off period in which the power supply voltages VCC and VDD are turned off to prevent an abnormal image from being visible on the display panel 100. The source driver SIC may compare the voltage level of the high potential voltage VDD with a reference value, and determine a period from the time when the voltage level of the high potential voltage VDD becomes lower than the reference value to the time when a predetermined amount of time is delayed as a power-off period. When the power-off period occurs, the source driver SIC may output a black gray voltage indicated by a logic value on the pin PN, and then stop its driving. During the power-off period, the IC power supply voltage VCC applied to the source driver SIC may be delayed and then discharged.

[0098] Figure 8 and Fig. 9 is a circuit diagram illustrating in detail a gamma voltage generator and an output multiplexer according to one embodiment of the present disclosure. Fig.10 is a diagram illustrating the operation of the output multiplexer.

[0099] refer to Figure 8 and Fig. 9, the logic controller 300 may include a first controller 302 for controlling the output multiplexer 310 based on the logic value on the pin PN, and a second controller 304 for controlling the gamma voltage generator 320 based on the logic value on the pin PN.

[0100] The output multiplexer 310 includes a first switch element 311 connected between the output buffer 117 and the output terminal of the source driver SIC, and a multiplexer 312 for selecting a high potential voltage VDD and a low potential voltage VSS. The multiplexer 312 may include a second switch element connected between the VDD node and the output terminal of the source driver SIC, and a third switch element connected between the VSS node and the output terminal of the source driver SIC. The high potential voltage VDD is applied to the VDD node, and the low potential voltage VSS is applied to the VSS node. Each switch element in the output multiplexer 310 may be implemented as a transistor.

[0101] The high potential voltage VDD applied to the VDD node can be interpreted as the first black gray voltage, and the low potential voltage VSS applied to the VSS node can be interpreted as the second black gray voltage. For example, the source driver can select one of the first black gray voltage and the second black gray voltage with different voltage levels according to the voltage level on the pin PN, and output the selected black gray voltage.

[0102] The output buffer 117 outputs the data voltage Vdata of the pixel data output from the DAC 116 to the first switch element 311. The first switch element 311 is turned on in response to the first switch enable signal CHMUX from the first controller 302 and outputs the data voltage Vdata to the output terminal. The second switch element in the multiplexer 312 is turned on in response to the second switch enable signal VDDEN to output the high potential voltage VDD to the output terminal, and the third switch element is turned on in response to the third switch enable signal VSSEN to output the low potential voltage VSS to the output terminal. Each switch element can be turned off in response to the first logic value (OFF) of the switch enable signal CHMUX, VDDEN, VSSEN, and turned on in response to the second logic value (ON) of the switch enable signal CHMUX, VDDEN, VSSEN.

[0103] During the normal driving period, regardless of the logic value (L or H) on the pin PN, the first controller 302 generates the first switch enable signal CHMUX of the second logic value (ON), and simultaneously generates the second switch enable signal VDDEN and the third switch enable signal VSSEN of the first logic value (OFF), so that the data voltage Vdata of the pixel data is output from the source driver SIC during the normal driving period. Fig.10As shown, during at least one of a power-on period, a power-off period, a low-power driving period (or a low-power mode), and an abnormal driving period, the first controller 302 generates one of a second switch enable signal VDDEN and a third switch enable signal VSSEN of a second logic value (ON) according to the logic value on the pin PN, and simultaneously generates a first switch enable signal CHMUX of a first logic value (OFF), so that a black grayscale voltage is output from the source driver SIC.

[0104] For example, during at least one of a power-on period, a power-off period, a low-power driving period (or a low-power mode), and an abnormal driving period, in response to a first logic value (L) on the pin PN, the first controller 302 outputs a second switch enable signal VDDEN of a second logic value (ON) and outputs a first switch enable signal CHMUX and a third switch enable signal VSSEN of a first logic value (OFF). During at least one of a power-on period, a power-off period, a low-power driving period (or a low-power mode), and an abnormal driving period, in response to a second logic value (H) on the pin PN, the first controller 302 outputs a third switch enable signal VSSEN of a second logic value (ON) and outputs a first switch enable signal CHMUX and a second switch enable signal VDDEN of a first logic value (OFF). Therefore, when driving the data line of the first type of panel, during at least one of a power-on period, a power-off period, a low-power driving period (or a low-power mode), and an abnormal driving period, the source driver SIC outputs a high potential voltage VDD as a black grayscale voltage regardless of the pixel data of the input image. When driving the data lines of the second type of panel, the source driver SIC outputs a low potential voltage VSS as a black grayscale voltage regardless of the pixel data of the input image during at least one of a power-on period, a power-off period, a low power driving period (or a low power mode) and an abnormal driving period.

[0105] The gamma voltage generator 320 may include a first circuit portion 322 and a second circuit portion 324. Figure 8 and Fig. 9 As shown. The first circuit portion 322 outputs the highest reference voltage VGH and the lowest reference voltage VGL. The first circuit portion 322 can be interpreted as a master gamma circuit. The second circuit portion 324 outputs gamma reference voltages with different voltage levels within a voltage range higher than the first input voltage VREFL and lower than the second input voltage VREFH. The second circuit portion 324 can be interpreted as a slave gamma circuit.

[0106] The highest reference voltage VGH has the highest voltage level among the gray voltages input to the DAC 116 of the source driver SIC. When the source driver is connected to the first type of panel, the highest reference voltage VGH is a black gray voltage, and when the source driver is connected to the second type of panel, the highest reference voltage VGH is a white gray voltage. On the other hand, when the source driver is connected to the first type of panel, the lowest reference voltage VGL is a white gray voltage, and when the source driver is connected to the second type of panel, the lowest reference voltage VGL is a black gray voltage.

[0107] The first circuit portion 322 includes a first voltage divider RS1, a first voltage selector MUX01, a second voltage selector MUX02, and first to fourth buffers B01 to B04. Buffers B01 to B04 may be voltage followers. When the first buffer enable signal ENB1 is input, each of the first buffer B01 and the third buffer B03 may be driven, thereby passing the input voltage to the output stage. When the second buffer enable signal ENB2 is input, each of the second buffer B02 and the fourth buffer B04 may be driven, thereby passing the input voltage to the output stage. Voltage selectors MUX01 and MUX02 may be implemented as multiplexers that select and output one of a plurality of inputs indicated by a register setting value.

[0108] The first buffer B01 applies the first input voltage VREFL to one end of the first voltage divider RS1. The second buffer B02 applies the second input voltage VREFH to the other end of the first voltage divider RS1.

[0109] The first voltage divider RS1 may include resistors connected in series. The first voltage divider RS1 outputs voltages with different voltage levels within a voltage range higher than the first input voltage VREFL and lower than the second input voltage VREFH through a voltage dividing node between the resistors. The first voltage selector MUX01 selects a voltage indicated by a first register setting value from the first input voltage VREFL and a plurality of lower voltages, and outputs the selected voltage to the third buffer B03. The third buffer B03 provides the voltage input from the first voltage selector MUX01 as the lowest reference voltage VGL to the second circuit portion 324. The second voltage selector MUX02 selects a voltage indicated by a second register setting value from the second input voltage VREFH and a plurality of higher voltages, and outputs the selected voltage to the fourth buffer B04. The fourth buffer B04 provides the voltage input from the second voltage selector MUX02 as the highest reference voltage VGH to the second circuit portion 324. The voltage levels of the highest reference voltage VGL and the lowest reference voltage VGH output from the first circuit portion 322 can be adjusted according to the first register setting value and the second register setting value, respectively.

[0110] During the normal driving period, the second controller 304 simultaneously outputs the first buffer enable signal ENB1 and the second buffer enable signal ENB2 of the second logic value (ON) to ensure that the buffers B01 to B02 of the first circuit portion 322 are driven simultaneously. In contrast, during at least one of the power-on period, the power-off period, the low-power driving period (or low-power mode), and the abnormal driving period, the second controller 304 may differently control the output timing of the first buffer enable signal ENB1 and the second buffer enable signal ENB2 to ensure that there is a difference between the driving timing of the buffer outputting the black gray voltage and the driving timing of the buffer outputting the white gray voltage. For example, the second controller 304 may control the output timing of the first buffer enable signal ENB1 and the second buffer enable signal ENB2 to ensure that there is a difference between the driving timing of the buffer outputting the black gray voltage and the driving timing of the buffer outputting the white gray voltage. Fig.11A and Fig. 11B The first buffer enable signal ENB1 and the second buffer enable signal ENB2 are output in the manner shown to control the enable time of the black gray voltage and the white gray voltage output from the first circuit portion 322 .

[0111] The second circuit portion 324 may include second and third voltage dividers RS2 and RS3 and fifth to sixteenth buffers B05 to B16. The buffers B05 to B16 may be voltage followers driven when an enable signal is input.

[0112] The fifth buffer B05 applies the lowest reference voltage VGL input from the first circuit part 322 to one end of the second voltage divider RS2. The sixth buffer B06 applies the intermediate reference voltage VGC input from the power supply to the intermediate voltage-dividing node of the second voltage divider RS2. The seventh buffer B07 applies the highest reference voltage VGH input from the first circuit part 322 to the other end of the second voltage divider RS2. The second voltage divider RS2 may include resistors connected in series. The second voltage divider RS2 outputs voltages with different voltage levels within a voltage range higher than the lowest reference voltage VGL and lower than the highest reference voltage VGH through a voltage-dividing node between the resistors.

[0113] The eighth buffer B08 outputs the lowest reference voltage VGL input from the first circuit portion 322 to the DAC 116. The output voltage VGmin of the eighth buffer B08 is a grayscale voltage with a minimum voltage level. The sixteenth buffer B16 outputs the highest reference voltage VGH input from the first circuit portion 322 to the DAC 116. The output voltage VGmax of the sixteenth buffer B16 is a grayscale voltage with a maximum voltage level. The ninth to eleventh buffers B09, B10 and B11 are connected to the low voltage-dividing node of the second voltage divider RS2, and apply lower voltages with different voltage levels within a voltage range higher than the lowest reference voltage VGL and lower than the intermediate reference voltage VGC to the low voltage-dividing node between the low resistors of the third voltage divider RS3. The twelfth buffer B12 applies the intermediate reference voltage VGC to the intermediate voltage-dividing node of the third voltage divider RS3. The thirteenth to fifteenth buffers B13, B14 and B15 are connected to the high voltage dividing nodes of the second voltage divider RS2, and apply higher voltages with different voltage levels within a voltage range higher than the intermediate reference voltage VGC and lower than the highest reference voltage VGH to the voltage dividing nodes between the high resistors of the third voltage divider RS3.

[0114] The third voltage divider RS3 may include resistors connected in series between voltage division nodes, and the output voltages of the buffers B08 to B16 are applied to the voltage division nodes. The third voltage divider RS3 outputs a middle gray voltage VGm having different voltage levels through the voltage division nodes between the resistors. The middle gray voltage VGm output by the third voltage divider RS3 is input to the DAC 116. The DAC 116 selects a gray voltage corresponding to the gray value of the pixel data input as a digital signal from the gray voltages VGmin, VGm, and VGmax input by the gamma voltage generator 320, and outputs the selected voltage to the output buffer 117.

[0115] exist Fig. 9 The output voltage VGmax of the sixteenth buffer B16 is the black gray voltage in the first type panel and the white gray voltage in the second type panel. On the other hand, the output voltage VGmin of the eighth buffer B08 is the white gray voltage in the first type panel and the black gray voltage in the second type panel.

[0116] Fig.11A and Fig. 11B is a diagram illustrating a method of controlling a buffer in a gamma voltage generator according to one embodiment of the present disclosure.

[0117] refer to Fig.11A and Fig. 11B, the second controller 304 may control the enable time of the black gray voltage and the white gray voltage output from the first circuit portion 322 of the gamma voltage generator 320 using the first buffer enable signal ENB1 and the second buffer enable signal ENB2.

[0118] During the power-on period POR and the power-off period PFR, the second controller 304 controls the buffer of the gamma voltage generator 320 to ensure that no abnormal image is visible. For example, the second controller 304 controls the buffer outputting the white gray voltage to be in an off state during the power-on period POR, and turns on the buffer outputting the black gray voltage to prevent the abnormal image from being visible during the POR. During the normal operation period NOR of the data voltage Vdata of the pixel data output from the source driver SIC, the second controller 304 drives the buffer outputting the black gray voltage and the buffer outputting the white gray voltage without a time difference. During the power-off period PFR, the second controller 304 first turns off the buffer outputting the white gray voltage to ensure that the white gray voltage is not output, and then turns off the buffer outputting the black gray voltage to prevent the abnormal image from being visible.

[0119] When the pin PN is at the first logic value (L), Fig.11A As shown, the second controller 304 generates the second buffer enable signal ENB2 of the second logic value ON during the power-on period POR, and then inverts the first buffer enable signal ENB1 from the first logic value OFF to the second logic value ON when entering the normal driving period NDR. Therefore, when the pin PN is at the first logic value (L), the second buffer enable signal ENB2 can be switched to the second logic value ON earlier than the first enable signal ENB1 during the power-on period POR when the display device is powered on.

[0120] When the pin PN is at the first logic value (L), Fig.11A As shown, the second controller 304 may invert the first buffer enable signal ENB1 from the second logic value ON to the first logic value OFF when entering the power-off period PFR, and then may invert the second buffer enable signal ENB2 from the second logic value ON to the first logic value OFF. Therefore, when the pin PN is at the first logic value (L), the first enable signal ENB1 may switch to the first logic value OFF earlier than the second buffer enable signal ENB2 in the power-off period PFR when the display device is powered off.

[0121] When the logic value of the pin PN is the first logic value (L), Fig.11AAs shown, during the power-on period POR and the power-off period PFR, the second buffer B02 and the fourth buffer B04 are driven by the buffer enable signals ENB1 and ENB2, while the first buffer B01 and the third buffer B03 are not driven. In this case, since during the power-on period POR and the power-off period PFR, the highest reference voltage VGH corresponding to the black gray voltage of the first type panel is input to the DAC 116, and the white gray voltage is not input to the DAC 116, the black gray voltage can be output from the DAC 116.

[0122] During the normal driving period NDR, the second controller 304 maintains the buffer enable signals ENB1 and ENB2 at the second logic value ON regardless of the logic value on the single pin PN. Therefore, the black gray voltage and the white gray voltage may be applied to the DAC 116 during the normal driving period NDR.

[0123] When the pin PN is at the second logic value (H), Fig. 11B As shown, the second controller 304 generates the first buffer enable signal ENB1 of the second logic value ON during the power-on period POR, and then inverts the second buffer enable signal ENB2 from the first logic value OFF to the second logic value ON when entering the normal driving period NDR. Therefore, when the pin PN is at the second logic value (H), the first buffer enable signal ENB1 can be switched to the second logic value ON earlier than the second buffer enable signal ENB2.

[0124] When the pin PN is at the second logic value (H), Fig. 11B As shown, the second controller 304 may invert the second buffer enable signal ENB2 from the second logic value ON to the first logic value OFF when entering the power-off period PFR, and then may invert the first buffer enable signal ENB1 from the second logic value ON to the first logic value OFF. Therefore, when the pin PN is at the second logic value (H), the second buffer enable signal ENB2 may be generated as the first logic value OFF earlier than the first buffer enable signal ENB1.

[0125] When the logic value on the pin PN is the second logic value (H), Fig. 11BAs shown, during the power-on period POR and the power-off period PFR, the first buffer B01 and the third buffer B03 are driven by the buffer enable signals ENB1 and ENB2, and the second buffer B02 and the fourth buffer B04 are not driven. In this case, during the power-on period POR and the power-off period PFR, since the lowest reference voltage VGL corresponding to the black gray voltage of the second type panel is input to the DAC 116, and the white gray voltage is not input to the DAC 116, the black gray voltage can be output from the DAC 116.

[0126] Fig.12 It shows that the generated Fig.11A and Fig. 11B A waveform diagram of an example of a method of showing a buffer enable signal.

[0127] refer to Fig.12 , the second controller 304 may generate a first buffer enable signal ENB1 and a second buffer enable signal ENB2 based on the gamma enable signal PGMA_EN for driving the gamma voltage generator 320 .

[0128] The second controller 304 may delay the gamma enable signal PGMA_EN for a predetermined time to generate a delayed enable signal D_EN. As a result of a logical sum (OR) operation and a logical multiplication (AND) operation of the gamma enable signal PGMA_EN and the delayed enable signal D_EN, the second controller 304 generates enable signals ENB_A and ENB_B. ENB_A is Fig.11A The second buffer enable signal ENB2 and Fig. 11B The first buffer enable signal ENB1 is shown. ENB_B is Fig.11A The first buffer enable signal ENB1 and Fig. 11B The second buffer enable signal ENB2 is shown.

[0129] Fig.13 and Fig.14 is a diagram showing a constant voltage input to a source driver and an output voltage of the source driver during a power-on period, a normal driving period, and a power-off period. Fig.13 In FIG. 1 , Yn represents the output voltage of the source driver SIC.

[0130] The source driver SIC may compare the high potential voltage VDD with a predetermined reference value to determine a power-on period POR and a power-off period PFR. For example, the source driver SIC may determine the power-on period POR as a period in which the high potential voltage VDD becomes higher than the reference voltage Vr after driving is started after receiving the IC power supply voltage VCC, the high potential voltage VDD reaches the target voltage, and then a predetermined time passes. The power-off period PFR may be determined as a period in which the high potential voltage VDD decreases from the target voltage, becomes lower than the reference voltage Vr, and then the IC power supply voltage VCC is discharged to the low potential voltage VSS.

[0131] The source driver SIC may determine the power-on state by reading a data code indicating a power-on period from data received from the timing controller 130. The timing controller 130 may be configured as follows. Fig.14 As shown, in each horizontal period, the digital signals are transmitted to the source driver SIC in the following order: clock training signal CTR, data enable signal DE, configuration data packet CONF, pixel data packet PDATA. These data can be transmitted as differential signals. Fig.14 In FIG, HBP represents horizontal blanking data used to separate one horizontal period.

[0132] The clock training signal CTR is an AC signal switching at a constant frequency so that the output phase of the built-in clock generator of the source driver SIC can be locked. Every horizontal period, the data enable signal DE is added to the data to separate the data of one pixel row. The configuration data packet CONF may include control data that defines various functions of the source driver SIC and indicates the driving mode. The configuration data packet CONF may include data indicating the power-on period, data indicating the low-power driving mode, etc. The pixel data packet PDATA includes pixel data of one pixel row in the display panel. The source driver SIC determines the data received before the normal driving period NDR as useless data, and determines the data received during the NDR as valid pixel data written to the pixel. Fig.13 and Fig.14 In the figure, Unknown represents useless data existing before the source driver SIC outputs the black grayscale voltage indicated by the logic value on the pin PN.

[0133] The configuration data packet CONF received by the source driver SIC during the power-on period POR may include data indicating the power-on period. During the power-on period POR, the source driver SIC counts the data indicating the power-on period as the clock CLK1 and may enter the normal driving period NDR at the fourth clock, but is not limited thereto.

[0134] The objects to be achieved by the present disclosure, means for achieving the objects, and the effects of the present disclosure described above do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the contents disclosed in the present disclosure.

[0135] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

Claims

1. A source driver, comprising: a pin to which the first voltage or the second voltage is applied; an output multiplexer configured to select a data voltage and a black grayscale voltage of pixel data; as well as A controller is configured to differently control a voltage level of the black grayscale voltage according to a voltage applied to the pin.

2. The source driver according to claim 1, wherein: When the voltage on the pin is the first voltage, the black grayscale voltage is higher than the white grayscale voltage, When the voltage on the pin is the second voltage, the black gray voltage is lower than the white gray voltage.

3. The source driver according to claim 1, further comprising: a digital-to-analog converter configured to convert an input digital signal into a grayscale voltage; a gamma voltage generator configured to provide the grayscale voltage to the digital-to-analog converter; as well as An output buffer is connected to an output terminal of the digital-to-analog converter.

4. The source driver according to claim 3, wherein: The output multiplexer selects one of an output voltage of the output buffer, a high potential voltage, and a low potential voltage lower than the high potential voltage under the control of the controller, and outputs the selected voltage.

5. The source driver according to claim 4, wherein: The output multiplexer is configured to select an output voltage of the output buffer and output the output voltage to an output terminal of the source driver during a normal driving period in which pixel data of an input image is received.

6. The source driver according to claim 5, wherein: The output multiplexer is configured as: in at least one of a power-on period, a power-off period, an abnormal driving period, and a low-power driving period, when the voltage on the pin is the first voltage, selecting the high potential voltage and outputting the high potential voltage to the output terminal of the source driver, In at least one of a power-on period, a power-off period, an abnormal driving period, and a low-power driving period, when the voltage on the pin is the second voltage, the low potential voltage is selected and output to the output terminal of the source driver.

7. The source driver according to claim 3, wherein: The gamma voltage generator comprises: A first buffer configured to output a minimum reference voltage; and The second buffer is configured to output the highest reference voltage, During a power-on period, when the voltage on the pin is the first voltage, the second buffer is turned on and the first buffer is in an off state, During a power-on period, when the voltage on the pin is the second voltage, the first buffer is turned on and the second buffer is in an off state.

8. The source driver according to claim 1, wherein: The pin is connected to any one of: a power line provided on a printed circuit board, a power line provided on a film on which the source driver is mounted, and a power line provided on a display panel electrically connected to the source driver.

9. A method for controlling a source driver, comprising: selecting one of a first black grayscale voltage and a second black grayscale voltage having different voltage levels according to a voltage level on the pin; as well as Outputs the selected black grayscale voltage.

10. The method according to claim 8, wherein: When the voltage on the pin is the first voltage, the selected black gray voltage is higher than the white gray voltage, When the voltage on the pin is the second voltage, the selected black gray voltage is lower than the white gray voltage.

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