Gate driving circuit, display panel

Abstract

The application provides a gate drive circuit and a display panel. The gate drive circuit comprises a plurality of cascaded gate drive sub-circuits. Each gate drive sub-circuit comprises a first output module and a second output module. The first output module and the second output module are controlled by the same clock signal. A second output end electrically connected with the second output module is electrically connected with a first power supply end through a pull-down maintaining module. The control of the gate control signal output by the same gate drive sub-circuit is realized. The layout space occupied by the gate drive circuit is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit and a display panel. BACKGROUND

[0002] The more the number of transistors included in the gate driving circuit, the larger the layout space occupied by the gate driving circuit. When the gate driving circuit is applied to the display panel, it is more difficult for the display panel to realize narrow frame design. SUMMARY

[0003] The embodiment of the present application provides a gate driving circuit and a display panel, which can reduce the layout space occupied by the gate driving circuit.

[0004] The embodiment of the present application provides a gate driving circuit, which comprises a plurality of cascaded gate driving sub-circuits. The gate driving sub-circuit comprises a node control module, a stage transmission module, a first output module, a second output module and a pull-down maintenance module. The node control module is electrically connected with a first node and a second node of the gate driving sub-circuit, and is configured to control the signals transmitted to the first node and the second node according to a start signal. The stage transmission module is electrically connected with the first node, and is configured to control the first clock signal to be transmitted to the stage transmission output end of the gate driving sub-circuit according to the signal of the first node. The first output module is electrically connected with the stage transmission output end and a first output end of the gate driving sub-circuit, and is configured to receive a second clock signal and a third clock signal to control the signal transmission between one of the stage transmission output end and a first power supply end and the first output end. The second output module is electrically connected with the stage transmission output end and a second output end of the gate driving sub-circuit, and is configured to control the signal transmission between the stage transmission output end and the second output end according to the third clock signal. The pull-down maintenance module is electrically connected with the second node, and is configured to control the signal transmission between the first power supply end and the second output end according to the signal of the second node.

[0005] The embodiment of the present application provides a display panel, which comprises any of the above-mentioned gate driving circuits.

[0006] The application provides a gate drive circuit and a display panel, the gate drive circuit comprises a plurality of cascaded gate drive sub-circuits, each gate drive sub-circuit comprises a first output module and a second output module, and the first output module and the second output module are controlled by the same clock signal, and a second output end electrically connected with the second output module is electrically connected with a first power supply end through a pull-down maintaining module, so as to control the gate control signal output by the same gate drive sub-circuit, and the layout space occupied by the gate drive circuit is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0008] Figures 1A-1B is a structural schematic diagram of the gate drive circuit provided by the embodiment of the present application;

[0009] Figures 2A-2C is a structural schematic diagram of the gate drive sub-circuit provided by the embodiment of the present application;

[0010] Figures 3A-3B is a timing diagram of the gate control signal provided by the embodiment of the present application;

[0011] Figures 4A-4B is a structural schematic diagram of the display panel provided by the embodiment of the present application;

[0012] Figure 5 is a sub-pixel Spi charging time length schematic diagram provided by the embodiment of the present application. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the outline of the device.

[0014] Specifically, as Figures 1A-1Bis a structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. The present application provides a gate drive circuit, which comprises a plurality of cascaded gate drive sub-circuits GA, each of which comprises a stage transmission output end OutS, a first output end Out1 and a second output end Out2, the stage transmission output end OutS is configured to output a stage transmission signal ST, the first output end Out1 is configured to output a first gate control signal Scan1, and the second output end Out2 is configured to output a second gate control signal Scan2.

[0015] The stage transmission signal ST output by the gate drive circuit comprises an N-4th stage transmission signal ST(N-4) output by an N-4th gate drive sub-circuit GA(N-4) to an N+5th gate drive sub-circuit GA(N+5). The first gate control signal Scan1 output by the gate drive circuit comprises an N-4th stage first gate control signal Scan1(N-4) output by the N-4th gate drive sub-circuit GA(N-4) to the N+5th gate drive sub-circuit GA(N+5). The second gate control signal Scan2 output by the gate drive circuit comprises an N-4th stage second gate control signal Scan2(N-4) output by the N-4th gate drive sub-circuit GA(N-4) to the N+5th gate drive sub-circuit GA(N+5). The gate control signal output by the gate drive circuit comprises the first gate control signal Scan1 and the second gate control signal Scan2.

[0016] Figures 2A-2C is a structural schematic diagram of a gate drive sub-circuit provided by an embodiment of the present application. Please continue to refer to Figures 1A-1B and Figures 2A-2B The gate drive sub-circuit GA comprises a node control module 100, a stage transmission module 200, a first output module 300, a second output module 400 and a pull-down maintenance module 500.

[0017] The node control module 100 is electrically connected with a first node QN and a second node KN of the present gate drive sub-circuit GA, and the node control module 100 is configured to control the signals transmitted to the first node QN and the second node KN according to a start signal.

[0018] The stage transmission module 200 is electrically connected with the first node QN, and the stage transmission module 200 is configured to control the transmission of a first clock signal CKa to the stage transmission output end OutS of the present gate drive sub-circuit GA according to the signal of the first node QN.

[0019] The first output module 300 is electrically connected with the stage transmission output terminal OutS and the first output terminal Out1 of the gate driving sub-circuit GA in the same stage, and is configured to receive the second clock signal CKb and the third clock signal CKc to control the signal transmission between one of the stage transmission output terminal OutS and the first power supply terminal VGL and the first output terminal Out1.

[0020] The second output module 400 is electrically connected with the stage transmission output terminal OutS and the second output terminal Out2 of the gate driving sub-circuit GA in the same stage, and is configured to control the signal transmission between the stage transmission output terminal OutS and the second output terminal Out2 according to the third clock signal CKc.

[0021] The pull-down maintaining module 500 is electrically connected with the second node KN, and is configured to control the signal transmission between the first power supply terminal VGL and the second output terminal Out2 according to the signal of the second node KN.

[0022] By making the gate driving sub-circuit GA include the stage transmission module 200, the first output module 300 and the second output module 400, and making the first output module 300 and the second output module 400 both controlled by the third clock signal CKc, the second output terminal Out2 realizes the signal transmission control between the first power supply terminal VGL through the pull-down maintaining module 500, so that the same gate driving sub-circuit GA can output the stage transmission signal ST, the first gate control signal Scan1 and the second gate control signal Scan2 at the same time, and realizes the control of the stage transmission signal ST, the first gate control signal Scan1 and the second gate control signal Scan2 output by the gate driving sub-circuit GA, which can reduce the number of gate driving sub-circuits GA included in the gate driving circuit, and then reduce the layout space occupied by the gate driving circuit.

[0023] Optionally, the first output module 300 is configured to control the signal transmission between the stage transmission output terminal OutS and the first output terminal Out1 according to the second clock signal CKb, and is configured to control the signal transmission between the first power supply terminal VGL and the first output terminal Out1 according to the third clock signal CKc, so that when the signal transmission path between the stage transmission output terminal OutS and the second output terminal Out2 is turned on, the signal transmission path between the stage transmission output terminal OutS and the first output terminal Out1 is disconnected, and the effective level of the first gate control signal Scan1 output by the same gate driving sub-circuit GA and the effective level of the second gate control signal Scan2 do not overlap.

[0024] It should be noted that the non-overlapping of the active level of the first gate control signal Scan1 and the active level of the second gate control signal Scan2 output by the same gate driving sub-circuit GA includes the case that the falling edge (or the rising edge) of the first gate control signal Scan1 overlaps with the rising edge (or the falling edge) of the first gate control signal Scan1. When the transistor controlled by the first gate control signal Scan1 is a P-type transistor, the active level of the first gate control signal Scan1 is a low level; when the transistor controlled by the first gate control signal Scan1 is an N-type transistor, the active level of the first gate control signal Scan1 is a high level. Similarly, the active level of the second gate control signal Scan2 and the stage transfer signal ST can also be determined according to the type of the transistor controlled by the second gate control signal Scan2 and the stage transfer signal ST.

[0025] Optionally, the first output module 300 can also be configured to control the signal transmission between the first power supply end VGL and the first output end Out1 according to the fourth clock signal, so as to make the active level of the first gate control signal Scan1 and the active level of the second gate control signal Scan2 output by the same gate driving sub-circuit GA have overlap by adjusting the timing of the fourth clock signal.

[0026] Please continue to refer to Figures 2A-2B The node control module 100 can include a pull-up control unit 101, the pull-up control unit 101 is electrically connected with the first node QN and the second power supply end VGH, and the pull-up control unit 101 is configured to control the signal transmission between the second power supply end VGH and the first node QN according to the start signal.

[0027] Optionally, the pull-up control unit 101 includes a first switch transistor Ts1, the first switch transistor Ts1 includes a control end configured to receive the start signal, a first source-drain end electrically connected with the second power supply end VGH, and a second source-drain end electrically connected with the first node QN.

[0028] Among the plurality of cascaded gate driving sub-circuits GA, the start signal received by the front Zth gate driving sub-circuit GA can correspond to a start signal, and the start signal received by the Nth gate driving sub-circuit GA(N) cascaded after the Zth gate driving sub-circuit GA(Z) can be a signal generated by the N-Xth gate driving sub-circuit GA(N-X), Z≥1, N>Z, X>1.

[0029] Optionally, the start signal received by the Nth gate driving sub-circuit GA(N) can be the N-Xth stage transfer signal ST(N-X) generated by the N-Xth gate driving sub-circuit GA(N-X), so that the stage transfer control function of the gate driving circuit is no longer controlled by the gate control signal.

[0030] As an example of Z=2 and X=2, in the plurality of cascaded gate drive sub-circuits GA, the starting signal received by the first stage gate drive sub-circuit GA(1) is the first starting signal, the starting signal received by the second stage gate drive sub-circuit GA(2) is the second starting signal, the starting signal received by the third stage gate drive sub-circuit GA(3) can be the stage transmission signal ST(3) generated by the first stage gate drive sub-circuit, and so on, to obtain the corresponding received starting signal of the plurality of cascaded gate drive sub-circuits GA. The starting signal can be generated by a timing controller or the like.

[0031] Please continue to refer to Figures 2A-2B The node control module 100 further includes an inverting unit 102, which is electrically connected with the first node QN, the second node KN, the first power supply end VGL and the second power supply end VGH. The inverting unit 102 is configured to control one of the first power supply end VGL and the second power supply end VGH to be electrically connected with the second node KN according to the signal of the first node QN, so as to control the second node KN to be electrically connected with the first power supply end VGL through the inverting unit 102 when the signal transmission path between the first clock signal CKa and the stage transmission output end OutS is turned on by the stage transmission module 200 according to the signal of the first node QN, thereby controlling the working state of the pull-down maintenance module 500.

[0032] Optionally, the inverting unit 102 includes a second switch transistor Ts2, a third switch transistor Ts3, a fourth switch transistor Ts4 and a fifth switch transistor Ts5.

[0033] The second switch transistor Ts2 includes a control end electrically connected with the second power supply end VGH, a first source-drain end electrically connected with the second power supply end VGH, and a second source-drain end electrically connected with the control end of the third switch transistor Ts3. The third switch transistor Ts3 includes a first source-drain end electrically connected with the second power supply end VGH, and a second source-drain end electrically connected with the second node KN. The fourth switch transistor Ts4 includes a control end electrically connected with the first node QN, a first source-drain end electrically connected with the first power supply end VGL, and a second source-drain end electrically connected with the control end of the third switch transistor Ts3. The fifth switch transistor Ts5 includes a control end electrically connected with the first node QN, a first source-drain end electrically connected with the first power supply end VGL, and a second source-drain end electrically connected with the second node KN.

[0034] Optionally, in order to make the first clock signal CKa no longer be transmitted to the stage transmission output end OutS at the required time, the node control module 100 includes a pull-down control unit 103, as shown in Figures 2A-2BThe pull-down control unit 103 is electrically connected with the first node QN and the first power supply end VGL, and is configured to control signal transmission between the first power supply end VGL and the first node QN according to a pull-down control signal.

[0035] Optionally, the pull-down control unit 103 includes a sixth switch transistor Ts6, which includes a control end configured to receive the pull-down control signal, a first source-drain end electrically connected with the first power supply end VGL, and a second source-drain end electrically connected with the first node QN.

[0036] In the plurality of cascaded gate driving sub-circuits GA, the pull-down control signal corresponding to the Mth gate driving sub-circuit GA(M) is the stage transfer signal ST(M+Y) generated by the M+Yth gate driving sub-circuit GA(M+Y), M≥1, Y>1. For example, when Y=2, the pull-down control signal corresponding to the Mth gate driving sub-circuit GA(M) is the M+2th stage transfer signal ST(M+2) generated by the M+2th gate driving sub-circuit GA(M+2).

[0037] To avoid the second gate control signal Scan2 output by the gate driving sub-circuit GA having no effective level, the starting moment of the effective level of the pull-down control signal applied to the gate driving sub-circuit GA can be later than the ending moment of the effective level of the first clock signal CKa applied to the gate driving sub-circuit GA.

[0038] Optionally, the voltage supplied by the first power supply end VGL can be smaller than the voltage supplied by the second power supply end VGH. Accordingly, the pull-up control unit 101 can control the potential of the first node QN to be pulled up according to the start signal, and the pull-down control unit 103 can control the potential of the first node QN to be pulled down according to the pull-down control signal.

[0039] Please continue to refer to Figures 2A-2B To realize output control of the effective level of the stage transfer signal ST, the stage transfer module 200 can include a stage transfer output transistor Tst and a first capacitor Cbt. The stage transfer output transistor Tst includes a control end electrically connected with the first node QN, a first source-drain end configured to receive the first clock signal CKa, and a second source-drain end electrically connected with a stage transfer output end OutS. The first capacitor Cbt is connected in series between the control end of the stage transfer output transistor Tst and the stage transfer output end OutS.

[0040] Please continue to refer to Figures 2A-2BTo achieve the output control of the effective level of the first gate control signal Scan1, the first output module 300 includes a first output transistor To1 and a second output transistor To2. The first output transistor To1 includes a control end configured to receive the second clock signal CKb, a first source-drain end electrically connected with the stage transmission output end OutS, and a second source-drain end electrically connected with the first output end Out1. The second output transistor To2 includes a control end configured to receive the third clock signal CKc or the fourth clock signal, a first source-drain end electrically connected with the first power supply end VGL, and a second source-drain end electrically connected with the first output end Out1.

[0041] Please continue to refer to Figures 2A-2B To achieve the output control of the effective level of the second gate control signal Scan2, the second output module 400 includes a third output transistor To3, which includes a control end configured to receive the third clock signal CKc, a first source-drain end electrically connected with the stage transmission output end OutS, and a second source-drain end electrically connected with the second output end Out2.

[0042] Please continue to refer to Figures 2A-2C To achieve the on-off control of the signal transmission path between the first power supply end VGL and the second output end Out2, the pull-down maintenance module 500 includes a first transistor T1, which includes a control end electrically connected with the second node KN, a first source-drain end electrically connected with the first power supply end VGL, and a second source-drain end electrically connected with the second output end Out2.

[0043] Since the level state of the third clock signal CKc and the fourth clock signal both have a switch between the effective level and the ineffective level, the on-off control of the signal transmission path between the first power supply end VGL and the first output end Out1 by the second output transistor To2 is periodic. Therefore, in the stage where the first gate control signal Scan1 needs to continuously output the ineffective level, the signal transmission path between the first power supply end VGL and the first output end Out1 is disconnected for part of the period, which reduces the ability of the potential of the second output end Out2 to maintain stability in that period. Therefore, the pull-down maintenance module 500 can also be electrically connected with the first output end Out1, and the pull-down maintenance module 500 is configured to control the signal transmission between the first power supply end VGL and the first output end Out1 according to the signal of the second node KN, so as to achieve the on-off control of the signal transmission path between the first power supply end VGL and the first output end Out1 by the pull-down maintenance module 500, and maintain the stable ineffective level state in the stage where the first gate control signal Scan1 needs to continuously output the ineffective level.

[0044] Correspondingly, the pull-down maintaining module 500 can include a second transistor T2, the second transistor T2 including a control terminal electrically connected with the second node KN, a first source-drain terminal electrically connected with the first power supply end VGL, and a second source-drain terminal electrically connected with the first output end Out1.

[0045] Similarly, the pull-down maintaining module 500 can also be used to control the on-off of the signal transmission channel between the first power supply end VGL and the stage transmission output end OutS, so that the stage transmission signal ST has a stable invalid level state during the period when the stage transmission signal ST continuously outputs the invalid level.

[0046] Correspondingly, the pull-down maintaining module 500 is electrically connected with the stage transmission output end OutS, and the pull-down maintaining module 500 is configured to control the electrical connection between the first power supply end VGL and the stage transmission output end OutS according to the signal of the second node KN.

[0047] Optionally, the pull-down maintaining module 500 includes a third transistor T3, the third transistor T3 including a control terminal electrically connected with the second node KN, a first source-drain terminal electrically connected with the first power supply end VGL, and a second source-drain terminal electrically connected with the stage transmission output end OutS.

[0048] To reduce the probability of false output of the gate driving sub-circuit GA caused by the potential change of the first node QN during the period when the stage transmission signal ST continuously outputs the invalid level, the pull-down maintaining module 500 can also be electrically connected with the first node QN, and the pull-down maintaining module 500 is configured to control the electrical connection between the first power supply end VGL and the first node QN according to the signal of the second node KN, so that the pull-down maintaining module 500 controls the on-off of the signal transmission channel between the first power supply end VGL and the stage transmission output end OutS, and the potential of the first node QN is maintained stable during the period when the stage transmission signal ST continuously outputs the invalid level.

[0049] Optionally, the pull-down maintaining module 500 includes a fourth transistor T4, the fourth transistor T4 including a control terminal electrically connected with the second node KN, a first source-drain terminal electrically connected with the first power supply end VGL, and a second source-drain terminal electrically connected with the first node QN.

[0050] Optionally, the gate driving sub-circuit GA can also include a reset module 600, the reset module 600 being electrically connected with the first power supply end VGL and the first node QN, and the reset module 600 being configured to control the signal transmission between the first power supply end VGL and the first node QN according to a reset control signal, so that the potential of the first node QN is reset by the reset module 600 when the gate driving circuit starts.

[0051] Correspondingly, the reset module 600 comprises a first reset transistor TrQ, the first reset transistor TrQ comprises a control terminal configured to receive a reset control signal, a first source-drain terminal electrically connected with the first power supply terminal VGL, and a second source-drain terminal electrically connected with the first node QN.

[0052] Optionally, the reset module 600 and the stage transmission output terminal OutS are electrically connected, and the reset module 600 is configured to control signal transmission between the first power supply terminal VGL and the stage transmission output terminal OutS according to the reset control signal, so as to reset the potential of the stage transmission output terminal OutS by the reset module 600 when the gate drive circuit starts.

[0053] Correspondingly, the reset module 600 comprises a second reset transistor TrG, the second reset transistor TrG comprises a control terminal configured to receive a reset control signal, a first source-drain terminal electrically connected with the first power supply terminal VGL, and a second source-drain terminal electrically connected with the stage transmission output terminal OutS.

[0054] Please continue to refer to Figure 2C , if the gate drive sub-circuit GA design shown in Figures 2A-2B is adopted, one gate drive sub-circuit GA outputs one gate control signal (such as the Nth gate drive sub-circuit GA(N) outputs the Nth gate control signal Scan(N)), and two gate drive sub-circuits GA need to be set to output two gate control signals, and 22 transistors need to be set for the gate drive sub-circuit GA corresponding to the gate drive sub-circuit GA outputting two gate control signals. If the gate drive sub-circuit GA design shown in Figure 2C is adopted, because one gate drive sub-circuit GA can simultaneously output the stage transmission signal ST and two gate control signals (i.e. the first gate control signal Scan1 and the second gate control signal Scan2). Thus, only 16 transistors need to be set for the gate drive sub-circuit GA corresponding to the gate drive sub-circuit GA outputting two gate control signals. Therefore, compared with the design of the gate drive sub-circuit GA shown in Figures 2A-2B , the design of the gate drive sub-circuit GA shown in Figures 1A-1B can correspondingly reduce the number of transistors included in the gate drive circuit, thereby reducing the layout space occupied by the gate drive circuit.

[0055] Further, the gate driving sub-circuit GA can output the stage transfer signal ST while outputting the gate control signal. The stage transfer control between the cascaded gate driving sub-circuits GA is realized through the stage transfer signal ST. Thus, the working state of the first output terminal Out1 and the second output terminal Out2 of the gate driving sub-circuit GA does not affect the stage transfer control between the multi-stage gate driving sub-circuits GA. When the gate driving circuit is applied to a display panel, and a short circuit occurs between the first output terminal Out1 or the second output terminal Out2 of a part of the gate driving sub-circuits GA and a signal line such as a common wire in the display panel, the cascade control between the multi-stage gate driving sub-circuits GA is realized through the stage transfer, and thus the cascade control between the multi-stage gate driving sub-circuits GA is not affected by the short circuit factor. The gate driving circuit can still provide the required gate control signal to the display panel, so that the part of the display panel where no short circuit problem occurs can still receive the corresponding gate control signal, thereby reducing the impact of the short circuit problem.

[0056] To further reduce the layout space occupied by the gate driving circuit, the clock signals provided by the plurality of clock lines can be shared to provide the required clock signals to the multi-stage gate driving sub-circuits GA. Accordingly, the gate driving circuit includes a plurality of clock lines, the plurality of clock lines are electrically connected with the multi-stage gate driving sub-circuits GA, and the plurality of clock lines are configured to transmit corresponding first clock signals CKa, second clock signals CKb, and third clock signals CKc to the multi-stage gate driving sub-circuits GA.

[0057] Alternatively, the gate driving circuit can include L clock lines to provide the required clock signals to the multi-stage gate driving sub-circuits GA. Wherein, L≥4.

[0058] As please continue to refer to Figures 2A-2B and Figure 1B Taking L=4 as an example, the design of the clock signals provided by the plurality of clock lines shared by the multi-stage gate driving sub-circuits GA is described. The L clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4.

[0059] The first clock line CKL1 is configured to transmit the corresponding first clock signal CKa to the 4K+1th gate driving sub-circuit GA(4K+1), configured to transmit the corresponding second clock signal CKb to the 4K+2th gate driving sub-circuit GA(4K+2), and configured to transmit the corresponding third clock signal CKc to the 4K+4th gate driving sub-circuit GA(4K+4).

[0060] The second clock line CKL2 is configured to transmit the corresponding third clock signal CKc to the 4K+1th gate driving sub-circuit GA(4K+1), configured to transmit the corresponding first clock signal CKa to the 4K+2th gate driving sub-circuit GA(4K+2), and configured to transmit the corresponding second clock signal CKb to the 4K+3th gate driving sub-circuit GA(4K+3).

[0061] The third clock line CKL3 is configured to transmit the corresponding third clock signal CKc to the 4K+2th gate driving sub-circuit GA(4K+2), configured to transmit the corresponding first clock signal CKa to the 4K+3th gate driving sub-circuit GA(4K+3), and configured to transmit the corresponding second clock signal CKb to the 4K+4th gate driving sub-circuit GA(4K+4).

[0062] The fourth clock line CKL4 is configured to transmit the corresponding second clock signal CKb to the 4K+1th gate driving sub-circuit GA(4K+1), configured to transmit the corresponding third clock signal CKc to the 4K+3th gate driving sub-circuit GA(4K+3), and configured to transmit the corresponding first clock signal CKa to the 4K+4th gate driving sub-circuit GA(4K+4). Wherein, K≥0.

[0063] In addition, the multi-stage gate driving sub-circuits GA can also be divided into different groups, and the gate driving sub-circuits GA in different groups are matched with different clock lines to generate the gate control signals.

[0064] As please continue to refer to Figures 2A-2B and Figure 1B , the plurality of clock lines are divided into a first group of clock lines and a second group of clock lines, and the gate driving circuit includes a first cascaded group GM1 and a second cascaded group GM2, the first cascaded group GM1 and the second cascaded group GM2 respectively include a plurality of cascaded gate driving sub-circuits GA. Wherein, the first group of clock lines is configured to transmit the corresponding first clock signal CKa, the second clock signal CKb and the third clock signal CKc to the plurality of gate driving sub-circuits GA in the first cascaded group GM1; the second group of clock lines is configured to transmit the corresponding first clock signal CKa, the second clock signal CKb and the third clock signal CKc to the plurality of gate driving sub-circuits GA in the second cascaded group GM2. In this way, the gate driving sub-circuits GA of the first cascaded group GM1 and the second cascaded group GM2 generate gate control signals according to mutually independent clock signals.

[0065] Optionally, the first cascade group GM1 includes odd-numbered stage gate drive sub-circuits GA, and the second cascade group GM2 includes even-numbered stage gate drive sub-circuits GA, so as to control the phase difference between the gate control signals output by the odd-numbered stage gate drive sub-circuits GA and the even-numbered stage gate drive sub-circuits GA according to the clock signals transmitted by the first group of clock lines and the second group of clock lines.

[0066] Optionally, L1 clock lines in the L clock lines are used as the first group of clock lines, and L2 clock lines in the L clock lines are used as the second group of clock lines, so as to reduce the layout space occupied by the gate drive circuit under the condition that the requirements of the clock signals required by the first cascade group GM1 and the second cascade group GM2 are met. Wherein, L>L1≥4, L>L2≥4.

[0067] As please continue to refer to Figure 1A Taking L1=4 as an example, the design relationship between the first group of clock lines and the first cascade group GM1 is explained. The first group of clock lines includes a first clock line CKL1, a second clock line CKL2, a third clock line CKL3 and a fourth clock line CKL4.

[0068] The first clock line CKL1 is configured to transmit a corresponding first clock signal CKa to the 4K+1 stage gate drive sub-circuit GA(4K+1) in the first cascade group GM1, and is configured to transmit a corresponding second clock signal CKb to the 4K+2 stage gate drive sub-circuit GA(4K+2), and is configured to transmit a corresponding third clock signal CKc to the 4K+4 stage gate drive sub-circuit GA(4K+4); the second clock line CKL2 is configured to transmit a corresponding third clock signal CKc to the 4K+1 stage gate drive sub-circuit GA(4K+1) in the first cascade group GM1, and is configured to transmit a corresponding first clock signal CKa to the 4K+2 stage gate drive sub-circuit GA(4K+2), and is configured to transmit a corresponding second clock signal CKb to the 4K+3 stage gate drive sub-circuit GA(4K+3); the third clock line CKL3 is configured to transmit a corresponding third clock signal CKc to the 4K+2 stage gate drive sub-circuit GA(4K+2) in the first cascade group GM1, and is configured to transmit a corresponding first clock signal CKa to the 4K+3 stage gate drive sub-circuit GA(4K+3), and is configured to transmit a corresponding second clock signal CKb to the 4K+4 stage gate drive sub-circuit GA(4K+4); the fourth clock line CKL4 is configured to transmit a corresponding second clock signal CKb to the 4K+1 stage gate drive sub-circuit GA(4K+1) in the first cascade group GM1, and is configured to transmit a corresponding third clock signal CKc to the 4K+3 stage gate drive sub-circuit GA(4K+3), and is configured to transmit a corresponding first clock signal CKa to the 4K+4 stage gate drive sub-circuit GA(4K+4); wherein, K≥0.

[0069] Optionally, the number of clock lines included in the first group of clock lines and the second group of clock lines can be equal. For example, L2=4.

[0070] Optionally, the design relationship between the second cascade group GM2 and the second group of clock lines can be obtained by referring to the design relationship between the first cascade group GM1 and the first group of clock lines. That is, the second group of clock lines can include a fifth clock line CKL5, a sixth clock line CKL6, a seventh clock line CKL7, and an eighth clock line CKL8. The fifth clock line CKL5 is configured to transmit a corresponding first clock signal CKa to the 4K+1th gate drive sub-circuit GA(4K+1) in the second cascade group GM2, and is configured to transmit a corresponding second clock signal CKb to the 4K+2th gate drive sub-circuit GA(4K+2), and is configured to transmit a corresponding third clock signal CKc to the 4K+4th gate drive sub-circuit GA(4K+4); the sixth clock line CKL6 is configured to transmit a corresponding third clock signal CKc to the 4K+1th gate drive sub-circuit GA(4K+1) in the second cascade group GM2, and is configured to transmit a corresponding first clock signal CKa to the 4K+2th gate drive sub-circuit GA(4K+2), and is configured to transmit a corresponding second clock signal CKb to the 4K+3th gate drive sub-circuit GA(4K+3); the seventh clock line CKL7 is configured to transmit a corresponding third clock signal CKc to the 4K+2th gate drive sub-circuit GA(4K+2) in the second cascade group GM2, and is configured to transmit a corresponding first clock signal CKa to the 4K+3th gate drive sub-circuit GA(4K+3), and is configured to transmit a corresponding second clock signal CKb to the 4K+4th gate drive sub-circuit GA(4K+4); the eighth clock line CKL8 is configured to transmit a corresponding second clock signal CKb to the 4K+1th gate drive sub-circuit GA(4K+1) in the second cascade group GM2, and is configured to transmit a corresponding third clock signal CKc to the 4K+3th gate drive sub-circuit GA(4K+3), and is configured to transmit a corresponding first clock signal CKa to the 4K+4th gate drive sub-circuit GA(4K+4).

[0071] Optionally, the phase difference design between the clock signals transmitted by the first group of clock lines can be used by the clock signals transmitted by the second group of clock lines, so as to reduce the control difficulty and maintain the consistency of the phase difference of the plurality of gate control signals output by the gate drive circuit.

[0072] The phase difference between the clock signals transmitted by two adjacent clock lines in the first group of clock lines is equal to the phase difference between the clock signals transmitted by two adjacent clock lines in the second group of clock lines, so that the phase difference between the plurality of gate control signals output by the first cascade group GM1 is consistent with the phase difference between the plurality of gate control signals output by the second cascade group GM2.

[0073] Correspondingly, when the first group of clock lines includes the first clock line CKL1 to the fourth clock line CKL4 and the second group of clock lines includes the fifth clock line to the eighth clock line, the phase difference between the first clock signal CK1 transmitted by the first clock line CKL1 and the second clock signal CK2 transmitted by the second clock line CKL2 is equal to the phase difference between the second clock signal CK2 and the third clock signal CK3 transmitted by the third clock line CKL3, equal to the phase difference between the third clock signal CK3 and the fourth clock signal CK4 transmitted by the fourth clock line CKL4, equal to the phase difference between the fifth clock signal CK5 transmitted by the fifth clock line and the sixth clock signal CK6 transmitted by the sixth clock line, equal to the phase difference between the sixth clock signal CK6 and the seventh clock signal CK7 transmitted by the seventh clock line, and equal to the phase difference between the seventh clock signal CK7 and the eighth clock signal CK8 transmitted by the eighth clock line.

[0074] Alternatively, the plurality of gate driving sub-circuits GA in the first cascade group GM1 and the plurality of gate driving sub-circuits GA in the second cascade group GM2 can be controlled to alternately output the gate control signals by controlling the timing of the clock signals transmitted by the first group of clock lines and the second group of clock lines. For example, the clock signals transmitted by the first clock line CKL1, the fifth clock line CKL5, the second clock line CKL2, the sixth clock line CKL6, the third clock line CKL3, the seventh clock line CKL7, the fourth clock line CKL4, and the eighth clock line CKL8 can be controlled to have valid levels in sequence, so that the plurality of gate driving sub-circuits GA in the first cascade group GM1 and the plurality of gate driving sub-circuits GA in the second cascade group GM2 alternately output the gate control signals.

[0075] Alternatively, to make the interval periods in which the plurality of gate control signals jump from the valid level to the invalid level consistent when the plurality of gate driving sub-circuits GA in the first cascade group GM1 and the plurality of gate driving sub-circuits GA in the second cascade group GM2 alternately output the gate control signals, the first clock signal CK1 transmitted by the first clock line CKL1 and the fifth clock signal CK5 transmitted by the fifth clock line CKL5 can have a first phase difference, and the fifth clock signal CK5 transmitted by the fifth clock line CKL5 and the second clock signal CK2 transmitted by the second clock line CKL2 can have a second phase difference. The first phase difference is smaller than the second phase difference.

[0076] It should be noted that, in order to avoid the second gate control signal Scan2 output by the gate drive sub-circuit GA having no effective level, X and Y can be set as 2 when only four clock lines are used to transmit corresponding clock signals to the cascaded gate drive sub-circuits GA in the gate drive circuit, that is, corresponding to the design shown in FIG. 4. Figure 1B In the design shown in FIG. 4, the start signal received by the Nth gate drive sub-circuit GA(N) is the stage transfer signal ST(N-2) output by the N-2th gate drive sub-circuit GA(N-2), and the pull-down control signal received by the Nth gate drive sub-circuit GA(N) is the stage transfer signal ST(N+2) output by the N+2th gate drive sub-circuit GA(N+2). Correspondingly, in the design shown in FIG. 5, Figure 1B In the design shown in FIG. 4, the start signal received by the Nth gate drive sub-circuit GA(N) in the first cascaded group GM1 is the stage transfer signal ST(N-2) output by the N-2th gate drive sub-circuit GA(N-2) in the first cascaded group GM1, and the pull-down control signal received by the Nth gate drive sub-circuit GA(N) in the first cascaded group GM1 is the stage transfer signal ST(N+2) output by the N+2th gate drive sub-circuit GA(N+2) in the first cascaded group GM1. Here, N can be equal to the maximum number of the cascaded gate drive sub-circuits GA. The gate drive sub-circuits GA in the first cascaded group GM1 and the gate drive sub-circuits GA in the second cascaded group GM2 are not cascaded.

[0077] If the first cascaded group GM1 includes odd-numbered gate drive sub-circuits GA, the second cascaded group GM2 includes even-numbered gate drive sub-circuits GA, and the first cascaded group GM1 and the second cascaded group GM2 alternately output gate control signals, in order to avoid the second gate control signal Scan2 output by the gate drive sub-circuit GA having no effective level, X and Y can be set as 4 when only eight clock lines are used to transmit corresponding clock signals to the cascaded gate drive sub-circuits GA in the gate drive circuit, that is, corresponding to the design shown in FIG. 6. Figures 3A-3B In the design shown in FIG. 6, the start signal received by the Nth gate drive sub-circuit GA(N) in the gate drive circuit (i.e., simultaneously including the first cascaded group GM1 and the second cascaded group GM2) is the stage transfer signal ST(N-4) output by the N-4th gate drive sub-circuit GA(N-4) in the gate drive circuit, and the pull-down control signal received by the Nth gate drive sub-circuit GA(N) in the gate drive circuit is the stage transfer signal ST(N+4) output by the N+4th gate drive sub-circuit GA(N+4) in the gate drive circuit. Here, N can be equal to the maximum number of all the gate drive sub-circuits GA included in the gate drive circuit.

[0078] Figure 1Ais a timing diagram of the gate control signal provided by the embodiment of the present application. With each transistor included in the gate driving sub-circuit GA being an N-type transistor, the third clock line CKL3 is configured to transmit the first clock signal CKa for the Nth gate driving sub-circuit GA(N), the second clock line CKL2 is configured to transmit the second clock signal CKb for the Nth gate driving sub-circuit GA(N), the fourth clock line CKL4 is configured to transmit the third clock signal CKc for the Nth gate driving sub-circuit GA(N), the start signal corresponding to the Nth gate driving sub-circuit GA(N) is the N-2th stage transmission signal ST(N-2)(N-2) output by the N-2th gate driving sub-circuit GA(N-2), and the pull-down control signal corresponding to the Nth gate driving sub-circuit GA(N) is the N+2th stage transmission signal ST(N+2)(N+2) output by the N+2th gate driving sub-circuit GA(N+2). The working principle of the plurality of cascaded gate driving sub-circuits GA in the gate driving circuit is described by taking the Nth gate driving sub-circuit GA(N) as an example.

[0079] Please continue to refer to Figures 2A-2B , Figure 3A and Figure 1B In the first stage t1, the N-2th stage transmission signal ST(N-2) is at a high level, the N+2th stage transmission signal ST(N+2) is at a low level, the first clock signal CK1 transmitted by the first clock line CKL1 and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 are at a high level, and the second clock signal CK2 transmitted by the second clock line CKL2 and the third clock signal CK3 transmitted by the third clock line CKL3 are at a low level. The first switch transistor Ts1, the fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission output transistor Tst, the second output transistor To2 and the third output transistor To3 in the Nth gate driving sub-circuit GA(N) are turned on, and the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the first output transistor To1, the first reset transistor TrQ and the second reset transistor TrG are turned off. The Nth stage transmission signal ST(N), the Nth first gate control signal Scan1(N) and the Nth second gate control signal Scan2(N) output by the Nth gate driving sub-circuit GA(N) are at a low level.

[0080] In the second stage t2, the stage transmission signal ST(N-2) of the N-2th stage is high level, the stage transmission signal ST(N+2) of the N+2th stage is low level, the first clock signal CK1 is high level, and the second clock signal CK2 to the fourth clock signal CK4 are low level. The first switch transistor Ts1, the fourth switch transistor Ts4, the fifth switch transistor Ts5, and the stage transmission output transistor Tst in the Nth gate driving sub-circuit GA(N) are turned on; the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the first output transistor To1 to the third output transistor To3, the first reset transistor TrQ, and the second reset transistor TrG are turned off. The Nth stage transmission signal ST(N), the Nth first gate control signal Scan1(N), and the Nth second gate control signal Scan2(N) output by the Nth gate driving sub-circuit GA(N) are low level.

[0081] In the third stage t3, the stage transmission signal ST(N-2) of the N-2th stage and the stage transmission signal ST(N+2) of the N+2th stage are low level, the first clock signal CK1 and the fourth clock signal CK4 are low level, and the second clock signal CK2 and the third clock signal CK3 are high level. The fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission output transistor Tst, and the first output transistor To1 in the Nth gate driving sub-circuit GA(N) are turned on; the first switch transistor Ts1, the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the second output transistor To2, the third output transistor To3, the first reset transistor TrQ, and the second reset transistor TrG are turned off. The Nth stage transmission signal ST(N) and the Nth first gate control signal Scan1(N) are high level, and the Nth second gate control signal Scan2(N) is low level.

[0082] In the fourth stage t4, the stage transmission signal ST(N-2) of the N-2th stage and the stage transmission signal ST(N+2) of the N+2th stage are low level, the first clock signal CK1 and the second clock signal CK2 are low level, and the third clock signal CK3 and the fourth clock signal CK4 are high level. The fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission output transistor Tst, the second output transistor To2, and the third output transistor To3 in the Nth gate driving sub-circuit GA(N) are turned on; the first switch transistor Ts1, the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the first output transistor To1, the first reset transistor TrQ, and the second reset transistor TrG are turned off. The Nth stage transmission signal ST(N) and the Nth second gate control signal Scan2(N) are high level, and the Nth first gate control signal Scan1(N) is low level.

[0083] In the fifth stage t5, the stage transmission signal ST(N-2) and the stage transmission signal ST(N+2) of the N-2th stage and the N+2th stage are low, the first clock signal CK1 to the third clock signal CK3 are low, and the fourth clock signal CK4 is high. The fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission output transistor Tst, the second output transistor To2 and the third output transistor To3 in the Nth gate driving sub-circuit GA(N) are turned on; the first switch transistor Ts1, the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the first output transistor To1, the first reset transistor TrQ and the second reset transistor TrG are turned off. The stage transmission signal ST(N) of the Nth stage, the first gate control signal Scan1(N) of the Nth stage and the second gate control signal Scan2(N) of the Nth stage are low.

[0084] In the sixth stage t6, the stage transmission signal ST(N-2) of the N-2th stage is low, the stage transmission signal ST(N+2) of the N+2th stage is high, the first clock signal CK1 and the fourth clock signal CK4 are high, and the second clock signal CK2 and the third clock signal CK3 are low. The first switch transistor Ts1, the second switch transistor Ts2, the third switch transistor Ts3, the sixth switch transistor Ts6, the first transistor T1 to the fourth transistor T4, the second output transistor To2 and the third output transistor To3 in the Nth gate driving sub-circuit GA(N) are turned on; the fourth switch transistor Ts4, the fifth switch transistor Ts5, the stage transmission output transistor Tst, the first output transistor To1, the first reset transistor TrQ and the second reset transistor TrG are turned off. The stage transmission signal ST(N) of the Nth stage, the first gate control signal Scan1(N) of the Nth stage and the second gate control signal Scan2(N) of the Nth stage are low.

[0085] Similarly, the working principle of the gate driving circuit using the design shown in Figure 3B and the corresponding timing diagram shown in Figure 2B will not be described here.

[0086] It can be understood that by adjusting the phase of the clock signals transmitted by the plurality of clock lines, the pulse width of the effective level of the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate driving sub-circuit GA can be adjusted. Thus, by adjusting the duty cycle, phase and other parameters of the clock signals, the first gate control signal Scan1 and the second gate control signal Scan2 can have the same pulse width of the effective level.

[0087] The inventor found that the gate driving circuit using the design shown in Figure 1AThe gate driving circuit of the gate driving sub-circuit GA shown is verified by experiments. When the gate driving circuit is applied to a display panel, the rising edge of the first gate control signal Scan1 output by the gate driving sub-circuit GA corresponds to the rising edge of the first clock signal CKa applied thereto, the falling edge of the first gate control signal Scan1 output by the gate driving sub-circuit GA corresponds to the rising edge of the third clock signal CKc applied thereto, the rising edge of the second gate control signal Scan2 output by the gate driving sub-circuit GA corresponds to the rising edge of the third clock signal CKc applied thereto, and the falling edge of the second gate control signal Scan2 output by the gate driving sub-circuit GA corresponds to the falling edge of the first clock signal CKa applied thereto. In order to meet the requirement of charging uniformity of the data signal to the sub-pixel Spi or the pixel, and reduce the problem of display difference, the display panel requires that the falling edge interval time difference between two adjacent gate control signals output by the gate driving circuit is 1H. Therefore, the period of the clock signal needs to be set to 8H, and the duty cycle of the clock signal transmitted by the clock line is <50%. The actual verification result shows that when the duty cycle of the clock signal transmitted by the clock line is set to 37.5%, the requirement of the display panel on the gate control signal can be met, and the probability of the problem of display difference of the display panel is reduced.

[0088] In addition, when the gate driving circuit is applied to a display panel, in order to meet the requirement of the display panel on the gate control signal, the number of clock lines included in the gate driving circuit can also be increased to improve the design. That is, when the gate driving circuit adopts the design shown in Figure 3A The period of the clock signal is set to 8H, the falling edge interval of the Nth first gate control signal Scan1(N), the Nth second gate control signal Scan2(N), the N+1th first gate control signal Scan1 and the N+1th second gate control signal Scan2 is 1H, as shown in Figure 1B However, because the pulse width of the effective level of the first gate control signal Scan1 and the second gate control signal Scan2 is different, the sub-pixel Spi or the pixel corresponding to the first gate control signal Scan1 has a pre-charging phase with a time length of 1H, while the sub-pixel Spi or the pixel corresponding to the second gate control signal Scan2 does not have a pre-charging phase, which may cause display difference between the sub-pixel Spi or the pixel corresponding to the first gate control signal Scan1 and the sub-pixel Spi or the pixel corresponding to the second gate control signal Scan2. Therefore, the gate driving circuit can adopt the structural design shown in Figure 2B and the clock signal applied thereto is as shown in Figures 4A-4BThe timing design shown is to make the falling edge interval of the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate drive circuit become 2H, the pulse width of the effective level of the first gate control signal Scan1 become 4H, and the pulse width of the effective level of the second gate control signal Scan2 become 2H, so that the sub-pixel Spi or pixel applying the first gate control signal Scan1 has a pre-charge phase with a time length of 3H, and the sub-pixel Spi or pixel applying the second gate control signal Scan2 has a pre-charge phase with a time length of 1H. After the sub-pixel Spi or pixel has the pre-charge phase, the charge difference between the sub-pixels Spi or pixels can be reduced, and then the display difference problem caused by the uneven charging of the sub-pixels Spi or pixels is improved.

[0089] Figures 4A-4B is a structural schematic diagram of a display panel provided by an embodiment of the present application, and the present application further provides a display panel comprising any of the above gate drive circuits. Wherein, Figures 4A-4B The STV in corresponds to receiving a start signal, and the Dcs corresponds to receiving a pull-down control signal.

[0090] Please continue to refer to Figure 4A , the display panel comprises a plurality of sub-pixels Spi, and the plurality of sub-pixels Spi are electrically connected with the gate drive circuit. Wherein, the sub-pixel Spi can comprise a transistor controlled by a corresponding gate control signal (such as Figure 4A shown as Ts), so as to realize the control of the working state of the sub-pixel Spi through the transistor controlled by the corresponding gate control signal.

[0091] It should be noted that the sub-pixel Spi can also comprise a storage capacitor Cs and the like. The structure of the sub-pixel Spi is not limited to Figure 5 shown form.

[0092] Optionally, the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate drive sub-circuit GA can be used to control two transistors of the same sub-pixel Spi, or can be used to control two transistors in different sub-pixels Spi.

[0093] It should be noted that when the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate drive sub-circuit GA are used to control two transistors in different sub-pixels Spi, it can mean that the first gate control signal Scan1 and the second gate control signal Scan2 output by the same gate drive sub-circuit GA are used to control transistors with the same function in different sub-pixels Spi, or can mean that they are used to control transistors with different functions in different sub-pixels Spi.

[0094] It can be understood that the display panel can include a plurality of pixels, and each pixel can include at least one sub-pixel Spi.

[0095] Figures 4A-4B is a schematic diagram of a charging time length of a sub-pixel provided by an embodiment of the present application. Optionally, the first gate control signal Scan1 output by the first output end Out1 of the gate drive sub-circuit GA can control the corresponding sub-pixel Spi to have a pre-charging period with a first time length tA, and the second gate control signal Scan2 output by the second output end Out2 of the gate drive sub-circuit GA can control the corresponding sub-pixel Spi to have a pre-charging period with a second time length tB; the first time length tA is greater than or equal to the second time length tB, so as to reduce the charging difference between the sub-pixels Spi, and then improve the display difference problem caused by the uneven charging of the sub-pixels Spi.

[0096] Optionally, the gate drive circuit can be arranged in the non-display area NA, and the sub-pixel Spi can be arranged in the display area AA, and the non-display area NA is located at one side of the display area AA, as shown in Figure 4B , so as to reduce the influence of the gate drive circuit on the resolution.

[0097] Optionally, the first cascade group GM1 and the second cascade group GM2 can be arranged at opposite sides of the display area AA, so as to reduce the layout space occupied by the gate drive circuit in the single side frame, as shown in Figures 4A-4B .

[0098] Optionally, the sub-pixels Spi in the 4H+1th row and the sub-pixels Spi in the 4H+2th row receive the gate control signals output by the first cascade group GM1, and the sub-pixels Spi in the 4H+3th row and the sub-pixels Spi in the 4H+4th row receive the gate control signals output by the second cascade group GM2, so as to cross drive the sub-pixels Spi in the display panel by the first cascade group GM1 and the second cascade group GM2. Wherein, H≥0.

[0099] Optionally, the sub-pixels Spi in the 4H+1th row receive the first gate control signal Scan1 output by the first cascade group GM1, and the sub-pixels Spi in the 4H+2th row receive the second gate control signal Scan2 output by the first cascade group GM1; the sub-pixels Spi in the 4H+3th row receive the first gate control signal Scan1 output by the second cascade group GM2, and the sub-pixels Spi in the 4H+4th row receive the second gate control signal Scan2 output by the second cascade group GM2, so that the gate control signals received by the sub-pixels Spi in the odd-numbered rows are all the first gate control signal Scan1, and the gate control signals received by the sub-pixels Spi in the even-numbered rows are all the second gate control signal Scan2, so as to weaken the display difference problem.

[0100] In addition, the fourth H+1 row of sub-pixels Spi and the fourth H+3 row of sub-pixels Spi can receive the gate control signals output by the first cascade group GM1, and the fourth H+2 row of sub-pixels Spi and the fourth H+4 row of sub-pixels Spi can receive the gate control signals output by the second cascade group GM2, so as to cross drive the sub-pixels Spi in the display panel by the first cascade group GM1 and the second cascade group GM2. Wherein, H≥0.

[0101] Correspondingly, the fourth H+1 row of sub-pixels Spi can receive the first gate control signal Scan1 output by the first cascade group GM1, and the fourth H+2 row of sub-pixels Spi can receive the first gate control signal Scan1 output by the second cascade group GM2; the fourth H+3 row of sub-pixels Spi can receive the second gate control signal Scan2 output by the first cascade group GM1, and the fourth H+4 row of sub-pixels Spi can receive the second gate control signal Scan2 output by the second cascade group GM2, so that the gate control signals received by the fourth H+1 row of sub-pixels Spi and the fourth H+2 row of sub-pixels Spi are both the first gate control signal Scan1, and the gate control signals received by the fourth H+3 row of sub-pixels Spi and the fourth H+4 row of sub-pixels Spi are both the second gate control signal Scan2, so as to improve the display difference problem.

[0102] Please continue to refer to ​ The display panel further includes a scan line SL and a data line DL, and the sub-pixel Spi is electrically connected with the corresponding scan line SL and data line DL. The scan line SL is electrically connected with the gate drive circuit, and is configured to transmit the corresponding gate control signal. The data line DL is configured to transmit the data signal to the sub-pixel Spi, so as to charge the sub-pixel Spi by using the data signal.

[0103] The gate drive circuit and the display panel provided by the present application can reduce the number of gate drive sub-circuits GA included in the gate drive circuit, and reduce the layout space occupied by the gate drive circuit. When the gate drive circuit is used in the display panel, it is helpful for the display panel to realize the narrow frame design. In addition, since the sub-pixel Spi receives the gate control signal but does not receive the stage transmission signal ST, when there is a signal short circuit in the display area of the display panel, it will not affect the stage transmission control function of the gate drive circuit in the opposite direction, thereby improving the stability of the gate drive circuit.

[0104] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed, and the above description should not be understood as the limitation of the present application.

Claims

1. A gate drive circuit characterized by comprising: The gate drive sub-circuit comprises a plurality of cascaded gate drive sub-circuits, and the gate drive sub-circuit comprises: a node control module electrically connected to a first node and a second node of the gate drive sub-circuit, configured to control signals transmitted to the first node and the second node according to a start signal; a stage transmission module electrically connected to the first node, configured to control a first clock signal transmitted to a stage transmission output terminal of the gate drive sub-circuit according to a signal of the first node; a first output module electrically connected to the stage transmission output terminal and a first output terminal of the gate drive sub-circuit, configured to receive a second clock signal and a third clock signal to control signal transmission between one of the stage transmission output terminal and the first power terminal and the first output terminal; a second output module electrically connected to the stage transmission output terminal and a second output terminal of the gate drive sub-circuit, configured to control signal transmission between the stage transmission output terminal and the second output terminal according to the third clock signal; and a pull-down maintenance module electrically connected to the second node, configured to control signal transmission between the first power terminal and the second output terminal according to a signal of the second node.

2. The gate drive circuit according to claim 1, characterized by The first output module comprises: a first output transistor comprising a control terminal configured to receive the second clock signal, a first source-drain terminal electrically connected to the stage transmission output terminal, and a second source-drain terminal electrically connected to the first output terminal; a second output transistor comprising a control terminal configured to receive the third clock signal, a first source-drain terminal electrically connected to the first power terminal, and a second source-drain terminal electrically connected to the first output terminal.

3. The gate drive circuit according to claim 1, characterized by The second output module comprises: a third output transistor comprising a control terminal configured to receive the third clock signal, a first source-drain terminal electrically connected to the stage transmission output terminal, and a second source-drain terminal electrically connected to the second output terminal.

4. The gate drive circuit according to claim 1, characterized by The pull-down maintenance module comprises: a first transistor comprising a control terminal electrically connected to the second node, a first source-drain terminal electrically connected to the first power terminal, and a second source-drain terminal electrically connected to the second output terminal.

5. The gate drive circuit according to claim 1, characterized by The pull-down maintenance module is electrically connected to the first output terminal, and is configured to control signal transmission between the first power terminal and the first output terminal according to a signal of the second node.

6. The gate drive circuit according to claim 1, characterized by The pull-down maintenance module is electrically connected to the first node and the stage transmission output terminal, and is configured to control electrical connection between the first power terminal and the first node and the stage transmission output terminal according to a signal of the second node.

7. The gate drive circuit according to claim 1, wherein The node control module comprises: a pull-up control unit electrically connected to the first node, a second power terminal, configured to control signal transmission between the second power terminal and the first node according to the start signal; an inverting unit electrically connected to the first node, the second node, the first power terminal, and the second power terminal, configured to control electrical connection between one of the first power terminal and the second power terminal and the second node according to a signal of the first node; The starting signal corresponding to the first-stage gate drive sub-circuit in the plurality of cascaded gate drive sub-circuits is a start signal, and the starting signal corresponding to the Nth-stage gate drive sub-circuit is a stage transmission signal generated by the N-Xth-stage gate drive sub-circuit, where N>1 and X>1.

8. The gate drive circuit according to claim 1, characterized by The node control module comprises: The pull-down control unit is electrically connected with the first node and the first power supply end, and is configured to control signal transmission between the first power supply end and the first node according to a pull-down control signal. The pull-down control signal corresponding to the Mth-stage gate drive sub-circuit in the plurality of cascaded gate drive sub-circuits is a stage transmission signal generated by the M+Yth-stage gate drive sub-circuit, where M≥1 and Y>1.

9. The gate drive circuit according to claim 1, characterized by Comprise: A plurality of clock lines are electrically connected with the plurality of gate drive sub-circuits, and are configured to transmit the first clock signal, the second clock signal and the third clock signal corresponding to the plurality of gate drive sub-circuits.

10. The gate drive circuit according to claim 9, characterized by The plurality of clock lines comprise: The first clock line is configured to transmit the first clock signal corresponding to the 4K+1th-stage gate drive sub-circuit, is configured to transmit the second clock signal corresponding to the 4K+2th-stage gate drive sub-circuit, and is configured to transmit the third clock signal corresponding to the 4K+4th-stage gate drive sub-circuit; The second clock line is configured to transmit the third clock signal corresponding to the 4K+1th-stage gate drive sub-circuit, is configured to transmit the first clock signal corresponding to the 4K+2th-stage gate drive sub-circuit, and is configured to transmit the second clock signal corresponding to the 4K+3th-stage gate drive sub-circuit; The third clock line is configured to transmit the third clock signal corresponding to the 4K+2th-stage gate drive sub-circuit, is configured to transmit the first clock signal corresponding to the 4K+3th-stage gate drive sub-circuit, and is configured to transmit the second clock signal corresponding to the 4K+4th-stage gate drive sub-circuit; and The fourth clock line is configured to transmit the second clock signal corresponding to the 4K+1th-stage gate drive sub-circuit, is configured to transmit the third clock signal corresponding to the 4K+3th-stage gate drive sub-circuit, and is configured to transmit the first clock signal corresponding to the 4K+4th-stage gate drive sub-circuit; where K≥0.

11. The gate drive circuit according to claim 9, characterized by The plurality of clock lines are divided into a first group of clock lines and a second group of clock lines, and the gate drive circuit comprises a first cascaded group and a second cascaded group, the first cascaded group and the second cascaded group each comprising a plurality of cascaded gate drive sub-circuits. The first group of clock lines is configured to transmit the first clock signal, the second clock signal and the third clock signal corresponding to the plurality of gate drive sub-circuits in the first cascaded group, and the second group of clock lines is configured to transmit the first clock signal, the second clock signal and the third clock signal corresponding to the plurality of gate drive sub-circuits in the second cascaded group.

12. The gate drive circuit according to claim 11, characterized by The first cascaded group comprises odd-stage gate drive sub-circuits, and the second cascaded group comprises even-stage gate drive sub-circuits.

13. The gate drive circuit of claim 11, wherein, The first group of clock lines comprises a first clock line, a second clock line, a third clock line and a fourth clock line; The first clock line is configured to transmit the corresponding first clock signal to the 4K+1 stage gate drive sub-circuit in the first cascade group, and is configured to transmit the corresponding second clock signal to the 4K+2 stage gate drive sub-circuit, and is configured to transmit the corresponding third clock signal to the 4K+4 stage gate drive sub-circuit; the second clock line is configured to transmit the corresponding third clock signal to the 4K+1 stage gate drive sub-circuit in the first cascade group, and is configured to transmit the corresponding first clock signal to the 4K+2 stage gate drive sub-circuit, and is configured to transmit the corresponding second clock signal to the 4K+3 stage gate drive sub-circuit; the third clock line is configured to transmit the corresponding third clock signal to the 4K+2 stage gate drive sub-circuit in the first cascade group, and is configured to transmit the corresponding first clock signal to the 4K+3 stage gate drive sub-circuit, and is configured to transmit the corresponding second clock signal to the 4K+4 stage gate drive sub-circuit; The fourth clock line is configured to transmit the corresponding second clock signal to the 4K+1 stage gate drive sub-circuit in the first cascade group, and is configured to transmit the corresponding third clock signal to the 4K+3 stage gate drive sub-circuit, and is configured to transmit the corresponding first clock signal to the 4K+4 stage gate drive sub-circuit; wherein K≥0.

14. The gate drive circuit according to claim 13, characterized by The second group of clock lines comprises a fifth clock line, a sixth clock line, a seventh clock line and an eighth clock line; The fifth clock line is configured to transmit the corresponding first clock signal to the 4K+1 stage gate drive sub-circuit in the second cascade group, and is configured to transmit the corresponding second clock signal to the 4K+2 stage gate drive sub-circuit, and is configured to transmit the corresponding third clock signal to the 4K+4 stage gate drive sub-circuit; the sixth clock line is configured to transmit the corresponding third clock signal to the 4K+1 stage gate drive sub-circuit in the second cascade group, and is configured to transmit the corresponding first clock signal to the 4K+2 stage gate drive sub-circuit, and is configured to transmit the corresponding second clock signal to the 4K+3 stage gate drive sub-circuit; The seventh clock line is configured to transmit the corresponding third clock signal to the 4K+2 stage gate drive sub-circuit in the second cascade group, and is configured to transmit the corresponding first clock signal to the 4K+3 stage gate drive sub-circuit, and is configured to transmit the corresponding second clock signal to the 4K+4 stage gate drive sub-circuit; The eighth clock line is configured to transmit the corresponding second clock signal to the 4K+1 stage gate drive sub-circuit in the second cascade group, and is configured to transmit the corresponding third clock signal to the 4K+3 stage gate drive sub-circuit, and is configured to transmit the corresponding first clock signal to the 4K+4 stage gate drive sub-circuit.

15. The gate drive circuit of claim 14, wherein, A phase difference between clock signals transmitted by two adjacent clock lines in the first group of clock lines is equal to a phase difference between clock signals transmitted by two adjacent clock lines in the second group of clock lines.

16. The gate drive circuit of claim 15, wherein, The clock signal transmitted by the first clock line has a first phase difference with the clock signal transmitted by the fifth clock line, and the clock signal transmitted by the fifth clock line has a second phase difference with the clock signal transmitted by the second clock line. The first phase difference is smaller than the second phase difference.

17. The gate drive circuit according to claim 9 or 11, characterized by The duty cycle of the clock signal transmitted by the clock line is 37.5%.

18. A display panel, characterized by The display panel comprises a plurality of sub-pixels, and the plurality of sub-pixels are electrically connected with the gate drive circuit.

19. The display panel of claim 18, wherein, The first gate control signal output by the first output end of the gate drive sub-circuit controls the corresponding sub-pixel to have a first time length of pre-charge period, and the second gate control signal output by the second output end of the gate drive sub-circuit controls the corresponding sub-pixel to have a second time length of pre-charge period. The first time length is greater than the second time length. ​

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