Driving circuit and display device

Abstract

The invention discloses a driving circuit and a display device. The driving circuit is coupled to a control circuit for controlling a plurality of pixels. The driving circuit comprises a detection circuit and an output circuit. The detection circuit is used for detecting whether an abnormal event occurs. The output circuit is used for outputting an enable signal to the control circuit. When an abnormal event occurs, the enable signal is switched from the first level to the second level, so that the control circuit stops outputting the plurality of control signals to the plurality of pixels. The driving circuit can prevent the display device from displaying snowflake images (noise images) so as to maintain comfortable user experience.

Description

Technical Field

[0001] The present disclosure relates to display technology, and more particularly to a driving circuit and a display device. Background Art

[0002] With the advancement of technology, display devices are applied to various electronic devices. In some related methods, when an abnormal event occurs, the decoder in the display device cannot restore the current data, resulting in the display device showing a snowflake image (noise image). How to solve this problem is an important issue in this field. Summary of the invention

[0003] Some aspects of the present disclosure provide a driving circuit. The driving circuit is coupled to a control circuit for controlling a plurality of pixels. The driving circuit includes a detection circuit and an output circuit. The detection circuit is used to detect whether an abnormal event occurs. The output circuit is used to output an enable signal to the control circuit. When an abnormal event occurs, the enable signal switches from a first level to a second level, so that the control circuit stops outputting a plurality of control signals to the plurality of pixels.

[0004] In some embodiments of the driving circuit, the first level is lower than the second level.

[0005] In some embodiments of the driving circuit, when an abnormal event occurs at an abnormal time point of the Nth frame, the enable signal switches from the first level to the second level at the abnormal time point of the Nth frame, and switches from the second level to the first level at the starting time point of the (N+1)th frame.

[0006] In some embodiments of the driving circuit, when an abnormal event occurs at an abnormal time point of a slice of the Nth frame, the enable signal is switched from the first level to the second level at the abnormal time point of the slice of the Nth frame, and is switched from the second level to the first level at the end time point of the slice of the Nth frame.

[0007] Some aspects of the disclosure document provide a display device. The display device includes an active area, a control circuit, and a driving circuit. The active area includes a plurality of pixels. The control circuit is used to control the plurality of pixels. The driving circuit is used to detect whether an abnormal event occurs, and to output an enable signal to the control circuit. When the abnormal event occurs, the enable signal switches from a first level to a second level, so that the control circuit stops outputting a plurality of control signals to the plurality of pixels.

[0008] In some embodiments of the display device, the first level is lower than the second level.

[0009] In some embodiments of the display device, when an abnormal event occurs at an abnormal time point of the Nth frame, the enable signal switches from the first level to the second level at the abnormal time point of the Nth frame, and switches from the second level to the first level at the starting time point of the (N+1)th frame.

[0010] In some embodiments of a display device where an abnormal event occurs at an abnormal time point of the Nth frame, the active area includes an update area and a reserved area, the update area displays image data of the Nth frame, and the reserved area displays another image data of the (N-1)th frame.

[0011] In some embodiments of the display device, when an abnormal event occurs at an abnormal time point of a slice of the Nth frame, the enable signal switches from the first level to the second level at the abnormal time point of the slice of the Nth frame, and switches from the second level to the first level at the end time point of the slice of the Nth frame.

[0012] In some embodiments of a display device in which an abnormal event occurs at an abnormal time point of a slice of the Nth frame, the active area includes an update area and a reserved area, the update area displays image data of the Nth frame, and the reserved area displays another image data of the (N-1)th frame.

[0013] In some embodiments of the display device, the control circuit includes a control signal generating circuit and a logic circuit. The control signal generating circuit is used to generate a plurality of control signals. The logic circuit is used to receive the plurality of control signals from the control signal generating circuit, receive an enable signal from the driving circuit, and output the plurality of control signals to a plurality of pixels according to the enable signal.

[0014] In some embodiments of the display device, the logic circuit includes a plurality of logic gates, each of which is used to perform a logic operation on an enable signal and one of the plurality of control signals.

[0015] In some embodiments of the display device, the plurality of logic gates include a plurality of OR gates.

[0016] In some embodiments of the display device, the driving circuit includes a detection circuit for detecting whether an abnormal event occurs.

[0017] In some embodiments of the display device, the display device includes an organic light emitting diode display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present disclosure can be more fully understood by reading the following detailed description in conjunction with the accompanying drawings and embodiments:

[0019] Figure 1 is a schematic diagram of a display device according to some embodiments of the present disclosure;

[0020] Figure 2According to some embodiments of the present disclosure Figure 1 A schematic diagram of the operation of the display device;

[0021] Figure 3 According to some embodiments of the present disclosure Figure 1 Schematic diagram of logic circuit and active area;

[0022] Figure 4 According to some embodiments of the present disclosure Figure 1 A schematic diagram of the operation of the display device;

[0023] Figure 5A is a schematic diagram of a sub-pixel circuit during data writing according to some embodiments of the present disclosure; and

[0024] Figure 5B According to some embodiments of the present disclosure, Figure 5A Schematic diagram of the sub-pixel circuit.

[0025]

Explanation of symbols

[0026] 100: Display device

[0027] 110: Active area

[0028] 120: Power circuit

[0029] 130: driving circuit

[0030] 132: Detection circuit

[0031] 134,136: Output circuit

[0032] 140: Control circuit

[0033] 142: Control signal generating circuit

[0034] 144:Logic Circuit

[0035] 500: Sub-pixel circuit

[0036] PX, PX1~PX4: Pixel

[0037] R1: Red sub-pixel

[0038] G1: Green sub-pixel

[0039] B1: Blue sub-pixel

[0040] VDD, VSS: power supply voltage

[0041] VGMP, VGSP, VGH, VGL: voltage

[0042] GE: Enable signal

[0043] GATE: control signal

[0044] VS: vertical synchronization signal

[0045] F1~F5: Frame

[0046] DA, DB, DC, DD, DE: Image data

[0047] ER1,ER2,ER3: Abnormal events

[0048] TP1,TP3,TP5: abnormal time points

[0049] TP2,TP4: starting time point

[0050] TP6: End time point

[0051] SL: Slice

[0052] UR: Update Zone

[0053] RR: Reserved Area

[0054] L1~L4: Logic Gate

[0055] T1~T7: Transistor

[0056] C1: Capacitor

[0057] LD: Light Emitting Element

[0058] G: Gate terminal

[0059] S: Source terminal

[0060] DATA: Image data

[0061] SCAN[N], SCAN[N-1]: scan control signal

[0062] EM[N]: Lighting control signal

[0063] VINI: Starting voltage DETAILED DESCRIPTION

[0064] In this disclosure, “connection” or “coupling” may refer to “electrical connection” or “electrical coupling”. “Connection” or “coupling” may also be used to indicate that two or more elements cooperate or interact with each other.

[0065] Please refer to Figure 1 . Figure 1 is a schematic diagram of a display device 100 according to some embodiments of the present disclosure.

[0066] In some embodiments, the display device 100 includes an organic light emitting diode display panel, but the present disclosure is not limited thereto.

[0067] like Figure 1 As shown, the display device 100 includes an active region 110 , a power circuit 120 , a driving circuit 130 , and a control circuit 140 . The active region 110 is coupled to the power circuit 120 , the driving circuit 130 , and the control circuit 140 . The driving circuit 130 is coupled to the control circuit 140 .

[0068] The active area 110 is used to display an image. The image may be a dynamic image. In practical applications, the active area 110 includes a plurality of pixels PX. For simplicity, Figure 1 Only one pixel PX is shown in the figure and other pixels are omitted. One pixel PX includes a red sub-pixel R1, a green sub-pixel G1 and a blue sub-pixel B1.

[0069] The power circuit 120 is used to provide power voltages VDD and VSS to the active region 110. The plurality of sub-pixels in the active region 110 can operate according to the power voltages VDD and VSS.

[0070] The driving circuit 130 is used to provide voltages VGMP and VGSP to the plurality of pixels PX in the active area 110. Figure 1 As shown, the driving circuit 130 includes a detection circuit 132 and output circuits 134 and 136. In practical applications, when an electrostatic discharge (ESD) event or other abnormal event occurs, a mobile industry processor interface (MIPI) abnormality, a cyclic redundancy check (CRC) abnormality, a synchronization loss abnormality, a bit abnormality or other abnormal events may occur. The detection circuit 132 is used to detect whether an abnormal event occurs. The output circuit 134 is used to output an enable signal GE to the control circuit 140 according to the detection result of the detection circuit 132. The output circuit 136 is used to output the voltage VGH and the voltage VGL to the control circuit 140.

[0071] The control circuit 140 is used to control the plurality of pixels PX in the active area 110. Figure 1As shown, the control circuit 140 includes a control signal generating circuit 142 and a logic circuit 144, and the logic circuit 144 is coupled to a plurality of pixels PX in the active region 110. The control signal generating circuit 142 is used to receive the voltages VGH and VGL from the output circuit 136, and to generate a plurality of control signals GATE according to the voltages VGH and VGL. The logic circuit 144 is used to receive the control signal GATE and the enable signal GE from the control signal generating circuit 142 and the output circuit 134, respectively. The logic circuit 144 is further used to output the plurality of control signals GATE to the plurality of pixels PX in the active region 110 according to the enable signal GE. In some embodiments, the control circuit 140 can be implemented by a gate-on-array (GOA) technology.

[0072] Then, the plurality of pixels PX in the active area 110 may be controlled to display corresponding images according to the input image data, the power voltages VDD, VSS, the voltages VGMP, VGSP and the control signal GATE.

[0073] Please refer to Figure 1 and Figure 2 . Figure 2 According to some embodiments of the present disclosure Figure 1 Schematic diagram of the operation of the display device 100.

[0074] like Figure 2As shown, it is assumed that an image has frames F1 to F5 in sequence. The input image data of frames F1 to F5 are image data DA, DB, DC, DD and DE respectively. The image data DA, DB, DC, DD and DE can be transmitted from the driving circuit 130 to the plurality of pixels PX in the active area 110. The vertical synchronization signal VS is an internal signal in the driving circuit 130, which is used to indicate the start of a frame. In this example, the abnormal event ER1 occurs at the abnormal time point TP1 in the frame F2 (for example, the Nth frame). The enable signal GE has a low level (for example, a logic value 0) in the frame F1, and switches from the low level to a high level (for example, a logic value 1) at the abnormal time point TP1 in the frame F2. The low level is lower than the high level. Then, the enable signal GE switches from the high level to the low level at the start time point TP2 of the next frame F3 (for example, the (N+1)th frame). Another abnormal event ER2 occurs at the abnormal time point TP3 in the frame F4. The enable signal GE has a low level in frame F3, and switches from the low level to the high level at the abnormal time point TP3 in frame F4. Then, the enable signal GE switches from the high level to the low level at the starting time point TP4 of the next frame F5. Regardless of whether the abnormal events ER1 and ER2 occur, the signals related to light emission operate normally. However, when the enable signal GE has a low level, the corresponding pixel PX can be scanned normally. When the enable signal GE has a high level, the corresponding pixel PX cannot be scanned normally. The details of the scanning operation will be described in the following paragraphs. Figure 3 Provide explanation.

[0075] Please refer to Figure 3 . Figure 3 According to some embodiments of the present disclosure Figure 1 Schematic diagram of the logic circuit 144 and the active region 110 .

[0076] like Figure 3 As shown, the logic circuit 144 includes logic gates L1-L4. Each of the logic gates L1-L4 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the logic gates L1-L4 is used to Figure 1 The control signal generating circuit 142 receives the control signal GATE. The second input terminals of the logic gates L1 to L4 are used to automatically Figure 1 The output circuit 134 receives the enable signal GE. The logic gates L1-L4 are used to perform a logic operation on the control signal GATE received at the first input terminal and the enable signal GE received at the second input terminal. In this example, the logic gates L1-L4 are implemented by OR gates, so the aforementioned logic operation is an OR logic operation. The output terminals of the logic gates L1-L4 are used to output the results of the OR logic operation of the logic gates L1-L4 to the pixels PX1-PX4 respectively.

[0077] It should be noted that Figure 3 The implementation of the logic gates L1 to L4 is only an example, and the present disclosure is not limited thereto. Other suitable implementations of the logic gates L1 to L4 are within the scope of the present disclosure.

[0078] Please refer to Figure 2 and Figure 3 Generally speaking, the pixels PX1 to PX4 are scanned row by row. In other words, the pixels PX1, PX2, PX3, and PX4 are scanned sequentially.

[0079] Before the abnormal time point TP1, the enable signal GE has a logic value of 0. Therefore, the logic gates L1-L2 perform a logic operation according to the enable signal GE having a logic value of 0. Taking the logic gate L1 as an example, when the enable signal GE has a logic value of 0, the operation result output by the output end of the logic gate L1 is equivalent to the control signal GATE received by the first input end of the logic gate L1. The logic gate L2 has a similar operation. In other words, the logic gates L1-L2 can correctly pass the control signal GATE to their output ends. This situation means that the pixels PX1 and PX2 can be scanned normally and can be updated by the control signal GATE transmitted by the logic gates L1 and L2. Therefore, the pixels PX1 and PX2 display the image data DB of the frame F2.

[0080] At the abnormal time point TP1, the abnormal event ER1 occurs and the enable signal GE switches from logic value 0 to logic value 1. Taking the logic gate L3 as an example, when the enable signal GE has a logic value of 1, the operation result output by the output end of the logic gate L3 is equivalent to the enable signal GE with a logic value of 1 received by the second input end of the logic gate L3, so that the logic gate L3 in the logic circuit 144 in the control circuit 140 stops outputting the control signal GATE to the pixel. The logic gate L4 has a similar operation. In other words, the logic gates L3~L4 cannot correctly transmit the control signal GATE to their output ends. This situation means that the pixels PX3 and PX4 cannot be scanned normally and cannot be updated by the control signal GATE transmitted by the logic gates L3 and L4. Therefore, the pixels PX3 and PX4 display the image data DA of the frame F1.

[0081] Therefore, the active area 110 is divided into an update area UR and a reserved area RR. The update area UR includes pixels PX1 and PX2 and displays image data DB of the current frame F2 (e.g., the Nth frame). The reserved area RR includes pixels PX3 and PX4 and displays image data DA of the previous frame F1 (e.g., the (N-1)th frame).

[0082] In some related methods, when an abnormal event occurs, a decoder in a display device cannot restore correct data, causing the display device to display a snowflake image (noise image).

[0083] Compared to the aforementioned related methods, in the present disclosure, when the abnormal event ER1 or ER2 occurs, the enable signal GE is switched from one level to another level, so that the corresponding pixel PX will not be updated and the image data of the previous frame will be displayed to prevent the display device from displaying a snow image (noise image). Since the difference between the current frame and the previous frame is almost imperceptible, the viewer can still have a comfortable user experience.

[0084] Please refer to Figure 4 . Figure 4 According to some embodiments of the present disclosure Figure 1 Schematic diagram of the operation of the display device 100.

[0085] In some embodiments, the Video Electronics Standards Association (VESA) compression technology is applied to the image data DA-DC. A unit of the VESA compression technology is a slice. Figure 4 As shown, the abnormal event ER3 occurs at an abnormal time point TP5 in a slice SL in a frame F2 (e.g., the Nth frame). The enable signal GE has a low level in the frame F1, and switches from the low level to the high level at the abnormal time point TP5 in the slice SL in the frame F2. Then, the enable signal GE switches from the high level to the low level at the end time point TP6 of the slice SL in the frame F2. Similar to Figure 2 In the frame F2, the pixel PX corresponding to the enable signal GE having a low level can be scanned normally, can be updated by the corresponding control signal GATE, and can display the image data DB of the frame F2. On the contrary, the pixel PX corresponding to the enable signal GE having a high level in the frame F2 cannot be scanned normally, cannot be updated by the corresponding control signal GATE, and displays the image data DA of the previous frame F1.

[0086] Please refer to Figure 5A and Figure 5B . Figure 5A FIG. 5 is a schematic diagram of a sub-pixel circuit 500 during data writing according to some embodiments of the present disclosure. Figure 5B According to some embodiments of the present disclosure, Figure 5A Schematic diagram of a sub-pixel circuit 500.

[0087] The sub-pixel circuit 500 may be arranged at Figure 1 In the red sub-pixel R1, green sub-pixel G1 or blue sub-pixel B1. Figure 5AAs shown, the sub-pixel circuit 500 includes transistors T1-T7, a capacitor C1 and a light-emitting element LD. In this example, each of the transistors T1-T7 is implemented by a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the light-emitting element LD is implemented by an organic light-emitting diode, but the present disclosure is not limited thereto.

[0088] The first end of transistor T1 is used to receive image data DATA. Transistor T1 is controlled by a scan control signal SCAN[N]. The second end of transistor T1 is coupled to the first end of transistor T2. The second end of transistor T2 and the first end of capacitor C1 are used to receive a power supply voltage VDD. Transistor T2 is controlled by a light emitting control signal EM[N]. The first end of transistor T3 is coupled between transistors T1 and T2. The control end of transistor T3 is coupled to the second end of capacitor C1. The second end of transistor T3 is coupled to the first end of transistor T4 and the first end of transistor T5. The second end of transistor T4 is coupled to the control end of transistor T3 and the second end of capacitor C1. Transistor T4 is controlled by a scan control signal SCAN[N]. The second end of transistor T5 is coupled to the anode end of light emitting element LD. Transistor T5 is controlled by a light emitting control signal EM[N]. The cathode end of light emitting element LD is used to receive a power supply voltage VSS. The first end of transistor T6 is coupled to the anode end of light emitting element LD. The second end of transistor T6 is used to receive a starting voltage VINI. The transistor T6 is controlled by the scan control signal SCAN[N-1]. The first terminal of the transistor T7 is used to receive the starting voltage VINI. The second terminal of the transistor T7 is coupled to the second terminal of the capacitor C1. The transistor T7 is controlled by the scan control signal SCAN[N-1].

[0089] It should be noted that Figure 5A and Figure 5B The implementation of the sub-pixel circuit 500 is only an example, and the present disclosure is not limited thereto. Other suitable implementations of the sub-pixel circuit 500 are within the scope of the present disclosure.

[0090] During the start period, the start voltage VINI is transmitted to the control terminal (eg, the gate terminal G) of the transistor T3 , and the power supply voltage VDD is transmitted to the first terminal (eg, the source terminal S) of the transistor T3 .

[0091] like Figure 5AAs shown, during the data writing period, transistors T1 and T4 are turned on by the scanning control signal SACN[N], transistors T2 and T5 are turned off by the light emitting control signal EM[N], and transistors T6 and T7 are turned off by the scanning control signal SACN[N-1]. Therefore, the image data DATA can be transmitted to the gate terminal G of the transistor T3 through the transistors T1, T3 and T4, wherein the transistor T3 adopts a diode-connected form.

[0092] like Figure 5B As shown, during the light-emitting period, transistors T1 and T4 are turned off by the scanning control signal SACN[N], transistors T2 and T5 are turned on by the light-emitting control signal EM[N], and transistors T6 and T7 are turned off by the scanning control signal SACN[N-1]. Therefore, the light-emitting current can be conducted from transistor T3 to the light-emitting element LD via transistor T5.

[0093] Figure 3 The control signal GATE can include Figure 5A and Figure 5B The scan control signals SCAN[N], SCAN[N-1], other start control signals and other clock signals are also included. Figure 2 As explained in the paragraph above, regardless of whether abnormal events ER1 and ER2 occur, the signals related to light emission operate normally. Figure 5A and Figure 5B The light emitting control signal EM[N] can operate normally.

[0094] As described above, the present disclosure can prevent a display device from displaying snow images (noise images) and maintain a comfortable user experience for viewers.

[0095] Although the present disclosure has been described in detail with reference to certain specific embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained in the present disclosure. It is obvious to those of ordinary skill in the art to which the present disclosure belongs that various modifications and equivalent changes can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the following claims are within the scope covered by the present disclosure.

Claims

1. A driving circuit, characterized in that: coupled to a control circuit for controlling a plurality of pixels, wherein the driving circuit comprises: a detection circuit for detecting whether an abnormal event occurs; and an output circuit for outputting an enable signal to the control circuit, When the abnormal event occurs, the enable signal is switched from a first level to a second level, so that the control circuit stops outputting a plurality of control signals to the plurality of pixels.

2. The driving circuit according to claim 1, characterized in that: The first level is lower than the second level.

3. The driving circuit according to claim 1, wherein: When the abnormal event occurs at an abnormal time point of an Nth frame, the enable signal switches from the first level to the second level at the abnormal time point of the Nth frame, and switches from the second level to the first level at a starting time point of an (N+1)th frame.

4. The driving circuit according to claim 1, wherein: When the abnormal event occurs at an abnormal time point of a slice of an N-th frame, the enable signal is switched from the first level to the second level at the abnormal time point of the slice of the N-th frame, and is switched from the second level to the first level at an end time point of the slice of the N-th frame.

5. A display device, characterized in that: Include: an active area, comprising a plurality of pixels; a control circuit for controlling the plurality of pixels; and a driving circuit for detecting whether an abnormal event occurs and for outputting an enabling signal to the control circuit, When the abnormal event occurs, the enable signal is switched from a first level to a second level, so that the control circuit stops outputting a plurality of control signals to the plurality of pixels.

6. The display device according to claim 5, characterized in that The first level is lower than the second level.

7. The display device according to claim 5, characterized in that When the abnormal event occurs at an abnormal time point of an Nth frame, the enable signal switches from the first level to the second level at the abnormal time point of the Nth frame, and switches from the second level to the first level at a starting time point of an (N+1)th frame.

8. The display device according to claim 7, characterized in that The active area includes an update area and a reserved area. The update area displays an image data of the Nth frame, and the reserved area displays another image data of the (N-1)th frame.

9. The display device according to claim 5, characterized in that When the abnormal event occurs at an abnormal time point of a slice of an N-th frame, the enable signal is switched from the first level to the second level at the abnormal time point of the slice of the N-th frame, and is switched from the second level to the first level at an end time point of the slice of the N-th frame.

10. The display device according to claim 9, characterized in that The active area includes an update area and a reserved area. The update area displays an image data of the Nth frame, and the reserved area displays another image data of the (N-1)th frame.

11. The display device according to claim 5, characterized in that The control circuit comprises: a control signal generating circuit, for generating the plurality of control signals; and A logic circuit is used for receiving the plurality of control signals from the control signal generating circuit, receiving the enabling signal from the driving circuit, and outputting the plurality of control signals to the plurality of pixels according to the enabling signal.

12. The display device according to claim 11, wherein: The logic circuit includes: A plurality of logic gates, each of which is used to perform a logic operation on the enable signal and one of the plurality of control signals.

13. The display device according to claim 12, wherein: The plurality of logic gates include a plurality of OR gates.

14. The display device according to claim 5, characterized in that The driving circuit comprises: A detection circuit is used to detect whether the abnormal event occurs.

15. The display device according to claim 5, characterized in that: The display device includes an organic light emitting diode display panel.

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