Semiconductor device and method for fabricating redistribution layer with intense pulsed light irradiation

Abstract

Semiconductor devices and methods for fabricating redistribution layers with intense pulsed light irradiation. The semiconductor device has a substrate. The electrical component is disposed on the substrate. An encapsulant is deposited on the electrical component. After depositing the encapsulant, a conductive layer is formed on the substrate opposite the electrical component. A conductive layer is deposited in the matrix as a plurality of graphene-coated metal balls. The conductive layer is sintered by intense pulsed light (IPL) irradiation.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device and method for fabricating a redistribution layer using intense pulsed light irradiation. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, power conversion, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor device manufacturers are continually striving to make smaller semiconductor devices to meet the needs of electronic device manufacturers and consumers alike. As the density of components within semiconductor packages increases, printed circuit boards (PCBs) used for semiconductor packages must have smaller spacing between conductors. Smaller spacing increases the vulnerability of the PCB to insulation failure, which can cause short circuits between adjacent conductive traces. One of the main problems causing short circuits is the migration of ions from one conductive trace, which can extend through adjacent insulation layers and ultimately reach another conductive trace. Therefore, a method for manufacturing PCBs that is not susceptible to ion migration is needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-Figure 1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0005] Figure 2a-2k A process for forming a semiconductor package using a graphene-based redistribution layer sintered by intense pulsed light irradiation is illustrated;

[0006] Figure 3a and Figure 3b illustrates the use of EHD jet printing to deposit conductive material for a redistribution layer;

[0007] Figure 4 Deposition of conductive material using aerosol jet printing is illustrated; and

[0008] Figure 5a and Figure 5b The integration of a semiconductor package into an electronic device is illustrated. DETAILED DESCRIPTION

[0009] In one or more embodiments, the present invention is described in the following description with reference to the figures, in which the same number represents the same or similar elements. Although the present invention is described in accordance with the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present invention, which are defined by the appended claims and their equivalents supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. The elements assigned the same reference numerals in the figures have similar functions to each other. The term "semiconductor die" as used herein refers to both the singular and plural forms of the term, and accordingly, may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0010] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components (such as transistors and diodes) have the ability to control the flow of current. Passive electrical components (such as capacitors, inductors, and resistors) create the relationship between voltage and current necessary to perform the circuit function.

[0011] Back-end manufacturing refers to cutting or singulating the finished wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scored and cut along the non-functional areas of the wafer (called saw streets or scribe lines). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are placed on a package substrate including pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads within the semiconductor package. Electrical connections can be made with conductive layers, bumps, stud bumps, conductive glue, or wire bonding. Encapsulants or other molding materials are deposited on the semiconductor package to provide physical support and electrical isolation. The finished semiconductor package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.

[0012] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm). Alternatively, the wafer 100 can be a mold surface, an organic or inorganic substrate, or a target substrate suitable for graphene transfer.

[0013] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110 that contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed on or within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, power devices, or other signal processing circuits. The semiconductor die 104 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

[0014] Conductive layer 112 is formed on active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 operates as a contact pad that is electrically connected to the circuit on active surface 110.

[0015] The conductive bump material is deposited on the conductive layer 112 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. For optional flux solutions, the bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder and combinations thereof. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, the bump 114 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesion layer. The bump 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bump 114 represents a type of interconnect structure that can be formed on the conductive layer 112. The interconnect structure can also use bonding wires, conductive glue, stud bumps, micro bumps or other electrical interconnects.

[0016] exist Figure 1c In the embodiment, semiconductor wafer 100 is singulated into individual semiconductor die 104 through saw streets 106 using a saw blade or laser cutting tool 118. After singulation, individual semiconductor die 104 may be inspected and electrically tested for identification of known good dies (KGDs) or known good units (KGUs).

[0017] Figure 2a-2k Illustrated is a process of forming a semiconductor package using a graphene-based redistribution layer sintered by intense pulsed light (IPL) irradiation. Figure 2a A cross-sectional view of a single-layer PCB or substrate 120 including a conductive layer 122 and an insulating layer 124 is shown. Although a single substrate 120 suitable for forming two semiconductor packages separated by saw streets 121 is shown, hundreds or thousands of units are typically manufactured and processed on a single substrate before being singulated from one another using the same steps performed together as described herein. A separate substrate 120 may also be used for each unit being manufactured, with the substrate being processed separately. Figure 2a The steps shown in FIG. 1 are preceded by singulation, and multiple individual substrates are placed on a common carrier for processing.

[0018] Conductive layer 122 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer may be formed using PVD, CVD, electrolytic plating, electroless plating, or another suitable metal deposition process. Conductive layer 122 provides horizontal electrical interconnects across substrate 120. Portions of conductive layer 122 may be electrically common or electrically isolated, depending on the design and function of semiconductor die 104 and other electrical components.

[0019] The insulating layer 124 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), poly (polymethylene benzobisoxazole) (PBO) and other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 124 provides structural support and electrical isolation for the conductive layer 122.

[0020] When only a single insulating and conductive layer is used, any number of conductive layers 122 and insulating layers 124 may be interleaved with each other to form Figure 2a The initial substrate 120 in the embodiment is used. In one embodiment, a copper clad laminate substrate is used. In other embodiments, any other suitable type of package substrate or lead frame is used for the substrate 120. The insulating layer 124 can be pre-formed, wherein the conductive layer 122 is patterned on the top surface of the insulating layer. The conductive layer 122 can also be embedded in the insulating layer 124.

[0021] The semiconductor die 104 and the electrical components 130 are disposed on the substrate 120 and are electrically and mechanically connected to the conductive layer 122. For example, the electrical components 130 can be discrete electrical devices such as diodes, transistors, resistors, capacitors, and inductors. The electrical components 130 disposed on the substrate 120 can include other semiconductor dies, semiconductor packages, surface mount devices, RF components, and discrete electrical devices. Any electrical component 130 can have an integrated passive device (IPD) formed in or on the electrical component. Any number and type of electrical components can be mounted on the substrate 120.

[0022] Semiconductor die 104 and electrical component 130 are positioned on substrate 120 using a pick and place machine or operation and contact conductive layer 122. Semiconductor die 104 is provided with bumps 114 oriented toward substrate 120. Semiconductor die 104 is electrically and mechanically connected to conductive layer 122 by reflowing bumps 114. Terminals 132 of electrical component 130 are electrically and mechanically connected to conductive layer 122 using solder or conductive glue 133.

[0023] exist Figure 2bIn the present invention, an encapsulant or molding compound 140 is deposited on and around the substrate 120, the semiconductor die 104, and the electrical components 130 using solder paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant 140 can be a liquid or granular polymer composite material, such as an epoxy resin, epoxy acrylate, or another suitable polymer, with or without a suitable filler. The encapsulant 140 is non-conductive, provides structural support and environmentally protects the semiconductor device from external elements and contaminants. The top surface of the semiconductor die 104 or one or more components 130 can be exposed from the encapsulant 140 by using film-assisted molding or by back grinding after the encapsulant is deposited to allow subsequent electrical, mechanical, or thermal connections.

[0024] exist Figure 2c In the embodiment, the panel of substrate 120 and encapsulant 140 is flipped and disposed on a carrier 150, which includes a sacrificial substrate such as silicon, polymer, beryllium oxide, glass or other suitable low-cost rigid material for structural support. An interface layer or double-sided tape 152 is formed or disposed on the carrier 150 as a temporary adhesive bonding film, thermal release layer or UV release layer.

[0025] A plurality of openings or vias 154 are formed through insulating layer 124 to expose conductive layer 122. Vias 154 are formed by laser ablation, chemical etching, mechanical etching, or other suitable process. Figure 2d In the embodiment, a redistribution layer (RDL) or a conductive layer 156 is formed on the insulating layer 124 by aerosol jet printing of a graphene-based conductive ink using a dispenser 157 . Figure 4 Additional details of the dispenser 157 and the aerosol jet printing process are illustrated. The dispenser 157 is moved across the substrate 120 to print the conductive layer 156 in the desired redistribution pattern. Portions of the conductive layer 156 are formed on and into the vias 154 to provide vertical wiring between the conductive layers. The conductive layer 156 makes physical and electrical contact with the conductive layer 122 through the openings 154.

[0026] Figure 2e Detail of one of the graphene-coated metal balls 158 of the conductive layer 156 is shown. The graphene-coated metal ball 158 is formed of a core 160 and a graphene shell or coating 162 formed on and around the core. In one embodiment, the core 160 is Cu, Ag, Ni, a phase change material (PCM), or other suitable metal or similar material. In some embodiments, a mixture of some Cu cores 160 and some Ag cores 160 is used. Figure 2eThe details of the graphene shell 162 formed as a mesh network around the core 160 are shown. The graphene shell 162 is an allotrope of carbon, which has one or more layers of carbon atoms, each layer of carbon atoms arranged in a two-dimensional (2D) honeycomb lattice. The graphene shell 162 can be formed by CVD, wet chemical synthesis or other suitable means. In some embodiments, a plurality of graphene coatings 162 are formed on each core 160.

[0027] For CVD, the core 160 is placed in a chamber heated to 900-1080° C. A gas mixture of CH4 / H2 / Ar is introduced into the chamber to initiate the CVD reaction. As the CVD reaction separates the carbon atoms from the hydrogen atoms, the carbon source decomposes in the high temperature reaction chamber, leaving a graphene shell 162 on the core 160. The release of carbon atoms on the core 160 forms a continuous sheet of graphene shell 162. Additional information related to the formation of the graphene coating 162 is disclosed in U.S. Patent No. 8,535,553, U.S. Patent No. 10,421,123, Korean Patent No. KR101465616, and Korean Patent No. KR101895114, all of which are incorporated herein by reference.

[0028] Figure 2f Further details of the conductive layer 156 formed by a plurality of graphene-coated metal balls 158 are shown. In one embodiment, the conductive layer 156 includes a matrix 164 and a plurality of cores 160, the cores 160 having a graphene coating 162 embedded in the matrix. In one embodiment, the matrix 164 is a thermosetting material, such as an epoxy resin or an adhesive, wherein the binder and filler contain aluminum oxide, Al, aluminum zinc oxide or other materials with good conductive properties. The matrix 164 can be a thermally conductive paste, such as silicon or a polymer type, for example, polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET). In other embodiments, the matrix 164 can be an epoxy resin, polyester or acrylate. In another embodiment, the matrix 164 is a polymer or composite epoxy resin with dispersed graphene, carbon nanotubes, conductive polymers and the like. The conductive layer 156 can be applied as an ink of the graphene-coated metal balls 158 floating in the matrix 164.

[0029] Each core 160 embedded in the matrix 164 is surrounded or covered by a graphene coating or shell 162. In one embodiment, the graphene shell 162 is a graphene paste or ink formed around a Cu or Ag core. In one embodiment, some cores 162 are formed of Cu and other cores are formed of Ag. The graphene coating 162 of each core 160 is in contact with the graphene coating of one or more adjacent cores. The cores 160 have sufficient density within the matrix 164 that most (if not all) of the graphene coatings around the cores will contact at least one graphene coating around an adjacent core, and will typically contact the graphene coatings of multiple adjacent cores.

[0030] Each graphene-coated metal sphere 158 physically contacts adjacent graphene-coated metal spheres within the matrix 164 to create a conductive path 178 that includes portions of the graphene shell 162 interconnected on adjacent spheres 158. The conductive paths 178 are the primary current carriers of the conductive lines of the conductive layer 156. Charge flowing through many conductive paths, such as 178, among the spheres 158 operates to carry electrical signals across the substrate 120.

[0031] To ensure that conductive paths 178 are established between all adjacent balls 158, the conductive layer 156 is sintered, such as Figure 2g 15. The sintering is performed using an IPL device 180. The IPL device 180 includes a xenon flash lamp 182 that emits light 184. A reflector 186 reflects the light 184 to increase the amount of light emitted downward toward the conductive layer 156. An ultraviolet filter 188 filters the light 184. A platform 189 holds the device being processed.

[0032] IPL uses intense pulses of incoherent light emitted over a range of wavelengths. In one embodiment, the IPL wavelength extends from approximately 350 nanometers (nm) to 1200 nm. A xenon flash lamp 182 produces a high output burst of broad spectrum light 184. The light 184 hitting the matrix 164 with the balls 158 sinters the conductive layer 156 to solidify the material and electrical connections between the balls. Sintering the conductive layer 156 with IPL irradiation can be completed in only a few milliseconds, while conventional conductive layers in the prior art require a thermal heating process that typically takes between 30 minutes and 90 minutes.

[0033] In some embodiments, the panel with the conductive layer 156 is placed in an oven for pretreatment before IPL irradiation. The oven temperature is set to between 170°C and 280°C, and the conductive layer 156 is heated for between 30 seconds and two minutes. In one embodiment, the conductive layer 156 is heated at 250°C for one minute. Oven pretreatment removes organic solvents from the conductive layer 156. In some embodiments, the panel is placed in an oven for posttreatment after IPL irradiation. The oven temperature for posttreatment is between 90°C and 120°C for a time length between five minutes and ten minutes. Posttreatment in the oven stabilizes the sintered material.

[0034] Forming the conductive layer 156 by sintering performed by IPL irradiation increases the number of units per hour (UPH) that can be manufactured, thereby reducing manufacturing costs. In addition, graphene itself has a conductivity that is ten times that of copper or silver, so the conductive layer 156 has an increased current carrying capacity compared to the prior art. The graphene coating 162 increases the thermal conductivity and hardness of the conductive layer 156. The graphene coating 162 also reduces metal oxidation and ion migration, thereby increasing the mean time between failures.

[0035] The substrate 120 with the graphene-based conductive layer 156 formed as an additional wiring layer can provide sufficient wiring for the package formed in some embodiments. After the conductive layer 156 is completed, the substrate 120 and the encapsulant 140 can be singulated to separate and ship the units. Alternatively, any additional number of graphene-based conductive layers can be formed continuously on the substrate 120 to complete the desired electrical wiring.

[0036] exist Figure 2h In the embodiment, an insulating layer 190 is formed on the substrate 120 and the conductive layer 156. The insulating layer 190 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, FR-4, and other materials having similar insulating and structural properties. The insulating layer 190 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation.

[0037] exist Figure 2i , an opening is formed through insulating layer 190, and a conductive layer 192 is formed on and through insulating layer 190, as described above for conductive layer 156. As described above, conductive layer 192 is formed from graphene-coated metal balls 158 and then sintered using IPL device 180. Conductive layer 192 may be the final conductive layer formed on substrate 120, or any suitable number of additional conductive layers may be successively formed in the same manner.

[0038] Figure 2jThe package layout is shown completed by forming a final insulating layer 194 and conductive layer 196. Insulating layer 194 is formed as described above for insulating layer 190, including an IPL irradiation process. Conductive layer 196 is graphene-based and formed as described above for conductive layers 156 and 192, including sintering by IPL irradiation. Bumps 190 are formed on conductive layer 196, as described above for bumps 114 on conductive layer 112. Encapsulant 140, substrate 120, insulating layer 190, and insulating layer 194 are singulated into individual semiconductor packages 200 using a saw blade or laser cutting tool 202.

[0039] Figure 2k The completed package 200 is illustrated. The semiconductor die 104, the electrical component 130, and any other electrical components mounted on the substrate 120 are electrically connected to the bump 198 through the conductive layers 122, 156, 192, and 196. The conductive layers 156, 192, and 196 are formed by the conductive balls 158 coated with graphene. The graphene coating 162 increases the electrical and thermal conductivity, hardness, and oxidation stability. Compared with the prior art, the formation of the redistribution layer during the packaging of the semiconductor die 104 saves costs, which requires the substrate 120 to have the total required number of pre-formed conductive layers. On the other hand, the package 200 has only a pre-formed single-layer PCB or substrate 120, and then forms the remaining part of the redistribution layer during packaging. By reducing the time required for each processing step, the IPL irradiation of the conductive layer and the insulating layer increases the number of units per hour (UPH) that can be manufactured compared to the prior art. IPL irradiation sintering enables the packaged PCB to be formed as part of the packaging process, rather than in advance as a completely separate process.

[0040] Figure 3a Deposition of a conductive layer 156 on a substrate 120 using electrohydrodynamic (EHD) jet printing is shown. The package 200 or package panel is placed on a substrate 240 that is capable of three-dimensional (x-, y-, and z-directions) movement to control the distribution of the conductive material on the substrate 120. A pneumatic regulator 242 with a pressure gauge applies pressure to an injection pump 244 containing a conductive material (such as conductive ink and non-conductive ink). The tapered section 246 narrows the ink path to an injection nozzle 248 that deposits the ink onto the substrate 120 in a controlled manner. More specifically, the injection nozzle 248 performs ink ejection through an electric field and pressure between the nozzle and the substrate. In Figure 3b , pressure is applied from pneumatic regulator 242. The voltage source induces an electric field, shown as negative charges 250 and positive charges 252. The printing liquid is driven by the electric field to enable direct pattern, high resolution printing of conductive layer 156.

[0041] Figure 4Deposition of the conductive layer 156 on the insulating layer 124 using aerosol jet printing is shown. The dispenser 157 includes a channel 262 for the flow of conductive material, such as conductive and non-conductive inks, and a channel 264 for the flow of gas, such as nitrogen. The conductive material is mixed with the gas, and the ink is deposited as an aerosol jet from a nozzle or head 270 on the insulating layer 124. The printing liquid, i.e., the conductive layer 156, is dispensed at the end of the head 270 as an aerosol jet focused by the sheath gas.

[0042] Figure 5a and Figure 5b The integration of the above-described semiconductor package (eg, semiconductor package 200 ) into a larger electronic device 300 is illustrated. Figure 5a A partial cross-section of a semiconductor package 200 mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300 is illustrated. Bumps 198 are reflowed onto a conductive layer 304 of PCB 302 to physically attach and electrically connect semiconductor package 200 to the PCB. In other embodiments, thermal compression or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between semiconductor package 200 and PCB 302. Semiconductor die 104 and electrical components 130 are electrically coupled to conductive layer 304 via bumps 198 and conductive layers 196, 192, 156, and 122.

[0043] Figure 5b An electronic device 300 is illustrated having a chip carrier substrate or PCB 302 with multiple semiconductor packages, including semiconductor package 200, disposed on a surface of PCB 302. Electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0044] The electronic device 300 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 300 may be a subcomponent of a larger system. For example, the electronic device 300 may be part of a tablet, a cellular phone, a digital camera, a communication system, or other electronic device. Alternatively, the electronic device 300 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and lightweighting are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density. The PCB 302 may have a more irregular shape to facilitate fitting into a more ergonomic and smaller device housing.

[0045] exist Figure 5bIn the embodiment of the present invention, PCB 302 provides a universal substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal lines 304 are formed on or within the surface of PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition processes. Signal lines 304 provide electrical communication between each of the semiconductor packages, mounted components and other external system components. Lines 304 also provide power and ground connections to each semiconductor package.

[0046] In some embodiments, the semiconductor device has two packaging levels. The first level of packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only the first level of packaging, where the die is mechanically and electrically disposed directly on the PCB.

[0047] For illustrative purposes, several types of first level packages are shown on PCB 302, including bond wire package 346 and flip chip 348. Additionally, several types of second level packages are shown, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) or SIP module 358, quad flat leadless package (QFN) 360, quad flat package 362, and embedded wafer level ball grid array (eWLB) 364, disposed on PCB 302. In one embodiment, eWLB 364 is a fan-out wafer level package (Fo-WLP) or a fan-in wafer level package (Fi-WLP).

[0048] Depending on the system requirements, any combination of semiconductor packages configured with any combination of first-level packaging styles and second-level packaging styles and other electrical components can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can integrate pre-made components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using cheaper components and streamlined manufacturing processes. The resulting device is less likely to fail and has lower manufacturing costs, resulting in lower costs for consumers.

[0049] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate; disposing electrical components on the substrate; depositing an encapsulant on the electrical component; After depositing the encapsulant, forming a conductive layer on the substrate opposite the electrical component, wherein the conductive layer is deposited as a plurality of graphene-coated metal balls in a matrix; and The conductive layer is sintered by intense pulsed light (IPL) irradiation. 2 . The method of claim 1 , wherein the plurality of graphene-coated metal balls comprises a plurality of cores formed of copper or silver, and each of the plurality of cores comprises a graphene coating. The method of claim 1 , further comprising depositing the conductive layer by jet printing. The method according to claim 1 , further comprising forming an insulating layer on the conductive layer.

5. The method of claim 4, further comprising forming a second conductive layer on the insulating layer, wherein the second conductive layer is deposited as a second plurality of graphene-coated metal spheres in a second matrix. The method according to claim 5 , further comprising sintering the second conductive layer by IPL irradiation.

7. A method for manufacturing a semiconductor device, comprising: providing a substrate; disposing electrical components on the substrate; depositing an encapsulant on the electrical component; A conductive layer is formed on the substrate opposite the electrical component, wherein the conductive layer includes graphene.

8. The method of claim 7, further comprising sintering the conductive layer by intense pulsed light (IPL) irradiation.

9. The method of claim 7, further comprising depositing the conductive layer by jet printing.

10. A semiconductor device comprising: substrate; an electrical component disposed on a substrate; encapsulants deposited on electrical components; as well as A conductive layer is formed on the substrate opposite the electrical component, wherein the conductive layer includes a plurality of graphene-coated metal balls.

11. The semiconductor device according to claim 10, further comprising: an insulating layer formed on the conductive layer; as well as A second conductive layer is formed on the insulating layer, wherein the second conductive layer includes a second plurality of graphene-coated metal balls.

12. The semiconductor device according to claim 11, further comprising: a second insulating layer formed on the second conductive layer; as well as A third conductive layer is formed on the second insulating layer, wherein the third conductive layer includes a third plurality of graphene-coated metal balls. 13 . The semiconductor device of claim 10 , wherein each of the plurality of graphene-coated metal balls comprises a copper core. 14 . The semiconductor device of claim 10 , wherein each of the plurality of graphene-coated metal balls comprises a silver core. 15 . The semiconductor device of claim 10 , wherein a first portion of the plurality of graphene-coated metal balls comprises a copper core, and a second portion of the plurality of graphene-coated metal balls comprises a silver core.

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