Calibration Method for Semiconductor Laser Materials

Abstract

The present application discloses a method for checking semiconductor laser materials, comprising: growing a check structure, wherein the check structure comprises a substrate layer, a first lattice matching layer, an InGaAs / InAlAs superlattice, a second lattice matching layer, an InGaAs / InAlAs superlattice, and a second lattice matching layer. y Al 1‑y As layer, the third lattice matching layer and In x Ga 1‑x As layer; perform XRD characterization to obtain an XRD diffraction spectrum, and calculate the composition and growth rate of the InGaAs / InAlAs superlattice. The semiconductor laser material calibration method disclosed in the present application can calibrate the composition and growth rate of InGaAs and InAlAs materials at the same time by calibrating the growth of the structure once, thereby reducing the number of calibration growths, improving calibration efficiency, reducing calibration costs, and ensuring production quality; it can eliminate the fluctuation of growth rates between different growths, improve calibration consistency, and improve calibration accuracy.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor lasers, and in particular, to a method for verifying semiconductor laser materials. Background Art

[0002] The active region structure of a mid-wave infrared quantum cascade laser with high power and high efficiency often consists of a periodically strained-compensated In x Ga 1-x As (0.53 < x < 1) / In y Al 1-y As (0 < y < 0.52) multi-quantum well structure. In terms of structure design, InGaAs and InAlAs materials are arranged alternately, and the tensile stress and compressive stress between adjacent layers partially cancel each other out, while the total strain of a single-period InGaAs / InAlAs superlattice structure is 0 or close to 0 (generally less than 200 arcsec). However, in the actual material epitaxial growth process, if there are deviations in the composition and growth rate of the InGaAs layer and the InAlAs layer, etc., it will cause excessive local strain and relaxation, and lead to a rapid deterioration of the epitaxial growth quality of the semiconductor material. Therefore, higher requirements are put forward for the verification of the composition and growth rate of the In x Ga 1-x As (0.53 < x < 1) layer and the In y Al 1-y As (0 < y < 0.52) layer.

[0003] The currently commonly used verification method is to grow multiple superlattice verification structures containing materials such as InGaAs or InAlAs, and perform multiple growth adjustments and verifications on InGaAs and InAlAs respectively, so as to complete the verification of the composition and growth rate of InGaAs and InAlAs materials. For example, by growing different superlattice verification structures, first preliminarily determine the component control amounts of In and Ga (such as the temperatures of the In source and the Ga source), then fix the In component control amount, continue to adjust the Ga component control amount, finally determine the component control amounts of In and Ga and determine the composition and growth rate of the InGaAs material, and then verify the composition and growth rate of the InAlAs material in the same way. Such a verification method requires growing multiple different verification structures, and each verification structure can only be adjusted and verified for InGaAs or InAlAs, resulting in low efficiency and high cost. At the same time, the increase in the number of verification growths may greatly increase the influence of the fluctuations between wafers of material epitaxial growth on the verification results, thereby reducing the verification reliability. Summary of the Invention

[0004] In order to solve one or more of the above problems, the present application proposes a method for verifying semiconductor laser materials.

[0005] According to one aspect of the present application, a method for calibrating semiconductor laser materials is provided, comprising:

[0006] The verification structure includes a substrate layer, a first lattice matching layer, an InGaAs / InAlAs superlattice, a second lattice matching layer, an InGaAs / InAlAs superlattice, and a second lattice matching layer. y Al 1-y As layer, the third lattice matching layer and In x Ga 1-x As layer, wherein the components of InGaAs and InAlAs in the InGaAs / InAlAs superlattice are respectively x Ga 1-x As layer and In y Al 1-y As layer is the same;

[0007] Carry out XRD characterization and obtain XRD diffraction spectrum.

[0008] According to In x Ga 1-x As layer and In y Al 1-y The XRD diffraction peaks of the As layer determine x and y, and the In x Ga 1-x The actual lattice mismatch ε1 of the As layer and In y Al 1-y The actual lattice mismatch of the As layer is ε2;

[0009] The overall lattice mismatch ε of the InGaAs / InAlAs superlattice is obtained based on the position of the 0th order diffraction peak of the InGaAs / InAlAs superlattice. total , the period thickness t of the InGaAs / InAlAs superlattice is obtained based on the peak spacing of the superlattice diffraction peaks total ;

[0010] Calculate the InGaAs layer thickness t1 and the InAlAs layer thickness t2 in the InGaAs / InAlAs superlattice;

[0011] The growth rate r1 of InGaAs and the growth rate r2 of InAlAs in the InGaAs / InAlAs superlattice are calculated based on the actual growth time.

[0012] In some embodiments, the lattice constant of the material of the first lattice matching layer, the second lattice matching layer, and the third lattice matching layer matches the lattice constant of the material of the substrate layer.

[0013] In some embodiments, the substrate layer material is an InP substrate.

[0014] In some embodiments, the material of the first lattice matching layer, the second lattice matching layer, and the third lattice matching layer is InP or In a (Ga 1-b Al b ) 1-a As.

[0015] In some embodiments, when the materials of the first lattice matching layer, the second lattice matching layer and the third lattice matching layer are In a (Ga 1-b Al b ) 1-a When As, a=0.53, b=0, the thickness of the first lattice matching layer, the second lattice matching layer and the third lattice matching layer ranges from 1000 to 3000Å.

[0016] In some embodiments, In x Ga 1-x The value range of x in the As layer is 0.53 <x<1,In x Ga 1-x The thickness of the As layer is 100Å-300Å.

[0017] In some embodiments, In y Al 1-y The value range of y in the As layer is 0 <y<0.52,In y Al 1-y The thickness of the As layer is 100Å-300Å.

[0018] In some embodiments, the number of periods of the InGaAs / InAlAs superlattice is 30-60.

[0019] In some embodiments, the thickness t1 of the InGaAs layer and the thickness t2 of the InAlAs layer in the InGaAs / InAlAs superlattice are calculated according to the following formula:

[0020] t total =t1+t2;

[0021] t total ×ε total =t1×ε1+t2×ε2.

[0022] The semiconductor laser material calibration method disclosed in the present application can calibrate the InGaAs and InAlAs material components and growth rates of the active region of the strain-compensated quantum cascade laser by calibrating the growth of the structure once, thereby reducing the number of calibration growths, improving the calibration efficiency, and reducing the calibration cost. The method can be used to quickly confirm the stability of epitaxial growth during mass epitaxial production to ensure production quality. At the same time, the material component calibration and the growth rate calibration are completed in the same calibration growth, which can eliminate the fluctuation of the growth rate between different growths, improve the consistency of the material component and growth rate calibration, and improve the overall calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of a verification structure in a verification method for semiconductor laser materials provided in one embodiment of the present application.

[0024] Figure 2 This is an XRD simulated diffraction spectrum of a verification structure in a verification method for semiconductor laser materials provided in one embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are part of the embodiments of the present invention, rather than all of the embodiments, and are only used to explain the present invention, and are not used to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0026] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "inner", "outer", "two ends", "both sides", "bottom", "top" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred elements must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "superior", "inferior", "primary", "secondary" and the like are only used for descriptive purposes and can be simply used to more clearly distinguish different components, but cannot be understood as indicating or implying relative importance.

[0027] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium. It can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0028] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0029] Embodiment:

[0030] Refer to the attached Figure 1-2 The embodiment of the present invention provides a method for verifying a semiconductor laser material, which may specifically include the following steps:

[0031] Step 1: Grow a verification structure.

[0032] Provide a verification object, which may be a strained-compensated quantum cascade laser active region composed of a periodic In x Ga 1-x As / In y Al 1-y As multiple quantum well structure, where the value range of x is 0.53 < x < 1, and the value range of y is 0 < y < 0.52. In this embodiment, x = 0.7 and y = 0.36.

[0033] The verification structure specifically includes a substrate layer 11, a first lattice-matching layer 12, an InGaAs / InAlAs superlattice 13, a second lattice-matching layer 14, an In y Al 1-y As layer 15, a third lattice-matching layer 16, and an In x Ga 1-x As layer 17, which are arranged in sequence from bottom to top.

[0034] The substrate layer 11 is an InP substrate, and the lattice constants of the materials of the first lattice-matching layer 12, the second lattice-matching layer 14, and the third lattice-matching layer 16 match the lattice constant of the material of the substrate layer 11. The materials of the first lattice-matching layer 12, the second lattice-matching layer 14, and the third lattice-matching layer 16 can be InP or a multi-element material In a (Ga 1-b Al b ) 1-a As, and the selection is made according to the specific requirements of the verification object.

[0035] When the material of the first lattice matching layer 12, the second lattice matching layer 14 and the third lattice matching layer 16 is In a (Ga 1- b Al b ) 1-a As, a can be 0.53, and b can be 0. The thickness of the first lattice matching layer 12, the second lattice matching layer 14, and the third lattice matching layer 16 can all range from 1000 Å to 3000 Å. Thus, the first lattice matching layer 12, the second lattice matching layer 14, and the third lattice matching layer 16 are respectively InGaAs / InAlAs superlattice 13, In y Al 1-y As layer 15 and In x Ga 1-x As layer 17 provides a flat growth surface and can act as a buffer layer to effectively relieve the accumulated strain of the structure and avoid In y Al 1-y As layer 15 and In x Ga 1-x The As layer 17 has a serious relaxation phenomenon, which causes the verification accuracy to decrease.

[0036] In the verification structure, y Al 1-y As layer 15 and In x Ga 1-x The composition of the As layer 17 is determined by the calibration object. x Ga 1- x The value range of x in the As layer is 0.53 <x<1,In x Ga 1-x The thickness of the As layer can range from 100Å to 300Å. y Al 1-y The value range of y in the As layer is 0 <y<0.52,In y Al 1-y The thickness of the As layer is 100Å-300Å.

[0037] In the verification structure, the compositions of InGaAs and InAlAs in the InGaAs / InAlAs superlattice 13 are respectively x Ga 1- x As layer 17 and In y Al 1-y The As layer 15 is the same.

[0038] The thickness of the InGaAs layer in the InGaAs / InAlAs superlattice 13 is denoted as t InGaAs, the thickness of the InAlAs layer in the InGaAs / InAlAs superlattice 13 is denoted as t InAlAs , then t InGaAs and t InAlAs The conditions that need to be met are:

[0039] t InGaAs ×ε InGaAs +t InAlAs ×ε InAlAs =0;

[0040] Among them, ε InGaAs represents the lattice mismatch of InGaAs in the InGaAs / InAlAs superlattice 13, ε InAlAs represents the lattice mismatch of InAlAs in the InGaAs / InAlAs superlattice 13. When t InGaAs ×ε InGaAs +t InAlAs ×ε InAlAs When the condition is equal to 0, the 0th order diffraction peak of the InGaAs / InAlAs superlattice 13 in the XRD diffraction spectrum completely coincides with the diffraction peak of the substrate layer 11.

[0041] In an alternative embodiment, t InGaAs and t InAlAs Satisfy t InGaAs ×ε InGaAs +t InAlAs ×ε InAlAs The condition that ρ is approximately equal to 0, at this time, the 0th order diffraction peak of the InGaAs / InAlAs superlattice 13 in the XRD diffraction spectrum partially overlaps with the diffraction peak of the substrate layer 11.

[0042] By InGaAs ×ε InGaAs +t InAlAs ×ε InAlAs =0 to get t InGaAs and t InAlAs The proportional relationship is as follows:

[0043] t InGaAs / t InAlAs =-ε InAlAs / ε InGaAs .

[0044] According to the above InGaAs and t InAlAs The ratio of t is adjusted synchronously according to the ratio InGaAs and t InAlAs until the XRD diffraction peak of InGaAs / InAlAs superlattice 13 in the XRD diffraction spectrum coincides with that of In y Al 1-y The XRD diffraction peaks of As layer 15 and Inx Ga 1- x The XRD diffraction peaks of the As layer 17 do not interfere with each other. InGaAs and t InAlAs The values ​​are respectively the InGaAs layer thickness and the InAlAs layer thickness in the InGaAs / InAlAs superlattice 13 when growing the verification structure.

[0045] The number of periods of the InGaAs / InAlAs superlattice 13 can be set to 30-60.

[0046] Therefore, by determining the InGaAs layer thickness and the InAlAs layer thickness in the InGaAs / InAlAs superlattice 13 through the above method, the peak position of each XRD diffraction peak in the XRD diffraction spectrum can be clearly determined, and the verification cost can be reduced and the verification efficiency can be improved.

[0047] Step 2: Perform XRD characterization to obtain the XRD diffraction spectrum.

[0048] Reference Manual Attached Figure 2 , shows the XRD simulated diffraction spectrum obtained by XRD characterization of the verification structure, where the horizontal axis represents the diffraction angle and the vertical axis represents the diffraction intensity. In the figure, InGaAs represents In x Ga 1-x XRD diffraction peaks of the As layer 17, InAlAs represents In y Al 1-y As layer 15 represents the XRD diffraction peak, InP represents the XRD diffraction peak of the substrate layer 11. In the present embodiment, the XRD diffraction peak of the substrate layer 11 completely coincides with the 0th order diffraction peak of the InGaAs / InAlAs superlattice 13. -1 represents the position of the -1st order diffraction peak of the InGaAs / InAlAs superlattice 13, +1 represents the position of the +1st order diffraction peak of the InGaAs / InAlAs superlattice 13, -2 represents the position of the -2nd order diffraction peak of the InGaAs / InAlAs superlattice 13, and +2 represents the position of the +2nd order diffraction peak of the InGaAs / InAlAs superlattice 13.

[0049] Step 3: According to In x Ga 1-x As layer 17 and In y Al 1-y The XRD diffraction peaks of the As layer 15 determine the actual x and y, and the In x Ga 1-x The actual lattice mismatch ε1 of the As layer and In y Al 1-y The actual lattice mismatch of the As layer is ε2.

[0050] Specifically, according to Inx Ga 1-x As layer 17 and In y Al 1-y The XRD diffraction peak of As layer 15 confirms the presence of In in the structure. x Ga 1-x As layer 17 and In y Al 1-y x and y in the As layer 15, thereby obtaining In x Ga 1-x As layer 17 and In y Al 1-y The actual composition and actual lattice mismatch of the As layer 15.

[0051] Among them, x Ga 1-x The In composition x and In in the As layer 17 x Ga 1-x At least one of the actual lattice mismatch degrees ε1 of the As layer 17 can be obtained by fitting with XRD analysis software, such as HighScore XRD analysis software. The relationship between x and ε1 is:

[0052]

[0053]

[0054] In the formula, represents the lattice constant of GaAs, represents the lattice constant of InAs, represents the lattice constant of InP, represents the lattice constant of InGaAs.

[0055] Similarly, y Al 1-y The In composition y and In in the As layer 15 y Al 1-y At least one of the actual lattice mismatch degrees ε2 of the As layer 15 can be obtained by fitting with the XRD analysis software, and the relationship between y and ε2 is:

[0056]

[0057]

[0058] In the formula, represents the lattice constant of AlAs, represents the lattice constant of InAs, represents the lattice constant of InP, represents the lattice constant of InAlAs.

[0059] Step 4: Obtain the actual overall lattice mismatch ε of the InGaAs / InAlAs superlattice 13 according to the 0th order diffraction peak position of the InGaAs / InAlAs superlattice 13 total The actual period thickness t of the InGaAs / InAlAs superlattice is obtained according to the interval between the -1st and +1st diffraction peaks or the -2nd and +2nd diffraction peaks. total .

[0060] The actual overall lattice mismatch ε of the InGaAs / InAlAs superlattice 13 total and the actual period thickness t total It can also be directly obtained through XRD analysis software.

[0061] Step 5: Calculate the actual layer thickness t1 of InGaAs and the actual layer thickness t2 of InAlAs in the InGaAs / InAlAs superlattice.

[0062] The calculation formulas for t1 and t2 are as follows:

[0063] t total =t1+t2;

[0064] t total ×ε total =t1×ε1+t2×ε2.

[0065] Among them, ε1, ε2, t total and ε total These are the actual data of the verification structure obtained from the XRD diffraction spectrum, and the final t1 and t2 obtained are also the actual layer thicknesses.

[0066] Step 6: Calculate the growth rate r1 of InGaAs and the growth rate r2 of InAlAs in the InGaAs / InAlAs superlattice based on the actual growth time.

[0067] The growth rate is obtained by dividing the actual layer thickness obtained in step 5 by the actual growth time.

[0068] In an optional embodiment, the verification structure includes a substrate layer 11, a first lattice matching layer 12, an InGaAs / InAlAs superlattice 13, a second lattice matching layer 14, an InGaAs / InAlAs superlattice 15, and a second lattice matching layer 16. y Al 1-y As layer 15, third lattice matching layer 16 and In x Ga 1-x As layer 17, the substrate layer 11 is an InP substrate, and the material of the first lattice matching layer 12 is In 0.53 Ga 0.47As, layer thickness is 1000Å, InGaAs / InAlAs superlattice 13 is In 0.7 Ga 0.3 As / In 0.36 Al 0.64 As superlattice, InGaAs / InAlAs superlattice 13 has a period of 40, and each layer of In 0.7 Ga 0.3 The thickness of the As layer is 20 Å, and each In layer 0.36 Al 0.64 The thickness of the As layer is 21 Å, and the XRD diffraction peaks of the InGaAs / InAlAs superlattice are 13 levels and the In y Al 1-y As layer 15 and In x Ga 1-x The XRD diffraction peaks of the As layer 17 do not interfere with each other, and the material of the second lattice matching layer 14 is In 0.53 Ga 0.47 As, layer thickness 2000Å, In y Al 1-y As layer 15 material is In 0.36 Al 0.64 As, layer thickness is 200Å, and the third lattice matching layer 16 material is In 0.53 Ga 0.47 As, layer thickness 2000Å, In x Ga 1-x The material of the As layer 17 is In 0.7 Ga 0.3 As, the layer thickness is 200Å, and the XRD diffraction pattern obtained by XRD simulation of the verification structure is shown in the attached manual. Figure 2 As shown, the 0th order diffraction peak of the InGaAs / InAlAs superlattice 13 completely coincides with the diffraction peak of the substrate layer 1 .

[0069] In an optional embodiment, a single verification structure growth and XRD characterization can completely obtain the material composition and growth rate of InGaAs and InAlAs. In different verification structure growths, the In component control amount (In source furnace temperature) in InGaAs and InAlAs can be fixed according to actual production needs, and the Ga and Al component control amounts (Ga and Al source furnace temperatures) can be adjusted to verify the material composition and growth rate until the laser structure design requirements are met. After the source furnace temperatures of all components in InGaAs and InAlAs are determined, the strain-compensated quantum cascade laser can be grown according to the laser structure design.

[0070] The semiconductor laser material calibration method disclosed in the present application can simultaneously realize the calibration of the InGaAs and InAlAs material components and growth rates of the strain-compensated quantum cascade laser active region through the growth of a calibration structure once, thereby reducing the number of calibration growths, improving the calibration efficiency, and reducing the calibration cost; due to the fast calibration speed, it can be applied to the calibration before normal epitaxial growth of quantum cascade laser structures, and can also be applied to the rapid confirmation and rapid adjustment of the stability of epitaxial growth during large-scale epitaxial production to ensure production quality; the material component calibration and the growth rate calibration are completed in the same calibration growth, which can eliminate the fluctuation of the growth rate between different growths, improve the consistency of the material component and growth rate calibration, and improve the overall calibration accuracy.

[0071] The above is only an optional implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for calibrating semiconductor laser materials, characterized in that: include: The verification structure includes a substrate layer, a first lattice matching layer, an InGaAs / InAlAs superlattice, a second lattice matching layer, an InGaAs / InAlAs superlattice, and a second lattice matching layer. y Al 1-y As layer, the third lattice matching layer and In x Ga 1-x As layer, wherein the components of InGaAs and InAlAs in the InGaAs / InAlAs superlattice are respectively x Ga 1-x As layer and In y Al 1-y As layer is the same; Carry out XRD characterization and obtain XRD diffraction spectrum. According to In x Ga 1-x As layer and In y Al 1-y The XRD diffraction peaks of the As layer determine the actual x and y, and the In x Ga 1-x The actual lattice mismatch ε1 of the As layer and In y Al 1-y The actual lattice mismatch of the As layer is ε2; The overall lattice mismatch ε of the InGaAs / InAlAs superlattice is obtained based on the position of the 0th order diffraction peak of the InGaAs / InAlAs superlattice. total , the period thickness t of the InGaAs / InAlAs superlattice is obtained based on the peak spacing of the superlattice diffraction peaks total ; Calculate the InGaAs layer thickness t1 and the InAlAs layer thickness t2 in the InGaAs / InAlAs superlattice; The growth rate r1 of InGaAs and the growth rate r2 of InAlAs in the InGaAs / InAlAs superlattice are calculated based on the actual growth time.

2. The semiconductor laser material calibration method according to claim 1, characterized in that: The lattice constant of the material of the first lattice matching layer, the second lattice matching layer, and the third lattice matching layer matches the lattice constant of the material of the substrate layer.

3. The semiconductor laser material calibration method according to claim 1, characterized in that: The material of the substrate layer is InP substrate.

4. The semiconductor laser material calibration method according to claim 3, characterized in that: The materials of the first lattice matching layer, the second lattice matching layer and the third lattice matching layer are InP or In a (Ga 1-b Al b ) 1-a As.

5. The semiconductor laser material calibration method according to claim 4, characterized in that: When the material of the first lattice matching layer, the second lattice matching layer and the third lattice matching layer is In a (Ga 1-b Al b ) 1-a When As, a=0.53, b=0, the thickness of the first lattice matching layer, the second lattice matching layer and the third lattice matching layer ranges from 1000 to 3000 Å.

6. The semiconductor laser material calibration method according to claim 1, characterized in that: In x Ga 1-x The value range of x in the As layer is 0.53 <x<1,In x Ga 1-x The thickness of the As layer is 100Å-300Å.

7. The semiconductor laser material calibration method according to claim 1, characterized in that: In y Al 1-y The value range of y in the As layer is 0 <y<0.52,In y Al 1-y The thickness of the As layer is 100Å-300Å.

8. The semiconductor laser material calibration method according to claim 1, characterized in that: The period number of the InGaAs / InAlAs superlattice is 30-60.

9. The semiconductor laser material calibration method according to claim 1, characterized in that: The layer thickness t1 of InGaAs and the layer thickness t2 of InAlAs in the InGaAs / InAlAs superlattice are calculated according to the following formula: t total =t1+t2; t total ×ε total =t1×ε1+t2×ε2。

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