Power supply controller and switching power supply

Abstract

The invention provides a power supply controller and a switching power supply. A power supply controller (10) provided in a switching power supply (1) configured to generate an output voltage (VOUT) from an input voltage (VIN) includes: a synchronous input terminal (SIN); a synchronous output terminal (SOUT); an output stage (MM) configured to convert an input voltage power into an output voltage; a switching control circuit (20) configured so as to convert input voltage power into output voltage by performing switching control of the output stage in synchronization with a reference clock signal (CLKREF); a synchronous output circuit (40) configured so as to set the state of the synchronous output terminal to any one of a plurality of output states including a first output state, a second output state, and a third output state; and a synchronous input circuit (50) configured so as to set the state of the synchronous input terminal to any one of a plurality of input states including a first input state and a second input state.

Description

Technical Field

[0001] The invention relates to a power supply controller and a switching power supply. Background Art

[0002] A method of configuring a multi-phase DC / DC converter by synchronizing DC / DC converters of a plurality of channels is known in the related art (for example, see Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-6829 Summary of the invention

[0006] A method for configuring a switching power supply by providing a plurality of power supply controllers each configured to be responsible for switch control and synchronizing the plurality of power supply controllers is provided. In this case, if information other than information for synchronization can be transmitted between the plurality of power supply controllers without adding a dedicated terminal, the application range for various controls is widened.

[0007] A power controller according to an embodiment of the present invention is a power controller provided in a switching power supply, the switching power supply being configured to generate an output voltage from an input voltage, the power controller comprising: a synchronous input terminal; a synchronous output terminal; an output stage configured to convert the input voltage power into an output voltage; a switch control circuit configured to convert the input voltage power into an output voltage by performing switch control of the output stage in synchronization with a reference clock signal; a synchronous output circuit configured to set the state of the synchronous output terminal to any one of a plurality of output states including a first output state, a second output state and a third output state; and a synchronous input circuit, the synchronous input The circuit is configured to set the state of a synchronization input terminal to any one of a plurality of input states including a first input state and a second input state, wherein the synchronization output circuit outputs a signal of a first level from the synchronization output terminal in the first output state, and outputs a signal of a second level higher than the first level from the synchronization output terminal in the second output state, and the output impedance of the synchronization output circuit is set to be higher in the third output state than in the first output state and the second output state, and wherein the synchronization input circuit is capable of pulling down the synchronization input terminal to the first level or pulling up the synchronization input terminal to the second level via a resistor, pulling down the synchronization input terminal in the first input state, and pulling up the synchronization input terminal in the second input state. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention.

[0009] Figure 1 is a general configuration diagram of a switching power supply according to an embodiment of the present invention.

[0010] Figure 2 is an external perspective view of a power controller according to an embodiment of the present invention.

[0011] Figure 3 is an overall configuration diagram of a switching power supply device according to an embodiment of the present invention.

[0012] Figure 4 is an internal configuration diagram of a power supply controller according to an embodiment of the present invention.

[0013] Figure 5 FIG. 4 is an internal configuration diagram of a power supply controller in a first switching state according to an embodiment of the present invention.

[0014] Figure 6 is an internal configuration diagram of a power supply controller in a second switching state according to an embodiment of the present invention.

[0015] Figure 7 is a timing diagram of a power controller according to an embodiment of the present invention.

[0016] Figure 8 is a diagram showing an example of an internal configuration of a synchronous output circuit according to an embodiment of the present invention.

[0017] Fig. 9 is a diagram showing an example of an internal configuration of a synchronous input circuit according to an embodiment of the present invention.

[0018] Fig.10 is an internal configuration diagram of a power supply controller according to an embodiment of the present invention.

[0019] Fig.11 It is a diagram for explaining a method of transmitting information from a subsequent-stage power supply controller to a preceding-stage power supply controller according to a first example pertaining to an embodiment of the present invention.

[0020] Fig.12 1 is a conceptual waveform diagram of a clock signal output from a front-stage power supply controller to a rear-stage power supply controller according to a first example of an embodiment of the present invention.

[0021] Fig.13 1 is a waveform diagram of a clock signal and a level detection signal when a synchronous input circuit is in a pull-down state in a subsequent-stage power supply controller according to a first example of an embodiment of the present invention.

[0022] Fig.141 is a waveform diagram of a clock signal and a level detection signal when a synchronous input circuit is in a pull-up state in a subsequent-stage power supply controller according to a first example of an embodiment of the present invention.

[0023] Fig.15 is a diagram showing how three clock signals propagate among a plurality of power supply controllers according to a first example pertaining to an embodiment of the present invention.

[0024] Fig.16 is a diagram showing how two clock signals propagate among a plurality of power supply controllers according to a first example pertaining to an embodiment of the present invention.

[0025] Fig.17 is an operation flow chart of a power supply controller operating in a first mode according to a first example pertaining to an embodiment of the present invention.

[0026] Fig.18 is an operation flow chart of the power supply controller operating in the second mode according to the first example pertaining to the embodiment of the present invention.

[0027] Fig.19 1 is a waveform diagram of four clock signals for synchronizing switching operations in four power supply controllers according to a first example of an embodiment of the present invention.

[0028] Fig. 20 is an internal configuration diagram of a synchronous output circuit according to a first example pertaining to an embodiment of the present invention.

[0029] Fig.21 1 is a conceptual waveform diagram of a clock signal output from a front-stage power supply controller to a rear-stage power supply controller according to a second example pertaining to an embodiment of the present invention.

[0030] Fig. 22 1 is a waveform diagram of a clock signal and a level detection signal when a synchronous input circuit is in a pull-down state in a subsequent-stage power supply controller according to a second example of an embodiment of the present invention.

[0031] Fig.23 1 is a waveform diagram of a clock signal and a level detection signal when a synchronous input circuit is in a pull-up state in a subsequent-stage power supply controller according to a second example of an embodiment of the present invention.

[0032] Fig.24 is an operation flow chart of a power supply controller operating in a first mode according to a second example pertaining to an embodiment of the present invention.

[0033] Fig.25 is an operation flow chart of a power supply controller operating in a second mode according to a second example pertaining to an embodiment of the present invention.

[0034] Fig.26 is an internal configuration diagram of a synchronous output circuit according to a second example pertaining to an embodiment of the present invention.

[0035] Fig. 27 1 is a waveform diagram of a clock signal that can be output from a front-stage power supply controller to a rear-stage power supply controller according to a fifth example pertaining to an embodiment of the present invention.

[0036] Fig.28 is a waveform diagram of four clock signals for synchronizing switches in four power supply controllers according to a fifth example pertaining to an embodiment of the present invention.

[0037] Fig.29 1 is a waveform diagram of a clock signal that can be output from a front-stage power supply controller to a rear-stage power supply controller according to a sixth example of an embodiment of the present invention. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a comprehensive understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other cases, well-known methods, processes, systems, and components are not described in detail to avoid unnecessary confusion of aspects of the various embodiments.

[0039] An example of an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In all the reference drawings, the same parts are represented by the same reference numerals, and in principle, their repeated description will be omitted. In the present invention, in order to simplify the description, by describing a symbol or code referring to information, a signal, a physical quantity, a functional part, a circuit, an element, a component, etc., the name of the information, signal, physical quantity, functional part, circuit, element, component, etc. corresponding to the symbol or code may be omitted or abbreviated. For example, by "S_IN" (see "S_IN" to be described later) Figure 1 ) may be described as a synchronous input terminal S_IN, and may also be abbreviated as terminal S_IN, but they refer to the same terminal.

[0040] First, some terms used in the description of the embodiments of the present invention will be explained. "Ground" refers to a reference conductive portion whose reference potential is 0V (zero volts), or refers to the 0V potential itself. The reference conductive portion can be formed by a conductor such as a metal. The 0V potential can be referred to as the ground potential. In the embodiments of the present invention, the voltage shown without providing a specific reference represents the potential from the ground.

[0041] Level refers to the level of electric potential. For any signal or voltage of concern, the high level has a higher electric potential than the low level. For any signal of concern, when the signal is at the high level, the inversion of the signal takes the low level, and when the signal is at the low level, the inversion of the signal takes the high level. In any signal or voltage of concern, the transition from the low level to the high level is called the rising edge, and the transition from the high level to the low level is called the falling edge.

[0042] For any transistor (including MOSFET) configured as an FET (field effect transistor), the on state refers to the state in which the drain and source of the transistor are electrically connected to each other, and the off state refers to the state in which the drain and source of the transistor are electrically disconnected from each other (cut-off state). This also applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is considered an enhancement-mode MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". In addition, unless otherwise specified, the back gate of any MOSFET can be considered short-circuited to the source.

[0043] Hereinafter, for any transistor, the on state and the off state can be simply expressed as on and off, respectively. For any transistor, the transition from the off state to the on state is expressed as turn-on, and the transition from the on state to the off state is expressed as turn-off. For any transistor, the period during which the transistor is in the on state is called the on period, and the period during which the transistor is in the off state is called the off period.

[0044] For any signal having a signal level that takes a high level or a low level, the period during which the signal level is at the high level is called the high-level period, and the period during which the signal level is at the low level is called the low-level period. This also applies to any voltage having a voltage level that takes a high level or a low level.

[0045] The connection between multiple parts of a circuit forming, such as any circuit element, wiring, and node, can be understood to refer to an electrical connection unless otherwise specified.

[0046] In the case where any two voltages to be compared are voltage v1 and v2, "v1>v2" indicates that voltage v1 is higher than voltage v2, and "v1<v2" indicates that voltage v1 is lower than voltage v2. This also applies to other expressions including physical quantities other than voltage.

[0047] Figure 1 The overall configuration of the switching power supply 1 according to an embodiment of the present invention is shown. The switching power supply 1 is supplied with a positive input voltage V from a voltage source (not shown), and by making the input voltage V IN and byIN Step down to generate positive output voltage V OUT Therefore, the output voltage V OUT Lower than the input voltage V IN The switching power supply 1 will output voltage V OUT Stabilize at the predetermined target voltage. That is, in the stable state, the output voltage V OUT Basically the same as the target voltage. In the following, the target voltage is represented by the symbol “V TG ” indicates that the switching power supply 1 includes n power supply controllers 10. Here, n represents any integer greater than 2.

[0048] Figure 2 1 is an external stereoscopic view of a power controller 10. The power controller 10 is an electronic component, which includes: a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) configured to accommodate the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the power controller 10. The power controller 10 is formed by enclosing the semiconductor chip in a housing (package) made of resin. Figure 2 The number of external terminals of the power supply controller 10 shown and the type of the housing of the power supply controller 10 are merely examples and can be arbitrarily designed. The plurality of external terminals provided at the power supply controller 10 include an input terminal IN, a switch terminal SW, a ground terminal GND, a feedback terminal FB, an error output terminal EOUT, a synchronization input terminal S_IN, and a synchronization output terminal S_OUT. External terminals other than these may also be provided at the power supply controller 10. In addition, the synchronization input terminal may be read differently as a synchronization clock input terminal, and the synchronization output terminal may be read differently as a synchronization clock output terminal.

[0049] In addition to the n power supply controllers 10, the switching power supply 1 also includes n coils L, output capacitors C OUT and feedback resistors R1 and R2. The n coils L are associated one-to-one with the n power controllers 10. That is, one coil L is associated with one power controller 10. The first end of the coil L associated with a specific power controller 10 is connected to the switch terminal SW of the specific power controller 10. The second ends of all coils L are commonly connected to the output node ND OUT In each coil L, the current flowing through the coil L is referred to as the coil current IL. In principle, the coil current IL flows from the switch terminal SW to the output node ND OUT (Only this principle is considered below).

[0050] At the output node ND OUT Insert an output capacitor C between OUT That is, the output capacitor C OUT The first end is connected to the output node NDOUT , output capacitor C OUT The second end of the output node ND is grounded. OUT The voltage at is the output voltage V OUT The load LD is connected to the output node ND OUT The load LD is based on the output voltage V OUT Any load being driven. From the output node ND OUT The current supplied to the load LD is called the load current I LD .

[0051] The first end of the feedback resistor R1 is connected to the output node ND OUT The second end of the feedback resistor R1 is connected to the first end of the feedback resistor R2, and the second end of the feedback resistor R2 is grounded. A voltage V OUT The corresponding feedback voltage V FB . Feedback voltage V FB is the output voltage V OUT The voltage is divided by the output voltage V OUT The feedback resistors R1 and R2 form a structure to generate a feedback voltage V FB The feedback voltage generating circuit of the n power supply controllers 10. The feedback terminal FB of one power supply controller 10 among the n power supply controllers 10 is connected to the connection node between the feedback resistors R1 and R2, and receives the feedback voltage V FB A sufficiently high voltage (for example, input voltage V IN The output voltage V OUT Itself can be used as feedback voltage V FB In any case, the feedback voltage V FB According to the output voltage V OUT voltage.

[0052] Input voltage V IN is supplied to the input terminal IN of each power controller 10. The ground terminal GND of each power controller 10 is grounded. The n error output terminals EOUT of the n power controllers 10 are connected to each other. The n power controllers 10 may be referred to as the first power controller 10 to the nth power controller 10. Among them, the feedback voltage V FBis input to the feedback terminal FB of the first power controller 10. The synchronization output terminal S_OUT of the i-th power controller 10 and the synchronization input terminal S_IN of the (i+1)-th power controller are connected to each other via the wiring connecting them. Here, i represents an arbitrary integer. However, since the total number of power controllers 10 is n, the "i" in the (i+1)-th power controller 10 represents any natural number below (n-1).

[0053] A power supply controller 10 and a set of coils L and output capacitors C OUT The output capacitor C is a single-channel DC / DC converter configured to perform current mode control. Therefore, in the switching power supply 1, an n-channel DC / DC converter is formed. OUT Shared by the n-channel DC / DC converter. In the switching power supply 1, the feedback voltage V FB The corresponding signal (error signal described later) is shared by the power supply controllers 10 of all channels, and multi-phase control can be performed by shifting the phase of switching control between the multiple channels.

[0054] In the following, when it is necessary to distinguish n power supply controllers 10 from each other, as shown in FIG. Figure 3 As shown, the n power controllers 10 are referred to as power controllers 10[1] to 10[n]. In addition, the coils L associated with the power controllers 10[1] to 10[n] are referred to as coils L[1] to L[n], respectively. That is, for each integer i satisfying "1≤i≤n", the switch terminal SW of the power controller 10[i] is connected to the first end of the coil L[i], and the second end of the coil L[i] is connected to the output node ND OUT The coil current IL flowing through the coil L[i] is specifically referred to as the coil current IL[i]. The power controllers 10[1] to 10[n] correspond to the first to nth power controllers described above, respectively. Therefore, only the feedback terminal FB of the power controller 10[1] is connected to the connection node between the feedback resistors R1 and R2 to receive the feedback voltage V FB , and a sufficiently high voltage (for example, input voltage V IN A power supply voltage VDD (or a power supply voltage VDD described later) is applied to each feedback terminal FB of the power supply controllers 10[2] to 10[n].

[0055] In addition, the synchronization input terminal S_IN and the synchronization output terminal S_OUT in the power supply controller 10[i] can be specifically referred to as the synchronization input terminal S_IN[i] and the synchronization output terminal S_OUT[i], respectively. The clock signal can be input from the outside to the synchronization input terminal S_IN[1], or it can not be input from the outside to the synchronization input terminal S_IN[1]. For each integer i that satisfies "1≤i≤(n-1)", the synchronization output terminal S_OUT[i] and the synchronization input terminal S_IN[i+1] are connected to each other via wiring provided between the power supply controllers 10[i] and 10[i+1]. Therefore, for example, the terminals S_OUT[1] and S_IN[2] are connected to each other, the terminals S_OUT[2] and S_IN[3] are connected to each other, and the terminals S_OUT[3] and S_IN[4] are connected to each other.

[0056] Figure 4 The internal configuration of one power supply controller 10 is shown. The internal configurations of the power supply controllers 10[1] to 10[n] are the same. Therefore, the internal configuration of the power supply controller 10 will be described by focusing on one power supply controller 10. The power supply controller 10 includes an output stage MM and a switch control circuit 20 for controlling the switching action of the output stage MM, and also includes a mode setting circuit 30, a synchronous output circuit 40, a synchronous input circuit 50, a level detection circuit 60, a pattern determination circuit 70, and a clock management circuit 80. Although not specifically shown, any circuit in the power supply controller 10 can output any signal or information to any other circuit. The synchronous output circuit can be read differently as a synchronous clock output circuit, and the synchronous input circuit can be read differently as a synchronous clock input circuit. In the following, in order to simplify the description, the power supply controllers 10 and 10[i] will be abbreviated as devices 10 and 10[i] in many cases.

[0057] The output stage MM includes transistors MH and ML configured as N-channel MOSFETs. The transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, the ground), and the input voltage V is controlled by controlling the switching action of these transistors. IN is switched and a rectangular waveform switching voltage appears at the switch terminal SW. The transistor MH is set at a higher potential side than the transistor ML. Specifically, the drain of the transistor MH is connected to the input voltage V IN The input terminal IN is applied to the input terminal, and the input voltage V IN The source of the transistor MH and the drain of the transistor ML are commonly connected to the switch terminal SW. The source of the transistor ML is connected to the ground terminal GND (and thus grounded). However, a current detection resistor may be inserted between the source of the transistor ML and the ground terminal GND.

[0058] The transistor MH is used as an output element (output transistor), and the transistor ML is used as a rectifying element (synchronous rectifying transistor). In the switch control of the output stage MM, the output element (MH) and the rectifying element (ML) are alternately turned on and off. The coil L and the output capacitor C connected to the switch terminal SW OUT A rectifying / smoothing circuit is configured to rectify and smooth the rectangular waveform switching voltage appearing at the switch terminal SW.

[0059] The gates of transistors MH and ML are respectively supplied with gate signals GH and GL as driving signals, and transistors MH and ML are turned on and off according to the gate signals GH and GL. When the gate signal GH is at a high level, transistor MH is turned on, and when the gate signal GH is at a low level, transistor MH is turned off. Similarly, when the gate signal GL is at a high level, transistor ML is turned on, and when the gate signal GL is at a low level, transistor ML is turned off. Basically, transistors MH and ML are turned on and off alternately, but transistors MH and ML can also be kept in an off state. Transistors MH and ML are not turned on at the same time. At least one selected from the group of output element (MH) and rectifying element (ML) can be set outside the device 10. The entire output stage MM can be set outside the device 10.

[0060] During the on period of transistor MH, coil current IL flows through the channel (between drain and source) of transistor MH. During the off period of transistor MH, coil current IL flows through the channel of transistor ML or the parasitic diode of transistor ML.

[0061] By controlling the switching action of the output stage MM, the input voltage V IN The power is converted into an output voltage V OUT The switch control circuit 20 is responsible for the switch control of the output stage MM, and controls the switch action of the output stage MM to adjust the input voltage V IN Converted to output voltage V OUT In the switch control, the switch control circuit controls the on / off state of the transistors MH and ML by controlling the level of the gate signals GH and GL, thereby generating a voltage at the output node ND. OUT The required output voltage V OUT When two or more switch control circuits 20 in two or more devices 10 perform switch control simultaneously, the input voltage V IN Converted to output voltage V OUT .

[0062] Although not particularly shown, the device 10 is provided with an internal power supply circuit configured to generate a power supply based on the input voltage VIN Generates various internal supply voltages. Based on the input voltage V IN or an internal power supply voltage to drive each circuit in the device 10. The power supply voltage VDD is generated as an internal power supply voltage. The power supply voltage VDD has a predetermined positive DC voltage value. In addition, the gate signal GL is a signal based on the ground potential, and the gate signal GH is a signal based on the potential of the switch terminal SW. The gate signal GH at a low level has the potential of the switch terminal SW, and the gate signal GH at a high level is higher than the potential of the switch terminal SW by a predetermined voltage. In this case, the predetermined voltage is greater than the gate threshold voltage of the transistor MH. A boost power supply configured to generate the gate signal GH can be generated by using a well-known bootstrap circuit (not shown). The transistor MH can be configured by a P-channel MOSFET, in which case a boost power supply is not required.

[0063] As a variation, the device 10 may adopt a diode rectification method. In this case, instead of the transistor ML, a synchronous rectification diode having an anode connected to the ground terminal GND and a cathode connected to the switch terminal SW is used as a rectification element. In this case, only the output element (MH) is turned on / off in the switch control of the output stage MM. In any case, the output voltage V is generated based on the current (IL) flowing through the coil L by switching the output element (MH) between on and off in the switch control of the output stage MM. OUT .

[0064] Before describing the operation of the switch control circuit 20, the mode setting circuit 30 provided in the device 10 will be described.

[0065] The mode setting circuit 30 sets the operation mode of the device 10 to the first mode or the second mode. The operation mode of the device 10 (hereinafter referred to as the operation mode) can be understood as the operation mode of the components (circuits 20, 40, 50, 60, 70 and 80) of the device 10 except the mode setting circuit 30.

[0066] In the switching power supply 1, only the operation mode of the device 10[1] is set to the first mode, and the operation modes of the devices 10[2] to 10[n] are all set to the second mode. The mode setting circuit 30 of the device 10[i] sets the operation mode of the device 10[i] based on the mode setting information provided to the device 10[i].

[0067] Here, the voltage of the feedback terminal FB is used as mode setting information. In the switching power supply 1, only the feedback voltage V is supplied to the feedback terminal FB of the device 10 [1]. FB In the specifications of the switching power supply 1, the feedback voltage V FBThe voltage value has a specified range. The specified range is from 0V to a predetermined voltage V FBH When the voltage of the feedback terminal FB of the device 10[i] is lower than or equal to the predetermined threshold voltage V THMODE , the mode setting circuit 30 of the device 10[i] sets the operation mode of the device 10[i] to the first mode, and when the voltage of the feedback terminal FB of the device 10[i] is higher than the predetermined threshold voltage V THMODE , the mode setting circuit 30 of the device 10[i] sets the operation mode of the device 10[i] to the second mode. In this case, “V THMODE >V FBH ” was established.

[0068] Since the feedback voltage V FB is supplied to the feedback terminal FB of the device 10[1], so the voltage of the feedback terminal FB of the device 10[1] is lower than or equal to the threshold voltage V THMODE Therefore, the mode setting circuit 30 of the device 10[1] sets the operation mode of the device 10[1] to the first mode. On the other hand, in the switching power supply 1, the voltage exceeding the threshold voltage V THMODE The voltage (for example, the input voltage V IN or power supply voltage VDD) is applied to each feedback terminal FB of the devices 10[2] to 10[n]. Therefore, the mode setting circuit 30 of the devices 10[2] to 10[n] respectively sets the operation mode of the devices 10[2] to 10[n] to the second mode.

[0069] Each device 10 may be provided with a dedicated external terminal (not shown) configured to set the operation mode. In this case, the input voltage to the dedicated external terminal is used as the mode setting information. Then, when the input voltage to the dedicated external terminal of the device 10[i] is lower than or equal to the threshold voltage V THMODE When the input voltage to the dedicated external terminal of the device 10[i] is higher than the threshold voltage V THMODE When the mode setting circuit 30 of the device 10[i] sets the operation mode of the device 10[i] to the second mode (or vice versa). Alternatively, the mode setting information may be stored in a memory (not shown) within the device 10. A host system (not shown) connected to the device 10 so that bidirectional communication between the host system and the device 10 is possible may write the mode setting information into the memory within the device 10.

[0070] The mode setting circuit 30 supplies a mode setting signal indicating the setting result of the operation mode to each circuit in the device 10. Specifically, when the operation mode of the device 10[i] is set to the first mode, the mode setting circuit 30 of the device 10[i] supplies a first mode setting signal indicating this effect to each circuit in the device 10[i]. When the operation mode of the device 10[i] is set to the second mode, the mode setting circuit 30 of the device 10[i] supplies a second mode setting signal indicating this effect to each circuit in the device 10[i]. Hereinafter, the device 10 in the first mode refers to the device 10 in which the first mode is set as the operation mode, and the device 10 in the second mode refers to the device 10 in which the second mode is set as the operation mode.

[0071] The switch control circuit 20 includes an error amplifier 21 , a ramp circuit 22 , a sensing circuit 23 , an adder 24 , a PWM comparator 25 , a switch circuit 26 , a clock supply circuit 27 , and a controller 28 .

[0072] The error amplifier 21 is a current output type transconductance amplifier. The error amplifier 21 includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplifier 21 is connected to the feedback terminal FB. A predetermined reference voltage V is supplied to the non-inverting input terminal of the error amplifier 21. REF . Reference voltage V REF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generation circuit (not shown) within the device 10. The output terminal of the error amplifier 21 is connected to the wiring WR ERR .

[0073] The error amplifier 21 operates only in the device 10 in the first mode, and the error amplifier 21 stops in the device 10 in the second mode. In the device 10[i], the first mode setting signal or the second mode setting signal from the mode setting circuit 30 is supplied to the switch control circuit 20. When the first mode setting signal is supplied to the switch control circuit 20, the switch control circuit 20 operates the error amplifier 21, and when the second mode setting signal is supplied to the switch control circuit 20, the switch control circuit 20 stops the error amplifier 21 (stops the operation of the error amplifier 21). Therefore, among the error amplifiers 21 of the devices 10[1] to 10[n], only the error amplifier 21 of the device 10 in the first mode (that is, only the error amplifier 21 of the device 10[1]) operates. In addition, when the device 10[1] is started, soft start control can be performed to lower the reference voltage V REF The value of gradually increases from 0V to a predetermined positive voltage value, but in the following, the existence of soft start control will be ignored.

[0074] In device 10[1], the feedback voltage VFB is input to the inverting input terminal of the error amplifier 21. In the device 10[1], the error amplifier 21 outputs a voltage which is equal to the feedback voltage V FB and reference voltage V REF The difference between the corresponding current signal, thus according to the feedback voltage V FB With reference voltage V REF The difference between the wiring WR ERR The error signal ERR is generated on the sensor. The error signal ERR and the ramp signal RAMP, the sensing signal ISNS and the slope signal SLP to be described later are all voltage signals. For any voltage signal, the rise or fall of the voltage signal represents the rise or fall of the potential of the voltage signal. The same applies to other similar expressions.

[0075] In device 10[1], when the feedback voltage V FB Lower than the reference voltage V REF When the error amplifier 21 sends the signal from the output terminal of the error amplifier 21 to the wiring WR ERR The output current causes the potential of the error signal ERR to rise. FB Higher than the reference voltage V REF When the error amplifier 21 is connected to the wiring WR ERR A current is drawn to the output terminal of the error amplifier 21, so that the potential of the error signal ERR decreases. Although not particularly shown, a phase compensation circuit including a capacitor may be connected to the wiring WR ERR Between ground and ground.

[0076] The ramp circuit 22 generates a ramp signal RAMP whose potential changes from a predetermined initial voltage V to a predetermined initial voltage V at a predetermined rate during the period in which the transistor MH is turned on. INT Monotonically rising. Initial voltage V INT For example, it is 0 V, but it may be different from 0 V. During the off period of the transistor MH, the potential of the ramp signal RAMP is fixed at the initial voltage V INT .

[0077] The sensing circuit 23 detects the coil current IL and generates a sensing signal ISNS indicating the detection result of the coil current IL. The sensing signal ISNS has a voltage value proportional to the value of the coil current IL with a proportional coefficient. Therefore, as the coil current IL increases, the potential of the sensing signal ISNS rises, and as the coil current IL decreases, the potential of the sensing signal ISNS decreases. The coil current IL detected by the sensing circuit 23 of the device 10[i] is the coil current IL[i].

[0078] The sensing circuit 23 can generate a sensing signal ISNS by detecting a current flowing through the transistor MH during the on period of the transistor MH (correspondingly, the coil current IL) or detecting a current flowing through the transistor ML during the on period of the transistor ML (correspondingly, the coil current IL). Alternatively, a shunt resistor (not shown) can be inserted between the connection node between the transistors MH and ML and the coil L, in which case the sensing circuit 23 can generate a sensing signal ISNS based on a voltage drop across the shunt resistor. In addition, the sensing signal ISNS can be generated by detecting a voltage at an arbitrary position where a voltage corresponding to the coil current IL is generated. The sensing signal ISNS indicates the detected value of the coil current IL only during the on period of the transistor MH. The sensing signal ISNS is fixed at the ground potential during the off period of the transistor MH.

[0079] The adder 24 adds the sensing signal ISNS and the ramp signal RAMP to generate a ramp signal SLP as their sum signal. That is, "SLP=RAMP+ISNS."

[0080] The ramp signal SLP is input to a non-inverting input terminal of the PWM comparator 25 , and the error signal ERR′ is input to an inverting input terminal of the PWM comparator 25 .

[0081] In this case, the switch circuit 26 is provided between the inverting input terminal of the PWM comparator 25 and the wiring WR ERR and error output terminal E OUT The switch circuit 26 has a first switch state or a second switch state. When the first mode setting signal is supplied to the switch control circuit 20, the switch control circuit 20 sets the switch circuit 26 to the first switch state, and when the second mode setting signal is supplied to the switch control circuit 20, the switch control circuit 20 sets the switch circuit 26 to the second switch state. Therefore, the switch circuit 26 of the device 10[1] is set to the first switch state, and each switch circuit 26 of the devices 10[2] to 10[n] is set to the second switch state.

[0082] Figure 5 shows how the switch circuit 26 of the device 10 [1] is set to a first switch state, while Figure 6 1 shows how the switch circuit 26 of the device 10[2] is set to the second switch state. Figure 5 As shown, the switch circuit 26 in the first switch state switches the wiring WR ERR is connected to the inverting input terminal and the error output terminal EOUT of the PWM comparator 25. Therefore, the error signal ERR' of the device 10[1] is consistent with the error signal ERR generated by the error amplifier 21 in the device 10[1]. Figure 6As shown, the switch circuit 26 in the second switch state connects the wiring WR ERR The inverting input terminal of the PWM comparator 25 is disconnected, and the error output terminal EOUT is connected to the inverting input terminal of the PWM comparator 25. As described above, since all the error output terminals EOUT of the devices 10[1] to 10[n] are connected to each other (see Figure 3 ), so the error signals ERR' of devices 10[2] to 10[n] are also consistent with the error signal ERR generated by the error amplifier 21 in device 10[1].

[0083] The PWM comparator 25 compares the error signal ERR' and the ramp signal SLP input to the PWM comparator 25, and generates and outputs a signal RST indicating a comparison result. When the potential of the error signal ERR' is higher than the potential of the ramp signal SLP, the PWM comparator 25 outputs a low-level signal RST, and when the potential of the ramp signal SLP is higher than the potential of the error signal ERR', the PWM comparator 25 outputs a high-level signal RST. When "ERR'=SLP", the signal RST has a high level or a low level.

[0084] The clock supply circuit 27 includes an oscillation circuit 27a. The oscillation circuit 27a generates and outputs a clock having a predetermined frequency f PWM The internal clock signal CLK A The clock supply circuit 27 is connected to the synchronous input terminal S_IN. The internal clock signal CLK A A clock signal is input from another device 10 or from an external clock supply circuit (not shown) to a synchronization input terminal S_IN of a certain device 10. The clock signal input to the synchronization input terminal S_IN is referred to as an input clock signal CLK B Any clock signal has a high level and a low level alternately. The clock supply circuit 27 will be based on the internal clock signal CLK A The clock signal or based on the input clock signal CLK B The clock signal is used as the reference clock signal CLK REF is supplied to the controller 28. Basically, the internal clock signal CLK A Or input clock signal CLK B Can be used as reference clock signal CLK REF is supplied to the controller 28. However, the internal clock signal CLK A Or input clock signal CLK B The signal or waveform signal obtained by performing logic inversion is used as the reference clock signal CLK REF Supplied to the controller 28. In the following, unless otherwise specified, it is assumed that the internal clock signal CLK AOr input clock signal CLK B As the reference clock signal CLK REF is supplied to the controller 28 .

[0085] Among the oscillator circuits 27a of the devices 10[1] to 10[n], only the oscillator circuit 27a of the device 10 in the first mode (i.e., only the oscillator circuit 27a of the device 10[1]) operates. Therefore, in the device 10[1], the internal clock signal CLK A Or input clock signal CLK B becomes the reference clock signal CLK REF In each of the devices 10[2] to 10[n], only when the input clock signal CLK B The reference clock signal CLK is generated only when it is supplied to the synchronous input terminal S_IN. REF In this case, the input clock signal CLK B becomes the reference clock signal CLK REF In addition, the clock supply circuit 27 can determine the input clock signal CLK based on the signal of the synchronization input terminal S_IN. B Whether it is supplied to the synchronization input terminal S_IN.

[0086] When the first mode setting signal is supplied from the mode setting circuit 30 to the switch control circuit 20, the clock supply circuit 27 supplies the input clock signal CLK to the synchronization input terminal S_IN. B The clock signal CLK is input during the period B As the reference clock signal CLK REF is supplied to the controller 28, and when the input clock signal CLK is not supplied to the synchronization input terminal S_IN B The internal clock signal CLK A As the reference clock signal CLK REF is supplied to the controller 28. Therefore, in the device 10[1] operating in the first mode, the clock supply circuit 27 supplies the input clock signal CLK to the synchronization input terminal S_IN[1]. B The clock signal CLK is input during the period B As the reference clock signal CLK REF is supplied to the controller 28, and when the input clock signal CLK is not supplied to the synchronization input terminal S_IN[1] B The internal clock signal CLK A As the reference clock signal CLK REF is supplied to the controller 28. Therefore, when the input clock signal CLK is supplied to the synchronization input terminal S_IN[1] BDuring the period of B The switching action of the output stage MM of the device 10[1] is controlled synchronously. When the input clock signal CLK is not supplied to the synchronous input terminal S_IN[1] B During the period of A The switching action of the output stage MM of the device 10 [ 1 ] is controlled synchronously.

[0087] When the second mode setting signal is supplied from the mode setting circuit 30 to the switch control circuit 20, the clock supply circuit 27 supplies the input clock signal CLK to the synchronization input terminal S_IN. B The clock signal CLK is input during the period B As the reference clock signal CLK REF is supplied to the controller 28, and when the input clock signal CLK is not supplied to the synchronization input terminal S_IN B The clock signal is not supplied to the controller 28 during the period of . Therefore, in the device 10[i] (where i is an integer greater than 2 and less than n) operating in the second mode, the clock supply circuit 27 supplies the input clock signal CLK to the synchronization input terminal S_IN[i]. B The clock signal CLK is input during the period B As the reference clock signal CLK REF is supplied to the controller 28, and when the input clock signal CLK is not supplied to the synchronization input terminal S_IN[i] B The clock signal is not supplied to the controller 28 during the period of . Therefore, for each integer i satisfying "2≤i≤n", the input clock signal CLK is supplied to the synchronization input terminal S_IN[i]. B During the period of time, the input clock signal CLK to the synchronous input terminal S_IN[i] B The switching action of the output stage MM of the device 10[i] is controlled synchronously. For each integer i satisfying "2≤i≤n", when the input clock signal CLK is not supplied to the synchronous input terminal S_IN[i] B During the period of , the switching control of the output stage MM of the device 10[i] is stopped. In the device 10[i], when the switching control of the output stage MM is stopped, both the transistors MH and ML of the output stage MM are fixed to be off.

[0088] Reference clock signal CLK REF The signal RST from the PWM comparator 25 is input to the controller 28. The controller 28 is connected to the reference clock signal CLK REF The controller 28 performs the switch control of the output stage MM synchronously.REF and RST supply gate signals GH and GL to transistors MH and ML, respectively controlling the states of transistors MH and ML. Figure 7 shows the signal CLK REF , ERR', SLP, RST, GH and GL waveforms. Reference clock signal CLK REF The duty cycle is not limited to Figure 7 The duty cycle is not shown but is arbitrary.

[0089] In response to the reference clock signal CLK REF The controller 28 turns on the transistor MH by generating a rising edge in the gate signal GH and turns off the transistor ML by generating a falling edge in the gate signal GL. Figure 7 Therefore, in response to the reference clock signal CLK REF The rising edge of Figure 7 The controller 28 of the example generates a rising edge in the gate signal GH and generates a falling edge in the gate signal GL. However, the above-mentioned setting edge may be a falling edge.

[0090] After turning on transistor MH and turning off transistor ML, through the monotonous rise of the ramp signal SLP, when the potential of the ramp signal SLP changes from a state where the potential of the ramp signal SLP is lower than the potential of the error signal ERR' to a state where the potential of the ramp signal SLP is higher than the potential of the error signal ERR', a rising edge appears in the signal RST. When the rising edge appears in the signal RST, the controller 28 generates a falling edge in the gate signal GH to turn off transistor MH, and generates a rising edge in the gate signal GL to turn on transistor ML. As transistor MH is turned off, the potential of the ramp signal RAMP drops to a sufficiently low initial voltage V INT , so that the potential of the ramp signal SLP returns to a state where the potential of the ramp signal SLP is lower than the potential of the error signal ERR′, and a falling edge is quickly generated in the signal RST.

[0091] When "V OUT =V TG ”, “V FB =V REF From "V OUT =V TG The state of "establishment" begins when the load current I LD The increase of OUT <V TG ”, the state changes to “V FB <V REF", so that the potential of the error signal ERR of the device 10[1] rises, and together with this, the potential of the error signal ERR' of each device 10[1] to 10[n] also rises. In the device 10 that performs switching control, the rise in the potential of the error signal ERR' causes the on-time period of the transistor MH to increase. As the on-time period of the transistor MH increases, the coil current IL increases, so the output voltage V OUT Towards the target voltage V TG On the contrary, from "V OUT =V TG The state of "establishment" begins when the load current I LD The decrease of OUT >V TG ”, the state changes to “V FB >V REF ", so that the potential of the error signal ERR decreases, and together with this, the potential of the error signal ERR' of each device 10[1] to 10[n] also decreases. In the device 10 that performs switching control, the decrease in the potential of the error signal ERR' causes the on-time period of the transistor MH to decrease. As the on-time period of the transistor MH decreases, the coil current IL decreases, and thus the output voltage V OUT Towards the target voltage V TG In this way, in the switching power supply 1 (in the device 10 that performs switching control), control is performed to reduce the output voltage V OUT With the target voltage V TG The difference between.

[0092] The synchronous output circuit 40 is connected to the synchronous output terminal S_OUT and outputs a signal from the synchronous output terminal S_OUT. The synchronous output circuit 40 operates based on the power supply voltage VDD. The synchronous output circuit 40 sets the state of the synchronous output terminal S_OUT to one of a plurality of output states including a low level output state, a high level output state and a Hi-Z state. In the present embodiment, the state of the synchronous output terminal S_OUT and the state of the synchronous output circuit 40 are understood to be synonymous with each other. Therefore, the synchronous output terminal S_OUT is in a low level output state and the synchronous output circuit 40 is in a low level output state refers to the same situation. This also applies to the high level output state and the Hi-Z state.

[0093] The synchronous output circuit 40 outputs a low-level signal from the synchronous output terminal S_OUT with a sufficiently low output impedance in the low-level output state, and outputs a high-level signal from the synchronous output terminal S_OUT with a sufficiently low output impedance in the high-level output state. In the Hi-Z state, the synchronous output circuit 40 makes the output impedance of the synchronous output terminal S_OUT higher than the output impedance in the low-level output state and the output impedance in the high-level output state. Figure 1 In the switching power supply 1, the output impedance of the synchronous output circuit 40 in the device 10[i] refers to the output impedance when the synchronous output circuit 40 of the device 10[i] outputs a signal to the outside of the device 10[i] via the synchronous output terminal S_OUT.

[0094] Figure 8 The configuration of a synchronous output circuit 40A as an example of a synchronous output circuit 40 is shown. The synchronous output circuit 40A includes a transistor 41 as a P-channel MOSFET, a transistor 42 as an N-channel MOSFET, and an output setting circuit 43. The source of the transistor 41 is connected to the application terminal of the power supply voltage VDD, and the power supply voltage VDD is supplied. Each drain of the transistors 41 and 42 is connected to the synchronous output terminal S_OUT. The source of the transistor 42 is grounded. The output setting circuit 43 is connected to each gate of the transistors 41 and 42, and the states of the transistors 41 and 42 are individually set to be turned on or off by controlling the corresponding gate potentials of the transistors 41 and 42.

[0095] When the output setting circuit 43 turns off the transistor 41 and turns on the transistor 42, the state of the synchronous output terminal S_OUT is a low level output state, and the synchronous output circuit 40A outputs a low level signal from the synchronous output terminal S_OUT. When the output setting circuit 43 turns on the transistor 41 and turns off the transistor 42, the state of the synchronous output terminal S_OUT is a high level output state, and the synchronous output circuit 40A outputs a high level signal from the synchronous output terminal S_OUT. The output impedance of the synchronous output circuit 40A in the low level output state is equal to the on-resistance of the transistor 42, and the output impedance of the synchronous output circuit 40A in the high level output state is equal to the on-resistance of the transistor 41. When both transistors 41 and 42 are set to disconnect by the output setting circuit 43, the state of the synchronous output terminal S_OUT is a Hi-Z state. The output impedance of the synchronous output circuit 40A in the Hi-Z state is much larger than the on-resistance of the transistor 41 and the on-resistance of the transistor 42. In the following, the on-resistance of transistors 41 and 42 is considered to be small enough and will be ignored.

[0096] Regarding the signal or voltage at the synchronous output terminal S_OUT and the synchronous input terminal S_IN, the high level refers to being higher than or equal to the predetermined upper threshold voltage VTHH The low level refers to a voltage lower than or equal to the predetermined lower threshold voltage V THL In this case, “VDD>V THH >V THL >0” holds. For example, the upper threshold voltage V THH is set to 0.7 times the power supply voltage VDD, and the lower threshold voltage V THL Set to 0.3 times the power supply voltage VDD.

[0097] The multiple output states of the synchronous output circuit 40 may include other output states that do not belong to any of the low-level output state, the high-level output state and the Hi-Z state (for example, a state in which a signal having an intermediate potential that is not classified as a high level or a low level is output from the synchronous output terminal S_OUT).

[0098] Reference again Figure 4 , the synchronous input circuit 50 is connected to the synchronous input terminal S_IN. The synchronous input circuit 50 operates based on the power supply voltage VDD. The synchronous input circuit 50 sets the state of the synchronous input terminal S_IN to one of a plurality of input states including a pull-down state and a pull-up state. In the present embodiment, the state of the synchronous input terminal S_IN and the state of the synchronous input circuit 50 are understood to be synonymous with each other. Therefore, the synchronous input terminal S_IN being in the pull-down state and the synchronous input circuit 50 being in the pull-down state refer to the same situation, while the synchronous input terminal S_IN being in the pull-up state and the synchronous input circuit 50 being in the pull-up state refer to the same situation.

[0099] The synchronous input circuit 50 pulls the synchronous input terminal S_IN to a low level through a pull-down resistor in the pull-down state, and pulls the synchronous input terminal S_IN to a high level through a pull-up resistor in the pull-up state. The pull-down resistor and the pull-up resistor may be a common resistor or two independent resistors.

[0100] Fig. 9The configuration of a synchronous input circuit 50A as an example of a synchronous input circuit 50 is shown. The synchronous input circuit 50A includes a transistor 51 as a P-channel MOSFET, a transistor 52 as an N-channel MOSFET, an input setting circuit 53, and a resistor 54. The source of the transistor 51 is connected to the application terminal of the power supply voltage VDD, and is supplied with the power supply voltage VDD. The first end of the resistor 54 is connected to the synchronous input terminal S_IN. The second end of the resistor 54 is connected to each drain of the transistors 51 and 52. The source of the transistor 52 is grounded. The input setting circuit 53 is connected to each gate of the transistors 51 and 52, and the states of the transistors 51 and 52 are individually set to be turned on or off by controlling the corresponding gate potentials of the transistors 51 and 52.

[0101] When the input setting circuit 53 turns off the transistor 51 and turns on the transistor 52, since the synchronous input terminal S_IN is pulled down to the ground (low level) via the resistor 54 and the transistor 52, the state of the synchronous input terminal S_IN is the pull-down state. When the input setting circuit 53 turns on the transistor 51 and turns off the transistor 52, since the synchronous input terminal S_IN is pulled up to the application terminal (high level) of the power supply voltage VDD via the resistor 54 and the transistor 51, the state of the synchronous input terminal S_IN is the pull-up state. The on-resistance value of transistors 51 and 52 is sufficiently smaller than the value of resistor 54. In the following, the on-resistance of transistors 51 and 52 will be ignored. In the synchronous input circuit 50A, the resistor 54 is used as a pull-down resistor in the pull-down state, and the resistor 54 is used as a pull-up resistor in the pull-up state, but the pull-down resistor and the pull-up resistor can be set separately.

[0102] The value of the resistor 54 is sufficiently larger than the output impedance of the synchronous output terminal S_OUT in the low level output state and the output impedance of the synchronous output terminal S_OUT in the high level output state, and is sufficiently smaller than the output impedance of the synchronous output terminal S_OUT in the Hi-Z state.

[0103] The plurality of input states regarding the synchronous input circuit 50 may include other input states that do not belong to the pull-down state and the pull-up state (eg, a state in which both the transistors 51 and 52 are set to be off).

[0104] Hereinafter, unless otherwise specified, it is assumed that the synchronous output circuit 40A and the synchronous input circuit 50A are used as the synchronous output circuit 40 and the synchronous input circuit 50 , respectively.

[0105] Reference again Figure 4 The level detection circuit 60 is connected to the synchronous output terminal S_OUT and outputs a level detection signal S according to the level of the synchronous output terminal S_OUT. DETThe pattern determination circuit 70 is connected to the synchronization input terminal S_IN, and outputs a pattern determination signal S according to the pattern of the signal supplied to the synchronization input terminal S_IN. PTN Signal S DET and S PTN The clock management circuit 80 is based on the sense signal ISNS, the level detection signal S DET and pattern determination signal S PTN The information is used to manage and control the state of the synchronous output circuit 40. The details of the circuits 60, 70 and 80 will be described later.

[0106] In addition, in the following, for the convenience of description, similar to the synchronous input terminal S_IN and the synchronous output terminal S_OUT in the device 10[i] represented by the symbols “S_IN[i]” and “S_OUT[i]”, respectively, as shown in FIG. Fig.10 As shown, the output stage MM, the switch control circuit 20, the mode setting circuit 30, the synchronous output circuit 40, the synchronous input circuit 50, the level detection circuit 60, the pattern determination circuit 70 and the clock management circuit 80 in the device 10[i] are represented by symbols "MM[i]", "20[i]", "30[i]", 40[i], "50[i]", "60[i]", "70[i]" and "80[i]", respectively. In addition, the sensing signal ISNS, the level detection signal S DET and pattern determination signal S PTN Respectively represented by the symbols “ISNS[i]”, “S DET [i]” and “S PTN [i]” indicates.

[0107] <<Reference Power Supply>>

[0108] Before describing a detailed operation example of the switching power supply 1, some reference power supplies will be described. In the first reference power supply, DC / DC converters for a plurality of channels are built into one electronic component. In the first reference power supply, multi-phase control can be easily achieved by shifting the phase of the switch control of each channel based on an internal clock signal generated in one electronic component. In the first reference power supply, since the operating state of the DC / DC converter of each channel in one electronic component can be grasped, it is relatively easy to increase or decrease the number of channels to be operated according to the load current.

[0109] On the other hand, there are multi-phase DC / DC converters formed of a plurality of electronic components separated from each other (e.g. Figure 1The method of the switching power supply 1 shown in FIG. 1 (hereinafter referred to as the multi-component method). When the multi-component method is adopted, one electronic component as the main electronic component is responsible for the main control and gives commands related to the operation to other electronic components. For example, in the second reference power supply constituting a 4-phase DC / DC converter, the main electronic component individually sends clock signals to the remaining three electronic components (sub-electronic components) to realize multi-phase control. However, in this case, since as many clock signal output terminals and output circuits as the number of sub-electronic components are required, the size of each electronic component increases.

[0110] Taking this into consideration, in the third reference power supply, a plurality of electronic components each responsible for switch control of one channel are connected in cascade. That is, in the third reference power supply, a clock signal for synchronization is transmitted from the main electronic component responsible for the first phase to the sub-electronic component responsible for the second phase, a clock signal for synchronization is transmitted from the sub-electronic component responsible for the second phase to the sub-electronic component responsible for the third phase, and a time signal for synchronization is transmitted from the sub-electronic component responsible for the third phase to the sub-electronic component responsible for the fourth phase. A four-phase DC / DC converter can be configured by transmitting a clock signal for synchronization so that the phase of the clock signal for switch control is offset between the four electronic components.

[0111] However, in the third reference power supply, when viewed from the main electronic component, the main electronic component cannot recognize how many sub-electronic components are connected, and cannot know how many of the sub-electronic components are in operation. In the third reference power supply, when multiple power controllers (multiple electronic components) and multiple coils are connected in parallel, Figure 1 When the switching power supply 1 is connected in the same manner, in principle, the same magnitude of current flows through the coil corresponding to the main power controller (main electronic component) and the coil corresponding to the sub-power controller (sub-electronic component). Therefore, when the total number of electronic components in the working state is known, the load current (the total number of electronic components in the working state × the current flowing through one coil) can also be known. However, in the third reference power supply formed by simply cascading a plurality of electronic components, the main electronic component cannot know the load current (the same is true for the sub-electronic component). As a result, it is difficult to increase or decrease the number of channels in operation (the total number of electronic components in the working state) according to the load current.

[0112] This is advantageous in that information can be transmitted from the device 10 at the subsequent stage to the device 10 at the preceding stage without adding a dedicated terminal because operation / non-operation of each channel can be controlled according to the load current.

[0113] Hereinafter, in a plurality of examples, specific configuration examples, operation examples, application techniques, deformation techniques, etc. related to the switching power supply 1 will be described. Unless otherwise specified and unless there is a contradiction (however, excluding matters regarding the first reference power supply to the third reference power supply), the above-mentioned matters in the present embodiment apply to each of the following examples. In each example, in the event that there is a matter that contradicts the above-mentioned matters, the description in each example may be given priority. In addition, as long as there is no contradiction, the matters described in any of the following examples may be applied to any other example (that is, any two or more examples may also be combined).

[0114] <<First Example>>

[0115] A first example will be described. In the first example, it is assumed that the synchronization input terminal S_IN of the device 10[1] is open. That is, in the first example, the input clock signal CLK is not supplied to the synchronization input terminal S_IN of the device 10[1]. B Thus, in a first example, the controller 28 of the device 10[1] uses an internal clock signal CLK generated within the device 10[1]. A As the reference clock signal CLK REF To perform switching control of the output stage MM[1].

[0116] In the switching power supply 1 , by using a signal between the terminals S_OUT and S_IN, a clock signal for synchronization can be transmitted from the device 10 [i] to the device 10 [i+1], and information can be transmitted from the device 10 [i+1] to the device 10 [i].

[0117] Will refer to Fig.11 The information transmission method from device 10[i+1] to device 10[i] is described. A clock signal for synchronization is output from synchronization output circuit 40[i]. The clock signal output by synchronization output circuit 40[i] is referred to as clock signal CLK[i]. The reference clock signal CLK of devices 10[i] and 10[i+1] is REF In particular, they are represented by the symbol "CLK REF [i]” and “CLK REF [i+1]”. Hereinafter, a period in which switch control is performed may be referred to as a switch execution period, and a period in which switch control is not performed may be referred to as a switch stop period. A period in which the clock signal CLK[i] is output by the synchronous output circuit 40[i] may be referred to as an output period of the clock signal CLK[i], and a period in which the synchronous output circuit 40[i] does not output the clock signal CLK[i] may be referred to as a non-output period of the clock signal CLK[i] or a stop period of the clock signal CLK[i].

[0118] In any device 10[i], during a period in which the switch control circuit 20[i] performs switch control and the clock signal CLK[i] is not output from the synchronization output circuit 40[i], the clock management circuit 80[i] monitors whether a predetermined clock output condition is satisfied. Then, when the clock output condition is satisfied, the clock management circuit 80[i] controls the synchronization output circuit 40[i] to output a clock signal based on the reference clock signal CLK[i] from the synchronization output terminal S_OUT[i]. REF [i], and as a result, the clock signal CLK[i] is output. When the clock output condition is not met, the synchronous output circuit 40[i] does not output the clock signal CLK[i]. When the clock signal CLK[i] is not output, the state of the synchronous output terminal S_OUT[i] can be fixed to the Hi-Z state by the synchronous output circuit 40[i].

[0119] The clock signal CLK[i] is the output clock signal of the device 10[i] and the input clock signal of the device 10[i+1]. The device 10[i+1] receives the clock signal CLK[i] as the input clock signal at the synchronization input terminal S_IN[i+1] and uses the clock signal CLK[i] as the reference clock signal CLK REF [i+1] to perform switch control.

[0120] The synchronous output circuit 40[i] makes the reference clock signal CLK REF [i] phase shift to make the clock signal CLK REF [i] and CLK[i] have the same frequency and different phases to generate the clock signal CLK[i].

[0121] Fig.12 The conceptual waveform diagram of the clock signal CLK[i] is shown. As time passes, times T1, T2, T3, and T4 arrive in this order. The unit time t as the time difference between time T1 and T4 U1 has a length of one cycle of the clock signal CLK[i], and in the first example, is the same as the internal clock signal CLK A The length of one cycle of PWM In the first example, each cycle of any clock signal is considered to start from the rising edge of the clock signal.

[0122] At time T1, the synchronous output circuit 40[i] switches the state of the synchronous output terminal S_OUT[i] from a low level output state to a high level output state. Thereafter, at time T2, the synchronous output circuit 40[i] switches the state of the synchronous output terminal S_OUT[i] from a high level output state to a Hi-Z state. Thereafter, at time T3, the synchronous output circuit 40[i] switches the state of the synchronous output terminal S_OUT[i] from a Hi-Z state to a low level output state. Thereafter, at time T4, the synchronous output circuit 40[i] switches the state of the synchronous output terminal S_OUT[i] from a low level output state to a high level output state. Thereafter, the same operation is repeated. When time T1 is the start time of the jth cycle of the clock signal CLK[i], time T4 corresponds to the start time of the (j+1)th cycle of the clock signal CLK[i]. In this case, j represents any natural number.

[0123] As described above, during the output period of the clock signal CLK[i], in each cycle of the clock signal CLK[i], the synchronous output circuit 40[i] includes a period P11 (in which the state of the synchronous output terminal S_OUT[i] is set to a high level output state) during which the state of the synchronous output terminal S_OUT[i] is set to a high level output state. Fig.12 The state of the synchronous output terminal S_OUT[i] is set to a low level output state during the period P13 (between the time T1 and T2 of Fig.12 The state of the synchronous output terminal S_OUT[i] is set to the Hi-Z state during the period P12 (between the time T3 and T4 of Fig.12 For example, the lengths of time periods P11, P12, and P13 are respectively the unit time t U1 However, the time periods P11, P12 and P13 are within the unit time t U1 The ratio in may be arbitrary. The output pattern of the clock signal CLK[i] of the synchronous output circuit 40[i] of the first example is referred to as a pattern PTN1a.

[0124] The on-resistance of transistors 41 and 42 is negligibly smaller than the value of resistor 54 (see Figure 8 and Fig. 9). Therefore, when the state of the synchronization output terminal S_OUT[i] is a low-level output state, the clock signal CLK[i] is at a low level (substantially having a ground potential), and when the state of the synchronization output terminal S_OUT[i] is a high-level output state, the clock signal CLK[i] is at a high level (substantially having a potential of the power supply voltage VDD). During the period in which the state of the synchronization output terminal S_OUT[i] is the Hi-Z state (i.e., the period between time T2 and T3), the level of the clock signal CLK[i] depends on the state of the synchronization input circuit 50[i+1].

[0125] Fig.13 FIG. 5 shows the waveform of the clock signal CLK[i] when the synchronous input circuit 50[i+1] is in the pull-down state. When the synchronous input circuit 50[i+1] is in the pull-down state, the potential of the clock signal CLK[i] drops from the potential of the power supply voltage VDD to the ground potential after time T2, and PRE Previously, the potential dropped to a low level. Time T3 PRE After time T2 and before time T3 by a predetermined minute time.

[0126] Fig.14 The waveform of the clock signal CLK[i] when the synchronous input circuit 50[i+1] is in the pull-up state is shown. When the synchronous input circuit 50[i+1] is in the pull-up state, the potential of the clock signal CLK[i] changes from time T2 to time T3. PRE And the potential of the power supply voltage VDD is maintained until time T3 (thus, maintained at a high level), and the potential of the clock signal CLK[i] drops sharply from the potential of the power supply voltage VDD to the ground potential at time T3.

[0127] When the synchronous output circuit 40[i] outputs the clock signal CLK[i], the level detection circuit 60[i] turns the synchronous output terminal S_OUT[i] on at time T3 PRE The voltage at the detection target voltage is designated as the detection target voltage, and it is detected whether the detection target voltage belongs to a high level or a low level. The level detection circuit 60[i] detects that the detection target voltage is higher than or equal to the upper threshold voltage V THH In the case of the detection target voltage being determined to be a high level, when the detection target voltage is lower than or equal to the lower threshold voltage V THL In this case, it is determined that the detection target voltage belongs to a low level.

[0128] When the level detection circuit 60[i] determines that the detection target voltage belongs to the low level, it outputs a level detection signal S1 of "1". DET [i](See Fig.13 ). When the output is the level detection signal SDET [i], then keep "S DET [i]=1” until it is determined that the detection target voltage belongs to a high level. When the level detection circuit 60[i] determines that the detection target voltage belongs to a high level, its output is a level detection signal S of “0”. DET [i](See Fig.14 ). When the output is the level detection signal S DET [i], then keep "S DET [i]=0”, until it is determined that the detection target voltage belongs to the low level. The level detection signal S DET [i] does not have a significant value during the non-output period of the clock signal CLK[i].

[0129] As described above, by switching the synchronous input circuit 50[i+1] between the pull-down state and the pull-up state, information can be transmitted from the subsequent-stage device 10[i+1] to the previous-stage device 10[i]. In addition, regardless of the state of the synchronous input circuit 50[i+1], a rising edge always appears in the clock signal CLK[i] at time T1. Therefore, by using the rising edge of the clock signal CLK[i], the switching actions between the devices 10[i] and 10[i+1] can be synchronized. In order to ensure this synchronization, when using Fig.12 In the first example of the pattern PTN1a, the setting edge is a rising edge. That is, when the clock signal CLK[i] of the pattern PTN1a is supplied to the device 10[i+1], the controller 28 of the device 10[i+1] turns on the transistor MH and turns off the transistor ML in response to the rising edge of the clock signal CLK[i].

[0130] In any device 10[i], during a period in which the switch control circuit 20[i] performs switch control and outputs the clock signal CLK[i] from the synchronization output circuit 40[i], the clock management circuit 80[i] monitors whether a predetermined clock stop condition is satisfied. Then, when the clock stop condition is satisfied, the clock management circuit 80[i] controls the synchronization output circuit 40[i] to stop the output of the clock signal CLK[i] from the synchronization output terminal S_OUT[i], and as a result, the output of the clock signal CLK[i] is stopped.

[0131] In the first example, the following first rule is adopted in each device 10. The device 10[i] according to the first rule sets the state of the synchronization input terminal S_IN[i] to the pull-down state during the output period of the clock signal CLK[i], and sets the state of the synchronization input terminal S_IN[i] to the pull-up state during the non-output period of the clock signal CLK[i].

[0132] Fig.15The state of the switching power supply 1 when the clock signals CLK[1] to CLK[3] are output in the case of "n=4" is shown. In response to the output of the clock signals CLK[1] to CLK[3], the synchronous input terminals S_IN[1] to S_IN[3] are set to the pull-down state. Fig.15 In the state, the clock signal CLK[4] is not output, and therefore, the synchronization input terminal S_IN[4] is set to the pull-up state. When the clock signal CLK[4] is output from the synchronization output terminal S_OUT[4], the synchronization input terminal S_IN[4] is set to the pull-down state (however, the device 10 receiving the clock signal CLK[4] does not exist). Fig.15 In this state, significant coil currents IL[1] to IL[4] are generated by performing switch control in each of devices 10[1] to 10[4].

[0133] Fig.16 The state of the switching power supply 1 when the clock signals CLK[1] and CLK[2] are output but the clock signal CLK[3] is not output is shown in the case of "n=4". In response to the output of the clock signals CLK[1] and CLK[2], the synchronization input terminals S_IN[1] and S_IN[2] are set to the pull-down state, and in response to the non-output of the clock signal CLK[3], the synchronization input terminal S_IN[3] is set to the pull-up state. In addition, Fig.16 In the example of FIG. 1 , in the device 10 [ 4 ] that does not receive the clock signal CLK [ 3 ], the synchronous input terminal S_IN [ 4 ] is set to a pull-up state as an initial state. Fig.15 and Fig.16 In the example of FIG. 1 , only in the device 10 [ 1 ] operating in the first mode, the state of the synchronization input terminal S_IN [i] can be arbitrary, regardless of whether the clock signal CLK [ 1 ] is output. Fig.16 In this state, significant coil currents IL[1] to IL[3] are generated by performing switching control in each of devices 10[1] to 10[3], but since the switching control in device 10[4] is stopped, the coil current IL[4] is zero.

[0134] Fig.17 FIG. 1 is a flow chart showing the operation of the device 10 [1] operating in the first mode. Fig.17 To describe the operation flow of device 10[1].

[0135] First, in step S10, the device 10[1] is supplied with an input voltage V INto activate the device 10[1]. In the subsequent step S11, a predetermined initialization process is performed in the device 10[1] so that the state of the device 10[1] becomes the initial state. In the initial state, the synchronization input terminal S_IN[1] is in a pull-up state, and the switch control is stopped. In addition, in the initialization process, the mode setting circuit 30 sets the operation mode of the device 10[1] to the first mode. After step S11, the process proceeds to step S12.

[0136] In step S12, the clock signal CLK is determined B Is it input to the synchronous input terminal S_IN[1]. When the clock signal CLK B When the clock signal CLK is input to the synchronization input terminal S_IN[1], the process proceeds from step S12 to step S18, in which a process that responds to the external clock is performed (the details of which will be shown in other examples). B When the synchronous input terminal S_IN[1] is not input, the process proceeds from step S12 to step S13. In the first example, since it is assumed that the clock signal CLK B Since it is not input to the synchronization input terminal S_IN[1], the process proceeds to step S13. As a variation, the process may always proceed to step S13 after step S11.

[0137] In the device 10[1] operating in the first mode, the internal clock signal CLK A As the reference clock signal CLK REF Supplied to the controller 28. For ease of description, the reference clock signal CLK supplied to the controller 28 of the device 10[1] REF It may be referred to as clock signal CLK[0] hereinafter.

[0138] In step S13, the device 10[1] starts the switching control of the output stage MM[1] in synchronization with the clock signal CLK[0]. The controller 28 of the device 10[1] turns on the transistor MH and turns off the transistor ML in response to the rising edge of the clock signal CLK[0]. The coil current IL[1] is generated by the switching control of the device 10[1]. The coil current IL[1] is periodically detected by the sensing circuit 23 of the device 10[1], and a sensing signal ISNS[1] indicating the detection value of the coil current IL[2] is generated. After step S13, the process proceeds to step S14.

[0139] In step S14, the clock management circuit 80[1] compares the detected coil current IL[1] with the predetermined upper limit threshold current I based on the sense signal ISNS[1]. THHThe clock output condition in step S14 is satisfied and the clock output condition is satisfied. THH " corresponds to the establishment of. When in step S14 "IL[1]>I THH " is established, a transition to step S15 occurs. When "IL[1]>I THH If " is not true, the process returns to step S14, in which it is repeatedly determined whether the clock output condition is satisfied (i.e., whether "IL[1]>I THH ” is established).

[0140] In step S15, the clock management circuit 80[1] controls the synchronous output circuit 40[1] so that the synchronous output circuit 40[1] starts outputting the clock signal CLK[1]. In addition, in step S15, the clock management circuit 80[1] changes the state of the synchronous input terminal S_IN[1] from the pull-up state to the pull-down state by controlling the synchronous input circuit 50[1]. After step S15, the process proceeds to step S16.

[0141] In step S16, the clock management circuit 80[1] determines whether the clock stop condition is satisfied. When the clock stop condition is not satisfied, the determination process in step S16 is repeated. When the clock stop condition is satisfied, a transition from step S16 to step S17 occurs. The clock stop condition will be described later.

[0142] In step S17, the clock management circuit 80[1] controls the synchronous output circuit 40[1] so that the synchronous output circuit 40[1] stops outputting the clock signal CLK[1]. In addition, in step S17, the clock management circuit 80[1] changes the state of the synchronous input terminal S_IN[1] from the pull-down state to the pull-up state by controlling the synchronous input circuit 50[1]. After step S17, the process returns to step S14.

[0143] Only when the detected coil current IL[1] satisfies "IL[1] THL " and the level detection signal S DET The clock stop condition in step S16 is satisfied only when the value of IL[1] is "0". The value of IL[1] can be determined based on the sense signal ISNS[1]. THL "Is it true? THL Indicates the upper threshold current I THH The lower predetermined lower threshold current. DET [1]=0" indicates that the synchronous input terminal S_IN[2] is in the pull-up state (see Fig.14 ​​), that is, the clock signal CLK[2] is not output (therefore, the switching control of the device 10[3] is stopped). In other words, assuming that the drive (switching control) of the device 10[3] is stopped, when the coil current IL[1] drops below the lower threshold current I THL When it is determined that the driving of the device 10[2] is not necessary, the output of the clock CLK[1] is stopped (S17).

[0144] Fig.18 A flow chart showing the operation of device 10[i] operating in a second mode is shown. Fig.18 The variable i in each step (S20 to S28) shown in FIG. Fig.18 The operational flow of device 10[i] operating in the second mode is described.

[0145] First, in step S20, the device 10[i] is supplied with an input voltage V IN to activate the device 10[i]. In the subsequent step S21, a predetermined initialization process is performed in the device 10[i] so that the state of the device 10[i] becomes the initial state. In the initial state, the synchronization input terminal S_IN[i] is in a pull-up state, and the switch control is stopped. In addition, in the initialization process, the mode setting circuit 30 sets the operation mode of the device 10[i] to the second mode (as described above, in this case, i is an arbitrary integer greater than 2). After step S21, the process proceeds to step S22.

[0146] In step S22, the clock signal CLK is determined B Whether the clock signal CLK is input to the synchronization input terminal S_IN[i]. For the device 10[i], the clock signal CLK B is the clock signal CLK[i-1] from device 10[i-1]. B When the clock signal CLK is not input to the synchronization input terminal S_IN[i], the determination process in step S22 is repeated. B When (CLK[i-1]) is input to the synchronization input terminal S_IN[i], the process proceeds from step S22 to step S23.

[0147] In the device 10[i] operating in the second mode, the input clock signal CLK for synchronizing the input terminal S_IN[i] is B (CLK[i-1]) is used as the reference clock signal CLK REF Supplied to the controller 28.

[0148] In step S23, the device 10[i] is connected to the reference clock signal CLK REFThe switching control of the output stage MM[i] is started synchronously with the clock signal CLK[i-1] of the device 10[i]. The controller 28 of the device 10[i] turns on the transistor MH and turns off the transistor ML in response to the rising edge of the clock signal CLK[i-1]. The coil current IL[i] is generated by the switching control of the device 10[i]. The coil current IL[i] is periodically detected by the sensing circuit 23 of the device 10[i], and a sensing signal ISNS[i] indicating the detection value of the coil current IL[i] is generated. After step S23, the process proceeds to step S24.

[0149] In step S24, the clock management circuit 80[i] compares the detected coil current IL[i] with the predetermined upper limit threshold current I based on the sensing signal ISNS[i]. THH The clock output condition in step S24 is satisfied and the clock output condition is satisfied. THH " corresponds to the establishment of. When in step S24 "IL[i]>I THH " is established, a transition to step S25 occurs. When "IL[i]>I THH If " is not true, the process returns to step S24, in which it is repeatedly determined whether the clock output condition is satisfied (i.e., whether "IL[i]>I THH ” is established).

[0150] In step S25, the clock management circuit 80[i] controls the synchronous output circuit 40[i] so that the synchronous output circuit 40[i] starts outputting the clock signal CLK[i]. In addition, in step S25, the clock management circuit 80[i] changes the state of the synchronous input terminal S_IN[i] from the pull-up state to the pull-down state by controlling the synchronous input circuit 50[i]. After step S25, the process proceeds to step S26.

[0151] In step S26, the clock management circuit 80[i] determines whether the clock stop condition is satisfied. When the clock stop condition is not satisfied, the determination process in step S26 is repeated. When the clock stop condition is satisfied, a transition from step S26 to step S27 occurs. The clock stop condition will be described later.

[0152] In step S27, the clock management circuit 80[i] controls the synchronous output circuit 40[i] so that the synchronous output circuit 40[i] stops outputting the clock signal CLK[i]. In addition, in step S27, the clock management circuit 80[i] changes the state of the synchronous input terminal S_IN[i] from the pull-down state to the pull-up state by controlling the synchronous input circuit 50[i]. After step S27, the process returns to step S24.

[0153] Only when the detected coil current IL[i] satisfies "IL[i] THL " and the level detection signal S DET The clock stop condition in step S26 is satisfied only when the value of IL[i] is "0". THL "Is it true?" DET [i] = 0" indicates that the synchronous input terminal S_IN[i+1] is in the pull-up state (see Fig.14 ). That is, “S DET [i]=0” indicates that the clock signal CLK[i+1] is not output (therefore, the switching control of the device 10[i+2] is stopped). In other words, assuming that the drive (switching control) of the device 10[i+2] is stopped, when the coil current IL[i] drops below the lower threshold current I THL When the drive of the device 10[i+1] is determined to be unnecessary, the output of the clock CLK[i] is stopped (S27). However, in the case of "i=n-1", the device 10[i+2] does not exist, and in the case of "i=n", the devices 10[i+1] and 10[i+2] do not exist.

[0154] Although not particularly shown, after the process proceeds from step S22 to step S23, when the supply of the clock signal CLK[i-1] to the synchronization input signal S_IN[i] is interrupted, the reference clock signal CLK[i-1] in the device 10[i] is REF , and thus the switch control of the device 10[i] is stopped. After the process proceeds from step S22 to step S23, the switch control circuit 20[i] monitors the signal change of the synchronization input signal S_IN[i]. In the case where there is no signal change in the synchronization input signal S_IN[i] for a certain period of time or longer, the switch control circuit 20[i] is sufficient to determine that the supply of the clock signal CLK[i-1] is interrupted, fixes the transistors MH and ML of the output stage MM[i] in the off state, and then transitions to step S22.

[0155] In the switching power supply 1, the output stages MM[1] to MM[m] among the output stages MM[1] to MM[n] are switched and the current is transferred from the input voltage V to the output voltage V through the output stages MM[1] to MM[m]. IN The apply terminal supplies the output voltage V OUT The application terminal (output node ND OUT ). In this case, m represents a natural number less than n.

[0156] ​​A specific example of the operation of the switching power supply 1 assuming that "n=4" will be given. When the input voltage V is supplied to each device 10[1] to 10[4], IN When the load current I LD When the load current I is relatively large, since the clock output condition is satisfied in the device 10[1], the output of the clock signal CLK[1] is started, and the coil current IL[2] is generated in addition to the coil current IL[1]. LD , the clock output conditions are also sequentially satisfied in devices 10[2] and 10[3]. As a result, a state is reached in which all devices 10[1] to 10[4] are switched (hereinafter referred to as a 4-channel driving state; Fig.15 In the 4-channel driving state assumed in this case, the clock output condition is not satisfied in the device 10[4], and as a result, the synchronization input terminal S_IN[4] is in a pull-up state.

[0157] Since current mode control is performed by using a common error signal between devices 10[1] to 10[4], the magnitudes of coil currents IL[1] to IL[4] are substantially the same when switching control is performed in each of devices 10[1] to 10[4]. In this way, by LD Now, consider the load current I LD The case where the current decreases from the 4-channel driving state. For the sake of specific explanation, assume that the lower threshold current I THL is 1.0A and the load current I LD Starting from the 4-channel driving state, the currents IL[1] to IL[4] are reduced from 5.0 A to 3.9 A. Due to this reduction, the coil currents IL[1] to IL[4] are all reduced to 0.975 A (in this case, the error is negligible).

[0158] At this time, although it is detected in each of the devices 10[1] to 10[4] that the coil current IL has dropped below the lower threshold current I THL , but the clock stop condition is satisfied only for device 10[3] among devices 10[1] to 10[3]. This is because Fig.15 In the corresponding 4-channel driving state, the level determination signal S DET [1] to S DET [3] only the signal S DET [3] has "0" (see Fig.17 S16 and Fig.18 Therefore, when the load current I LDWhen the current is reduced from 5.0A to 3.9A starting from the 4-channel driving state, the output of the clock signal CLK[3] from the device 10[3] stops, and Fig.15 The corresponding 4-channel drive status becomes the same as Fig.16 The corresponding state (hereinafter referred to as the 3-channel driving state) is shown in FIG. 1 . When the output of the clock signal CLK[3] stops, the state of the synchronous input terminal S_IN[3] changes from the pull-down state to the pull-up state. In the 3-channel driving state, only the devices 10[1] to 10[3] perform switching control. In the 3-channel driving state, the load current I LD While maintaining 3.9A, the coil currents IL[1] to IL[3] are each stabilized at 1.3A. LD When the voltage is sufficiently reduced, the switch control of device 10 [ 3 ] is stopped by stopping the output of clock signal CLK [ 2 ], and then the switch control of device 10 [ 2 ] can also be stopped by stopping the output of clock signal CLK [ 1 ].

[0159] As described above, in the switching power supply 1, by switching between pull-down and pull-up of the synchronization input terminal S_IN, information is transmitted from the device 10 located at the subsequent stage to the device 10 located at the preceding stage without adding a dedicated terminal or the like. As a result, it is possible to LD To control the operation / non-operation of each channel.

[0160] Furthermore, when the load current is reduced from 5.0 A to 3.9 A while driving four channels in the third reference power supply described above, each electronic component can recognize the fact that the current connected to its own coil has been reduced to 0.975 A. At this time, in the case where the main electronic component (corresponding to device 10[1]) located at the first stage stops supplying a clock signal to the subsequent electronic component (corresponding to device 10[2]), all electronic components connected to the main electronic component stop working. As a result, it is necessary to cover the load current of 3.9 A only through the channels of the main electronic component, which causes some inconvenience.

[0161] Fig.19 FIG. 4 shows the waveforms of the clock signals CLK[0] to CLK[3] in the above-mentioned 4-channel driving state. Fig.19 In the figure, for the convenience of illustration, it is assumed that the clock signals CLK[0] to CLK[3] are all rectangular wave signals with a duty cycle of 50%, and the existence of the Hi-Z state is ignored.

[0162] In the 4-channel driving state, the clock signals CLK[0] to CLK[3] are the reference clock signals CLK in devices 10[1] to 10[4], respectively. REF. Therefore, the controller 28 of the device 10[1] turns on the transistor MH of the output stage MM[1] and turns off its transistor ML in response to the rising edge of the clock signal CLK[0]. The controller 28 of the device 10[2] turns on the transistor MH of the output stage MM[2] and turns off its transistor ML in response to the rising edge of the clock signal CLK[1]. The controller 28 of the device 10[3] turns on the transistor MH of the output stage MM[3] and turns off the transistor ML of the output stage MM[3] in response to the rising edge of the clock signal CLK[2]. The controller 28 of the device 10[4] turns on the transistor MH of the output stage MM[4] and turns off the transistor ML of the output stage MM[4] in response to the rising edge of the clock signal CLK[3].

[0163] The synchronous output circuit 40[1] generates the clock signal CLK[1] by delaying the phase of the clock signal CLK[0] by a predetermined offset SHT[1]. The offset SHT[1] is 180 degrees. That is, the synchronous output circuit 40[1] generates the clock signal CLK[1] so that the rising edge of the clock signal CLK[1] occurs at a timing that is 180 degrees delayed from the rising edge of the clock signal CLK[0] (i.e., with “t U1 / 2" time delay timing).

[0164] The synchronous output circuit 40[2] generates the clock signal CLK[2] by delaying the phase of the clock signal CLK[1] by a predetermined offset SHT[2]. The offset SHT[2] is 90 degrees. That is, the synchronous output circuit 40[2] generates the clock signal CLK[2] so that the rising edge of the clock signal CLK[2] occurs at a timing that is delayed by 90 degrees from the rising edge of the clock signal CLK[1] (i.e., with a “t U1 / 4" time delay timing).

[0165] The synchronous output circuit 40[3] generates the clock signal CLK[3] by delaying the phase of the clock signal CLK[2] by a predetermined offset SHT[3]. The offset SHT[3] is 180 degrees. That is, the synchronous output circuit 40[3] generates the clock signal CLK[3] so that the rising edge of the clock signal CLK[3] occurs at a timing that is 180 degrees delayed from the rising edge of the clock signal CLK[2] (i.e., with a “t U1 / 2" time delay timing).

[0166] like Fig.19 As shown, multi-phase control of four channels can be performed by shifting the phases of the clock signals CLK[0] to CLK[3] from each other.

[0167] Any synchronization output circuit 40[i] determines the offset SHT[i] based on the offset setting information given to the device 10[i]. The external terminal of the device 10[i] may include a dedicated external terminal for specifying the offset setting information, in which case the synchronization output circuit 40[i] can obtain the offset setting information based on the voltage of the dedicated external terminal (the voltage applied to the dedicated external terminal from outside the device 10[i]). Alternatively, the offset setting information can be stored in a memory (not shown) within the device 10[i]. A host system (not shown) connected to the device 10 so that bidirectional communication can be carried out therebetween can write the offset setting information to the memory within the device 10.

[0168] Incidentally, the synchronization output terminal S_OUT of the device 10 (10[n]) at the last stage remains disconnected and is not connected to the synchronization input terminal S_IN of other devices 10. Therefore, in the device 10 at the last stage, during the period ( Fig.12 During the period P12 in the synchronous output terminal S_OUT, the voltage may become unstable, and the level detection signal S DET May also have a value of "1" (see Fig.13 ). This may lead to erroneous recognition that a device 10 at a subsequent stage (virtual device) is outputting a clock signal when viewed from the device 10 at the last stage, although there is no such virtual device.

[0169] Therefore, in the first example, it is preferred to use Fig. 20 The synchronous output circuit 40B is used as the synchronous output circuit 40 of each device 10. The synchronous output circuit 40B has a pull-up resistor 44 added to Figure 8 The configuration of the synchronous output circuit 40A is the same as that of the synchronous output circuit 40A except for this addition. The first end of the pull-up resistor 44 is connected to the application terminal of the power supply voltage VDD and is supplied with the power supply voltage VDD. The second end of the pull-up resistor 44 is connected to the synchronous output terminal S_OUT. In this case, the value of the pull-up resistor 44 is sufficiently greater than Fig. 9 For example, when the resistance of the resistor 54 is 50 kΩ (kilo ohms), the value of the pull-up resistor 44 is set to 5 MΩ (mega ohms).

[0170] As a result, during the period when the synchronous output terminal S_OUT[i] is in the Hi-Z state, when the synchronous input terminal S_IN[i+1] is in the pull-down state, since the potential of the synchronous output terminal S_OUT[i] is approximately 1 / 100 of the power supply voltage VDD (sufficiently lower than the lower limit threshold voltage V THL), so the level determination circuit 60[i] can reliably determine the detection target voltage (at time T3 PRE During the period when the synchronous output terminal S_OUT[i] is in the Hi-Z state, when the synchronous input terminal S_IN[i+1] is in the pull-up state, since the potential of the synchronous output terminal S_OUT[i] is consistent with the power supply voltage VDD, the level determination circuit 60[i] determines the detection target voltage (at time T3 PRE The voltage of the synchronous output terminal S_OUT[i] at ) is at a high level.

[0171] Regarding the device 10[n] at the last stage, during the period in which the synchronous output terminal S_OUT[n] is in the Hi-Z state, the level of the synchronous output terminal S_OUT[i] is maintained at the power supply voltage VDD due to the presence of the pull-up resistor 44, and as a result, the level determination circuit 60[n] determines the detection target voltage (at time T3 PRE The voltage of the synchronous output terminal S_OUT[n] at the output terminal is at a high level, and the level detection signal S is output as "0". DET . Therefore, the above-mentioned misidentification will not occur.

[0172] The value of the pull-up resistor 44 is much larger than the on-resistance value of the transistor 41 and the on-resistance value of the transistor 42. Therefore, in the synchronous output circuit 40B, as in the synchronous output circuit 40A, the output impedance of the synchronous output terminal S_OUT in the Hi-Z state is also sufficiently higher than the output impedance in the low-level output state and the output impedance in the high-level output state. It can be said that the synchronous output circuit 40B as the synchronous output circuit 40[i] outputs a high-level signal from the synchronous output terminal S_OUT[i] in the Hi-Z state with a higher output impedance than in the high-level output state.

[0173] <<Second Example>>

[0174] The second example will be described. The second example and the third to seventh examples described later are examples based on the first example, and unless there is a contradiction, the description in the first example can also apply to the second to seventh examples for matters not specifically described in the second to seventh examples. However, when interpreting the description of the second example, regarding matters inconsistent between the first example and the second example, the description of the second example may take precedence (the same applies to the third to seventh examples described later). Unless there is a contradiction, any multiple examples in the first to seventh examples can be combined.

[0175] In the second example, as in the first example, it is assumed that the synchronization input terminal S_IN of the device 10[1] is disconnected. Therefore, in the second example, the controller 28 of the device 10[1] uses the internal clock signal CLK generated in the device 10[1]. A As the reference clock signal CLK REF To perform switching control of the output stage MM[1].

[0176] Fig.21 A conceptual waveform diagram of a clock signal CLK[i] according to a second example is shown. In the second example, each cycle of any clock signal is considered to start from the falling edge of the clock signal. The synchronous output circuit 40[i] according to the second example switches the state of the synchronous output terminal S_OUT[i] from a high level output state to a low level output state at time T1, then switches the low level output state to a Hi-Z state at time T2, then switches from the Hi-Z state to a high level output state at time T3, and then switches from the high level output state to a low level output state at time T4. Thereafter, the same operation is repeated. When time T1 is the start time of the jth cycle of the clock signal CLK[i], time T4 corresponds to the start time of the (j+1)th cycle of the clock signal CLK[i]. In this case, j represents any natural number.

[0177] As described above, during the output of the clock signal CLK[i], in each cycle of the clock signal CLK[i], the synchronous output circuit 40[i] according to the second example includes a period P21 (in which the state of the synchronous output terminal S_OUT[i] is set to a low-level output state) during which the state of the synchronous output terminal S_OUT[i] is set to a low-level output state. Fig.21 The state of the synchronous output terminal S_OUT[i] is set to the high level output state during the period P23 (between the time T1 and T2 of Fig.21 and the state of the synchronous output terminal S_OUT[i] is set to the Hi-Z state during the period P22 (between the time T3 and T4 of Fig.21 For example, the lengths of time periods P21, P22, and P23 are respectively the unit time t U1 However, the time periods P21, P22 and P23 are in the unit time t U1 The ratio in may be arbitrary. The output pattern of the clock signal CLK[i] according to the second example is referred to as a pattern PTN1b.

[0178] Fig. 22 The waveform of the clock signal CLK[i] when the synchronous input circuit 50[i+1] is in the pull-down state is shown. When the synchronous input circuit 50[i+1] is in the pull-down state, the potential of the clock signal CLK[i] changes from time T2 to time T3.PRE And it is maintained at the ground potential (thus, maintained at the low level) until time T3, and the potential of the clock signal CLK[i] rises sharply from the ground potential to the potential of the power supply voltage VDD at time T3.

[0179] Fig.23 FIG. 5 shows the waveform of the clock signal CLK[i] when the synchronous input circuit 50[i+1] is in the pull-up state. When the synchronous input circuit 50[i+1] is in the pull-up state, since the potential of the clock signal CLK[i] rises from the ground potential to the potential of the power supply voltage VDD after time T2, at time T3 PRE The potential of the power supply voltage VDD rises before that, so the synchronous output terminal S_OUT[i] is at time T3 PRE At has a high level.

[0180] Similar to the first example, when the synchronous output circuit 40[i] outputs the clock signal CLK[i], the level detection circuit 60[i] sets the synchronous output terminal S_OUT[i] at time T3. PRE The voltage at is designated as a detection target voltage, and it is detected whether the detection target voltage belongs to a high level or a low level.

[0181] However, when the level detection circuit 60[i] according to the second example determines that the detection target voltage belongs to the high level, it outputs a level detection signal S1 of "1". DET [i](See Fig.23 ). When the output is the level detection signal S DET [i], then keep "S DET [i]=1” until it is determined that the detection target voltage belongs to the low level. When the level detection circuit 60[i] according to the second example determines that the detection target voltage belongs to the low level, the level detection signal S1 outputted is “0”. DET [i](See Fig. 22 ). When the output is the level detection signal S DET [i], then keep "S DET [i]=0” until it is determined that the detection target voltage belongs to a high level.

[0182] In the second example, regardless of the state of the synchronization input circuit 50[i+1], a falling edge always occurs in the clock signal CLK[i] at time T1. Therefore, by using the falling edge of the clock signal CLK[i], the switching between devices 10[i] and 10[i+1] can be synchronized. To ensure this synchronization, Fig.21In the second example of the pattern PTN1b, the setting edge is a falling edge. That is, when the clock signal CLK[i] of the pattern PTN1b is supplied to the device 10[i+1], the controller 28 of the device 10[i+1] turns on the transistor MH and turns off the transistor ML in response to the falling edge of the clock signal CLK[i].

[0183] In the second example, the following second rule is adopted in each device 10. In the second rule, the relationship between the pull-down state and the pull-up state is opposite to that in the first rule. In other words, the device 10[i] according to the second rule sets the state of the synchronization input terminal S_IN[i] to the pull-up state during the output period of the clock signal CLK[i], and sets the state of the synchronization input terminal S_IN[i] to the pull-down state during the non-output period of the clock signal CLK[i].

[0184] Fig.24 FIG. 1 is a flowchart of the operation of the device 10[1] operating in the first mode. In the second example, the operation of the device 10[1] is the same as that of the device 10[1] except that Fig.17 The processes in steps S10 to S18 shown are the same. That is, in the second example, steps S11, S15, S16, and S17 are replaced with steps S11a, S15a, S16a, and S17a, respectively.

[0185] In step S11a, the synchronous input terminal S_IN[1] is set to the pull-down state. Step S11a is similar to step S11 in other respects. In step S15a, the state of the synchronous input terminal S_IN[1] is changed from the pull-down state to the pull-up state. Step S15a is similar to step S15 in other respects. The processing content of step S16a itself is the same as the processing content of step S16. However, in the second example, “S DET [1]=0" indicates that the synchronous input terminal S_IN[2] is in the pull-down state (see Fig. 22 ). In step S17a, the state of the synchronization input terminal S_IN[1] is changed from the pull-up state to the pull-down state. Step S17a is similar to step S17 in other respects.

[0186] Fig.25 A flow chart showing the operation of device 10[i] operating in a second mode is shown. Fig.25 The variable i in each step shown represents any integer greater than 2. In the second example, the operation of device 10[i] is the same as Fig.18 The processes in steps S20 to S27 shown are the same. That is, in the second example, steps S21, S25, S26, and S27 are replaced with steps S21a, S25a, S26a, and S27a, respectively.

[0187] In step S21a, the synchronous input terminal S_IN[i] is set to the pull-down state. Step S21a is similar to step S21 in other respects. In step S25a, the state of the synchronous input terminal S_IN[i] is changed from the pull-down state to the pull-up state. Step S25a is similar to step S25 in other respects. The processing content of step S26a itself is the same as the processing content of step S26. However, in the second example, “S DET [i]=0" indicates that the synchronous input terminal S_IN[i+1] is in the pull-down state (see Fig. 22 ). In step S27a, the state of the synchronous input terminal S_IN[i] is changed from the pull-up state to the pull-down state. Step S27a is similar to step S27 in other respects.

[0188] In the second example, it is preferred to use Fig.26 The synchronous output circuit 40C is used as the synchronous output circuit 40 of each device 10. The synchronous output circuit 40C has a pull-down resistor 45 added to Figure 8 The configuration of the synchronous output circuit 40A is the same as the synchronous output circuit 40A except for this addition. The first end of the pull-down resistor 45 is grounded, and the second end of the pull-down resistor 45 is connected to the synchronous output terminal S_OUT. In this case, the value of the pull-down resistor 45 is sufficiently greater than Fig. 9 For example, when the resistance of the resistor 54 is 50 kΩ (kilo ohms), the value of the pull-down resistor 45 is set to 5 MΩ (mega ohms).

[0189] As a result, during the period when the synchronous output terminal S_OUT[i] is in the Hi-Z state, when the synchronous input terminal S_IN[i+1] is in the pull-up state, since the potential of the synchronous output terminal S_OUT[i] is approximately 99 / 100 of the power supply voltage VDD (sufficiently higher than the upper limit threshold voltage V THH ), so the level determination circuit 60[i] can reliably determine the detection target voltage (at time T3 PRE During the period when the synchronous output terminal S_OUT[i] is in the Hi-Z state, when the synchronous input terminal S_IN[i+1] is in the pull-down state, since the potential of the synchronous output terminal S_OUT[i] is consistent with the ground potential, the level determination circuit 60[i] determines the detection target voltage (at time T3 PRE The voltage of the synchronous output terminal S_OUT[i] at is at a low level.

[0190] Regarding the device 10[n] at the last stage, during the period in which the synchronous output terminal S_OUT[n] is in the Hi-Z state, the potential of the synchronous output terminal S_OUT[i] is maintained at the ground potential due to the presence of the pull-down resistor 45, and as a result, the level determination circuit 60[n] determines the detection target voltage (at time T3 PRE In other words, the erroneous recognition described in the first example does not occur.

[0191] The value of the pull-down resistor 45 is much larger than the on-resistance value of the transistor 41 and the on-resistance value of the transistor 42. Therefore, in the synchronous output circuit 40C, as in the synchronous output circuit 40A, the output impedance of the synchronous output terminal S_OUT in the Hi-Z state is also sufficiently higher than the output impedance in the low-level output state and the output impedance in the high-level output state. It can be said that the synchronous output circuit 40C as the synchronous output circuit 40[i] outputs a low-level signal from the synchronous output terminal S_OUT[i] in the Hi-Z state with a higher output impedance than in the low-level output state.

[0192] The waveforms of the clock signals CLK[0] to CLK[3] in the 4-channel driving state are similar to Fig.19 . However, in the second example, since the falling edge of the clock signal is used as the setting edge of the controller 28, the timing of the falling edge of the clock signal CLK[i+1] is determined based on the timing of the falling edge of the clock signal CLK[i]. That is, the synchronous output circuit 40[1] generates the clock signal CLK[1] so that the falling edge of the clock signal CLK[1] occurs at a timing that is 180 degrees phase delayed from the falling edge of the clock signal CLK[0] (i.e., with “t U1 Similarly, the synchronous output circuit 40[2] generates the clock signal CLK[2] so that the falling edge of the clock signal CLK[2] occurs at a timing that is phase-delayed by 90 degrees from the falling edge of the clock signal CLK[0] (i.e., with a time delay of “t U1 Similarly, the synchronous output circuit 40[3] generates the clock signal CLK[3] so that the falling edge of the clock signal CLK[3] occurs at a timing that is 180 degrees phase delayed from the falling edge of the clock signal CLK[0] (i.e., with a time delay of “t U1 / 2" time delay timing).

[0193] <<Third Example>>

[0194] The third example will be described. In the first example, Fig.12The pattern PTN1a shown is combined with the first rule. As already mentioned, the device 10[i] according to the first rule sets the state of the synchronization input terminal S_IN[i] to the pull-down state during the output period of the clock signal CLK[i], and sets the state of the synchronization input terminal S_IN[i] to the pull-up state during the non-output period of the clock signal CLK[i]. In the second example, Fig.21 The pattern PTN1b shown is combined with the second rule. As already mentioned, the device 10[i] according to the second rule sets the state of the synchronization input terminal S_IN[i] to the pull-up state during the output period of the clock signal CLK[i], and sets the state of the synchronization input terminal S_IN[i] to the pull-down state during the non-output period of the clock signal CLK[i].

[0195] However, it is possible to use Fig.12 The first variant configuration in which the pattern PTN1a in the image and the second rule are combined. In the first variant configuration, according to the adoption of the second rule, the Fig.26 The synchronous output circuit 40C is used as the synchronous output circuit 40 of each device 10. However, when the synchronous output circuit 40C is used in the first modified configuration, due to the influence of the parasitic capacitance added to the synchronous output terminal S_OUT[n] at the last stage, Fig.12 From time T2 in the figure, the slope of the potential drop of the synchronous output terminal S_OUT[n] becomes smaller, and as a result, Fig.12 Time T3 PRE The potential of the synchronous output terminal S_OUT[n] at φ(n), which should originally be determined to belong to the low level, can be determined to belong to the high level. Therefore, for the pattern PTN1a, it is desirable to adopt the first rule.

[0196] Similarly, one can use Fig.21 The second variant configuration in which the pattern PTN1b in the first rule is combined. In the second variant configuration, according to the adoption of the first rule, it is possible to use Fig. 20 The synchronous output circuit 40B is used as the synchronous output circuit 40 of each device 10. However, when the synchronous output circuit 40B is used in the second modified configuration, due to the influence of the parasitic capacitance added to the synchronous output terminal S_OUT[n] at the last stage, Fig.21 From time T2 in the figure, the slope of the potential rise of the synchronous output terminal S_OUT[n] becomes smaller, and as a result, Fig.21 Time T3 PRE The potential of the synchronous output terminal S_OUT[n] at φ1, which should originally be determined to belong to the high level, can be determined to belong to the low level. Therefore, for the pattern PTN1b, it is desirable to adopt the second rule.

[0197] In the first example or the second example, the output pattern of the clock signal CLK[i] of the synchronous output circuit 40[i] is not limited to the pattern PTN1a or PTN1b. That is, in the first example or the second example, the output pattern of the clock signal CLK[i] can be arbitrary as long as each cycle of the clock signal CLK[i] includes a period in which the state of the synchronous output terminal S_OUT[i] is set to a high-level output state, a period in which the state of the synchronous output terminal S_OUT[i] is set to a low-level output state, and a period in which the synchronous output terminal S_OUT[i] is set to a Hi-Z state. However, considering the ease of various controls, determinations, etc., it is preferable to adopt the pattern PTN1a or PTN1b.

[0198] <<Fourth Example>>

[0199] A fourth example will be described. In the first example or the second example, it is assumed that the clock signal CLK B However, in the first example or the second example, when the clock signal CLK is supplied from an external clock supply circuit (not shown), B When input to the synchronization input terminal S_IN[1] of the device 10[1], in step S18 (see Fig.17 or Fig.24 ), the input clock signal CLK to the synchronous input terminal S_IN[1] can be B Set to clock signal CLK[0] (reference clock signal CLK in device 10[1] REF ). In this case, after the process proceeds from step S18 to step S13, the device 10[1] is connected to the synchronous input terminal S_IN[1] as the input clock signal CLK B The clock signal CLK[0] starts the switching control of the output stage MM[1] synchronously.

[0200] <<Fifth Example>>

[0201] A fifth example will be described. The synchronization timing can be notified from the device 10[i] at the previous stage to the device 10[i+1] at the subsequent stage by the clock signal CLK[i] described above. In the fifth example, a method of transmitting information other than the synchronization timing from the device 10[i] at the previous stage to the device 10[i+1] at the subsequent stage by using the clock signal CLK[i] will be described.

[0202] In each device 10, the synchronous output circuit 40 can output Fig. 27The clock signal CLK[i] of the pattern PTN2a in FIG. 1 will be described. As time passes, times T11, T12, T13, T14, T15, T16, and T17 arrive in this order. The time difference between time T11 and T14 is proportional to the unit time t U2 The time difference between time T14 and T17 is also consistent with the unit time t U2 The time difference between time T11 and T12 and the time difference between time T15 and T16 are consistent with time (t U2 / 4) but can be consistent with time (t U2 The time difference between time T12 and T13, the time difference between time T13 and T15, and the time difference between time T16 and T17 are all related to time (t U2 / 2) but can be consistent with time (t U2 / 2) is slightly different. However, in the clock signal CLK[i] of the pattern PTN2a, the interval between two adjacent rising edges is constant and is consistent with the unit time t U2 Consistent.

[0203] In pattern PTN2a, the state of the synchronous output terminal S_OUT[i] is a low-level output state at time T11, then switches from the low-level output state to the high-level output state at time T12, then switches from the high-level output state to the low-level output state at time T13, then switches from the low-level output state to the high-level output state at time T15, then switches from the high-level output state to the low-level output state at time T16, and then remains in the low-level output state until time T17.

[0204] One cycle of the clock signal CLK[i] of the pattern PTN2a corresponds to the period between time T11 and T17. In the pattern PTN2a, in the case where the period between time T11 and T17 is the jth cycle of the clock signal CLK[i], the period from time T17 (2×t U2 ) is the (j+1)th period of the clock signal CLK[i]. In this case, j represents any natural number. The waveform of the clock signal CLK[i] is the same in each period of the clock signal CLK[i] of the pattern PTN2a.

[0205] In pattern PTN2a, waveforms WV1 and WV2 appear alternately in clock signal CLK[i]. When focusing on the period between time T11 and T17, waveform WV1 is the waveform of clock signal CLK[i] between time T11 and T14, and waveform WV2 is the waveform of clock signal CLK[i] between time T14 and T17.

[0206] As described above, the synchronous output circuit 40[i] sets the state of the synchronous output terminal S_OUT[i] alternately to the low level output state and the high level output state during the output period of the clock signal CLK[i] of the pattern PTN2a, and does not set the state of the synchronous output terminal S_OUT[i] to the Hi-Z state. In this case, the unit time t U2 can be expressed as unit time t U1 The same as, or can be expressed as unit time t U1 Roughly the same (see Fig.12 ). In this case, assuming that “t U2 =t U1 . "

[0207] The pattern determination circuit 70[i] in the arbitrary device 10[i] determines whether the clock signal of the pattern PTN2a is input to the synchronization input terminal S_IN[i] based on the voltage of the synchronization input terminal S_IN[i], and outputs a pattern determination signal S indicating the determination result. PTN [i] The pattern determination circuit 70[i] outputs the pattern determination signal S having a value of "1" only when the clock signal determining the pattern PTN2a is input to the synchronization input terminal S_IN[i]. PTN [i] In other cases, the pattern determination signal S having a value of "0" is output. PTN [i].

[0208] The pattern determination circuit 70[i] determines the time T based on K1 and T K2 The above determination is made based on the voltage of the synchronous input terminal S_IN[i] at the time T. K1 is the time after a predetermined time Δt has passed since a rising edge appears in the signal of the synchronous input terminal S_IN[i], and the time T is determined. K2 is the time after a predetermined time Δt has passed after the next rising edge appears in the signal of the synchronous input terminal S_IN[i]. Fig. 27 In the K1 is a time later than time T12 by a predetermined time Δt, and determines time T K2 is a time later than time T15 by a predetermined time Δt. Fig. 27 In the K1 T 12 Late time (t U2 / 4) and earlier than time T 13 .exist Fig. 27 In the K2 Later than time T 16 And than time T 16 Late time (tU2 / 8) of time. For example, the predetermined time Δt is the unit time t U2 (3 / 8) times.

[0209] When the slave device 10[i] outputs Fig. 27 When the clock signal CLK[i] of the pattern PTN2a shown in FIG. 1 is received by the device 10[i+1] (see Fig.11 ). Therefore, for ease of description, reference will be made to Fig. 27 (See also Fig.11 ) describes the operation of the pattern determination circuit 70[i+1] in detail. Since the output impedance of the synchronous output circuit 40[i] during the output period of the clock signal CLK[i] of the pattern PTN2a is sufficiently smaller than the input impedance of the synchronous input circuit 50[i+1] (compared to the input impedance of the synchronous input circuit 50[i+1]), Fig. 9 ), so the voltage of the synchronous input terminal S_IN[i+1] is basically independent of the state of the synchronous input circuit 50[i+1].

[0210] The pattern determination circuit 70[i+1] determines whether the clock signal CLK[i] has the pattern PTN2a by determining whether the clock signal CLK[i] has a waveform that switches between the waveforms WV1 and WV2 based on the voltage of the synchronization input terminal S_IN[i+1]. More specifically, when the signal level of the synchronization input terminal S_IN[i+1] changes between a high level and a low level, the pattern determination circuit 70[i+1] extracts two consecutive rising edges in the signal of the synchronization input terminal S_IN[i+1] as a first rising edge and a second rising edge. Then, the pattern determination circuit 70[i+1] specifies the level of the synchronization input terminal S_IN[i+1] at a time after a predetermined time Δt has passed since the first rising edge and the level of the synchronization input terminal S_IN[i+1] at a time after a predetermined time Δt has passed since the second rising edge. The pattern determination circuit 70[i+1] determines that the clock signal of the pattern PTN2a is input to the synchronization input terminal S_IN[i+1] only when one of the specified two levels is high and the other is low, and outputs a pattern determination signal S_IN[i+1] of "1". PTN [i+1]; otherwise, the output value is "0" pattern determination signal S PTN [i] One of the time after the predetermined time Δt has passed from the first rising edge and the time after the predetermined time Δt has passed from the second rising edge is the determination time T. K1 , and the other is to determine the time T K2 .

[0211] The synchronous output circuit 40[i] according to the fifth example can selectively output the clock signal CLK[i] of the pattern PTN2a and Fig.12 The clock signal CLK[i] of the pattern PTN1a is shown.

[0212] When the synchronization input terminal S_IN[i+1] is set to a pull-up state by the synchronization input circuit 50[i+1], in the case where the clock signal CLK[i] of the pattern PTN2a consists only of the waveform WV1, the signal waveform appearing at the synchronization input terminal S_IN[i+1] is almost the same when the clock signal CLK[i] has the pattern PTN2b and when the clock signal CLK[i] has the pattern PTN1a. Similarly, when the synchronization input terminal S_IN[i+1] is set to a pull-down state by the synchronization input circuit 50[i+1], in the case where the clock signal CLK[i] of the pattern PTN2a consists only of the waveform WV2, the signal waveform appearing at the synchronization input terminal S_IN[i+1] is almost the same when the clock signal CLK[i] has the pattern PTN2a and when the clock signal CLK[i] has the pattern PTN1a. Therefore, in reality, Fig. 27 As shown, the clock signal CLK[i] of the pattern PTN2a includes waveforms WV1 and WV2.

[0213] In the case where the clock signal CLK[i] has the pattern PTN1a, when the synchronization input terminal S_IN[i+1] is set to the pull-up state, after a predetermined time Δt has passed from the rising edge of the signal of the synchronization input terminal S_IN[i+1], since the signal of the synchronization input terminal S_IN[i+1] always has a high level, the pattern determination signal S PTN [i+1] becomes "0". Similarly, in the case where the clock signal CLK[i] has the pattern PTN1a, when the synchronization input terminal S_IN[i+1] is set to the pull-down state, after a predetermined time Δt has passed from the rising edge of the signal of the synchronization input terminal S_IN[i+1], since the signal of the synchronization input terminal S_IN[i+1] always has a low level, the pattern determination signal S PTN [i+1] becomes "0".

[0214] On the other hand, when the clock signal CLK[i] has the pattern PTN2a, since the clock signal CLK[i] is in the two determined times T regardless of the state of the synchronous input terminal S_IN[i+1], K1 and T K2 One of the levels of the synchronization input terminal S_IN[i+1] at the 1000 MHz is a high level, and the other is a low level, so a pattern determination signal S1 of “1” is generated. PTN [i+1]. Therefore, the pattern determination signal S is "1". PTN [i+1] indicates that the clock signal CLK[i] input to the synchronization input terminal S_IN[i+1] has the pattern PTN2a.

[0215] By using the clock signal CLK[i] having a pattern PTN2a which will be described in detail, switching control can be forcibly performed on all channels.

[0216] The forced output determination circuit in the device 10[1] operating in the first mode determines whether a predetermined forced output condition is satisfied. In this case, it is assumed that when a clock signal having a predetermined duty cycle is input to the synchronization input terminal S_IN[1], the forced output condition is satisfied, and when a clock signal having a predetermined duty cycle is not input to the synchronization input terminal S_IN[1], the forced output condition is not satisfied. In this case, the forced output determination circuit may be a pattern determination circuit 70[1] or a switch control circuit 20[1]. The predetermined duty cycle is a duty cycle within a certain range, and in this case, as an example, it is assumed that the predetermined duty cycle is greater than 40% and less than 60%. The duty cycle of a clock signal refers to the ratio of the high level period of the relevant clock signal to the sum of the high level period and the low level period of the relevant clock signal.

[0217] Alternatively, the forced output setting information may be stored in a memory (not shown) in the device 10[1]. In this case, when the forced output setting information in the memory is "1", the forced output condition is satisfied, and when the forced output setting information in the memory is "0", the forced output condition is not satisfied. A host system (not shown) connected to the device 10 so that bidirectional communication can be performed therebetween may write "1" or "0" in the forced output setting information in the memory in the device 10[1].

[0218] The fifth example can be implemented in combination with the first example as described below. In the fifth example, the first rule described in the first example is adopted, and the setting edge is a rising edge. That is, the controller 28 of the device 10[i+1] turns on the transistor MH and turns off the transistor ML in response to the rising edge of the clock signal CLK[i]. In the fifth example combined with the first example, it is preferred to use Fig. 20 The synchronous output circuit 40B serves as the synchronous output circuit 40 of each device 10.

[0219] Consider the case FORCE_ON, in which after device 10[1] is activated, the clock signal CLK with a 50% duty cycle B The input clock signal CLK to the synchronous input terminal S_IN[1] of the device 10[1] is input from an external clock supply circuit (not shown). In this case, the forced output condition is satisfied. In the case of FORCE_ON, the input clock signal CLK to the synchronous input terminal S_IN[1] is B As the reference clock signal CLK REFis input to the controller 28 of the device 10[1]. For ease of description, the reference clock signal CLK supplied to the controller 28 of the device 10[1] REF It can be referred to as the clock signal CLK[0]. In the case of FORCE_ON, the output stage MM[1] switches synchronously with the clock signal CLK[0]. That is, in response to the input clock signal CLK B At the rising edge of the clock signal CLK[0], the transistor MH of the output stage MM[1] is turned on and the transistor ML thereof is turned off.

[0220] When switching control is performed in device 10[1] in the case of FORCE_ON, whether the clock output condition ( Fig.17 The clock output condition in step S14 in step S14 is obtained by the clock management circuit 80[1] controlling the synchronous output circuit 40[1] to make the synchronous output circuit 40[1] output the clock signal CLK[1] having the pattern PTN2a from the synchronous output terminal S_OUT[1]. Based on the reference clock signal CLK of the device 10[1] REF (ie, clock signal CLK[0]) generates clock signal CLK[1] having pattern PTN2a.

[0221] When the clock signal CLK[1] having the pattern PTN2a is input to the synchronization input terminal S_IN[2], the clock signal CLK[1] having the pattern PTN2a serves as the reference clock signal CLK of the device 10[2]. REF is input to the controller 28 of the device 10[2]. Therefore, the output stage MM[2] switches synchronously with the clock signal CLK[1]. That is, in response to the rising edge of the clock signal CLK[1] having the pattern PTN2a, the transistor MH of the output stage MM[2] is turned on and the transistor ML thereof is turned off.

[0222] Furthermore, when the clock signal CLK[1] having the pattern PTN2a is input to the synchronization input terminal S_IN[2], the pattern determination signal S PTN [2] has a value of "1". PTN [2]=1”, regardless of whether the clock output condition ( Fig.18 The clock output condition in step S24 in step S24 is obtained by the clock management circuit 80[2] controlling the synchronous output circuit 40[2] to cause the synchronous output circuit 40[2] to output the clock signal CLK[2] having the pattern PTN2a from the synchronous output terminal S_OUT[2]. The clock signal CLK[2] having the pattern PTN2a is based on the reference clock signal CLK of the device 10[2]. REF (i.e., the input clock signal CLK[1] to device 10[2]).

[0223] The operation of other devices 10 (e.g., device 10[3]) operating in the second mode is similar to the operation of device 10[2]. That is, for example, when the clock signal CLK[2] having the pattern PTN2a is input to the synchronization input terminal S_IN[3], the clock signal CLK[2] having the pattern PTN2a serves as the reference clock signal CLK of device 10[3]. REF is input to the controller 28 of the device 10[3]. Therefore, the output stage MM[3] switches synchronously with the clock signal CLK[2]. That is, in response to the rising edge of the clock signal CLK[2] having the pattern PTN2a, the transistor MH of the output stage MM[3] is turned on and the transistor ML thereof is turned off.

[0224] Furthermore, when the clock signal CLK[2] having the pattern PTN2a is input to the synchronization input terminal S_IN[3], the pattern determination signal S PTN [3] has a value of "1". PTN [3]=1”, regardless of whether the clock output condition ( Fig.18 The clock output condition in step S24 in step S24 is obtained by the clock management circuit 80[3] controlling the synchronous output circuit 40[3] to output the clock signal CLK[3] having the pattern PTN2a from the synchronous output terminal S_OUT[3]. The clock signal CLK[3] having the pattern PTN2a is based on the reference clock signal CLK of the device 10[3]. REF (i.e., the input clock signal CLK[2] to device 10[3]).

[0225] The same applies to devices 10[4] to 10[n]. Therefore, in case of FORCE_ON, switching control is performed in devices 10 of all channels regardless of whether the clock output condition is satisfied.

[0226] The operation of device 10[1] when the forced output condition is not met is the same as Fig.17 The operation is the same as shown in FIG. 1 , and the operation of each device 10[2] to 10[n] when the forced output condition is not satisfied is the same as Fig.18The operation shown is the same. However, when the forced output condition is not met, the clock signal CLK[i] that can be output from the device 10[i] has the same pattern PTN1a as in the first example. Therefore, when the forced output condition is not met, when the clock signal CLK[1] is not supplied to the synchronization input terminal S_IN[2], the synchronization output circuit 40[2] of the device 10[2] does not output any clock signal (keeping the synchronization output terminal S_OUT[2] in the Hi-Z state). When the forced output condition is not met, when the clock signal CLK[1] of the pattern PTN1a is supplied to the synchronization input terminal S_IN[2], the device 10[2] performs switching control synchronously with the clock signal CLK[1]. When the clock output condition is met in the device 10[2], the synchronization output circuit 40[2] outputs the clock signal CLK[2] of the pattern PTN1a based on the clock signal CLK[1] (the input clock signal CLK[1] to the device 10[2]) from the synchronization output terminal S_OUT[2]. The same applies to other devices 10 operating in the second mode (eg, device 10 [3]).

[0227] In the device 10[1] operating in the first mode, when the forced output condition is not satisfied, after the synchronous output circuit 40[1] starts outputting the clock signal CLK[1] of the pattern PTN1a, in response to the clock stop condition ( Fig.17 When the clock stop condition in step S16 in the process is satisfied, the output of the clock signal CLK[1] of the pattern PTN1a is stopped.

[0228] When the forced output condition is not satisfied, the clock signal CLK[1] of the pattern PTN1a may be supplied to the synchronization input terminal S_IN[2]. In the device 10[2] operating in the second mode, when the clock signal CLK[1] of the pattern PTN1a is supplied to the synchronization input terminal S_IN[2], after the synchronization output circuit 40[2] starts outputting the clock signal CLK[2] of the pattern PTN1a, in response to the clock stop condition ( Fig.18 When the clock stop condition in step S26 in the second mode is satisfied, the output of the clock signal CLK[2] of the pattern PTN1a is stopped. The same applies to other devices 10 (eg, device 10[3]) operating in the second mode.

[0229] Fig.28 1 shows the waveforms of clock signals CLK[0] to CLK[3] in a 4-channel driving state in the case of FORCE_ON. In the case of FORCE_ON, the clock signal CLK[0] supplied from the external clock supply circuit (not shown) to the device 10[1] is a rectangular wave signal with a duty cycle of 50%, and the length of one cycle of the clock signal CLK[0] is the unit time tU2 .

[0230] In the 4-channel driving state associated with the condition FORCE_ON, the clock signals CLK[0] to CLK[3] are the reference clock signals CLK in devices 10[1] to 10[4], respectively. REF . Therefore, the controller 28 of the device 10[1] turns on the transistor MH of the output stage MM[1] and turns off its transistor ML in response to the rising edge of the clock signal CLK[0]. The controller 28 of the device 10[2] turns on the transistor MH of the output stage MM[2] and turns off its transistor ML in response to the rising edge of the clock signal CLK[1]. The controller 28 of the device 10[3] turns on the transistor MH of the output stage MM[3] and turns off its transistor ML in response to the rising edge of the clock signal CLK[2]. The controller 28 of the device 10[4] turns on the transistor MH of the output stage MM[4] and turns off its transistor ML in response to the rising edge of the clock signal CLK[3].

[0231] In the case of FORCE_ON, the synchronous output circuit 40[1] generates the clock signal CLK[1] based on the clock signal CLK[0]. At this time, the synchronous output circuit 40[1] generates the clock signal CLK[1] so that the time from the time when the rising edge of the clock signal CLK[0] appears is delayed by the offset SHT[1] to the time T12 of the clock signal CLK[1] (see also Fig. 27 ).

[0232] In the case of FORCE_ON, the synchronous output circuit 40[2] generates the clock signal CLK[2] based on the clock signal CLK[1]. At this time, the synchronous output circuit 40[2] generates the clock signal CLK[2] so that the time from the time when the rising edge of the clock signal CLK[1] appears is delayed by the offset SHT[2] to the time T12 of the clock signal CLK[2] (see also Fig. 27 ).

[0233] In the case of FORCE_ON, the synchronous output circuit 40[3] generates the clock signal CLK[3] based on the clock signal CLK[2]. At this time, the synchronous output circuit 40[3] generates the clock signal CLK[3] so that the time from the time when the rising edge of the clock signal CLK[2] appears is delayed by the offset SHT[3] to the time T12 of the clock signal CLK[3] (see also Fig. 27 ).

[0234] The offsets SHT[1], SHT[2] and SHT[3] are respectively related to the time (t U2 / 2), time (t U2 / 4) and time (t U2As a result, since the phases of the clock signals CLK[0] to CLK[3] are shifted from each other (the rising edge timings of the clock signals CLK[0] to CLK[3] are shifted from each other), multi-phase control of four channels is performed.

[0235] <<Sixth Example>>

[0236] A sixth example will be described. The fifth example can be modified in the same manner as the case of changing the first example to the second example. That is, in each device 10 according to the sixth example, the synchronous output circuit 40 may be capable of outputting Fig.29 The clock signal CLK[i] of the pattern PTN2b corresponds to the inversion of the clock signal CLK[i] of the pattern PTN2a according to the fifth example. The sixth example is a partial variation of the fifth example, and unless there is a contradiction, the description in the fifth example can be applied to the sixth example with respect to matters not described in the sixth example.

[0237] Pattern PTN2b will be described. The relationship between time T11 to T17 is as described in the fifth example. However, the state of the synchronous output terminal S_OUT[i] is reversed between patterns PTN2a and PTN2b. That is, in pattern PTN2b, the state of the synchronous output terminal S_OUT[i] is a high-level output state at time T11, then switches from the high-level output state to the low-level output state at time T12, then switches from the low-level output state to the high-level output state at time T13, then switches from the high-level output state to the low-level output state at time T15, then switches from the low-level output state to the high-level output state at time T16, and then remains in the high-level output state until time T17.

[0238] One cycle of the clock signal CLK[i] of the pattern PTN2b corresponds to the period between time T11 and T17. In the pattern PTN2b, when the period between time T11 and T17 is the jth cycle of the clock signal CLK[i], the period from time T17 (2×t U2 ) is the (j+1)th period of the clock signal CLK[i]. In this case, j represents any natural number. The waveform of the clock signal CLK[i] is the same in each period of the clock signal CLK[i] of the pattern PTN2b.

[0239] In pattern PTN2b, waveforms WV3 and WV4 appear alternately in clock signal CLK[i]. When focusing on the period between time T11 and T17, waveform WV3 is the waveform of clock signal CLK[i] between time T11 and T14, and waveform WV4 is the waveform of clock signal CLK[i] between time T14 and T17.

[0240] As described above, the synchronous output circuit 40[i] sets the state of the synchronous output terminal S_OUT[i] alternately to the low level output state and the high level output state during the output period of the clock signal CLK[i] of the pattern PTN2b, and does not set the state of the synchronous output terminal S_OUT[i] to the Hi-Z state. In this case, the unit time t U2 can be expressed as unit time t U1 The same as, or can be expressed as unit time t U1 Roughly the same (see Fig.21 ). In this case, assuming that “t U2 =t U1 . "

[0241] The operation of the pattern determination circuit 70 according to the sixth example is similar to that of the fifth example. However, when the description of the fifth example is applied to the sixth example, the waveform symbols "WV1" and "WV2" in the fifth example are read as "WV3" and "WV4" in the sixth example, respectively. The pattern symbol "PTN2a" in the fifth example is read as "PTN2b" in the sixth example.

[0242] The pattern determination circuit 70[i] determines whether the clock signal of the pattern PTN2b is input to the synchronization input terminal S_IN[i] based on the voltage of the synchronization input terminal S_IN[i], and outputs a pattern determination signal S_IN[i] indicating the determination result. PTN [i] At this time, the pattern determination circuit 70[i] determines the time T based on K1 and T K2 The above determination is performed based on the voltage of the synchronous input terminal S_IN[i] at the sixth example. In the sixth example, the processing of the rising edge and the falling edge is opposite to that of the fifth example. In other words, in the sixth example, the time T is determined. K1 is the time after a predetermined time Δt has passed since a falling edge appears in the signal of the synchronous input terminal S_IN[i], and the time T is determined. K2 It is the time after a predetermined time Δt has passed after the next falling edge appears in the signal of the synchronous input terminal S_IN[i].

[0243] When the slave device 10[i] outputs Fig.29 When the clock signal CLK[i] of the pattern PTN2b shown in FIG. 1 is received by the device 10[i+1] (see Fig.11 ). Therefore, when focusing on the operation of the pattern determination circuit 70[i+1] in the device 10[i+1], the operation of the pattern determination circuit 70[i+1] is as follows.

[0244] The pattern determination circuit 70[i+1] determines whether the clock signal CLK[i] has the pattern PTN2b by determining whether the clock signal CLK[i] has a waveform that switches between waveforms WV3 and WV4 based on the voltage of the synchronization input terminal S_IN[i+1]. More specifically, when the signal level of the synchronization input terminal S_IN[i+1] changes between a high level and a low level, the pattern determination circuit 70[i+1] extracts two consecutive falling edges in the signal of the synchronization input terminal S_IN[i+1] as a first falling edge and a second falling edge. Then, the pattern determination circuit 70[i+1] specifies the level of the synchronization input terminal S_IN[i+1] at a time after a predetermined time Δt has passed since the first falling edge and the level of the synchronization input terminal S_IN[i+1] at a time after a predetermined time Δt has passed since the second falling edge. The pattern determination circuit 70[i+1] determines that the clock signal of the pattern PTN2b is input to the synchronization input terminal S_IN[i+1] only when one of the specified two levels is high and the other is low, and outputs a pattern determination signal S_IN[i+1] of "1". PTN [i+1]; otherwise, the output value is "0" pattern determination signal S PTN [i] One of the time after the predetermined time Δt has passed from the first falling edge and the time after the predetermined time Δt has passed from the second falling edge is the determination time T K1 , and the other is to determine the time T K2 .

[0245] The synchronous output circuit 40[i] according to the sixth example can selectively output the clock signal CLK[i] of the pattern PTN2b and Fig.21 The pattern PNT1b is shown as the clock signal CLK[i].

[0246] In the case where the clock signal CLK[i] has the pattern PTN1b, when the synchronization input terminal S_IN[i+1] is set to the pull-up state, after a predetermined time Δt has passed from the falling edge of the signal of the synchronization input terminal S_IN[i+1], since the signal of the synchronization input terminal S_IN[i+1] always has a high level, the pattern determination signal S PTN [i+1] becomes "0". Similarly, in the case where the clock signal CLK[i] has the pattern PTN1b, when the synchronization input terminal S_IN[i+1] is set to the pull-down state, after a predetermined time Δt has passed from the falling edge of the signal of the synchronization input terminal S_IN[i+1], since the signal of the synchronization input terminal S_IN[i+1] always has a low level, the pattern determination signal S PTN [i+1] becomes "0".

[0247] On the other hand, when the clock signal CLK[i] has the pattern PTN2b, since the clock signal CLK[i] is in the two determined times T regardless of the state of the synchronization input terminal S_IN[i+1], K1 and T K2 One of the levels of the synchronization input terminal S_IN[i+1] at the 1000 MHz is a high level, and the other is a low level, so a pattern determination signal S1 of “1” is generated. PTN [i+1]. Therefore, the pattern determination signal S is "1". PTN [i+1] indicates that the clock signal CLK[i] input to the synchronization input terminal S_IN[i+1] has the pattern PTN2b.

[0248] Similar to the fifth example, switching control can be forcibly performed on all channels by using the clock signal CLK[i] having the pattern PTN2b. The matters regarding the forced output condition described in the fifth example also apply to the sixth example.

[0249] The sixth example can be implemented in combination with the second example as described below. In the sixth example, the second rule described in the second example is adopted, and the setting edge is the falling edge. That is, the controller 28 of the device 10[i+1] turns on the transistor MH and turns off the transistor ML in response to the falling edge of the clock signal CLK[i]. Therefore, when the description of the fifth example is applied to the sixth example, the "rising edge" in the fifth example can be read as the "falling edge" in the sixth example. In addition, in the sixth example combined with the second example, it is preferred to use Fig.26 The synchronous output circuit 40C serves as the synchronous output circuit 40 of each device 10.

[0250] When switching control is performed in device 10[1] in the case of FORCE_ON, whether the clock output condition ( Fig.24 The clock output condition in step S14 in step S14 is obtained by the clock management circuit 80[1] controlling the synchronous output circuit 40[1] to make the synchronous output circuit 40[1] output the clock signal CLK[1] having the pattern PTN2b from the synchronous output terminal S_OUT[1]. Based on the reference clock signal CLK of the device 10[1] REF (ie, clock signal CLK[0]) generates clock signal CLK[1] having pattern PTN2b.

[0251] When the clock signal CLK[1] having the pattern PTN2b is input to the synchronization input terminal S_IN[2], the clock signal CLK[1] having the pattern PTN2b serves as the reference clock signal CLK of the device 10[2]. REFis input to the controller 28 of the device 10[2]. Therefore, the output stage MM[2] switches synchronously with the clock signal CLK[1]. That is, in response to the falling edge of the clock signal CLK[1] having the pattern PTN2b, the transistor MH of the output stage MM[2] is turned on and the transistor ML thereof is turned off.

[0252] Furthermore, when the clock signal CLK[1] having the pattern PTN2b is input to the synchronization input terminal S_IN[2], the pattern determination signal SPTN[2] has a value of "1". PTN [2]=1”, regardless of whether the clock output condition ( Fig.25 The clock output condition in step S24 in step S24 is obtained by the clock management circuit 80[2] controlling the synchronous output circuit 40[2] to output the clock signal CLK[2] having the pattern PTN2b from the synchronous output terminal S_OUT[2]. The clock signal CLK[2] having the pattern PTN2b is based on the reference clock signal CLK of the device 10[2]. REF (i.e., the input clock signal CLK[1] to device 10[2]).

[0253] The operation of other devices 10 (e.g., device 10[3]) operating in the second mode is similar to the operation of device 10[2]. That is, for example, when the clock signal CLK[2] having the pattern PTN2b is input to the synchronization input terminal S_IN[3], the clock signal CLK[2] having the pattern PTN2b serves as the reference clock signal CLK of device 10[3]. REF is input to the controller 28 of the device 10[3]. Therefore, the output stage MM[3] switches synchronously with the clock signal CLK[2]. That is, in response to the falling edge of the clock signal CLK[2] having the pattern PTN2b, the transistor MH of the output stage MM[3] is turned on and the transistor ML thereof is turned off.

[0254] Furthermore, when the clock signal CLK[2] having the pattern PTN2b is input to the synchronization input terminal S_IN[3], the pattern determination signal S PTN [3] has a value of "1". PTN [3]=1”, regardless of whether the clock output condition ( Fig.25 The clock output condition in step S24 in step S24 is obtained by the clock management circuit 80[3] controlling the synchronous output circuit 40[3] to output the clock signal CLK[3] having the pattern PTN2b from the synchronous output terminal S_OUT[3]. The clock signal CLK[3] having the pattern PTN2b is based on the reference clock signal CLK of the device 10[3]. REF(i.e., the input clock signal CLK[2] to device 10[3]).

[0255] The same applies to devices 10[4] to 10[n]. Therefore, in case of FORCE_ON, switching control is performed in devices 10 of all channels regardless of whether the clock output condition is satisfied.

[0256] The operation of device 10[1] when the forced output condition is not met is the same as Fig.24 The operation is the same as shown in FIG. 1 , and the operation of each device 10[2] to 10[n] when the forced output condition is not satisfied is the same as Fig.25 The operation shown is the same. However, when the forced output condition is not satisfied, the clock signal CLK[i] that can be output from the device 10[i] has the same pattern PTN1b as in the second example. Therefore, when the forced output condition is not satisfied, when the clock signal CLK[1] is not supplied to the synchronization input terminal S_IN[2], the synchronization output circuit 40[2] of the device 10[2] does not output any clock signal (keeping the synchronization output terminal S_OUT[2] in the Hi-Z state). When the forced output condition is not satisfied, when the clock signal CLK[1] of the pattern PTN1b is supplied to the synchronization input terminal S_IN[2], the device 10[2] performs switching control synchronously with the clock signal CLK[1]. When the clock output condition is satisfied in the device 10[2], the synchronization output circuit 40[2] outputs the clock signal CLK[2] of the pattern PTN1b based on the clock signal CLK[1] (the input clock signal CLK[1] to the device 10[2]) from the synchronization output terminal S_OUT[2]. The same applies to other devices 10 operating in the second mode (eg, device 10 [3]).

[0257] In the device 10[1] operating in the first mode, when the forced output condition is not satisfied, after the synchronous output circuit 40[1] starts outputting the clock signal CLK[1] of the pattern PTN1b, in response to the clock stop condition ( Fig.24 When the clock stop condition in step S16a in FIG. 1 is satisfied, the output of the clock signal CLK[1] of the pattern PTN1b is stopped.

[0258] When the forced output condition is not satisfied, the clock signal CLK[1] of the pattern PTN1b may be supplied to the synchronization input terminal S_IN[2]. In the device 10[2] operating in the second mode, when the clock signal CLK[1] of the pattern PTN1b is supplied to the synchronization input terminal S_IN[2], after the synchronization output circuit 40[2] starts outputting the clock signal CLK[2] of the pattern PTN1b, in response to the clock stop condition ( Fig.25When the clock stop condition in step S26a in the second mode is satisfied, the output of the clock signal CLK[2] of the pattern PTN1b is stopped. The same applies to other devices 10 (eg, device 10[3]) operating in the second mode.

[0259] For convenience, the waveforms of the clock signals CLK[0] to CLK[3] in the 4-channel driving state in the case of FORCE_ON according to the sixth example are referred to as the clock signal CLK[0] to CLK[3]. EX6 To CLK[3] EX6 For convenience, the waveforms of the clock signals CLK[0] to CLK[3] in the 4-channel driving state in the case of FORCE_ON according to the fifth example are referred to as the clock signal CLK[0] EX5 To CLK[3] EX5 . Clock signal CLK[0] EX5 To CLK[3] EX5 yes Fig.28 In the sixth example, the setting edge corresponds to the falling edge, and for an integer i from 0 to 3, the clock signal CLK[i] EX6 Can be clock signal CLK[i] EX5 reversal.

[0260] <<Seventh Example>>

[0261] A seventh example will be described.

[0262] exist Figure 1 and Figure 3 In the switching power supply 1, the device 10[1] operates in the first mode, and the devices 10[2] to 10[n] operate in the second mode. Therefore, the operation of the device 10[1] has been described as the operation of the device 10 in the first mode, and the operation of the devices 10[2] to 10[n] has been described as the operation of the device 10 in the second mode. However, depending on how each device 10 is incorporated into the switching power supply 1, each device 10 can operate in the first mode or the second mode. That is, depending on the operation mode, each device 10 can implement the operation of the device 10[1] or the operation of any one of the devices 10[2] to 10[n].

[0263] Therefore, in an arbitrary device 10[i] of interest (hereinafter referred to as the device 10[i] of interest), the switch control circuit 20[i]:

[0264] When the device 10[i] of interest operates in the first mode, the clock signal CLK A Or based on the input clock signal CLK B The reference clock signal CLK REFThe switching control of the output stage MM[i] is carried out synchronously,

[0265] When the device 10[i] of interest operates in the second mode and inputs the clock signal CLK B When the synchronous input terminal S_IN[i] is not supplied, the switching control of the output stage MM[i] is stopped, and

[0266] When the device 10[i] of interest operates in the second mode and inputs the clock signal CLK B When supplied to the synchronous input terminal S_IN[i], it is synchronized with the input clock signal CLK B The reference clock signal CLK REF The switching control of the output stage MM[i] is carried out synchronously.

[0267] Furthermore, for example, in the device 10[i] of interest according to the fifth example or the sixth example, the synchronous output circuit 40[i]:

[0268] When the device 10[i] of interest operates in the first mode and the forced output condition is not satisfied, in response to the establishment of the clock output condition during the execution period of the switch control of the output stage MM[i], a clock based on the reference clock signal CLK is output from the synchronous output terminal S_OUT[i]. REF The first pattern (PTN1a or PTN1b) outputs a clock signal CLK[i],

[0269] When the device 10[i] of interest operates in the first mode and satisfies the forced output condition, a clock based on the reference clock signal CLK is output from the synchronous output terminal S_OUT[i] regardless of whether the clock output condition is satisfied during the execution period of the switch control of the output stage MM[i]. REF The second pattern (PTN2a or PTN2b) outputs a clock signal CLK[i],

[0270] When the device 10[i] of interest operates in the second mode and inputs the clock signal CLK B When (CLK[i]) is not supplied to the synchronization input terminal S_IN[i], neither the first pattern output clock signal nor the second pattern output clock signal is output from the synchronization output terminal S_OUT[i],

[0271] When the device 10[i] of interest operates in the second mode and the first pattern (PTN1a or PTN1b) inputs the clock signal CLK BWhen (CLK[i-1]) is supplied to the synchronization input terminal S_IN[i], in response to the establishment of the clock output condition during the execution period of the switch control of the output stage MM[i], a clock based on the input clock signal CLK is output from the synchronization output terminal S_OUT[i]. B The first pattern (PTN1a or PTN1b) of (CLK[i-1]) outputs the clock signal CLK[i], and

[0272] When the device 10[i] of interest operates in the second mode and the second pattern (PTN2a or PTN2b) inputs the clock signal CLK B When (CLK[i-1]) is supplied to the synchronization input terminal S_IN[i], a clock based on the input clock signal CLK is output from the synchronization output terminal S_OUT[i] regardless of whether the clock output condition is satisfied during the execution period of the switch control of the output stage MM[i]. B The second pattern (PTN2a or PTN2b) outputs the clock signal CLK[i].

[0273] Various other operations are similarly understood.

[0274] In the above description, it is assumed that the electronic components including only one device 10 are configured in one housing, but the electronic components including two or more devices 10 may be configured in one housing. That is, for example, when "n=4", a first electronic component (first semiconductor device) formed by accommodating the devices 10[1] and 10[2] in a common first housing and a second electronic component (second semiconductor device) formed by accommodating the devices 10[3] and 10[4] in another common second housing may be provided in the switch controller 1. Even in this case, when the method of each of the above examples is used, information other than the synchronization clock signal may be transmitted between the first electronic component and the second electronic component by using the terminals S_OUT[2] and S_IN[3].

[0275] When switching control is performed by two or more devices 10 in the switching power supply 1, it is not necessary to shift the phases of the switching control in the two or more devices 10 from each other. Therefore, for example, in the above-mentioned 4-channel driving state, the phases of the clock signals CLK[0] to CLK[3] can be the same. That is, for example, when the setting edge is a rising edge, the rising edges of the clock signals CLK[0] to CLK[3] can occur simultaneously in the 4-channel driving state. Similarly, for example, when the setting edge is a falling edge, the falling edges of the clock signals CLK[0] to CLK[3] can occur simultaneously in the 4-channel driving state.

[0276] Alternatively, for example, when the setting edge is a rising edge, in the 4-channel driving state, the rising edges of the clock signals CLK[0] and CLK[2] may occur simultaneously, the rising edges of the clock signals CLK[1] and CLK[3] may occur simultaneously, and the timing of the rising edge of the clock signal CLK[0] and the timing of the rising edge of the clock signal CLK[1] may be different from each other. Similarly, for example, when the setting edge is a falling edge, in the 4-channel driving state, the falling edges of the clock signals CLK[0] and CLK[2] may occur simultaneously, the falling edges of the clock signals CLK[1] and CLK[3] may occur simultaneously, and the timing of the falling edge of the clock signal CLK[0] and the timing of the falling edge of the clock signal CLK[1] may be different from each other.

[0277] The DC / DC converter of each channel constituting the above-described switching power supply 1 is a step-down DC / DC converter, but may be a step-up or step-up / step-down DC / DC converter.

[0278] For any signal or voltage, the relationship between the high level and the low level can be reversed from that described above without impairing the above characteristics.

[0279] The channel type of the field effect transistor (FET) shown in each embodiment is just an example. Without impairing the above-mentioned characteristics, the channel type of any FET can be changed between the P-channel type and the N-channel type.

[0280] Any of the above transistors can be any type of transistor as long as it does not cause any inconvenience. For example, any of the above transistors as MOSFET can be replaced by a junction FET, an insulated gate bipolar transistor (IGBT) or a bipolar transistor as long as it does not cause any inconvenience. Any transistor includes a first electrode, a second electrode and a control electrode. In a FET, one of the first electrode and the second electrode is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first electrode and the second electrode is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first electrode and the second electrode is a collector, the other is an emitter, and the control electrode is a base.

[0281] The embodiments of the present invention may be appropriately modified in various ways within the scope of the technical features of the claims. The above embodiments are merely examples of embodiments of the present invention, and the meanings or configuration requirements of the terms of the present invention are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and needless to say, these values ​​may be changed to various numerical values.

[0282] <<Additional Notes>>

[0283] Supplementary notes will be provided to the present invention in which specific configuration examples are shown in the above-mentioned embodiments.

[0284] A power supply controller according to one aspect of the present invention is a power supply controller (10) configured to receive an input voltage (V IN ) generates an output voltage (V OUT ) in a switching power supply (1) and having a configuration (first configuration) comprising: a synchronous input terminal (S_IN); a synchronous output terminal (S_OUT); an output stage (MM) configured to convert an input voltage power into an output voltage; a switch control circuit (20) configured to generate a synchronous output voltage by a reference clock signal (CLK REF ) synchronously performs switch control of the output stage to convert the input voltage power into the output voltage; a synchronous output circuit (40), which is configured to set the state of the synchronous output terminal to any one of a plurality of output states including a first output state, a second output state and a third output state; and a synchronous input circuit (50), which is configured to set the state of the synchronous input terminal to any one of a plurality of input states including a first input state and a second input state, wherein the synchronous output circuit outputs a signal of a first level (low level) from the synchronous output terminal in the first output state (low level output state), and outputs a signal of a second level (high level) higher than the first level from the synchronous output terminal in the second output state (high level output state), and the output impedance of the synchronous output circuit is set to be higher in the third output state (Hi-z state) than in the first output state and the second output state, and wherein the synchronous input circuit is capable of pulling down the synchronous input terminal to the first level or pulling up the synchronous input terminal to the second level via a resistor (54), pulling down the synchronous input terminal in the first input state (pull-down state), and pulling up the synchronous input terminal in the second input state (pull-up state).

[0285] According to the above configuration, by connecting the synchronization output terminal of the first power controller and the synchronization input terminal of the second power controller and switching the state of the synchronization output terminal of the first power controller, the clock signal for synchronization can be supplied to the synchronization input terminal of the second power controller. At this time, the synchronization input circuit of the second power controller selectively pulls down or pulls up the synchronization input terminal, so that when the synchronization output terminal of the first power controller is in the third output state, information can be transmitted from the second power controller to the first power controller. That is, information can be transmitted from the second power controller to the first power controller by using the synchronization terminal (synchronization output terminal and synchronization input terminal) without providing a dedicated terminal for information transmission. By using this information, the switching power supply can be properly operated.

[0286] The power supply controller of the first configuration may have a configuration (second configuration) further comprising: a mode setting circuit (30) configured to set the operation mode of the power supply controller to the first mode or the second mode based on given mode setting information, wherein the switch control circuit is configured to: in the first mode, based on the internal clock signal (CLK A ) or an input clock signal (CLK) supplied to the synchronization input terminal from outside the power supply controller B ), the switch control is performed synchronously with the reference clock signal; in the second mode, when the input clock signal is not supplied to the synchronization input terminal, the switch control is stopped; and in the second mode, when the input clock signal is supplied to the synchronization input terminal, the switch control is performed synchronously with the reference clock signal based on the input clock signal.

[0287] When multiple power controllers are cascade-connected, the first-stage power controller can operate in the first mode, while the other power controllers can operate in the second mode. At this time, information can be sent from the power controller at the rear stage to the power controller at the front stage by using the synchronization terminals (synchronization output terminal and synchronization input terminal).

[0288] The power supply controller of the second configuration may have a configuration (third configuration) in which the synchronous output circuit responds to the establishment of a predetermined clock output condition (e.g., Fig.17 Y in S14, Fig.18 The output clock signal based on the reference clock signal is output from the synchronous output terminal (see S24 in S25). Fig.12 or Fig.21 ), in each cycle of the output clock signal, the synchronous output circuit includes a first time period in which the state of the synchronous output terminal is set to a first output state, a second time period in which the state of the synchronous output terminal is set to a second output state, and a third time period in which the state of the synchronous output terminal is set to a third output state.

[0289] The power supply controller of the third configuration may have a configuration (fourth configuration) in which the synchronization input circuit sets the state of the synchronization input terminal to one of the first input state and the second input state (pull-down state / pull-up state) during an output period of the output clock signal, and sets the state of the synchronization input terminal to the other of the first input state and the second input state (pull-up state / pull-down state) during a non-output period of the output clock signal.

[0290] The power supply controller of the fourth configuration may have a configuration (fifth configuration), which also includes: a level detection circuit (60) connected to a synchronous output terminal, wherein when the synchronous output circuit outputs an output clock signal, the level detection circuit detects whether the voltage of the synchronous output terminal in a third time period belongs to the first level or the second level.

[0291] Based on the detection result of the level detection circuit, information may be received from a power supply controller at a subsequent stage.

[0292] The power supply controller of the fifth configuration may have a configuration (sixth configuration) in which the synchronization input circuit sets the state of the synchronization input terminal to the first input state (pull-down state) during the output period of the output clock signal, and sets the state of the synchronization input terminal to the second input state (pull-up state) during the non-output period of the output clock signal, and the synchronization output circuit stops the output of the output clock signal in response to the establishment of a predetermined clock stop condition (e.g., Fig.17 Y in S16, Fig.18 The output of the output clock signal is stopped by Y in S26 in the output clock signal detection circuit, and the clock stop condition includes the condition that the voltage of the synchronization output terminal in the third period is detected by the level detection circuit as belonging to the second level (high level).

[0293] As a result, by the necessary condition that the power supply controller at the subsequent stage stops outputting the output clock signal to the power supply controller at the further subsequent stage, the stop of the output clock signal to the power supply controller at the subsequent stage can be controlled.

[0294] The power supply controller of the fifth configuration may have a configuration (seventh configuration) in which the synchronization input circuit sets the state of the synchronization input terminal to the second input state (pull-up state) during an output period of the output clock signal, and sets the state of the synchronization input terminal to the first input state (pull-down state) during a non-output period of the output clock signal, and the synchronization output circuit stops the output of the output clock signal in response to the establishment of a predetermined clock stop condition (e.g., Fig.17 Y in S16, Fig.18 The output of the output clock signal is stopped by Y in S26 in the output clock signal detection circuit, and the clock stop condition includes the condition that the voltage of the synchronization output terminal in the third period is detected by the level detection circuit as belonging to the first level (high level).

[0295] Therefore, by the necessary condition that the power supply controller at the subsequent stage stops outputting the output clock signal to the power supply controller at the further subsequent stage, the stop of the output clock signal to the power supply controller at the subsequent stage can be controlled.

[0296] The power supply controller of any one of the first to seventh configurations may have a configuration (eighth configuration) in which, in the third output state, the synchronous output circuit ( Fig.26 40C or Fig. 20 40B) in the first output state outputs a signal of the first level with an output impedance higher than that in the first output state, or outputs a signal of the second level with an output impedance higher than that in the second output state.

[0297] As a result, it is possible to prevent the potential of the synchronous output terminal from becoming unstable in the third output state.

[0298] The power supply controller of the second configuration (see the fifth example or the sixth example) may have a configuration (ninth configuration) in which the synchronization output circuit outputs an output clock signal from the synchronization output terminal or does not output an output clock signal from the synchronization output terminal, and the synchronization output circuit is configured to: when a predetermined forced output condition is not satisfied in the first mode, in response to the establishment of a predetermined clock output condition during an execution period of the switch control, output an output clock signal (PTN1a or PTN1b) of a first pattern based on a reference clock signal from the synchronization output terminal; when the forced output condition is satisfied in the first mode, regardless of whether the clock output condition is satisfied during the execution period of the switch control, output an output clock signal (PTN2a or PTN2b) of a second pattern based on the reference clock signal from the synchronization output terminal. N2b); when the input clock signal is not supplied to the synchronization input terminal in the second mode, neither the output clock signal of the first pattern nor the output clock signal of the second pattern is output from the synchronization output terminal; when the input clock signal is supplied to the synchronization input terminal in the second mode and the input clock signal has the first pattern, in response to the establishment of the clock output condition during the execution period of the switch control, an output clock signal based on the first pattern of the input clock signal is output from the synchronization output terminal; and when the input clock signal is supplied to the synchronization input terminal in the second mode and the input clock signal has the second pattern, regardless of whether the clock output condition is satisfied during the execution period of the switch control, an output clock signal based on the second pattern of the input clock signal is output from the synchronization output terminal.

[0299] When a plurality of power supply controllers are connected in cascade, all the power supply controllers can be forced to perform switching control by using the output clock signal of the second pattern.

[0300] The power supply controller of the ninth configuration may have a configuration (tenth configuration) in which the synchronous output circuit is configured to output the output clock signal of the first pattern during the output period (see Fig.12 or Fig.21), in each cycle of the output clock signal of the first pattern, including a first period in which the state of the synchronization output terminal is set to the first output state, a second period in which the state of the synchronization output terminal is set to the second output state, and a third period in which the state of the synchronization output terminal is set to the third output state; and in the output period of the output clock signal of the second pattern (see Fig. 27 or Fig.29 ) period, the state of the synchronous output terminal is alternately set to the first output state and the second output state.

[0301] The power controller of the tenth configuration (see Fig. 27 or Fig.29 ) may have a configuration (eleventh configuration), namely, the synchronous output circuit mixes a period in which the output clock signal has a first waveform (WV1 / WV3) and a period in which the output clock signal has a second waveform (WV2 / WV4) in an output period of the output clock signal of the second pattern, the power supply controller is provided with a pattern determination circuit (70) connected to the synchronous input terminal, and the pattern determination circuit determines whether the input clock signal has the second pattern by determining whether the input clock signal has a waveform that switches between the first waveform and the second waveform based on the voltage of the synchronous input terminal.

[0302] The power controller of the eleventh configuration may have a configuration (twelfth configuration), which also includes a level detection circuit (60) connected to a synchronization output terminal, wherein when the synchronization output circuit outputs an output clock signal of a first pattern, the level detection circuit detects whether the voltage of the synchronization output terminal in a third time period belongs to the first level or the second level.

[0303] When the first mode is used, information may be received from a power supply controller at a subsequent stage based on the detection result of the level detection circuit.

[0304] The power supply controller of the twelfth configuration may have a configuration (thirteenth configuration) in which the synchronization input circuit sets the state of the synchronization input terminal to the first input state (pull-down state) during a period in which the synchronization output circuit outputs the output clock signal of the first pattern, and sets the state of the synchronization input terminal to the second input state (pull-up state) during a period in which the output of the output clock signal of the first pattern by the synchronization output circuit is stopped, wherein after the output of the output clock signal of the first pattern is started when the forced output condition is not satisfied in the first mode, or after the output of the output clock signal of the first pattern is started when the input clock signal of the first pattern is supplied to the synchronization input terminal in the second mode, the synchronization output circuit responds to the establishment of a predetermined clock stop condition (for example, Fig.17 Y in S16, Fig.18The output of the output clock signal of the first pattern is stopped by Y in S26 in the circuit, and the clock stop condition includes the condition that the voltage of the synchronization output terminal in the third period is detected by the level detection circuit as belonging to the second level (high level).

[0305] As a result, when the first pattern is used, the stop of the output clock signal to the power supply controller at the subsequent stage can be controlled by the necessary condition that the power supply controller at the subsequent stage stops the output of the output clock signal to the power supply controller at the further subsequent stage.

[0306] The power supply controller of the twelfth configuration may have a configuration (a fourteenth configuration) in which the synchronization input circuit sets the state of the synchronization input terminal to the second input state (pull-up state) during a period in which the synchronization output circuit outputs the output clock signal of the first pattern, and sets the state of the synchronization input terminal to the first input state (pull-down state) during a period in which the output of the output clock signal of the first pattern by the synchronization output circuit is stopped, and the synchronization output circuit responds to the establishment of a predetermined clock stop condition (for example, after starting the output of the output clock signal of the first pattern when the forced output condition is not satisfied in the first mode, or after starting the output of the output clock signal of the first pattern when the input clock signal of the first pattern is supplied to the synchronization input terminal in the second mode. Fig.17 Y in S16, Fig.18 The output of the output clock signal of the first pattern is stopped by Y in S26 in the circuit, and the clock stop condition includes the condition that the voltage of the synchronization output terminal in the third period is detected by the level detection circuit as belonging to the first level (low level).

[0307] As a result, when the first pattern is used, the stop of the output clock signal to the power supply controller at the subsequent stage can be controlled by the necessary condition that the power supply controller at the subsequent stage stops the output of the output clock signal to the power supply controller at the further subsequent stage.

[0308] The power supply controller of any one of the ninth to fourteenth configurations may have a configuration (fifteenth configuration) in which, when the output clock signal of the first pattern is output, in the third output state, the synchronous output circuit ( Fig.26 40C or Fig. 20 40B) in the first output state outputs a signal of the first level with an output impedance higher than that in the first output state, or outputs a signal of the second level with an output impedance higher than that in the second output state.

[0309] As a result, when the first pattern is used, it is possible to prevent the potential of the synchronous output terminal from becoming unstable in the third output state.

[0310] The power supply controller of any one of the first to fifteenth configurations can have a configuration (sixteenth configuration) in which the output stage includes an output element (MH) composed of a switching element and a rectifying element (ML) connected to the output element, a coil (L) is connected to a connection node between the output element and the rectifying element, and an output voltage is generated based on a current (IL) flowing through the coil when the output element is switched between on and off in a switching control of the output stage.

[0311] The power supply controller of any one of the first to sixteenth configurations may have a configuration (seventeenth configuration) in which a synchronization output terminal in the power supply controller is configured to be connected to a synchronization input terminal of another power supply controller provided in the switching power supply.

[0312] The power supply controller of any one of the first to sixteenth configurations may have a configuration (eighteenth configuration) in which a synchronization input terminal in the power supply controller is configured to be connected to a synchronization output terminal of another power supply controller provided in the switching power supply.

[0313] A switching power supply according to another aspect of the present invention is a switching power supply device (1) configured to receive an input voltage (V IN ) generates an output voltage (V OUT ), and having a configuration (the nineteenth configuration), comprising: a first power supply controller to an nth power supply controller (10[1] to 10[n]), wherein n represents an integer greater than 2, wherein each power supply controller is a power supply controller of any one of the second configuration to the seventh configuration and the ninth configuration to the fifteenth configuration, wherein the synchronization output terminal (S_OUT[i]) of the i-th power supply controller is connected to the synchronization input terminal (S_IN[i+1]) of the (i+1)-th power supply controller, wherein i represents a natural number less than (n-1), wherein in the first to n-th power supply controllers, the first power supply controller (10[1]) operates in a first mode, and each of the other power supply controllers (10[2] to 10[n]) operates in a second mode, wherein the output stages in the first to n-th power supply controllers are first to n-th output stages, and wherein current is supplied from an application terminal of an input voltage to an application terminal of an output voltage through one or more output stages in which switching is performed in the first to n-th output stages.

[0314] According to the above configuration, for example, by switching the state of the synchronization output terminal of the first power controller, a clock signal for synchronization can be supplied to the synchronization input terminal of the second power controller. At this time, the synchronization input circuit of the second power controller selectively pulls down or pulls up the synchronization input terminal, so that when the synchronization output terminal of the first power controller is in the third output state, information can be transmitted from the second power controller to the first power controller. That is, information can be transmitted from the second power controller to the first power controller by using the synchronization terminal (synchronization output terminal and synchronization input terminal) without providing a dedicated terminal for information transmission. By using this information, the switching power supply can be properly operated.

[0315] Although certain embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present invention. In fact, the embodiments described herein may be embodied in various other forms. In addition, without departing from the spirit of the present invention, various omissions, substitutions and changes may be made to the forms of the embodiments described herein. The attached claims and their equivalents are intended to cover such forms or variations that fall within the scope and spirit of the present invention.

[0316] Description of Reference Numerals

[0317] 1: Switching power supply

[0318] 10. 10[i]: Power Controller

[0319] L, L[i]: coil

[0320] C OUT : Output capacitor

[0321] ND OUT : Output node

[0322] R1, R2: Feedback resistors

[0323] LD: Load

[0324] I LD : Load current

[0325] IL, IL[i]: coil current

[0326] V OUT : Output voltage

[0327] V FB : Feedback voltage

[0328] IN: Input terminal

[0329] SW: switch terminal

[0330] GND: Ground terminal

[0331] FB: Feedback terminal

[0332] EOUT: Error output terminal

[0333] S_IN, S_IN[i]: Synchronous input terminals

[0334] S_OUT, S_OUT[i]: Synchronous output terminals

[0335] MM, MM[i]: output stage

[0336] MH, ML: Transistor

[0337] 20, 20[i]: Switch control circuit

[0338] 21: Error Amplifier

[0339] 22: Tilt Circuit

[0340] 23: Sensing circuit

[0341] 24: Adder

[0342] 25:PWM Comparator

[0343] 26: Switching Circuit

[0344] 27: Clock supply circuit

[0345] 28: Controller

[0346] 27a: Oscillator Circuit

[0347] 30, 30[i]: Mode setting circuit

[0348] 40, 40[i], 40A, 40B, 40C: Synchronous output circuit

[0349] 41, 42: Transistor

[0350] 43: Output setting circuit

[0351] 44: Pull-up resistor

[0352] 45: Pull-down resistor

[0353] 50, 50[i], 50A: Synchronous input circuit

[0354] 51, 52: Transistor

[0355] 53: Input setting circuit

[0356] 54: Resistor

[0357] 60, 60[i]: Level detection circuit

[0358] 70, 70[i]: Pattern determination circuit

[0359] 80, 80[i]: Clock management circuit

[0360] ERR, ERR': Error signal

[0361] RAMP: ramp signal

[0362] ISNS, ISNS[i]: sensing signal

[0363] SLP: ramp signal

[0364] RST: signal

[0365] CLK A : Internal clock signal

[0366] CLK B : Input clock signal

[0367] CLK REF : Reference clock signal

[0368] CLK[i]: clock signal

[0369] GH, GL: Gate signal

[0370] S DET , S DET [i]: Level detection signal

[0371] S PTN , S PTN [i]: Pattern determination signal

[0372] PTN1a, PTN1b, PTN2a, PTN2b: Pattern.

Claims

1. A power supply controller, arranged in a switching power supply configured to generate an output voltage from an input voltage, the power supply controller comprising: Synchronous input terminal; Synchronous output terminal; an output stage configured to convert the input voltage power into the output voltage; a switch control circuit configured to convert the input voltage power into the output voltage by performing switch control of the output stage in synchronization with a reference clock signal; a synchronous output circuit configured to set the state of the synchronous output terminal to any one of a plurality of output states including a first output state, a second output state, and a third output state; and a synchronous input circuit configured to set the state of the synchronous input terminal to any one of a plurality of input states including a first input state and a second input state, wherein the synchronous output circuit outputs a signal of a first level from the synchronous output terminal in the first output state, outputs a signal of a second level higher than the first level from the synchronous output terminal in the second output state, and the output impedance of the synchronous output circuit is set to be higher in the third output state than in the first output state and the second output state, and The synchronous input circuit is capable of pulling down the synchronous input terminal to the first level or pulling up the synchronous input terminal to the second level via a resistor, pulling down the synchronous input terminal in the first input state, and pulling up the synchronous input terminal in the second input state.

2. The power controller according to claim 1, further comprising a mode setting circuit configured to set the operation mode of the power controller to the first mode or the second mode based on given mode setting information, The switch control circuit is composed of: In the first mode, the switch control is performed in synchronization with the reference clock signal based on an internal clock signal or an input clock signal supplied to the synchronization input terminal from outside the power supply controller; In the second mode, when the input clock signal is not supplied to the synchronization input terminal, the switch control is stopped; and In the second mode, when the input clock signal is supplied to the synchronization input terminal, the switch control is performed in synchronization with the reference clock signal based on the input clock signal.

3. The power controller according to claim 2, wherein: the synchronous output circuit outputting an output clock signal based on the reference clock signal from the synchronous output terminal in response to the establishment of a predetermined clock output condition during an execution period of the switch control in the first mode or the second mode, and Wherein, during the output period of the output clock signal, in each cycle of the output clock signal, the synchronous output circuit includes a first period in which the state of the synchronous output terminal is set to the first output state, a second period in which the state of the synchronous output terminal is set to the second output state, and a third period in which the state of the synchronous output terminal is set to the third output state.

4. The power controller according to claim 3, wherein: The synchronization input circuit sets the state of the synchronization input terminal to one of the first input state and the second input state during the output period of the output clock signal, and sets the state of the synchronization input terminal to the other of the first input state and the second input state during the non-output period of the output clock signal.

5. The power supply controller according to claim 4, further comprising a level detection circuit connected to the synchronization output terminal, in, When the synchronous output circuit outputs the output clock signal, the level detection circuit detects which of the first level and the second level the voltage of the synchronous output terminal in the third period belongs to.

6. The power controller according to claim 5, wherein: the synchronization input circuit sets the state of the synchronization input terminal to the first input state during the output period of the output clock signal, and sets the state of the synchronization input terminal to the second input state during the non-output period of the output clock signal, wherein the synchronous output circuit stops outputting the output clock signal in response to the establishment of a predetermined clock stop condition after starting outputting the output clock signal, and The clock stop condition includes a condition that the voltage of the synchronization output terminal in the third period is detected by the level detection circuit as belonging to the second level.

7. The power controller according to claim 5, wherein: the synchronization input circuit sets the state of the synchronization input terminal to the second input state during the output period of the output clock signal, and sets the state of the synchronization input terminal to the first input state during the non-output period of the output clock signal, wherein the synchronous output circuit stops outputting the output clock signal in response to the establishment of a predetermined clock stop condition after starting outputting the output clock signal, and The clock stop condition includes a condition that the voltage of the synchronization output terminal in the third period is detected by the level detection circuit as belonging to the first level.

8. The power controller according to claim 1, wherein: In the third output state, the synchronous output circuit outputs the signal of the first level with a higher output impedance than in the first output state, or outputs the signal of the second level with a higher output impedance than in the second output state.

9. The power controller according to claim 2, wherein: The synchronous output circuit outputs an output clock signal from the synchronous output terminal or does not output an output clock signal from the synchronous output terminal, and Wherein, the synchronous output circuit is composed of: outputting an output clock signal based on a first pattern of the reference clock signal from the synchronization output terminal in response to establishment of a predetermined clock output condition during an execution period of the switch control when a predetermined forced output condition is not satisfied in the first mode; when the forced output condition is satisfied in the first mode, outputting an output clock signal based on a second pattern of the reference clock signal from the synchronization output terminal regardless of whether the clock output condition is satisfied during an execution period of the switch control; when the input clock signal is not supplied to the synchronization input terminal in the second mode, neither the output clock signal of the first pattern nor the output clock signal of the second pattern is output from the synchronization output terminal; when the input clock signal is supplied to the synchronization input terminal in the second mode and the input clock signal has the first pattern, in response to the clock output condition being established during the execution period of the switch control, outputting an output clock signal based on the first pattern of the input clock signal from the synchronization output terminal; and When the input clock signal is supplied to the synchronization input terminal in the second mode and the input clock signal has the second pattern, an output clock signal based on the second pattern of the input clock signal is output from the synchronization output terminal regardless of whether the clock output condition is met during the execution period of the switch control.

10. The power controller according to claim 9, wherein: The synchronous output circuit is composed of: During an output period of the output clock signal of the first pattern, in each cycle of the output clock signal of the first pattern, including a first period in which the state of the synchronization output terminal is set to the first output state, a second period in which the state of the synchronization output terminal is set to the second output state, and a third period in which the state of the synchronization output terminal is set to the third output state; and During an output period of the output clock signal of the second pattern, the state of the synchronization output terminal is alternately set to the first output state and the second output state.

11. The power controller according to claim 10, wherein: the synchronous output circuit mixes a period in which the output clock signal has a first waveform and a period in which the output clock signal has a second waveform in the output period of the output clock signal of the second pattern, wherein the power supply controller is provided with a pattern determination circuit connected to the synchronization input terminal, and The pattern determination circuit determines whether the input clock signal has the second pattern by determining whether the input clock signal has a waveform that switches between the first waveform and the second waveform based on a voltage of the synchronization input terminal.

12. The power supply controller according to claim 11, further comprising a level detection circuit connected to the synchronization output terminal, in, When the synchronous output circuit outputs the output clock signal of the first pattern, the level detection circuit detects to which of the first level and the second level the voltage of the synchronous output terminal in the third period belongs.

13. The power controller according to claim 12, wherein: the synchronous input circuit sets the state of the synchronous input terminal to the first input state during a period in which the synchronous output circuit outputs the output clock signal of the first pattern, and sets the state of the synchronous input terminal to the second input state during a period in which the synchronous output circuit stops outputting the output clock signal of the first pattern, wherein, after starting to output the output clock signal of the first pattern when the forced output condition is not satisfied in the first mode, or after starting to output the output clock signal of the first pattern when the input clock signal of the first pattern is supplied to the synchronization input terminal in the second mode, the synchronization output circuit stops outputting the output clock signal of the first pattern in response to the establishment of a predetermined clock stop condition, and The clock stop condition includes a condition that the voltage of the synchronization output terminal in the third period is detected by the level detection circuit as belonging to the second level.

14. The power controller according to claim 12, wherein: the synchronous input circuit sets the state of the synchronous input terminal to the second input state during a period in which the synchronous output circuit outputs the output clock signal of the first pattern, and sets the state of the synchronous input terminal to the first input state during a period in which the synchronous output circuit stops outputting the output clock signal of the first pattern, wherein, after starting to output the output clock signal of the first pattern when the forced output condition is not satisfied in the first mode, or after starting to output the output clock signal of the first pattern when the input clock signal of the first pattern is supplied to the synchronization input terminal in the second mode, the synchronization output circuit stops outputting the output clock signal of the first pattern in response to the establishment of a predetermined clock stop condition, and The clock stop condition includes a condition that the voltage of the synchronization output terminal in the third period is detected by the level detection circuit as belonging to the first level.

15. The power controller according to claim 9, wherein: When outputting the output clock signal of the first pattern, in the third output state, the synchronous output circuit outputs the signal of the first level with higher output impedance than in the first output state, or outputs the signal of the second level with higher output impedance than in the second output state.

16. The power supply controller according to any one of claims 1 to 15, wherein: The output stage includes an output element constituted by a switching element and a rectifying element connected to the output element, and wherein a coil is connected to a connection node between the output element and the rectifying element, and the output voltage is generated based on a current flowing through the coil when the output element is switched between on and off in switch control of the output stage.

17. The power supply controller according to any one of claims 1 to 15, wherein: The synchronization output terminal in the power supply controller is configured to be connected to a synchronization input terminal of another power supply controller provided in the switching power supply.

18. The power supply controller according to any one of claims 1 to 15, wherein: The synchronization input terminal in the power supply controller is configured to be connected to a synchronization output terminal of another power supply controller provided in the switching power supply.

19. A switching power supply configured to generate an output voltage from an input voltage, the switching power supply comprising: a first power controller to an nth power controller, wherein n represents an integer greater than 2, wherein each of the power supply controllers is a power supply controller according to any one of claims 2 to 7 and 9 to 15, The synchronous output terminal of the i-th power supply controller is connected to the synchronous input terminal of the (i+1)-th power supply controller, wherein i represents a natural number less than (n-1), wherein, among the first to nth power controllers, the first power controller operates in the first mode, and each of the other power controllers operates in the second mode, Wherein, the output stages in the first power supply controller to the nth power supply controller are the first output stage to the nth output stage, and The current is supplied from the input voltage application terminal to the output voltage application terminal through one or more output stages among the first to n-th output stages that perform the switch control.

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