Memristive Neural Network Circuit for Generating Multi-Directional and Multi-Double Scroll Chaotic Attractors

Abstract

The invention discloses a memristive neural network circuit for generating multi-direction and multi-double-scroll chaotic attractors, comprising: a first to a third integration channel circuit, a first to a third memristor, and a first to a third switch. The first integration channel circuit includes three input terminals and one output terminal; the second integration channel circuit includes three input terminals and one output terminal; the third integration channel circuit includes two input terminals and one output terminal. By controlling the switch states of the memristive channels connected to the input terminals of each integration channel circuit, the memristive neural network circuit can generate multi-direction and multi-scroll chaotic attractors. This circuit has a discharge characteristic closer to that of interacting neurons in a real nervous system, can provide new possibilities for physically constructing an intelligent neuromorphic system, and has important value in the fields of chaotic secure communication, image encryption, and complex signal processing, etc.

Description

Technical Field

[0001] The present invention relates to a memristive neural network circuit for generating multi-direction and multi-double-scroll chaotic attractors, belonging to the technical field of memristive neural network circuit design. Background Art

[0002] A memristor is a non-linear element with a memory function, and its resistance value changes with the amount of charge passing through. The concept of the memristor was first proposed by Leon Chua in 1971, but it wasn't until 2008 that HP Labs successfully fabricated the first physical model. The emergence of the memristor has brought new possibilities to the design and application of electronic circuits, especially in the fields of chaotic systems and neural networks. The official launch of the "China Brain Project" has created a new situation for brain science research in China. Memristive neural networks combine the advantages of memristors and neural networks and can simulate the learning and memory functions of biological neural networks. By introducing memristors into neural networks, dynamic adjustment of neuron connection weights can be achieved, thereby enhancing the learning ability and adaptability of the network and accurately and meticulously describing the dynamic evolution process of neural networks.

[0003] Multi-scroll chaotic systems are a class of non-linear systems with complex dynamic behaviors. By changing system parameters, different numbers and types of scrolls can be generated, thereby increasing the complexity and pseudo-randomness of the system. The multi-direction and multi-double-scroll chaotic attractor further expands this concept. By introducing double-scroll structures in multiple directions, the system exhibits more complex chaotic behaviors in higher dimensions.

[0004] Currently, a series of achievements have been made in the research on chaotic circuits that can generate chaotic attractors with controllable quantities. For example, the Chinese patent application with publication number CN107135063A discloses a method for realizing a chaotic circuit that generates grid multi-wing hyperchaotic hidden attractors, and the Chinese patent application with publication number CN116388951A discloses a multi-structure chaotic circuit based on a memristive Hopfield neural network. However, these circuits can only regulate the quantity or type of attractors in one or two directions, while multi-double-scroll attractors with controllable quantities in multiple directions have more complex dynamic behaviors. Therefore, there is a need to design a memristive circuit that can generate different types of multi-double-scroll chaotic attractors in different directions. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a memristive neural network circuit for generating multi-direction and multi-double-scroll chaotic attractors, which can generate different types of multi-double-scroll chaotic attractors in different directions and the generated chaotic attractors have complex dynamic characteristics.

[0006] The present invention adopts the following technical solutions to solve the above technical problems:

[0007] A memristive neural network circuit for generating multi-directional and multi-double-scroll chaotic attractors, comprising: first to third integral channel circuits, first to third memristors, and first to third switches; the first integral channel circuit includes three input terminals, one output terminal, first to third resistors, a first membrane resistor, a first capacitor, and a first operational amplifier; the second integral channel circuit includes three input terminals, one output terminal, fourth to sixth resistors, a second membrane resistor, a second capacitor, and a second operational amplifier; the third integral channel circuit includes two input terminals, one output terminal, seventh to eighth resistors, a third membrane resistor, a third capacitor, and a third operational amplifier;

[0008] The output of the second integral channel circuit is sequentially connected to a first negative hyperbolic tangent circuit and a first inverter, and the output of the first inverter is connected to the first input terminal of the first integral channel circuit. The first input terminal of the first integral channel circuit is connected to the inverting input terminal of the first operational amplifier through a first resistor or a first memristor, and the first resistor and the first memristor are switched by a first switch ; the output of the first integral channel circuit is connected to a second negative hyperbolic tangent circuit, and the output A of the second negative hyperbolic tangent circuit is connected to the second input terminal of the first integral channel circuit. The second input terminal of the first integral channel circuit is connected to the inverting input terminal of the first operational amplifier through a second resistor or a second memristor, and the second resistor and the second memristor are switched by a second switch ; the output of the third integral channel circuit is connected to a third negative hyperbolic tangent circuit, and the output C of the third negative hyperbolic tangent circuit is connected to the third input terminal of the first integral channel circuit. The third input terminal of the first integral channel circuit is connected to the inverting input terminal of the first operational amplifier through a third resistor; the non-inverting input terminal of the first operational amplifier is grounded, the first capacitor is connected across the inverting input terminal and the output terminal of the first operational amplifier, the first membrane resistor is connected in parallel with the first capacitor, and the output of the first operational amplifier is used as the output of the first integral channel circuit;

[0009] The output A of the second negative hyperbolic tangent circuit is connected to the first input terminal of the second integral channel circuit. The first input terminal of the second integral channel circuit is connected to the inverting input terminal of the second operational amplifier through a fourth resistor; the output B of the first negative hyperbolic tangent circuit is connected to the second input terminal of the second integral channel circuit. The second input terminal of the second integral channel circuit is connected to the inverting input terminal of the second operational amplifier through a fifth resistor; the output C of the third negative hyperbolic tangent circuit is connected to the third input terminal of the second integral channel circuit. The third input terminal of the second integral channel circuit is connected to the inverting input terminal of the second operational amplifier through a sixth resistor; the non-inverting input terminal of the second operational amplifier is grounded, the second capacitor is connected across the inverting input terminal and the output terminal of the second operational amplifier, the second membrane resistor is connected in parallel with the second capacitor, and the output of the second operational amplifier is used as the output of the second integral channel circuit;

[0010] The output of the second negative hyperbolic tangent circuit passes through a second inverter, and the output of the second inverter is connected to the first input terminal of a third integration channel circuit. The first input terminal of the third integration channel circuit is connected to the inverting input terminal of a third operational amplifier through a seventh resistor; the output of the third negative hyperbolic tangent circuit is connected to a third inverter, and the output of the third inverter is connected to the second input terminal of the third integration channel circuit. The second input terminal of the third integration channel circuit is connected to the inverting input terminal of the third operational amplifier through an eighth resistor or a third memristor. The eighth resistor and the third memristor are switched through a third switch ; the non-inverting input terminal of the third operational amplifier is grounded, a third capacitor is connected across the inverting input terminal and the output terminal of the third operational amplifier, the third film resistor is in parallel with the third capacitor, and the output of the third operational amplifier serves as the output of the third integration channel circuit;

[0011] and When both are not closed, the circuit equations of the first, second, and third integration channel circuits are as follows:

[0012] ,

[0013] wherein, and respectively represent the outputs of the first, second, and third integration channel circuits, and respectively represent the first, second, third, fourth, fifth, sixth, seventh, and eighth resistors, represents hyperbolic tangent, represents the first, second, and third film resistors, and the resistance values of the first, second, and third film resistors are equal, represents the first, second, and third capacitors, and the capacitance values of the first, second, and third capacitors are equal.

[0014] As a preferred embodiment of the circuit of the present invention, the first memristor includes a fourth to seventh operational amplifier, a ninth to fourteenth resistor, a fourth to fifth film resistor, a fourth capacitor, a fourth to fifth inverter, a fourth negative hyperbolic tangent circuit, a first multiplier, and a first coupling resistor;

[0015] The output of the first inverter As the input of the first memristor; the input of the first memristor is connected to the inverting input terminal of the sixth operational amplifier through the thirteenth resistor, the output terminal of the sixth operational amplifier is connected to the inverting input terminal of the fourth operational amplifier, the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the fifth operational amplifier through the ninth resistor, the tenth resistor is connected across the inverting input terminal and the output terminal of the fifth operational amplifier, and after the output terminal of the fifth operational amplifier passes through the fourth inverter and the eleventh resistor in sequence, it is connected to the inverting input terminal of the sixth operational amplifier;

[0016] The fourth capacitor is connected across the inverting input terminal and the output terminal of the sixth operational amplifier, the twelfth resistor is in parallel with the fourth capacitor, the output terminal of the sixth operational amplifier is connected to the first input terminal of the first multiplier through the fourth negative hyperbolic tangent circuit, the input of the first memristor is connected to the second input terminal of the first multiplier, and the output terminal of the first multiplier is connected to the inverting input terminal of the seventh operational amplifier through the fourteenth resistor; the input of the first memristor is connected to the inverting input terminal of the seventh operational amplifier through the fifth inverter and the fourth membrane resistor in sequence, the fifth membrane resistor is connected across the inverting input terminal and the output terminal of the seventh operational amplifier, and the output terminal of the seventh operational amplifier obtains the output of the first memristor through the first coupling resistor; the non-inverting input terminals of the fourth, fifth, sixth, and seventh operational amplifiers are all grounded;

[0017] The circuit equation of the first memristor is as follows:

[0018] ,

[0019] In the formula, and respectively represent the twelfth, thirteenth, and fourteenth resistors, represents the fourth capacitor, and the capacitance value of the fourth capacitor is equal to that of the first capacitor, represents the output of the sixth operational amplifier, represents the voltage variable obtained by inverting the output of the second integration channel circuit, represents the hyperbolic tangent, represents the sign function.

[0020] As a preferred solution of the circuit of the present invention, the second memristor includes the eighth to eleventh operational amplifiers, the fifteenth to twenty-first resistors, the sixth membrane resistor, the fifth capacitor, the sixth to seventh inverters, the fifth negative hyperbolic tangent circuit, the second multiplier, and the second coupling resistor;

[0021] The output A of the second negative hyperbolic tangent circuit serves as the input of the second memristor; after the input of the second memristor passes through the sixth inverter and the eighteenth resistor in sequence, it is connected to the inverting input terminal of the tenth operational amplifier. The output terminal of the tenth operational amplifier is connected to the inverting input terminal of the eighth operational amplifier. The output terminal of the eighth operational amplifier is connected to the inverting input terminal of the ninth operational amplifier via the fifteenth resistor. The sixteenth resistor is connected across the inverting input terminal and the output terminal of the ninth operational amplifier. After the output terminal of the ninth operational amplifier passes through the seventh inverter and the nineteenth resistor in sequence, it is connected to the inverting input terminal of the tenth operational amplifier;

[0022] The fifth capacitor is connected across the inverting input terminal and the output terminal of the tenth operational amplifier. The twentieth resistor is in parallel with the fifth capacitor. The output terminal of the tenth operational amplifier is connected to the first input terminal of the second multiplier via the fifth negative hyperbolic tangent circuit. The input of the second memristor is connected to the second input terminal of the second multiplier. The output terminal of the second multiplier is connected to the inverting input terminal of the eleventh operational amplifier via the twenty - first resistor. The input of the second memristor passes through the sixth inverter and the seventeenth resistor in sequence and is connected to the inverting input terminal of the eleventh operational amplifier. The sixth film resistor is connected across the inverting input terminal and the output terminal of the eleventh operational amplifier. The output terminal of the eleventh operational amplifier obtains the output of the second memristor via the second coupling resistor. The non - inverting input terminals of the eighth, ninth, tenth, and eleventh operational amplifiers are all grounded;

[0023] The circuit equation of the second memristor is as follows:

[0024] ,

[0025] In the formula, and respectively represent the nineteenth, twentieth, and twenty - first resistors, represents the fifth capacitor, and the capacitance value of the fifth capacitor is equal to that of the first capacitor, represents the output of the tenth operational amplifier, represents the voltage variable obtained by inverting the output of the first integration channel circuit, represents the hyperbolic tangent, represents the sign function.

[0026] As a preferred solution of the circuit of the present invention, the third memristor includes the twelfth to fifteenth operational amplifiers, the twenty - second to twenty - eighth resistors, the seventh film resistor, the sixth capacitor, the eighth to ninth inverters, the sixth negative hyperbolic tangent circuit, the third multiplier, and the third coupling resistor;

[0027] The output of the third inverter As the input of the third memristor; the input of the third memristor is connected to the inverting input terminal of the fourteenth operational amplifier through the twenty-third resistor, the output terminal of the fourteenth operational amplifier is connected to the inverting input terminal of the twelfth operational amplifier, the output terminal of the twelfth operational amplifier is connected to the inverting input terminal of the thirteenth operational amplifier through the twenty-second resistor, the twenty-sixth resistor is connected across the inverting input terminal and the output terminal of the thirteenth operational amplifier, and after the output terminal of the thirteenth operational amplifier passes through the ninth inverter and the twenty-fourth resistor in sequence, it is connected to the inverting input terminal of the fourteenth operational amplifier;

[0028] The sixth capacitor is connected across the inverting input terminal and the output terminal of the fourteenth operational amplifier, the twenty-fifth resistor is in parallel with the sixth capacitor, the output terminal of the fourteenth operational amplifier is connected to the first input terminal of the third multiplier through the sixth negative hyperbolic tangent circuit, the input of the third memristor is connected to the second input terminal of the third multiplier, and the output terminal of the third multiplier is connected to the inverting input terminal of the fifteenth operational amplifier through the twenty-eighth resistor; the input of the third memristor is connected to the inverting input terminal of the fifteenth operational amplifier after passing through the eighth inverter and the twenty-seventh resistor in sequence, the seventh membrane resistor is connected across the inverting input terminal and the output terminal of the fifteenth operational amplifier, and the output terminal of the fifteenth operational amplifier obtains the output of the third memristor through the third coupling resistor; the non-inverting input terminals of the twelfth, thirteenth, fourteenth, and fifteenth operational amplifiers are all grounded;

[0029] The circuit equation of the third memristor is as follows:

[0030] ,

[0031] In the formula, and respectively represent the twenty-fourth, twenty-fifth, and twenty-sixth resistors, represents the sixth capacitor, and the capacitance value of the sixth capacitor is equal to that of the first capacitor, represents the output of the fourteenth operational amplifier, represents the voltage variable obtained by inverting the output of the third integration channel circuit, represents the hyperbolic tangent, represents the sign function.

[0032] Based on the above-mentioned implementation method of the memristive neural network circuit for generating multi-directional and multi-double-scroll chaotic attractors, it includes:

[0033] When the switch is closed, and are turned on, the memristive neural network circuit is a single-memristor neural network circuit, which generates a single-direction distributed multi-double-scroll chaotic attractor on the plane;

[0034] When the switch Closed, and when turned on, the memristive neural network circuit is a single-memristive neural network circuit, which generates a multi-bidirectional scroll chaotic attractor with a single-direction distribution on the plane;

[0035] When the switch is closed, and is turned on, the memristive neural network circuit is a single-memristive neural network circuit, which generates a multi-bidirectional scroll chaotic attractor with a single-direction distribution on the plane;

[0036] When the switch and are closed, and is turned on, the memristive neural network circuit is a double-memristive neural network circuit, which generates a multi-bidirectional scroll chaotic attractor with a two-direction distribution on the

[0037] plane; and are closed, and is turned on, the memristive neural network circuit is a double-memristive neural network circuit, which generates a multi-bidirectional scroll chaotic attractor with a two-direction distribution on the

[0038] plane; and are closed, and is turned on, the memristive neural network circuit is a double-memristive neural network circuit, which generates a multi-bidirectional scroll chaotic attractor with a two-direction distribution on the

[0039] plane; , and are all closed, the memristive neural network circuit is a triple-memristive neural network circuit, which generates a multi-bidirectional scroll chaotic attractor with a three-direction distribution on the and plane.

[0040] Compared with the prior art, the present invention adopts the above technical solutions and has the following technical effects:

[0041] 1. The present invention uses the first switch , the second switch and the third switch The on and off states are used to control the number of memristors accessing the integration channel to output different chaotic signals, enabling the memristive neural network circuit to generate different types of multi-double-scroll chaotic attractors in different directions. The generated chaotic attractors have complex dynamic characteristics. This circuit is closer to the discharge characteristics of interacting neurons in the real nervous system and can provide new possibilities for physically constructing an intelligent neuromorphic system.

[0042] 2. By changing the system parameters, the topological structure and quantity of the scrolls can be altered in the present invention. Meanwhile, the memristive neural network circuit has the advantages of simple structure and easy implementation, and has important reference value and application prospects in the fields of chaotic secure communication, image encryption, and complex signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is the overall structural block diagram of the memristive neural network circuit for generating multi-directional multi-double-scroll chaotic attractors in the present invention;

[0044] Figure 2 is the circuit diagram of the main circuit in the present invention;

[0045] Figure 3 is the circuit diagram of the first memristor in the present invention;

[0046] Figure 4 is the circuit diagram of the second memristor in the present invention;

[0047] Figure 5 is the circuit diagram of the third memristor in the present invention;

[0048] Figure 6 is when closed the circuit simulation diagram of the phase-plane chaotic attractor;

[0049] Figure 7 is when closed the circuit simulation diagram of the phase-plane chaotic attractor;

[0050] Figure 8 is when closed the circuit simulation diagram of the phase-plane chaotic attractor;

[0051] Figure 9 is 、 when closed the circuit simulation diagram of the phase-plane chaotic attractor;

[0052] Figure 10 is 、 when closed Circuit simulation diagram of phase-plane chaotic attractor;

[0053] Figure 11 is 、 when closed Circuit simulation diagram of phase-plane chaotic attractor;

[0054] Figure 12 is 、 and when closed Circuit simulation diagram of phase-plane chaotic attractor;

[0055] Figure 13 is 、 and when closed Circuit simulation diagram of phase-plane chaotic attractor;

[0056] Figure 14 is 、 and when closed Circuit simulation diagram of phase-plane chaotic attractor. Specific embodiments

[0057] The following describes in detail the embodiments of the present invention. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present invention and should not be construed as limiting the present invention.

[0058] As Figure 1 shown, the present invention proposes a memristive neural network circuit for generating multi-directional multi-double-scroll chaotic attractors, including: a main circuit with three integral channel circuits, three memristors, and three switches. The three memristors are respectively connected to the input ends of the integral channel circuits through switches and , and the output ends of the integral channel circuits are connected to the input ends of the three memristors. By controlling the on and off states of switches and , the memristive neural network circuit generates different types of multi-double-scroll chaotic attractors on different phase planes.

[0059] As Figure 2 shown, the first to third integral channel circuits. The first integral channel circuit has first to third input ends and one output end. The second integral channel circuit has first to third input ends and one output end. The third integral channel circuit has first to second input ends and one output end.

[0060] The first input terminal of the first integration channel circuit is connected to the first memristor or the first resistor, and the two are switched by the first switch The output of the second integration channel circuit Passes through the first negative hyperbolic tangent circuit and the first inverter, and the output of the first inverter Is connected to the first input terminal of the first integration channel circuit; the second input terminal of the first integration channel circuit is connected to the second memristor or the second resistor, and the two are switched by the second switch The output of the first integration channel circuit Passes through the second negative hyperbolic tangent circuit, and the output A of the second negative hyperbolic tangent circuit is connected to the second input terminal of the first integration channel circuit. The third input terminal of the first integration channel circuit is connected to the third resistor. The first integration channel circuit includes a first resistor, a second resistor, a third resistor, a first film resistor, a first capacitor, and a first operational amplifier. The first resistor, the second resistor, and the third resistor are connected to the inverting input terminal of the first operational amplifier. The non-inverting input terminal of the first operational amplifier is grounded. The output terminal of the first operational amplifier serves as the output terminal of the first integration channel circuit. The first capacitor is connected across the inverting input terminal and the output terminal of the first operational amplifier. The first film resistor is connected in parallel with the first capacitor.

[0061] The first input terminal of the second integration channel circuit is connected to the output terminal of the second negative hyperbolic tangent circuit, the second input terminal is connected to the output terminal of the first negative hyperbolic tangent circuit, and the third input terminal is connected to the output terminal of the third negative hyperbolic tangent circuit. The second integration channel circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a second film resistor, a second capacitor, and a second operational amplifier. The first input terminal of the second integration channel circuit is connected to the inverting input terminal of the second operational amplifier through the fourth resistor, the second input terminal is connected to the inverting input terminal of the second operational amplifier through the fifth resistor, the third input terminal is connected to the inverting input terminal of the second operational amplifier through the sixth resistor. The non-inverting input terminal of the second operational amplifier is grounded. The second capacitor is connected across the output terminal and the inverting input terminal of the second operational amplifier. The output terminal of the second operational amplifier serves as the output terminal of the second integration channel. The second film resistor is connected in parallel with the second capacitor.

[0062] The first input terminal of the third integration channel circuit is connected to the output terminal of the second inverter; the second input terminal of the third integration channel circuit is connected to the third memristor or the eighth resistor, and the two are switched by the third switch The output of the third integration channel circuit After passing through the third negative hyperbolic tangent circuit and the third inverter, it is connected to the first input terminal of the third integration channel circuit. The third integration channel circuit includes a seventh resistor, an eighth resistor, a third thin-film resistor, a third capacitor, and a third operational amplifier. The first input terminal of the third integration channel circuit is connected to the inverting input terminal of the third operational amplifier through the seventh resistor, and the second input terminal is connected to the inverting input terminal of the third operational amplifier through the eighth resistor or the third memristor. The non-inverting input terminal of the third operational amplifier is grounded, and the output terminal of the third operational amplifier serves as the output terminal of the third integration channel circuit. The third capacitor is connected across the output terminal and the inverting input terminal of the third operational amplifier, and the third thin-film resistor is connected in parallel with the third capacitor.

[0063] As Figure 3 shown, the first memristor includes a fourth operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a seventh operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fourth capacitor, a fourth thin-film resistor, a fifth thin-film resistor, a fourth inverter, a fifth inverter, a fourth negative hyperbolic tangent circuit, a first multiplier, and a first coupling resistor , the non-inverting input terminals of the fourth operational amplifier, the fifth operational amplifier, the sixth operational amplifier, and the seventh operational amplifier are grounded. The inverting input terminal of the fourth operational amplifier is connected to the output terminal of the sixth operational amplifier. The output terminal of the fourth operational amplifier is connected to the ninth resistor, and the output terminal of the ninth resistor is connected to the inverting input terminal of the fifth operational amplifier. The tenth resistor is connected across the output terminal and the inverting input terminal of the fifth operational amplifier. The output of the fifth operational amplifier is connected to the fourth inverter, and the output terminal of the fourth inverter is connected to the eleventh resistor; the input terminal of the first memristor is connected to the inverting input terminal of the sixth operational amplifier through the thirteenth resistor, the output terminal of the eleventh resistor is connected to the inverting input terminal of the sixth operational amplifier, the fourth capacitor is connected across the output terminal and the inverting input terminal of the sixth operational amplifier, the twelfth resistor is connected across the output terminal and the inverting input terminal of the sixth operational amplifier, the output of the sixth operational amplifier is connected to the fourth negative hyperbolic tangent circuit, the output of the fourth negative hyperbolic tangent circuit and the input of the first memristor are connected to the first multiplier, the output of the first multiplier is connected to the fourteenth resistor, the output of the fourteenth resistor is connected to the inverting input terminal of the seventh operational amplifier, the input terminal of the first memristor is connected to the inverting input terminal of the seventh operational amplifier through the fifth inverter and the fourth thin-film resistor, the fifth thin-film resistor is connected across the output terminal and the inverting input terminal of the seventh operational amplifier, and the output terminal of the seventh operational amplifier is connected to the first coupling resistor , The output terminal of

[0064] As Figure 4As shown, the second memristor includes a sixth inverter, a seventh inverter, a fifth negative hyperbolic tangent circuit, an eighth operational amplifier, a ninth operational amplifier, a tenth operational amplifier, an eleventh operational amplifier, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a fifth capacitor, a second multiplier, and a second coupling resistor , the non-inverting inputs of the eighth operational amplifier, the ninth operational amplifier, the tenth operational amplifier, and the eleventh operational amplifier are grounded. The inverting input of the eighth operational amplifier is connected to the output of the tenth operational amplifier. The output of the eighth operational amplifier is connected to the fifteenth resistor, and the output of the fifteenth resistor is connected to the inverting input of the ninth operational amplifier. The sixteenth resistor is connected across the output and the inverting input of the ninth operational amplifier. The output of the ninth operational amplifier is connected to the input of the seventh inverter. The output of the seventh inverter is connected to the input of the nineteenth resistor. The output of the nineteenth resistor is connected to the inverting input of the tenth operational amplifier. The fifth capacitor is connected across the output and the inverting input of the tenth operational amplifier. The twentieth resistor is connected across the output and the inverting input of the tenth operational amplifier. The input of the second memristor is connected to the sixth inverter and then to the inputs of the seventeenth resistor and the eighteenth resistor. The output of the eighteenth resistor is connected to the inverting input of the tenth operational amplifier. The output of the tenth operational amplifier is connected to the fifth negative hyperbolic tangent circuit. The output of the fifth negative hyperbolic tangent circuit is connected to the second multiplier. The input of the second memristor is connected to the second multiplier. The output of the second multiplier is connected to the input of the twenty-first resistor. The output of the twenty-first resistor is connected to the inverting input of the eleventh operational amplifier. The output of the seventeenth resistor is connected to the inverting input of the eleventh operational amplifier. The sixth film resistor is connected across the output and the inverting input of the eleventh operational amplifier. The output of the eleventh operational amplifier is connected to the second coupling resistor , The output of

[0065] As Figure 5 shown, the third memristor includes an eighth inverter, a ninth inverter, a sixth negative hyperbolic tangent circuit, a twelfth operational amplifier, a thirteenth operational amplifier, a fourteenth operational amplifier, a fifteenth operational amplifier, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a third multiplier, a sixth capacitor, a seventh film resistor, and a third coupling resistor , the non-inverting inputs of the twelfth operational amplifier, the thirteenth operational amplifier, the fourteenth operational amplifier, and the fifteenth operational amplifier are all grounded. The inverting input of the twelfth operational amplifier is connected to the output of the fourteenth operational amplifier. The output of the twelfth operational amplifier is connected to the input of the twenty-second resistor. The output of the twenty-second resistor is connected to the inverting input of the thirteenth operational amplifier. The twenty-sixth resistor is connected across the output and the inverting input of the thirteenth operational amplifier. The output of the thirteenth operational amplifier is connected to the input of the ninth inverter. The output of the ninth inverter is connected to the input of the twenty-fourth resistor. The output of the twenty-fourth resistor is connected to the inverting input of the fourteenth operational amplifier. The input of the third memristor is connected to the input of the twenty-third resistor. The output of the twenty-third resistor is connected to the inverting input of the fourteenth operational amplifier. The sixth capacitor is connected across the inverting input and the output of the fourteenth operational amplifier. The twenty-fifth resistor is connected across the inverting input and the output of the fourteenth operational amplifier. The output of the fourteenth operational amplifier is connected to the input of the sixth negative hyperbolic tangent. The output of the sixth negative hyperbolic tangent is connected to the third multiplier. The input of the third memristor is connected to the third multiplier. The output of the third multiplier is connected to the input of the twenty-eighth resistor. The input of the third memristor is connected to the eighth inverter. The output of the eighth inverter is connected to the input of the twenty-seventh resistor. The output of the twenty-seventh resistor is connected to the inverting input of the fifteenth operational amplifier. The output of the twenty-eighth resistor is connected to the inverting input of the fifteenth operational amplifier. The seventh membrane resistor is connected across the output and the inverting input of the fifteenth operational amplifier. The output of the fifteenth operational amplifier is connected to the input of the third coupling resistor of , and the output of

[0066] Figure 2 is used as the output of the third memristor. Figure 3 , Figure 4 and Figure 5 involved in the circuit equations are as follows:

[0067] ,

[0068] The above circuit equations are all the prototype equations when no switch in the first, second, and third integration channel circuits is closed. The capacitance values of the first to sixth capacitors are equal, represented by . The resistance values of the first to seventh membrane resistors are equal, represented by .

[0069] Taking the single memristor-coupled neural network model as an example, that is, when the switch is closed, and are both in the open state. The circuit equations after connecting the first memristor can be obtained as follows:

[0070] ,

[0071] and The remaining two closing and opening states are the same as the above The circuit equations after closing can be obtained in the same way.

[0072] Taking the double memristor-coupled neural network model as an example, that is, when the switch is closed and the switch is in the open state. The circuit equations after connecting the first memristor and the second memristor are as follows:

[0073] ,

[0074] Taking the triple memristor-coupled neural network model as an example, that is, when the switches and are in the closed state, the circuit equations after connecting the first memristor, the second memristor, and the third memristor are as follows:

[0075] ,

[0076] where are six voltage variables. The circuit equations for any other switch states are the same as the above equations.

[0077] The implementation method of the memristive neural network circuit that generates multi-direction and multi-double-scroll chaotic attractors is as follows:

[0078] When is turned off and is turned on, the single memristor-coupled neural network model generates a single-direction distributed multi-double-scroll chaotic attractor on the plane;

[0079] When is turned off and is turned on, the single memristor-coupled neural network model generates a single-direction distributed multi-double-scroll chaotic attractor on the plane;

[0080] When is turned off and is turned on, the single memristor-coupled neural network model generates a single-direction distributed multi-double-scroll chaotic attractor on the plane;

[0081] When is turned off and is turned on, the double memristor-coupled neural network model generates two-direction distributed multi-double-scroll chaotic attractors on the

[0082] When is turned off and When turned on, the double memristor-coupled neural network model generates two multi-double-scroll chaotic attractors with two-direction distributions on the plane;

[0083] When is turned off, When turned on, the double memristor-coupled neural network model generates two multi-double-scroll chaotic attractors with two-direction distributions on the plane;

[0084] When are both turned off, the triple memristor-coupled neural network model generates three multi-double-scroll chaotic attractors with three-direction distributions on , and planes.

[0085] Selection of circuit components and power supply voltage in the present invention: Figures 1 to 5 For all operational amplifiers in, the model is TL082CP, and all power supply voltages are , and the output saturation value of each operational amplifier is . For all analog multipliers in the figure, the model is AD633, and the voltage is .

[0086] Parameters of each component are: set the integration time constant to 0.1 ms, the resistance values of the first to seventh membrane resistors are all , and the capacitance values of the first to sixth capacitors are all , and the multiplier ratio is 0.1. Based on the synaptic weight matrix model of the neural network, all theoretical resistances of Figures 2 to 5 can be derived according to the modular design method of the improved chaotic circuit as shown in Table 1:

[0087] Table 1

[0088]

[0089] Conduct experiments on the present invention according to Table 1 and the above time parameters, and control the switch states of switches and to obtain the corresponding relationship table of the phase plane for generating multi-double-scroll chaotic attractors as shown in Table 2:

[0090] Table 2

[0091]

[0092] Conduct experiments on the present invention according to the corresponding relationship in Table 2, Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 ,Figure 11 , Figure 12 , Figure 13 and Figure 14 , respectively give the attractor phase diagrams, attractor phase diagrams, attractor phase diagrams, attractor phase diagrams, attractor phase diagrams, attractor phase diagrams, and , , attractor phase diagrams.

[0093] As can be seen from Table 2, the present invention can generate multi - double - scroll chaotic attractors in multiple different directions, has complex dynamic characteristics and excellent pseudo - randomness, and can ensure the security of encrypted information.

[0094] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. A memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors, characterized in that: include: first to third integrating channel circuits, first to third memristors, and first to third switches; The first integrating channel circuit includes three input terminals, one output terminal, first to third resistors, a first membrane resistor, a first capacitor, and a first operational amplifier; The second integral channel circuit includes three input terminals, one output terminal, fourth to sixth resistors, a second film resistor, a second capacitor and a second operational amplifier; the third integral channel circuit includes two input terminals, one output terminal, seventh to eighth resistors, a third film resistor, a third capacitor and a third operational amplifier; The output of the second integral channel circuit is sequentially transmitted through the first negative hyperbolic tangent circuit and the first inverter. The output of the first inverter The first input end of the first integral channel circuit is connected to the inverting input end of the first operational amplifier via the first resistor or the first memristor, and the first resistor and the first memristor are connected via the first switch Switching; the output of the first integral channel circuit passes through the second negative hyperbolic tangent circuit, the output A of the second negative hyperbolic tangent circuit is connected to the second input end of the first integral channel circuit, the second input end of the first integral channel circuit is connected to the inverting input end of the first operational amplifier through the second resistor or the second memristor, the second resistor and the second memristor are connected through the second switch Switching; the output of the third integral channel circuit passes through the third negative hyperbolic tangent circuit, the output C of the third negative hyperbolic tangent circuit is connected to the third input terminal of the first integral channel circuit, the third input terminal of the first integral channel circuit is connected to the inverting input terminal of the first operational amplifier through the third resistor; the non-inverting input terminal of the first operational amplifier is grounded, the first capacitor is connected across the inverting input terminal and the output terminal of the first operational amplifier, the first membrane resistor is connected in parallel with the first capacitor, and the output of the first operational amplifier is used as the output of the first integral channel circuit; The output A of the second negative hyperbolic tangent circuit is connected to the first input terminal of the second integrating channel circuit, and the first input terminal of the second integrating channel circuit is connected to the inverting input terminal of the second operational amplifier via a fourth resistor; the output B of the first negative hyperbolic tangent circuit is connected to the second input terminal of the second integrating channel circuit, and the second input terminal of the second integrating channel circuit is connected to the inverting input terminal of the second operational amplifier via a fifth resistor; the output C of the third negative hyperbolic tangent circuit is connected to the third input terminal of the second integrating channel circuit, and the third input terminal of the second integrating channel circuit is connected to the inverting input terminal of the second operational amplifier via a sixth resistor; the in-phase input terminal of the second operational amplifier is grounded, the second capacitor is connected across the inverting input terminal and the output terminal of the second operational amplifier, the second membrane resistor is connected in parallel with the second capacitor, and the output of the second operational amplifier is used as the output of the second integrating channel circuit; The output of the second negative hyperbolic tangent circuit is passed through the second inverter, and the output of the second inverter The output of the third negative hyperbolic tangent circuit is connected to the third inverter, and the output of the third inverter is connected to the inverting input terminal of the third operational amplifier through the seventh resistor. The second input end of the third integral channel circuit is connected to the inverting input end of the third operational amplifier via the eighth resistor or the third memristor, and the eighth resistor and the third memristor are connected via the third switch Switching; the non-inverting input terminal of the third operational amplifier is grounded, the third capacitor is connected between the inverting input terminal and the output terminal of the third operational amplifier, the third membrane resistor is connected in parallel with the third capacitor, and the output of the third operational amplifier is used as the output of the third integration channel circuit; and When none of them are closed, the circuit equations of the first, second and third integration channel circuits are as follows: ， In the formula, and Respectively represent the outputs of the first, second and third integration channel circuits, and denote the first, second, third, fourth, fifth, sixth, seventh and eighth resistors respectively, represents the hyperbolic tangent, Represents the first, second and third membrane resistors, the resistance values ​​of the first, second and third membrane resistors are equal, represents the first, second and third capacitors, and the capacitance values ​​of the first, second and third capacitors are equal.

2. The memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors according to claim 1, characterized in that: The first memristor includes fourth to seventh operational amplifiers, ninth to fourteenth resistors, fourth to fifth membrane resistors, a fourth capacitor, fourth to fifth inverters, a fourth negative hyperbolic tangent circuit, a first multiplier, and a first coupling resistor; The output of the first inverter as the input of the first memristor; the input of the first memristor is connected to the inverting input terminal of the sixth operational amplifier via the thirteenth resistor, the output terminal of the sixth operational amplifier is connected to the inverting input terminal of the fourth operational amplifier, the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the fifth operational amplifier via the ninth resistor, the tenth resistor is connected across the inverting input terminal and the output terminal of the fifth operational amplifier, the output terminal of the fifth operational amplifier is connected to the inverting input terminal of the sixth operational amplifier after passing through the fourth inverter and the eleventh resistor in sequence; The fourth capacitor is connected between the inverting input terminal and the output terminal of the sixth operational amplifier, the twelfth resistor is connected in parallel with the fourth capacitor, the output terminal of the sixth operational amplifier is connected to the first input terminal of the first multiplier via the fourth negative hyperbolic tangent circuit, the input of the first memristor is connected to the second input terminal of the first multiplier, and the output terminal of the first multiplier is connected to the inverting input terminal of the seventh operational amplifier via the fourteenth resistor; the input of the first memristor is connected to the inverting input terminal of the seventh operational amplifier after passing through the fifth inverter and the fourth membrane resistor in sequence, the fifth membrane resistor is connected between the inverting input terminal and the output terminal of the seventh operational amplifier, and the output terminal of the seventh operational amplifier obtains the output of the first memristor via the first coupling resistor; the in-phase input terminals of the fourth, fifth, sixth and seventh operational amplifiers are all grounded; The circuit equation for the first memristor is as follows: ， In the formula, and Respectively represent the twelfth, thirteenth and fourteenth resistors, represents the fourth capacitor, and the capacitance value of the fourth capacitor is equal to that of the first capacitor. represents the output of the sixth operational amplifier, represents the voltage variable obtained by inverting the output of the second integral channel circuit, represents the hyperbolic tangent, Represents a symbolic function.

3. The memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors according to claim 1, characterized in that: The second memristor includes eighth to eleventh operational amplifiers, fifteenth to twenty-first resistors, a sixth membrane resistor, a fifth capacitor, sixth to seventh inverters, a fifth negative hyperbolic tangent circuit, a second multiplier, and a second coupling resistor; The output A of the second negative hyperbolic tangent circuit is used as the input of the second memristor; the input of the second memristor is connected to the inverting input terminal of the tenth operational amplifier after passing through the sixth inverter and the eighteenth resistor in sequence, the output terminal of the tenth operational amplifier is connected to the inverting input terminal of the eighth operational amplifier, the output terminal of the eighth operational amplifier is connected to the inverting input terminal of the ninth operational amplifier through the fifteenth resistor, the sixteenth resistor is connected across the inverting input terminal and the output terminal of the ninth operational amplifier, and the output terminal of the ninth operational amplifier is connected to the inverting input terminal of the tenth operational amplifier after passing through the seventh inverter and the nineteenth resistor in sequence; The fifth capacitor is connected between the inverting input terminal and the output terminal of the tenth operational amplifier, the twentieth resistor is connected in parallel with the fifth capacitor, the output terminal of the tenth operational amplifier is connected to the first input terminal of the second multiplier via the fifth negative hyperbolic tangent circuit, the input of the second memristor is connected to the second input terminal of the second multiplier, and the output terminal of the second multiplier is connected to the inverting input terminal of the eleventh operational amplifier via the twenty-first resistor; the input of the second memristor is connected to the inverting input terminal of the eleventh operational amplifier after passing through the sixth inverter and the seventeenth resistor in sequence, the sixth memristor is connected between the inverting input terminal and the output terminal of the eleventh operational amplifier, and the output terminal of the eleventh operational amplifier obtains the output of the second memristor via the second coupling resistor; the in-phase input terminals of the eighth, ninth, tenth and eleventh operational amplifiers are all grounded; The circuit equation for the second memristor is as follows: ， In the formula, and represent the nineteenth, twentieth and twenty-first resistors respectively, represents the fifth capacitor, and the capacitance value of the fifth capacitor is equal to that of the first capacitor. represents the output of the tenth operational amplifier, represents the voltage variable obtained by inverting the output of the first integral channel circuit, represents the hyperbolic tangent, Represents a symbolic function.

4. The memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors according to claim 1, characterized in that: The third memristor includes twelfth to fifteenth operational amplifiers, twenty-second to twenty-eighth resistors, a seventh membrane resistor, a sixth capacitor, eighth to ninth inverters, a sixth negative hyperbolic tangent circuit, a third multiplier and a third coupling resistor; The output of the third inverter as the input of the third memristor; the input of the third memristor is connected to the inverting input terminal of the fourteenth operational amplifier via the twenty-third resistor, the output terminal of the fourteenth operational amplifier is connected to the inverting input terminal of the twelfth operational amplifier, the output terminal of the twelfth operational amplifier is connected to the inverting input terminal of the thirteenth operational amplifier via the twenty-second resistor, the twenty-sixth resistor is connected across the inverting input terminal and the output terminal of the thirteenth operational amplifier, the output terminal of the thirteenth operational amplifier is connected to the inverting input terminal of the fourteenth operational amplifier after passing through the ninth inverter and the twenty-fourth resistor in sequence; The sixth capacitor is connected between the inverting input terminal and the output terminal of the fourteenth operational amplifier, the twenty-fifth resistor is connected in parallel with the sixth capacitor, the output terminal of the fourteenth operational amplifier is connected to the first input terminal of the third multiplier via the sixth negative hyperbolic tangent circuit, the input of the third memristor is connected to the second input terminal of the third multiplier, and the output terminal of the third multiplier is connected to the inverting input terminal of the fifteenth operational amplifier via the twenty-eighth resistor; the input of the third memristor is connected to the inverting input terminal of the fifteenth operational amplifier after passing through the eighth inverter and the twenty-seventh resistor in sequence, the seventh membrane resistor is connected between the inverting input terminal and the output terminal of the fifteenth operational amplifier, and the output terminal of the fifteenth operational amplifier obtains the output of the third memristor via the third coupling resistor; the in-phase input terminals of the twelfth, thirteenth, fourteenth and fifteenth operational amplifiers are all grounded; The circuit equation for the third memristor is as follows: ， In the formula, and denote the twenty-fourth, twenty-fifth and twenty-sixth resistors respectively, represents the sixth capacitor, and the capacitance value of the sixth capacitor is equal to that of the first capacitor. represents the output of the fourteenth operational amplifier, represents the voltage variable obtained by inverting the output of the third integral channel circuit, represents the hyperbolic tangent, Represents a symbolic function.

5. A method for implementing a memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors based on any one of claims 1 to 4, characterized in that: include: When the switch closure, and When turned on, the memristor neural network circuit is a single memristor neural network circuit. Multiple double vortex chaotic attractors with unidirectional distribution are generated on the plane; When the switch closure, and When turned on, the memristor neural network circuit is a single memristor neural network circuit. Multiple double vortex chaotic attractors with unidirectional distribution are generated on the plane; When the switch closure, and When turned on, the memristor neural network circuit is a single memristor neural network circuit. Multiple double vortex chaotic attractors with unidirectional distribution are generated on the plane; When the switch and closure, When turned on, the memristor neural network circuit is a dual memristor neural network circuit. Multiple double vortex chaotic attractors distributed in two directions are generated on the plane; When the switch and closure, When turned on, the memristor neural network circuit is a dual memristor neural network circuit. Multiple double vortex chaotic attractors distributed in two directions are generated on the plane; When the switch and closure, When turned on, the memristor neural network circuit is a dual memristor neural network circuit. Multiple double vortex chaotic attractors distributed in two directions are generated on the plane; When the switch , and When all are closed, the memristor neural network circuit is a three-memristor neural network circuit. and Multiple double vortex chaotic attractors distributed in three directions are generated on the plane.

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