Hard disk management system, method, electronic device and storage medium

Abstract

The present disclosure provides a hard disk management system, method, electronic device, and storage medium, relating to the field of hard disk management. The system includes: a CPU, configured to send a VPP signal to an I2CSWITCH chip; at least one I2CSWITCH chip, configured to receive the VPP signal output by the CPU and distribute the VPP signal into multiple shunt signals according to different PCIe ports, respectively, for transmission through corresponding I2CSWITCH channels; a parsing module, connected to the I2CSWITCH chip via multiple I2CSWITCH channels, configured to receive the shunt signals from the I2CSWITCH chip, determine a target hard disk from multiple NVME hard disks based on the shunt signals, and send corresponding management instructions to the target hard disk. The present disclosure effectively expands the number of available VPP addresses, meeting the growing demand for NVME hard disk management.

Description

Technical Field

[0001] The present disclosure relates to the field of hard disk management, and in particular to a hard disk management system, method, electronic device, and storage medium. Background Art

[0002] With the development of the internet and data centers, data storage and management are becoming increasingly important. NVME (Non-Volatile Memory Express) hard drives are widely used in server platforms due to their high performance and low latency. To efficiently manage these NVME hard drives, servers typically use VPP (Virtual Pin Port) signals for control and monitoring.

[0003] In traditional VPP topology solutions, the CPU communicates with the backplane's parsing chip (such as a CPLD) via a VPP signal to manage NVMe drives connected to multiple PCIe ports. However, the number of pre-set VPP addresses is limited to only eight. This makes it difficult to meet growing management needs as the CPU platform upgrades and the number of PCIe ports increases, leading to insufficient addresses. Summary of the Invention

[0004] The embodiments of the present disclosure provide a hard disk management system, method, electronic device, and storage medium, aiming to solve the problems existing in the above-mentioned background technology.

[0005] In order to solve the above technical problems, the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a hard disk management system, the system comprising:

[0007] The CPU deployed on the motherboard is used to send a VPP signal to the I2CSWITCH chip. The VPP signal includes a management instruction, which is used to instruct the management of the NVME hard disk;

[0008] At least one I2CSWITCH chip is deployed on the motherboard, the I2CSWITCH chip is used to receive the VPP signal output by the CPU, and distribute the VPP signal into multiple shunt signals according to different PCIe ports. The multiple shunt signals are multiple independent signals output by the I2CSWITCH chip based on the input VPP signal, and the multiple shunt signals are transmitted through their corresponding I2CSWITCH channels;

[0009] A parsing module deployed on the NVME hard disk backplane is connected to the I2CSWITCH chip through the multiple I2CSWITCH channels. The parsing module is used to receive a shunt signal from the I2CSWITCH chip, and determine a target hard disk from the multiple NVME hard disks according to the shunt signal, and send corresponding management instructions to the target hard disk.

[0010] Optionally, among the multiple shunt signals, the VPP address of each shunt signal is the same.

[0011] Optionally, for the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound to the corresponding high-speed data transmission signal.

[0012] Optionally, the system further includes an uplink device, which is connected to the analysis module by reusing the I2CSWITCH channel; the uplink device is used to send an I2C signal to the analysis module, and the I2C signal is used to instruct the management of the NVME hard disk.

[0013] Optionally, the parsing module includes any one of the following: a complex programmable logic device (CPLD), a microcontroller (MCU), and a PCA9555 expander.

[0014] In a second aspect, an embodiment of the present disclosure provides a hard disk management method, which is applied to a hard disk management system. The method includes:

[0015] Receive a VPP signal from the CPU, where the VPP signal includes a management instruction, where the management instruction is used to instruct management of the NVME hard disk;

[0016] The VPP signal is distributed into multiple shunt signals according to different PCIe ports through an I2CSWITCH chip, and the multiple shunt signals are transmitted to the analysis module through one-to-one corresponding I2CSWITCH channels. The multiple shunt signals are multiple independent signals output by the I2CSWITCH chip according to the input VPP signal;

[0017] Through the analysis module, a target hard disk is determined from the multiple NVME hard disks according to the shunt signal, and a management instruction corresponding to the shunt signal is sent to the target hard disk.

[0018] Optionally, determining a target hard disk from the multiple NVME hard disks according to the shunt signal by the parsing module, and sending a management instruction corresponding to the shunt signal to the target hard disk includes:

[0019] Receiving each shunt signal through the parsing module, wherein the VPP address of each shunt signal is the same, for the different PCIe ports, merging the VPP signal line of each PCIe port with the corresponding high-speed data transmission signal line, and binding the VPP signal of each PCIe port with the corresponding high-speed data transmission signal;

[0020] The shunt signal is matched with the high-speed data transmission signals of each of the multiple NVME hard disks to determine the target hard disk, and a corresponding management instruction is sent to the target hard disk.

[0021] Optionally, after sending the management instruction corresponding to the diversion signal to the target hard disk, the method further includes:

[0022] Acquire, via the corresponding I2CSWITCH channel, management information returned by the parsing module, in which the target hard disk responds to the management instruction;

[0023] Integrating the management information according to different PCIe ports, and sending the integrated management information to the CPU;

[0024] The CPU parses the management information and performs corresponding management operations according to the management information.

[0025] In a third aspect, an embodiment of the present disclosure provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the steps of a hard disk management method when executed by the processor.

[0026] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of a hard disk management method are implemented.

[0027] The technical solutions provided by the embodiments of the present disclosure bring at least the following beneficial effects:

[0028] This disclosure introduces the I2CSWITCH chip, which distributes the VPP signal into multiple shunt signals, effectively expanding the number of available VPP addresses to meet the growing demand for NVME hard drive management. This allows for efficient management even as the number of PCIe ports increases. The parsing module can quickly identify the target NVME hard drive and send corresponding management instructions based on the shunt signals from the I2CSWITCH chip, improving system response speed, reducing management latency, and enhancing the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 This is a topological diagram of a hard disk management system in the related art;

[0031] Figure 2 This is a topological diagram of a hard disk management system provided by an embodiment of the present disclosure;

[0032] Figure 3 This is a topology diagram of a hard disk management system under different VPP uplink signal multiplexing conditions provided by an embodiment of the present disclosure;

[0033] Figure 4 This is a schematic diagram of the steps of a hard disk management method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0035] In today's data centers and high-performance computing environments, the management and monitoring of NVMe drives is becoming increasingly important. As storage demands continue to grow, traditional drive management systems face numerous challenges, including insufficient VPP addresses, redundant cables, and low resolution efficiency, which restrict system scalability and flexibility. Figure 1 This is a topological diagram of a hard disk management system in related technology, such as Figure 1As shown, the CPU outputs a VPP signal, which is connected to the backplane's parsing module (VPP parsing IC) via an independent VPP cable. During this process, the CPU manages multiple PCIe ports, each of which corresponds to a different NVMe hard drive. The CPU transmits management information to the parsing module via this single VPP signal line, and the parsing module parses the VPP signal to identify and process the management instructions of each NVMe hard drive based on a specific VPP address. The parsing module on the backplane determines the NVMe disk to be operated based on the address information in the transmitted VPP signal and performs corresponding operations, such as fault diagnosis, lighting up the hard drive status indicator (the embodiment of this disclosure uses lighting as an example), etc. NVMe hard drives are distinguished by VPP addresses. Currently, there are only 8 available VPP addresses (0x40, 0x42, 0x44, 0x46, 0x48, 0x4A, 0x4C, 0x4E), so each CPU can only manage a maximum of 4 PCIe ports (because each port corresponds to two NVMe disks, and each disk requires an address). Each backplane is connected to the motherboard's CPU via a separate VPP cable. If the server configuration includes multiple backplanes, additional VPP cables are required to connect each backplane in series (using a daisy-chain topology) to ensure that all backplanes can receive the VPP signal from the CPU.

[0036] visible, Figure 1 The illustrated disk management system topology has several significant drawbacks. First, there are only eight available VPP addresses, limiting the number of NVMe drives that can be managed by each CPU. As CPU platforms upgrade, the number of PCIe ports continues to increase, and eight VPP addresses are no longer sufficient. Expansion chips are required for address multiplexing, increasing system design complexity. Second, each backplane requires a separate VPP cable, resulting in redundant cables. In a multi-backplane configuration, the number of cables increases dramatically, making cable management difficult and increasing assembly and maintenance complexity. Using a daisy-chain topology to connect backplanes can lead to signal quality degradation due to cable length, impacting overall performance. Furthermore, the parsing module on the backplane must parse each NVMe drive based on the VPP signal address information. As the number of ports increases, the parsing module's workload increases, consuming significant parsing resources, increasing hardware cost and design complexity. If support for multiple upstream controllers (such as the motherboard and RAID card) is required, the parsing module must simultaneously parse VPP signals from different buses, further increasing parsing complexity.

[0037] This paper proposes an innovative hard disk management system, which aims to introduce an I2CSWITCH chip to intelligently divert VPP signals and distribute them to various PCIe ports on demand, thereby achieving efficient NVME hard disk management. This not only simplifies cable wiring and reduces hardware costs, but also significantly improves analysis efficiency and system response speed. Figure 2 This is a topological diagram of a hard disk management system provided by an embodiment of the present disclosure, such as Figure 2 As shown, the system includes: a CPU deployed on a motherboard, configured to send a VPP signal to an I2CSWITCH chip, wherein the VPP signal includes a management instruction, and the management instruction is used to instruct management of an NVME hard disk; at least one I2CSWITCH chip deployed on the motherboard, wherein the I2CSWITCH chip is configured to receive the VPP signal output by the CPU and distribute the VPP signal into multiple shunt signals according to different PCIe ports. The multiple shunt signals are multiple independent signals output by the I2CSWITCH chip according to the input VPP signal, and the multiple shunt signals are transmitted through their respective corresponding I2CSWITCH channels; a parsing module deployed on the NVME hard disk backplane, wherein the parsing module is connected to the I2CSWITCH chip through the multiple I2CSWITCH channels, and the parsing module is configured to receive the shunt signal from the I2CSWITCH chip, and determine a target hard disk from the multiple NVME hard disks according to the shunt signal, and send corresponding management instructions to the target hard disk.

[0038] The hard drive management system provided in the embodiments of the present disclosure primarily consists of the following key components: The first component is the CPU, deployed on the server motherboard, responsible for generating and sending VPP signals. The VPP signal is generated by the CPU and contains management instructions that instruct the system to perform various management operations on NVMe hard drives, such as fault diagnosis, hard drive location, and hot-swap processing. The VPP signal transfers management instructions from the CPU to the I2CSWITCH chip, which then transmits the instructions to the corresponding NVMe hard drive through a shunt mechanism. The CPU controls NVMe hard drive management by transmitting the VPP signal to the I2CSWITCH chip. The second component is the I2CSWITCH chip, also deployed on the motherboard, which receives and shunts the VPP signal from the CPU. Specifically, the I2CSWITCH chip can distribute the VPP signal into multiple shunt signals based on different PCIe ports. These shunt signals are transmitted through different channels of the I2CSWITCH for precise delivery to their corresponding NVMe hard drive backplanes. The shunt signals are multiple independent signals generated by the I2CSWITCH chip based on the input VPP signal. Each shunt signal corresponds to a specific PCIe port and a corresponding NVMe drive. By splitting the VPP signal into multiple shunt signals, multiple NVMe drives can be managed simultaneously. Each shunt signal is transmitted through its own corresponding I2CSWITCH channel, ensuring that each drive receives the correct management instructions. Multiple shunt signals enable the system to flexibly expand and manage multiple drives without requiring complex signal paths for each drive. The third component is the parsing module, deployed on the NVMe drive's backplane. It is responsible for receiving the VPP signal shunt from the I2CSWITCH chip. Based on the received shunt signal, the parsing module identifies the location of the target drive and executes the corresponding management instructions. In this disclosed embodiment, the target drive is the NVMe drive that the VPP signal is intended to manage. This can be one drive or multiple drives, depending on the management instructions issued by the CPU. For example, if the CPU needs to read the status information of Drive A through Port 1 and issues the corresponding VPP signal, Drive A is the target drive. This module connects to the various channels of the I2CSWITCH chip to ensure independent control and management of each NVMe drive.

[0039] In this disclosure, the I2C SWITCH chip uses a shunt mechanism to achieve efficient management of multiple NVMe hard drives. Specifically, the I2C SWITCH chip is a multi-channel switch chip, typically used to manage signal transmission within the I2C bus. In an embodiment of this disclosure, the I2C SWITCH chip is connected between the motherboard's CPU and multiple NVMe hard drive backplanes, primarily used to shunt the CPU-generated VPP signals to each hard drive according to different requirements. When multiple NVMe hard drives need to be managed, the CPU generates one or more VPP signals and transmits them to the I2C SWITCH chip on the motherboard. After receiving the signals from the CPU, the I2C SWITCH chip distributes these signals to multiple channels based on predefined configurations or instructions. Each channel transmits the assigned signal to a specific hard drive backplane. Suppose the CPU sends a VPP signal indicating that an operation is to be managed for a specific NVMe hard drive. During this process, the I2C SWITCH chip's main task is to shunt the VPP signal into multiple independent signals, each corresponding to a different PCIe port or hard drive backplane. The I2CSWITCH chip splits a VPP signal into multiple sub-signals based on its internal channel configuration. These sub-signals are then transmitted to the subsequent NVMe drive backplane via its multiple channels. The signal in each channel is associated with a corresponding PCIe port, ensuring that each NVMe drive receives independent management signals. This allows multiple drives to be managed in parallel without conflict or interference.

[0040] As mentioned above, one problem that may be encountered in VPP signal transmission is that the VPP address space is limited, making it difficult to manage a large number of NVMe hard drives. In related technologies, only 8 VPP addresses are supported (for example: 0x40, 0x42, 0x44, 0x46, 0x48, 0x4A, 0x4C, 0x4E), which means that in a server, a maximum of 8 NVME hard drives can be managed. However, with the development of technology, the number of PCIe ports on modern server platforms continues to increase, and it may be necessary to manage 16, 32 or even more NVME hard drives at the same time. The present disclosure deploys one or more I2CSWITCH chips, and the VPP signal output by the CPU can be diverted into multiple independent signal channels. For example, assuming that an I2CSWITCH chip can divide the VPP signal into 4 independent channels, each channel can be connected to multiple NVME hard drives. In this way, assuming that each channel can manage 4 hard drives, then through a single I2CSWITCH chip, the hard drive management system can manage up to 16 hard drives (4 channels x 4 hard drives). Furthermore, if multiple I2CSWITCH chips are added, or higher-specification I2CSWITCH chips are used, the number of managed hard drives can be further expanded. For example, if two I2CSWITCH chips each support four channels, and each channel can manage four hard drives, the hard drive management system can manage up to 32 hard drives (2 chips x 4 channels x 4 hard drives). This not only solves the problem of insufficient VPP addresses, but also provides unlimited possibilities for future expansion, allowing users to easily manage a large number of NVME hard drives according to actual needs and meet the ever-growing demand for data storage.

[0041] This disclosure introduces the I2CSWITCH chip, which effectively expands the number of available VPP addresses by dividing the VPP signal into multiple shunt signals, meeting the growing demand for NVME hard drive management. This enables efficient management even as the number of PCIe ports increases. The parsing module can quickly identify the target NVME hard drive based on the shunt signals from the I2CSWITCH chip and send corresponding management instructions, improving system response speed, reducing management latency, and enhancing the user experience.

[0042] Exemplarily, among the multiple shunt signals, the VPP address of each shunt signal is the same.

[0043] In traditional I2C architectures, each NVMe drive backplane or device typically requires a unique VPP address to distinguish management commands and signals. As the number of drive devices in a system increases, the VPP address space can become insufficient. Managing a large number of devices can exhaust the available address space, making it impossible to assign unique addresses to each drive.

[0044] If multiple devices share the same I2C bus and use the same VPP address, address conflicts will occur, and signals cannot be transmitted and parsed correctly. As the number of hard disk devices increases, assigning different VPP addresses also increases the complexity of configuration and management.

[0045] The present disclosure allows multiple shunt signals to share the same VPP address by using the I2CSWITCH chip, thereby solving the problem of insufficient address space and conflict in the traditional architecture. Specifically, the VPP signal is shunted by the I2CSWITCH chip, and each shunt signal carries the same VPP address, which can greatly simplify the management and expansion capabilities of the VPP signal. After the I2CSWITCH chip receives the VPP signal transmitted by the CPU, it can shunt the VPP signal to multiple channels through an internal multi-channel design, and the signal sent by each channel carries the same VPP address. That is, the VPP address is consistent in the signals actually received by all NVMe hard disk devices. Under the topological architecture of the present disclosure, no matter how many hard disk devices there are in the system, the I2CSWITCH chip allows these devices to share the same VPP address. It greatly saves the address space used for management and configuration in the system, making it possible to expand the number of hard disks on a large scale without changing the VPP address.

[0046] Suppose a system has eight NVMe drive backplanes. In a traditional architecture, these drives require eight different VPP addresses. If the number of available VPP addresses is limited, expanding to more drives may result in insufficient address space. However, in the disclosed embodiment, through traffic diversion using the I2CSWITCH chip, the drives on each backplane can use the same VPP address. For example, all eight drive backplanes use address 0x10. Even if the number increases to 16 or more drives, the same VPP address can still be used, solving the problem of insufficient address space. Because all drive devices use the same VPP address and the I2CSWITCH chip allocates independent channels for signal transmission, address conflicts, as in traditional architectures, are eliminated. Signals from each channel are precisely routed to a specific drive device without the risk of signal confusion or conflicts. In a system without an I2CSWITCH chip, if two NVMe drive devices share the same VPP address 0x20, the transmitted signals may conflict, causing operation failure. However, in the disclosed architecture, even if multiple drives use the same VPP address 0x20, since the signals are transmitted through different channels, each drive can still receive the signal correctly, eliminating conflicts.

[0047] Furthermore, each shunt signal uses the same VPP address, providing tremendous flexibility for system expansion. When adding new hard drives, there's no need to configure a separate VPP address for each new device; instead, the address can be assigned through the channels of the I2CSWITCH chip. This not only reduces management complexity but also significantly enhances system scalability. For example, if the system expands from 8 to 16 hard drives, simply increase the number of channels in the I2CSWITCH chip, eliminating the need to configure new VPP addresses for each new drive, simplifying system expansion.

[0048] In the topology architecture disclosed in the present invention, multiple shunt signals use the same VPP address, which is achieved through the multi-channel allocation mechanism of the I2CSWITCH chip. This solves the problems of VPP address conflicts and insufficient address space in traditional architectures, greatly improves the system's scalability and signal management efficiency, and can significantly simplify configuration and improve system performance.

[0049] Exemplarily, for the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound to the corresponding high-speed data transmission signal.

[0050] In traditional server NVMe management systems, each PCIe port has two distinct signal cables: one for transmitting VPP signals and the other for high-speed data transmission (MCIO). VPP signals are used to manage NVMe drive status, fault diagnosis, drive location, hot swapping, and other functions, while high-speed data transmission signals are used to handle the rapid transmission of large amounts of data. Traditional designs require two separate signal cables for each PCIe port: one for VPP signals and one for MCIO high-speed signals. However, as the number of NVMe drives in servers increases, the number of signal cables required for each port increases significantly, resulting in complex cabling and difficult assembly and maintenance. Independent signal cables require precise cable management and layout, especially in multi-backplane configurations. Redundant VPP cables further complicate connectivity. Furthermore, long cable runs can cause signal attenuation and interference, impacting VPP signal transmission quality.

[0051] Considering the above issues, the present disclosure proposes a solution that merges the VPP signal line with the high-speed data transmission signal line. Specifically, the VPP signal for each PCIe port is merged with its corresponding high-speed data transmission signal line (MCIO), achieving signal bundling. The VPP signal no longer travels via a separate cable, but instead shares the same cable with the high-speed data transmission signal (MCIO). The I2C SWITCH chip manages multiple PCIe ports through different channels, with each channel simultaneously transmitting the VPP signal and the high-speed data transmission signal. By bundling these two signals, the system can simultaneously transmit management information (VPP) and data information (MCIO). In a traditional solution, assuming a server has four backplanes, each connected to eight NVMe drives, separate VPP and MCIO cables are required for each backplane. This requires a total of 32 cables (4 backplanes x 8 ports x 2 cables). The proposed merging solution reduces the number of cables by half, requiring only 16 cables (4 backplanes x 8 ports x 1 cable), significantly simplifying the design. Bundling the VPP and MCIO signals avoids VPP signal interference caused by excessively long cables. The signals are uniformly transmitted through MCIO high-speed cables, which have higher cable quality and transmission stability, effectively improving the transmission efficiency of VPP signals.

[0052] In addition, in the traditional solution, the parsing module needs to parse the source address of each VPP signal and perform operations and management according to different NVMe disk slots. However, with the improvement of the present disclosure, since the VPP signal is bound to the MCIO high-speed signal and the transmission path is unified, the parsing logic of the parsing module has been simplified, and there is no need to perform independent parsing for each VPP address, which reduces the resource usage of the parsing module and reduces the design complexity. In the combined solution of the present disclosure, the parsing module no longer needs to assign a different VPP address to each NVMe hard drive for parsing, but can manage it through the unified VPP signal transmitted by MCIO, which greatly reduces resource usage and improves parsing efficiency.

[0053] In general, the present disclosure optimizes the existing VPP management solution by merging the VPP signal with the high-speed data transmission signal line, significantly improving the design simplicity, performance and scalability of the system.

[0054] Exemplarily, the system further includes an uplink device, which is connected to the analysis module by reusing the I2CSWITCH channel; the uplink device is used to send an I2C signal to the analysis module, and the I2C signal is used to instruct management of the NVME hard disk.

[0055] In the traditional VPP solution, the motherboard and upstream devices (such as Tri-mode RAID cards) are each connected and communicated with the analysis module (such as CPLD) through independent channels. Each upstream device sends its own management signal (VPP signal or I2C signal) to manage the NVMe hard drive. Due to the different signal sources of the two upstream devices, the backplane analysis module, such as the complex programmable logic device CPLD, needs to allocate different resources for each device, such as GPIO pins and signal channels. The CPLD needs to process the signals of the motherboard and RAID card separately, occupying more GPIO and logic resources. The inconsistent signals of the two upstream devices make the CPLD analysis logic complex and increase the cost of CPLD material selection.

[0056] Figure 3 FIG. 1 is a topology diagram of a hard disk management system under different VPP uplink signal multiplexing conditions provided by an embodiment of the present disclosure, such as Figure 3 As shown, the present disclosure is based on I2CSWITCH technology, which unifies the signals of different upstream devices (such as motherboards and Tri-modeRAID cards) and connects them to the parsing module by multiplexing the same I2C channel. The I2CSWITCH chip acts as a multiplexer, which is used to transmit management signals (including VPP signals and I2C signals) to the parsing module through corresponding channels according to different PCIe ports and other upstream devices. I2CSWITCH is capable of processing I2C signals or VPP signals from multiple different upstream devices, and selects appropriate channels to send these signals to the CPLD for parsing. The VPP signal output by the motherboard is no longer transmitted through an independent VPP cable, but is multiplexed with the I2CSWITCH channel and transmitted to other upstream devices through the same I2CSWITCH channel. In Figure 3 In the Tri-modeRAID card shown, the I2C signal is used to manage the NVMe hard drive. In the traditional design, it is transmitted through different paths. In the embodiment of the present disclosure, the I2C signal of the Tri-modeRAID card and the VPP signal of the motherboard can share the same I2CSWITCH channel and be passed to the parsing module through the same path. The VPP signal of the motherboard and the I2C signal of the Tri-modeRAID card can share the same VPP address. Due to the use of I2CSWITCH, the parsing module no longer needs to allocate different address spaces for different devices. It only needs to parse the multiplexed channels, which greatly simplifies the parsing logic of the parsing module. Since the I2CSWITCH chip can uniformly manage the signals of different upstream devices, the parsing module, such as CPLD, no longer needs to independently allocate GPIO pins or complex logic resources for each device. It only needs to parse the signals sent from the I2CSWITCH channel and execute the management instructions of the NVMe hard drive (such as lighting, fault reporting, etc.).

[0057] Exemplarily, the parsing module includes any one of the following: a complex programmable logic device (CPLD), a microcontroller (MCU), and a PCA9555 expander.

[0058] CPLD (Complex Programmable Logic Device) is a digital logic integrated circuit that can define its logical behavior through programming and is used to implement various complex logic control and signal processing tasks. Its hardware logic can be customized and programmed according to needs. As mentioned above, CPLD can receive signals transmitted by upstream devices (such as motherboards and Tri-mode RAID cards) through I2C SWITCH in real time, parse their contents and manage NVMe hard drives. CPLD can achieve compatible processing of different signal protocols through programming. Because CPLD is highly programmable, it can dynamically configure internal logic resources according to different hardware requirements to cope with different signal types (such as VPP signals and I2C signals). In addition, CPLD has parallel processing capabilities and can manage the status of multiple NVMe hard drives at the same time, including hard drive fault monitoring, LED status indication, startup and deactivation operations. Therefore, the present invention prefers CPLD as the parsing module.

[0059] An MCU (Microcontroller Unit) is a single-chip computer that integrates a processor, memory, and input / output (I / O) interfaces. It is typically used in embedded systems to perform specific control tasks. Compared to CPLDs, MCUs typically offer richer software programming capabilities and higher processor performance. Compared to CPLDs, MCUs have relatively lower hardware costs and are suitable for simpler or moderately complex systems. Therefore, MCUs are suitable for scenarios that require certain signal processing and hard disk management but do not require overly complex logic control. They are also well-suited for scenarios requiring flexible control logic implemented through software, particularly systems where signal analysis is relatively simple but require a degree of intelligent management.

[0060] The PCA9555 is an I / O expander with an I2C interface. It provides additional I / O pins, communicates with the host controller via the I2C bus, and expands the GPIO (general-purpose input / output) port. This allows systems with insufficient I / O pin resources to control or monitor peripheral devices by extending the I2C bus to include more signal pins. As an I / O expander, the PCA9555 offers a simple, low-cost design and is suitable for systems requiring extensive GPIO expansion. When the CPLD or MCU's I / O resources are insufficient, the PCA9555 can be used to extend additional pins for controlling and monitoring the status of multiple NVMe drives.

[0061] Exemplarily, the system also includes a status monitoring module, which is connected to the analysis module and is used to monitor the operating status of the target hard disk in real time and feed back monitoring information to the CPU. The monitoring information includes hard disk health status, temperature, data transmission rate and fault diagnosis information.

[0062] The status monitoring module is designed to comprehensively monitor the operating status of NVMe drives. By communicating with the parsing module, it can obtain the operating status of each target drive in real time. Optionally, it can periodically read the SMART information of each NVMe drive. Monitoring information such as drive health status, temperature, data transfer rate, and fault diagnosis information is fed back to the CPU.

[0063] The status monitoring module collects key hard drive metrics in real time, effectively identifying potential hard drive failures or performance issues. When a hard drive experiences an anomaly, the module promptly issues a warning signal, prompting the CPU to issue appropriate management instructions (such as shutting down the failed drive or performing recovery operations). For example, if a hard drive's SMART value indicates that its operating time is nearing the end of its lifespan, the status monitoring module immediately transmits this information to the CPU. Upon receiving this information, the CPU issues a warning signal and instructs the administrator to replace the drive as soon as possible to avoid data loss. Furthermore, by monitoring parameters such as temperature and transfer rate, resource allocation is optimized to prevent hard drive overload or overheating from impacting overall performance. Optionally, a threshold comparison can be used for checking. If a hard drive's temperature exceeds a safe range, the status monitoring module immediately transmits this temperature data to the CPU. Upon receiving this information, the CPU can automatically take action, such as adjusting fan speed, reducing the hard drive's workload, or even temporarily disabling the drive until the temperature returns to normal. For example, if an NVMe hard drive overheats and its temperature rises to 75°C, the status monitoring module immediately feeds this information back to the CPU, which then adjusts the hard drive's load to prevent further temperature increases and damage. In scenarios where large data or high-concurrency requests are processed, the status monitoring module tracks the data transfer rate of the NVMe hard drive in real time.

[0064] If a drive's transfer rate fluctuates abnormally (for example, falling far below normal), the status monitoring module will report this anomaly to the CPU. The CPU uses this information to assess the drive's performance bottleneck and decide whether to optimize data flow paths or implement load balancing. For example, if a drive's data transfer rate consistently falls below expectations, the status monitoring module will detect this issue and report it to the CPU. The CPU will then reallocate data flow, alleviating pressure on the drive and optimizing system performance.

[0065] The status monitoring module provided by the disclosed embodiments comprehensively monitors the operating status of each NVMe hard drive, ensuring timely resolution before any issues arise, preventing data loss and system crashes. This module also improves the hard drive's lifespan and overall system stability. Specific monitoring information provides strong support for system management decisions, making it particularly suitable for high-intensity, high-reliability application scenarios such as data centers and cloud computing platforms. Automated monitoring and management reduces the need for human intervention, improving system efficiency and security.

[0066] Figure 4 This is a schematic diagram of the steps of a hard disk management method provided by an embodiment of the present disclosure, which is applied to the hard disk management system as described above. Figure 4 As shown, the method includes:

[0067] Step S101, receiving a VPP signal from a CPU, wherein the VPP signal includes a management instruction, and the management instruction is used to instruct management of an NVME hard disk;

[0068] Step S102: Distribute the VPP signal into multiple shunt signals according to different PCIe ports through an I2C SWITCH chip, and transmit the multiple shunt signals to a parsing module through one-to-one corresponding I2C SWITCH channels. The multiple shunt signals are multiple independent signals output by the I2C SWITCH chip based on the input VPP signal.

[0069] Step S103: Determine a target hard disk from the multiple NVME hard disks according to the shunt signal through the analysis module, and send a management instruction corresponding to the shunt signal to the target hard disk.

[0070] In step S101, the CPU receives a VPP signal via the I2C SWITCH chip. This signal initiates the entire NVMe drive management process. In this step, the CPU, acting as the control center, first processes the overall system requirements and then sends the corresponding VPP signal to the I2C SWITCH chip via a specific PCIe interface. The VPP signal contains management instructions for specific NVMe drives and indicates the management task to be performed. It serves as the starting point for management operations, ensuring that the system promptly responds to and processes instructions issued by the CPU.

[0071] Involving step S102, when the I2CSWITCH chip receives the VPP signal from the CPU, it shunts the VPP signal into multiple management signals for different hard disks according to the different PCIe ports specified in the signal. A VPP signal sent by the CPU is disassembled into multiple sub-signals, and each is transmitted to the hard disk parsing module through a one-to-one corresponding I2CSWITCH channel. At this stage, the I2CSWITCH chip effectively acts as a signal scheduler, matching the control information in the VPP signal to different PCIe ports and ensuring that the signal can be accurately transmitted to the corresponding hard disk parsing module. The shunt signal transmitted by each channel contains specific management instructions, indicating which operation to perform on which hard disk.

[0072] Involving step S103, after receiving the shunt signal transmitted through the I2CSWITCH chip, the parsing module starts working. It determines the specific target hard disk based on the received shunt signal. The parsing module will analyze the shunt signal, extract the identification information of the target hard disk, and determine which hard disk to manage next in combination with the management instructions. Once the parsing module determines the target hard disk, it will send the corresponding management instructions to the target hard disk according to the instructions carried in the shunt signal. After receiving these instructions, the target hard disk performs the corresponding management operations according to the instruction requirements, such as starting, stopping or performing data transmission. Throughout the process, the core task of the parsing module is to ensure that the management instructions are accurately transmitted to the target hard disk and prompt the hard disk to execute according to the predetermined requirements.

[0073] This disclosure introduces the I2CSWITCH chip, which effectively expands the number of available VPP addresses by dividing the VPP signal into multiple shunt signals, meeting the growing demand for NVME hard drive management. This enables efficient management even as the number of PCIe ports increases. The parsing module can quickly identify the target NVME hard drive based on the shunt signals from the I2CSWITCH chip and send corresponding management instructions, improving system response speed, reducing management latency, and enhancing the user experience.

[0074] Exemplarily, the analysis module determines the target hard disk from the multiple NVME hard disks according to the shunt signal, and sends the management instruction corresponding to the shunt signal to the target hard disk, including: receiving each shunt signal through the analysis module, wherein the VPP address of each shunt signal is the same, for the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound to the corresponding high-speed data transmission signal; matching the shunt signal with the high-speed data transmission signals of each of the multiple NVME hard disks, determining the target hard disk, and sending the corresponding management instruction to the target hard disk.

[0075] The parsing module first receives the split signal from the I2CSWITCH. The split signal is the result of the CPU's VPP signal being split through the I2CSWITCH chip. Although all split signals have the same VPP address, they are distributed and transmitted, and each split signal is now associated with a different PCIe port. Suppose there are three NVMe drives in the system, connected to PCIe ports 1, 2, and 3. The CPU issues a common VPP signal, which is split into three separate signals through the I2CSWITCH and sent to the parsing module, one for each PCIe port. The VPP signal line for each PCIe port is merged with its corresponding high-speed data transmission signal line. This VPP signal not only manages the start and stop of the drive but also binds it to the NVMe drive's data transmission channel. For example, an NVMe drive connected to PCIe port 1 will have a bound VPP signal line and a corresponding data transmission signal line, which are merged during transmission. Therefore, whenever a VPP signal is received from this port, the parsing module can also use this signal line to access the corresponding drive's high-speed data transmission status.

[0076] After receiving these signals, the parsing module needs to perform a matching operation. It compares each shunt signal with the high-speed data transmission signals of multiple NVMe hard drives to find the signal corresponding to a specific hard drive. In other words, the parsing module will identify which specific hard drive is communicating through each PCIe port based on the signal of that port. For example, the parsing module receives a VPP signal from PCIe port 1 and simultaneously detects the corresponding high-speed data transmission signal on the port. Through this matching, the parsing module can confirm that this VPP signal is for the first NVMe hard drive connected to PCIe port 1.

[0077] When the parsing module completes the matching of the shunt signal and the high-speed data transmission signal, the specific target hard disk is determined. Then, the parsing module sends the management instructions contained in the shunt signal to the target hard disk, and the hard disk performs corresponding management operations according to these instructions, such as starting, stopping, or data processing. For example, after the parsing module confirms through matching that the NVMe hard disk on PCIe port 1 is the target hard disk, it will send management instructions (such as starting the hard disk or starting data transmission) to the hard disk. After receiving the management instructions, the target hard disk performs the task as required.

[0078] Exemplarily, after sending the management instruction corresponding to the diversion signal to the target hard disk, the method further includes: obtaining, through the corresponding I2CSWITCH channel, the management information of the target hard disk in response to the management instruction, which is returned by the parsing module; integrating the management information according to different PCIe ports, and sending the integrated management information to the CPU; parsing the management information by the CPU, and performing corresponding management operations based on the management information.

[0079] After sending the management instructions to the target hard disk, the target hard disk will perform corresponding operations according to the instructions and generate management information. The management information is returned to the parsing module through the corresponding I2CSWITCH channel. The parsing module is responsible for collecting and processing this information. Assume that the target hard disk is an NVMe hard disk connected through PCIe port 1, and the CPU sends a startup instruction to the hard disk. After the hard disk is started, it will return status information through the I2CSWITCH channel, such as "startup successful" or "startup failed", and the status information is first received by the parsing module. When the parsing module receives management information from different hard disks from multiple PCIe ports, it integrates the management information according to the different PCIe ports. The purpose of integration is to organize the information of each hard disk and return it to the CPU in a unified format. For example, the parsing module receives the following management information from multiple PCIe ports:

[0080] PCIe port 1 returns information that the hard disk is successfully started;

[0081] PCIe port 2 returns information: Hard disk data reading is normal;

[0082] PCIe port 3 returns a message indicating a hard drive failure. The parsing module then marks these responses as originating from different PCIe ports and aggregates them into a single packet, also sending it to the CPU as a VPP signal. After receiving this aggregated management information, the CPU parses it and takes appropriate management actions based on the feedback from each hard drive. Based on the status of each hard drive, the CPU can make adjustments or issue new instructions.

[0083] In this example, after receiving the management information, the CPU parses it and finds that: the hard disk on PCIe port 1 has started successfully and no further operation is required; the hard disk on PCIe port 2 is operating normally, and the CPU can continue to assign data tasks to it; the hard disk on PCIe port 3 fails, and the CPU will issue a new instruction, which may be to stop the operation of the hard disk or perform diagnostic and recovery operations.

[0084] The present disclosure realizes efficient management of multiple NVMe hard disks by introducing the I2CSWITCH chip. By shunting the VPP signal from the CPU and transmitting it to each NVMe hard disk, different hard disk devices can be accurately identified and managed. At the same time, the parsing module quickly determines the target hard disk and sends corresponding management instructions by matching the shunted signal with the high-speed data transmission signal. It not only improves the management accuracy of the system, but also optimizes the status monitoring and response speed of the hard disk by integrating the management information of the hard disk and sending it to the CPU, effectively reducing management delays and improving the scalability of the system and user experience. Even when the number of PCIe ports increases, efficient and reliable management operations of NVMe hard disks can still be ensured.

[0085] An embodiment of the present disclosure also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the various processes in the above-mentioned embodiment of a hard disk management method are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0086] The present disclosure also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the various processes in the above-mentioned embodiment of a hard disk management method are implemented, and the same technical effects are achieved. To avoid repetition, they are not described here. The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to in detail.

[0087] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, electronic devices, and computer-readable media. Therefore, the embodiments of the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the embodiments of the present disclosure may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0088] The embodiments of the present disclosure are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer readable memory that can guide a computer or other programmable data processing terminal device to work in a specific way, so that the instructions stored in the computer readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0089] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0090] Finally, it should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variant thereof is intended to encompass non-exclusive inclusion, such that a process, method, article, or terminal device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or terminal device. Without further limitation, elements defined by the phrase "comprising..." do not preclude the presence of additional identical elements in the process, method, article, or terminal device comprising the elements. The above detailed description of a hard disk management system, method, electronic device, and storage medium provided by the present disclosure has been provided. Specific examples have been used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is intended only to facilitate understanding of the methods and core concepts of the present disclosure. Furthermore, those skilled in the art will appreciate that variations in the specific implementation methods and scope of application are possible based on the concepts of the present disclosure. In summary, the contents of this specification should not be construed as limiting the present disclosure.

Claims

1. A hard disk management system, characterized in that: The system comprises: The CPU deployed on the motherboard is used to send a VPP signal to the I2C SWITCH chip. The VPP signal includes a management instruction, which is used to instruct the management of the NVME hard disk. At least one I2C SWITCH chip is deployed on the motherboard, the I2C SWITCH chip is used to receive the VPP signal output by the CPU and distribute the VPP signal into multiple shunt signals according to different PCIe ports. The multiple shunt signals are multiple independent signals output by the I2C SWITCH chip based on the input VPP signal, and the multiple shunt signals are transmitted through their corresponding I2C SWITCH channels; A parsing module deployed on the NVME hard disk backplane is connected to the I2C SWITCH chip through the multiple I2C SWITCH channels. The parsing module is used to receive a shunt signal from the I2C SWITCH chip, and determine a target hard disk from the multiple NVME hard disks based on the shunt signal, and send corresponding management instructions to the target hard disk.

2. The system according to claim 1, wherein: Among the plurality of shunt signals, the VPP address of each shunt signal is the same.

3. The system according to claim 2, characterized in that For the different PCIe ports, the VPP signal line of each PCIe port is merged with the corresponding high-speed data transmission signal line, and the VPP signal of each PCIe port is bound to the corresponding high-speed data transmission signal.

4. The system according to claim 1, wherein: The system also includes an uplink device, which is connected to the analysis module by multiplexing the I2C SWITCH channel; the uplink device is used to send an I2C signal to the analysis module, and the I2C signal is used to instruct the management of the NVME hard disk.

5. The system according to claim 1, wherein: The analysis module includes any one of the following: a complex programmable logic device CPLD, a microcontroller MCU and a PCA9555 expander.

6. A hard disk management method, characterized in that: Applied to the system according to any one of claims 1 to 5, the method comprises: Receive a VPP signal from the CPU, where the VPP signal includes a management instruction, where the management instruction is used to instruct management of the NVME hard disk; The VPP signal is distributed into a plurality of shunt signals according to different PCIe ports through an I2C SWITCH chip, and the plurality of shunt signals are transmitted to a parsing module through one-to-one corresponding I2C SWITCH channels. The plurality of shunt signals are a plurality of independent signals output by the I2C SWITCH chip according to the input VPP signal; Through the analysis module, a target hard disk is determined from the multiple NVME hard disks according to the shunt signal, and a management instruction corresponding to the shunt signal is sent to the target hard disk.

7. The method according to claim 6, characterized in that The step of determining a target hard disk from the plurality of NVME hard disks according to the shunt signal by the parsing module, and sending a management instruction corresponding to the shunt signal to the target hard disk, includes: Receiving each shunt signal through the parsing module, wherein the VPP address of each shunt signal is the same, for the different PCIe ports, merging the VPP signal line of each PCIe port with the corresponding high-speed data transmission signal line, and binding the VPP signal of each PCIe port with the corresponding high-speed data transmission signal; The shunt signal is matched with the high-speed data transmission signals of each of the multiple NVME hard disks to determine the target hard disk, and a corresponding management instruction is sent to the target hard disk.

8. The method according to claim 6, characterized in that After sending the management instruction corresponding to the diversion signal to the target hard disk, the method further includes: Acquire, through the corresponding I2C SWITCH channel, management information returned by the parsing module, in which the target hard disk responds to the management instruction; Integrating the management information according to different PCIe ports, and sending the integrated management information to the CPU; The CPU parses the management information and performs corresponding management operations according to the management information.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the steps of the method according to any one of claims 6 to 8 when executed by the processor.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 6 to 8 are implemented.

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