Display device and method of manufacturing same

Abstract

The invention discloses a display device and a method of manufacturing the same. The display device includes: a display element; a semiconductor pattern including a first region having a first thickness and a second region having a second thickness, where the second thickness is greater than the first thickness; a first transistor including a first gate electrode and a first channel region as a part of the semiconductor pattern, at least a part of the first gate electrode overlapping the first channel region; and a second transistor including a second gate electrode and a second channel region as a part of the semiconductor pattern, at least a part of the second gate electrode overlapping the second channel region, in which a second region of the semiconductor pattern includes a corner portion of the semiconductor pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0090031 filed in the Korean Intellectual Property Office on July 11, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of one or more embodiments are directed to a display device and a method of manufacturing the display device. Background Art

[0004] Generally speaking, a display device includes a plurality of pixels, and each of the plurality of pixels includes a display element and a pixel circuit for controlling the display element. The pixel circuit may include a storage capacitor, wiring, and one or more thin film transistors (TFTs).

[0005] In order to more accurately control whether a display element emits light and the degree of light emission, the number of thin film transistors electrically connected to one display element may be relatively increased.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of one or more embodiments relate to a display device and a method of manufacturing the display device, and, for example, to a display device that can display a high-quality image and a method of manufacturing the display device.

[0008] In some display devices, it may be relatively difficult to display high-quality images.

[0009] Aspects of one or more embodiments include a display device that can display relatively high-quality images and a method of manufacturing a display device. However, these characteristics are merely illustrative, and the scope of the embodiments according to the present disclosure is not limited thereto.

[0010] Various additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments presented in the disclosure.

[0011] According to some embodiments, a display device includes: a display element; a semiconductor pattern including a first region having a first thickness and a second region having a second thickness, wherein the second thickness is greater than the first thickness; a first transistor including a first gate electrode and a first channel region as part of the semiconductor pattern, at least a portion of the first gate electrode overlapping with the first channel region; and a second transistor including a second gate electrode and a second channel region as part of the semiconductor pattern, at least a portion of the second gate electrode overlapping with the second channel region, wherein the second region of the semiconductor pattern includes a corner portion of the semiconductor pattern.

[0012] According to some embodiments, the first transistor may include a driving transistor, and the second transistor may include a switching transistor, and the first channel region may overlap with the second region, and the second channel region may overlap with the first region.

[0013] According to some embodiments, the first channel region and the second channel region may be integrally provided.

[0014] According to some embodiments, the semiconductor pattern may include polysilicon, and a size of crystallized grains included in the first region may be greater than a size of crystallized grains included in the second region.

[0015] According to some embodiments, in the second channel region, the number of grain boundaries perpendicular to a longitudinal direction of the second channel region may be one or less.

[0016] According to some embodiments, in the second channel region, the number of grain boundaries parallel to the longitudinal direction of the second channel region may be one or less.

[0017] According to some embodiments, the display device may further include: an insulating layer having a contact hole through which a portion of the semiconductor pattern is exposed; and a conductive pattern on the insulating layer, at least a portion of the conductive pattern being buried in the contact hole, and the contact hole may overlap with the second region.

[0018] According to some embodiments, an edge of a corner portion of the semiconductor pattern may have an arc shape.

[0019] According to some embodiments, a curvature of an inner edge of a corner portion of the semiconductor pattern may be greater than a curvature of an outer edge of the corner portion of the semiconductor pattern.

[0020] According to some embodiments, the first thickness may be about to about And the second thickness may be about to about

[0021] According to some embodiments, a method for manufacturing a display device includes: forming an amorphous material layer; forming a sub-pattern by half-etching the amorphous material layer, the sub-pattern including a first preliminary region and a second preliminary region having different thicknesses; forming a polycrystalline material layer by crystallizing the amorphous material layer formed with the sub-pattern; forming a semiconductor pattern by etching the polycrystalline material layer, the semiconductor pattern including a first region having a first thickness and a second region having a second thickness greater than the first thickness; forming a first transistor including a first channel region and a first gate electrode; forming a second transistor including a second channel region and a second gate electrode; and forming a display element, wherein the second region of the semiconductor pattern includes a corner portion of the semiconductor pattern.

[0022] According to some embodiments, the semiconductor pattern may include polysilicon, and a size of crystallized grains included in the first region may be greater than a size of crystallized grains included in the second region.

[0023] According to some embodiments, the semiconductor pattern may include a first channel region and a second channel region, and the first channel region may overlap with the second region, and the second channel region may overlap with the first region.

[0024] According to some embodiments, in the second channel region, the number of grain boundaries perpendicular to a longitudinal direction of the second channel region may be one or less.

[0025] According to some embodiments, the first transistor may control an amount of current flowing from a second node connected to a power supply voltage line to a display element in response to a voltage applied to the first node.

[0026] According to some embodiments, the method may further include: forming an insulating layer having a contact hole formed therein between the semiconductor pattern and the display element; and forming a conductive pattern on the insulating layer at least a portion of which is buried in the contact hole, and the contact hole may overlap the second region.

[0027] According to some embodiments, an edge of a corner portion of the semiconductor pattern may have an arc shape.

[0028] According to some embodiments, a curvature of an inner edge of a corner portion of the semiconductor pattern may be greater than a curvature of an outer edge of the corner portion of the semiconductor pattern.

[0029] According to some embodiments, the first channel region and the second channel region may be integrally provided.

[0030] According to some embodiments, the first thickness may be about to about And the second thickness may be about to about

[0031] Other aspects, features, and characteristics in addition to those described above will become apparent from the following detailed description, claims, and accompanying drawings for implementing the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects, features and characteristics of specific embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a perspective view schematically illustrating a display device according to some embodiments;

[0034] Figure 2 illustrates a display element provided in any pixel of a display device according to some embodiments and a pixel circuit connected to the display element;

[0035] Figure 3 It is a schematic diagram Figure 2 A layout diagram of the positions of thin film transistors and storage capacitors in a pixel;

[0036] Figure 4 It is a schematic diagram Figure 3 A layout diagram of a semiconductor pattern;

[0037] Figure 5 is along Figure 3 A schematic cross-sectional view of a display device according to some embodiments, taken along line II';

[0038] Figure 6 is along Figure 3 A schematic cross-sectional view of a display device according to some embodiments, taken along line II-II';

[0039] Figure 7 It is a schematic diagram Figure 4 a view of a portion of

[0040] FIG. 8A to FIG. 8G is a cross-sectional view schematically illustrating a method of manufacturing a display device according to some embodiments. DETAILED DESCRIPTION

[0041] Now will refer to the aspects of some embodiments in more detail, these embodiments are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements from beginning to end. In this regard, the present embodiment can have different forms, and should not be construed as being limited to the description set forth herein. Accordingly, the following only describes the embodiments with reference to the accompanying drawings to explain the various aspects of this description. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items. Throughout the disclosure, the statement "at least one of a, b, and c" represents only a, only b, only c, a and b, a and c, b and c, a, b, and c, all or any suitable combination of a, b, and / or c. In addition, the x-axis direction may also be referred to as the x-direction, and may include +x direction and -x direction, the y-axis direction may also be referred to as the y-direction, and may include +y direction and -y direction, and the z-axis direction may also be referred to as the z-direction, and may include +z direction and -z direction.

[0042] Since various modifications and various embodiments of the present disclosure are possible, specific embodiments are illustrated in the drawings and described in detail in the specific embodiments. The effects and features of the present disclosure and methods for achieving them will be apparent with reference to the embodiments described in detail below in conjunction with the drawings. However, the present disclosure is not limited to the embodiments disclosed herein, but can be implemented in various forms.

[0043] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings, and the same or corresponding components are denoted by and assigned the same reference numerals, and repeated explanations will be omitted.

[0044] In the following embodiments, the terms first, second, etc. are used for the purpose of distinguishing one element from other elements, and are not limiting.

[0045] In the following embodiments, unless the context clearly indicates otherwise, an expression in a singular form includes an expression in a plural form.

[0046] In the following embodiments, terms such as “include” or “have” mean that the features or elements described in the present specification are present, and do not preclude the possibility of adding one or more other features or elements.

[0047] In the following embodiments, when a part such as a layer, a region, or an element is on other parts, this means not only that the part is on the other parts but also that other elements are interposed therebetween.

[0048] In the drawings, the size of the elements may be exaggerated or reduced for convenience of explanation. For example, since the size and thickness of each component shown in the drawings are arbitrarily marked for convenience of explanation, the present disclosure is not necessarily limited to the drawings.

[0049] In the following embodiments, when layers, regions, components, etc. are connected to each other, these layers, regions, and components are directly connected to each other, or these layers, regions, and components may be indirectly connected to each other with other layers, other regions, and other components interposed between these layers, regions, and components. For example, in this specification, when layers, regions, components, etc. are electrically connected to each other, these layers, regions, components, etc. are directly electrically connected to each other, or these layers, regions, components, etc. are indirectly electrically connected to each other with other layers, other regions, and other components interposed between these layers, regions, and components.

[0050] In the following embodiments, the x-axis direction, the y-axis direction, and the z-axis direction are not limited to the directions corresponding to the three axes on the Cartesian coordinate system, and can be interpreted in a broader sense including these directions. For example, the x-axis direction, the y-axis direction, and the z-axis direction can be perpendicular to each other, but can refer to different directions that are not orthogonal to each other.

[0051] In this specification, "A and / or B" means A, B, or A and B.

[0052] Figure 1 is a perspective view schematically illustrating a display device 1 according to some embodiments.

[0053] The display device 1 according to some embodiments may be implemented as an electronic device such as a smart phone, a mobile phone, a navigation device, a game console, a television (TV), a vehicle-mounted unit, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP) and a personal digital assistant (PDA), or any other suitable electronic device capable of displaying an image. In addition, the electronic device may be a flexible device.

[0054] like Figure 1 As shown in FIG. 1 , the display device 1 according to some embodiments may include a display area DA and a peripheral area PA. The display device 1 may include a substrate (see FIG. 1 ). Figure 5 101), and the shape of the substrate 101 is not limited to Figure 1 The substrate 101 is not in the rectangular shape (on the xy plane perpendicular to the thickness direction (z-axis direction) of the display device 1) shown in FIG. 1 , but may be in various shapes such as a circle. In addition, the substrate 101 may have a bending region, and may also be bent in the bending region.

[0055] The substrate 101 may include glass or metal. In addition, the substrate 101 may include various flexible or bendable materials, for example, polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate.

[0056] Of course, the substrate 101 may have a multilayer structure including two layers including such a polymer resin and a barrier layer including an inorganic material located between these layers, and various modifications are possible. In this case, the barrier layer may include silicon oxide, silicon nitride and / or silicon oxynitride, etc.

[0057] A plurality of display elements may be located in the display area DA. According to some embodiments, the display elements may be organic light emitting diodes (see Figure 2 OLED) and can emit red, green, blue or white light. Figure 1 One (sub) pixel in the display area DA of the display device 1 may include such an organic light emitting diode OLED, and may also include a thin film transistor and a storage capacitor for controlling the light emission degree of the organic light emitting diode OLED.

[0058] A driving unit and power wiring, etc. may be arranged in the peripheral area PA. In addition, the peripheral area PA may include a pad area, which is an area to which various electronic devices such as a driving integrated circuit, a printed circuit board, etc. are electrically attached.

[0059] Figure 2 yes Figure 1 The equivalent circuit diagram of a (sub) pixel of the display device 1 is shown in FIG. Figure 2 is an equivalent circuit diagram of a (sub) pixel located in the display area DA of the display device 1. The pixel circuit PC located in one (sub) pixel may include a plurality of thin film transistors T1 to T7 and a storage capacitor Cst. The thin film transistors T1 to T7 and the storage capacitor Cst may be connected to the signal lines SL, SL-1, SL+1, EL and DL, the first initialization voltage line VL1, the second initialization voltage line VL2 and the power supply voltage line PL.

[0060] The signal lines SL, SL-1, SL+1, EL, and DL may include a scan line SL configured to transmit a scan signal Sn to the switching thin film transistor T2, a previous signal line SL-1 for transmitting a previous scan signal Sn-1 to the first initialization thin film transistor T4, a subsequent scan line SL+1 for transmitting the scan signal Sn to the second initialization thin film transistor T7, an emission control line EL for transmitting an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL crossing the scan line SL and transmitting a data signal Dm to the pixel circuit PC. The power supply voltage line PL may be configured to transmit a driving voltage ELVDD to the driving thin film transistor T1, and the first initialization voltage line VL1 may transmit an initialization voltage Vint to the first initialization thin film transistor T4, and the second initialization voltage line VL2 may transmit an initialization voltage Vint to the second initialization thin film transistor T7.

[0061] The driving gate electrode G1, which is the first gate electrode of the driving thin film transistor T1 as the first transistor, may be connected to the lower electrode CE1 of the storage capacitor Cst, the driving source region S1 of the driving thin film transistor T1 may be connected to the power supply voltage line PL via the operation control thin film transistor T5, and the driving drain region D1 of the driving thin film transistor T1 may be electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. That is, the driving thin film transistor T1 may control the driving current I flowing from the second node N2 connected to the power supply voltage line PL through the organic light emitting diode OLED in response to the voltage applied to the first node N1 (i.e., the voltage applied to the driving gate electrode G1 of the driving thin film transistor T1). OLED Therefore, the driving thin film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin film transistor T2, and can OLED The organic light emitting diode OLED is supplied. The operation control thin film transistor T5 may be located between the second node N2 and the power supply voltage line PL.

[0062] The switching gate electrode G2, which is the second gate electrode of the switching thin film transistor T2 as the second transistor, may be connected to the scan line SL, the switching source region S2 of the switching thin film transistor T2 may be connected to the data line DL, and the switching drain region D2 of the switching thin film transistor T2 may be connected to the second node N2, may be connected to the driving source region S1 of the driving thin film transistor T1, and may be connected to the power supply voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 may be turned on in response to the scan signal Sn transmitted through the scan line SL, and may perform a switching operation of transmitting the data signal Dm transmitted to the data line DL to the driving source region S1 of the driving thin film transistor T1.

[0063] The compensation thin film transistor T3 as the third transistor may be connected between the driving thin film transistor T1 and the organic light emitting diode OLED between the third node N3 and the first node N1, thereby diode-connecting the driving thin film transistor T1 in response to the voltage applied to the compensation gate electrode G3 as the third gate electrode. That is, the compensation gate electrode G3 of the compensation thin film transistor T3 may be connected to the scan line SL, and the compensation drain region D3 of the compensation thin film transistor T3 may be connected to the driving drain region D1 of the driving thin film transistor T1, and may be connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. In addition, the compensation source region S3 of the compensation thin film transistor T3 may be connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain region D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1.

[0064] The compensation thin film transistor T3 may be turned on in response to the scan signal Sn transmitted through the scan line SL, and may electrically connect the drive gate electrode G1 to the drive drain region D1 of the drive thin film transistor T1, thereby diode-connecting the drive thin film transistor T1. The compensation thin film transistor T3 may have a dual gate electrode. That is, the compensation gate electrode G3 of the compensation thin film transistor T3 may have a 3-1 gate electrode (see Figure 3 etc.) and the 3-2 gate electrode (see Figure 3 etc.). Although the compensation thin film transistor T3 is Figure 2 Although shown as having two gate electrodes, the embodiment is not limited thereto. The compensation thin film transistor T3 may have one gate electrode.

[0065] The first initialization thin film transistor T4 as the fourth transistor may be connected between the first node N1 and the first initialization voltage line VL1, and may initialize the voltage of the driving gate electrode G1 in response to the voltage applied to the first initialization gate electrode G4 as the fourth gate electrode. That is, the first initialization gate electrode G4 of the first initialization thin film transistor T4 may be connected to the previous scan line SL-1, and the first initialization source region S4 of the first initialization thin film transistor T4 may be connected to the first initialization voltage line VL1. In addition, the first initialization drain region D4 of the first initialization thin film transistor T4 may be connected to the lower electrode CE1 of the storage capacitor Cst, the compensation source region S3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 may be turned on in response to Sn-1 transmitted through the previous scan line SL-1, and may perform an initialization operation of transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1 and initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1.

[0066] Although the first initialization thin film transistor T4 is Figure 2 The first initialization thin film transistor T4 is shown as having two gate electrodes, but the embodiment is not limited thereto. The first initialization thin film transistor T4 may have one gate electrode.

[0067] The operation control thin film transistor T5 as the fifth transistor may be connected between the second node N2 and the power supply voltage line PL, and may be turned on in response to a voltage applied to the operation control gate electrode G5 as the fifth gate electrode. That is, the operation control gate electrode G5 of the operation control thin film transistor T5 may be connected to the emission control line EL, and the operation control source region S5 of the operation control thin film transistor T5 may be connected to the power supply voltage line PL. In addition, the operation control drain region D5 of the operation control thin film transistor T5 may be connected to the driving source region S1 of the driving thin film transistor T1 and the switching drain region D2 of the switching thin film transistor T2.

[0068] The emission control thin film transistor T6 as the sixth transistor may be connected between the third node N3 and the organic light emitting diode OLED, and may be turned on in response to a voltage applied from the emission control line EL to the emission control gate electrode G6 as the sixth gate electrode. That is, the emission control gate electrode G6 of the emission control thin film transistor T6 may be connected to the emission control line EL, and the emission control source region S6 of the emission control thin film transistor T6 may be connected to the driving drain region D1 of the driving thin film transistor T1 and the compensation drain region D3 of the compensation thin film transistor T3. In addition, the emission control drain region D6 of the emission control thin film transistor T6 may be electrically connected to the second initialization source region S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0069] The operation control thin film transistor T5 and the emission control thin film transistor T6 may be simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL, so that the driving voltage ELVDD may be transmitted to the organic light emitting diode OLED and the driving current I OLED It can flow through an organic light emitting diode OLED.

[0070] The second initialization gate electrode G7, which is the seventh gate electrode of the second initialization thin film transistor T7 as the seventh transistor, may be connected to the subsequent scan line SL+1, and the second initialization source region S7 of the second initialization thin film transistor T7 may be connected to the emission control drain region D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED. In addition, the second initialization drain region D7 of the second initialization thin film transistor T7 may be connected to the second initialization voltage line VL2.

[0071] Since the scan line SL and the subsequent scan line SL+1 are electrically connected to each other, the same scan signal Sn may be applied to the scan line SL and the subsequent scan line SL+1. Therefore, the second initialization thin film transistor T7 may be turned on in response to the scan signal Sn transmitted through the subsequent scan line SL+1, and may perform an operation of initializing the pixel electrode of the organic light emitting diode OLED. If necessary, the second initialization thin film transistor T7 may be omitted.

[0072] The upper electrode CE2 of the storage capacitor Cst may be connected to the power supply voltage line PL, and the common electrode of the organic light emitting diode OLED may be connected to a line transmitting a common voltage ELVSS. Therefore, the organic light emitting diode OLED may receive a driving current I from the driving thin film transistor T1. OLED , and can emit light to display images.

[0073] Figure 2 The pixel circuit PC shown in the figure is not limited to Figure 2For example, according to some embodiments, the pixel circuit PC may include additional components or fewer components without departing from the spirit and scope of the embodiments according to the present disclosure.

[0074] Figure 3 It is schematically shown Figure 2 A layout diagram showing the positions of the storage capacitor Cst and the plurality of thin film transistors T1 to T7 in a (sub) pixel, Figure 4 It is schematically shown that Figure 3 A layout diagram of a semiconductor pattern 1130 of a portion of a display device, and Figure 5 is along Figure 3 Schematic cross-sectional view of a display device according to some embodiments, taken along line II'. Figure 6 is along Figure 3 Schematic cross-sectional view of a display device according to some embodiments, taken along line II-II'. In the cross-sectional view, the size of each component is exaggerated and / or reduced for the sake of convenience. This also applies to the cross-sectional view described later.

[0075] The driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 may be arranged along the semiconductor pattern 1130. Some regions of the semiconductor pattern 1130 may form a semiconductor layer of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. That is, some regions of the semiconductor pattern 1130 may form a channel region, a source region, or a drain region of a thin film transistor.

[0076] According to some embodiments, the driving thin film transistor T1 may include a driving semiconductor layer, and the driving semiconductor layer may include a driving channel region A1, a driving source region S1, and a driving drain region D1. Figure 3 The overlapping portion of G1) may be the driving channel region A1.

[0077] According to some embodiments, the switch thin film transistor T2 may include a switch semiconductor layer, and the switch semiconductor layer may include a switch channel region A2, a switch source region S2, and a switch drain region D2. Figure 2 The overlapping portion of G2) may be the switching channel region A2.

[0078] According to some embodiments, the compensation thin film transistor T3 may include a compensation semiconductor layer, and the compensation semiconductor layer may include a compensation channel region A3, a compensation source region S3, and a compensation drain region D3. Figure 2 The overlapping portion of G3) may be the compensation channel region A3.

[0079] According to some embodiments, the first initialization thin film transistor T4 may include a first initialization semiconductor layer, and the first initialization semiconductor layer may include a first initialization channel region A4, a first initialization source region S4, and a first initialization drain region D4. For example, the first initialization semiconductor layer and the first initialization gate electrode ( Figure 2 The overlapping portion of G4) may be the first initialization channel region A4.

[0080] According to some embodiments, the operation control thin film transistor T5 may include an operation control semiconductor layer, and the operation control semiconductor layer may include an operation control channel region A5, an operation control source region S5, and an operation control drain region D5. For example, the operation control semiconductor layer and the operation control gate electrode ( Figure 2 The overlapping portion of G5) may be the operation control channel region A5.

[0081] According to some embodiments, the emission control thin film transistor T6 may include an emission control semiconductor layer, and the emission control semiconductor layer may include an emission control channel region A6, an emission control source region S6, and an emission control drain region D6. For example, the emission control semiconductor layer and the emission control gate electrode ( Figure 2 The overlapping portion of G6) may be the emission control channel region A6.

[0082] According to some embodiments, the second initialization thin film transistor T7 may include a second initialization semiconductor layer, and the second initialization semiconductor layer may include a second initialization channel region A7, a second initialization source region S7, and a second initialization drain region D7. For example, the second initialization semiconductor layer and the second initialization gate electrode ( Figure 2 The overlapping portion of G7) may be the second initialization channel region A7.

[0083] like Figure 4 As shown in FIG. 1 , each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 may be provided with two gate electrodes, but the embodiment is not limited thereto. Each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 may be provided with one gate electrode.

[0084] The semiconductor pattern 1130 may be located on the substrate 101 . Of course, the buffer layer 105 may be formed on the substrate 101 , and the semiconductor pattern 1130 may be formed on the buffer layer 105 .

[0085] The buffer layer 105 can reduce or block the penetration of foreign matter, moisture or external air from the lower part of the substrate 101, and can provide a flat surface for the substrate 101. The buffer layer 105 may include an inorganic material, an organic material, or an organic / inorganic composite material such as an oxide or a nitride, and may have a single layer or multilayer structure of an inorganic material and / or an organic material. According to some embodiments, the buffer layer 105 may have a structure in which a first buffer layer and a second buffer layer are stacked on each other. In this case, the first buffer layer and the second buffer layer may include different materials. For example, the first buffer layer may include silicon nitride, and the second buffer layer may include silicon oxide.

[0086] In this way, when the first buffer layer includes silicon nitride, the first buffer layer may include hydrogen when the silicon nitride is formed. Therefore, the carrier mobility of the semiconductor pattern 1130 formed on the buffer layer 105 may be enhanced, so that the electrical characteristics of the thin film transistor (TFT) may be relatively enhanced. In addition, the semiconductor pattern 1130 may include a silicon material. In this case, the interface bonding characteristics between the semiconductor pattern 1130 including silicon and the second buffer layer including silicon oxide may be enhanced, so that the electrical characteristics of the thin film transistor (TFT) may be enhanced.

[0087] The semiconductor pattern 1130 may include low temperature polysilicon (LTPS). Since polysilicon material has high electron mobility (100 cm 2 / Vs or higher), so the polysilicon material has low energy consumption and excellent reliability. In another example, the semiconductor pattern 1130 may include amorphous silicon (a-Si) and / or an oxide semiconductor. Alternatively, some semiconductor layers of the plurality of thin film transistors may include LTPS, and some other semiconductor layers may include a-Si and / or an oxide semiconductor.

[0088] The source region and the drain region of the semiconductor pattern 1130 may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The source region and the drain region may be changed according to the characteristics of the transistor. In the following, terms such as source region and drain region are used instead of source electrode or drain electrode. Figure 2 In the equivalent circuit diagram of FIG. 1 , some portions of the semiconductor pattern 1130 may be doped with P-type impurities, and the thin film transistor may be implemented as a P-channel metal oxide semiconductor field effect transistor (MOSFET) (PMOS). Of course, other portions of the semiconductor pattern 1130 may also be doped with impurities, and these portions may be used as wiring to connect the thin film transistor and / or the storage capacitor to each other.

[0089] A first insulating layer 111 may be positioned on the semiconductor pattern 1130 , and a driving gate electrode G1 , a scan line SL, a previous scan line SL- 1 , a next scan line SL+1 , and an emission control line EL may be positioned on the first insulating layer 111 .

[0090] The region in the scan line SL that overlaps with the switch channel region A2 of the switch thin film transistor T2 and the compensation channel region A3 of the compensation thin film transistor T3 may be the switch gate electrode G2 and the compensation gate electrode G3, respectively, and the region in the previous scan line SL-1 that overlaps with the first initialization channel region A4 of the first initialization thin film transistor T4 may be the first initialization gate electrode G4. In addition, the region in the subsequent scan line SL+1 that overlaps with the second initialization channel region A7 of the second initialization thin film transistor T7 may be the second initialization gate electrode G7, and the region in the emission control line EL that overlaps with the operation control channel region A5 of the operation control thin film transistor T5 and the emission control channel region A6 of the emission control thin film transistor T6 may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0091] The driving gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multi-layer structure or a single-layer structure including the above materials. According to some embodiments, the driving gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL may have a multi-layer structure of Mo / Al or a multi-layer structure of Mo / Al / Mo.

[0092] The second insulating layer 113 may be disposed on the driving gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL+1, and the emission control line EL. The second insulating layer 113 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which may be ZnO and / or ZnO 2 ).

[0093] The electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 may be disposed on the second insulating layer 113. The electrode voltage line HL may cover at least a portion of the driving gate electrode G1, and may form a storage capacitor Cst together with the driving gate electrode G1.

[0094] The lower electrode CE1 of the storage capacitor Cst may be formed integrally with the driving gate electrode G1 of the driving thin film transistor T1. For example, the driving gate electrode G1 of the driving thin film transistor T1 may be used as the lower electrode CE1 of the storage capacitor Cst. The region of the electrode voltage line HL that overlaps with the driving gate electrode G1 may be the upper electrode CE2 of the storage capacitor Cst. Therefore, the second insulating layer 113 may be used as a dielectric layer of the storage capacitor Cst.

[0095] The electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 may include a conductive material including Mo, Al, Cu, Ti, etc., and may have a multilayer structure or a single layer structure including the above materials. In an example, the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 may have a multilayer structure of Mo / Al or a multilayer structure of Mo / Al / Mo.

[0096] The interlayer insulating layer 115 may be located on the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2. The interlayer insulating layer 115 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which may be ZnO and / or ZnO 2 ).

[0097] The data line DL, the power supply voltage line PL, the first initialization connection line 1173a and the second initialization connection line 1173b, the node connection line 1174, and the contact metal 1175 may be arranged on the interlayer insulating layer 115. The data line DL, the power supply voltage line PL, the first initialization connection line 1173a and the second initialization connection line 1173b, the node connection line 1174, and the contact metal 1175 may include a conductive material including Mo, Al, Cu, Ti, etc., and may have a multi-layer structure or a single-layer structure including the above materials. In an example, the data line DL, the power supply voltage line PL, the first initialization connection line 1173a and the second initialization connection line 1173b, the node connection line 1174, and the contact metal 1175 may have a multi-layer structure of Ti / Al / Ti.

[0098] The data line DL may be connected to the switching source region S2 of the switching thin film transistor T2 through the contact hole 1154. If necessary, a portion of the data line DL may be understood as a switching source electrode.

[0099] The power supply voltage line PL may be connected to the upper electrode CE2 of the storage capacitor Cst through a contact hole 1158 formed in the interlayer insulating layer 115. Therefore, the electrode voltage line HL may have the same voltage level (constant voltage) as the power supply voltage line PL. In addition, the power supply voltage line PL may be connected to the operation control source region S5 through the contact hole 1155.

[0100] The first initialization voltage line VL1 may be connected to the first initialization thin film transistor T4 through the first initialization connection line 1173a. One end of the first initialization connection line 1173a may be connected to the first initialization voltage line VL1 through the contact hole 1151, and the other end of the first initialization connection line 1173a may be connected to the first initialization source region S4 of the first initialization thin film transistor T4 through the contact hole 1152. The second initialization voltage line VL2 may be connected to the second initialization thin film transistor T7 through the second initialization connection line 1173b. On the other hand, the first initialization voltage line VL1 and the second initialization voltage line VL2 may have the same constant voltage (e.g., -2V, etc.).

[0101] One end of the node connection line 1174 may be connected to the compensation source region S3 through the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 through the contact hole 1157 .

[0102] The contact metal 1175 may be connected to the emission control semiconductor layer of the emission control thin film transistor T6 through the contact hole 1153 passing through the interlayer insulating layer 115, the second insulating layer 113, and the first insulating layer 111. The contact metal 1175 may be connected to the pixel electrode 210 of the organic light emitting diode OLED through the contact hole 1163. Therefore, the emission control thin film transistor T6 may be electrically connected to the pixel electrode 210 of the organic light emitting diode OLED.

[0103] The planarization layer 117 may be on the data line DL, the power voltage line PL, the first and second initialization link lines 1173 a and 1173 b , the node connection line 1174 , and the contact metal 1175 , and the organic light emitting diode OLED may be on the planarization layer 117 .

[0104] on the other hand, Figure 2 A pixel circuit PC is shown in the figure, and Figure 3 Although the structure of one (sub) pixel circuit SPX is shown, a plurality of (sub) pixels SPX having the same pixel circuit PC may be arranged in the first direction (x-axis direction) and the second direction (y-axis direction). In this case, two pixel circuits PC positioned adjacent to each other in the second direction (y-axis direction) may share the first initialization voltage line VL1, the previous scan line SL-1, the second initialization voltage line VL2, and the next scan line SL+1.

[0105] That is, the first initialization voltage line VL1 and the previous scan line SL-1 may be electrically connected to the first initialization voltage line VL1 located at the second direction (y-axis direction) based on the drawing. Figure 3 1. The second initialization thin film transistor of another pixel circuit PC is located at the upper part (+y direction) of the pixel circuit PC shown in FIG. Therefore, the previous scan signal applied to the previous scan line SL-1 can be transmitted to the second initialization thin film transistor of another pixel circuit PC as the subsequent scan signal. Similarly, the second initialization voltage line VL2 and the subsequent scan line SL+1 can be electrically connected to the second initialization thin film transistor connected to the pixel circuit PC in the second direction (y-axis direction) based on the drawing. Figure 3 The first initialization thin film transistor of another pixel circuit PC is positioned adjacent to the lower part (-y direction) of the pixel circuit PC shown in FIG. 1 , and can be configured to transmit the initialization voltage and the previous scanning signal, respectively.

[0106] Return to reference Figures 3 to 5The planarization layer 117 may have a flat upper surface on which the pixel electrode 210 may be flatly formed. The planarization layer 117 may include an organic material and may have a single-layer or multi-layer structure. The planarization layer 117 may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer or a vinyl alcohol polymer. The planarization layer 117 may also include an inorganic material. The planarization layer 117 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which may be ZnO and / or ZnO 2 When the planarization layer 117 includes an inorganic material, chemical planarization polishing may be performed as needed. The planarization layer 117 may include both an organic material and an inorganic material.

[0107] The organic light emitting diode OLED may include a pixel electrode 210 , a common electrode 230 , and an intermediate layer 220 located between the pixel electrode 210 and the common electrode 230 and including a light emitting layer.

[0108] The pixel electrode 210 can be connected to the contact metal 1175 through the contact hole 1163, and the contact metal 1175 can be connected to the emission control drain region D6 through the contact hole 1153. The pixel electrode 210 can be a (semi) transparent electrode or a reflective electrode. In some embodiments, the pixel electrode 210 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and compounds thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may have a stack structure of ITO / Ag / ITO.

[0109] The pixel defining layer 119 may be located on the planarization layer 117, and the pixel defining layer 119 may have an opening through which the center of the pixel electrode 210 is exposed to define the emission region of the pixel. In addition, the pixel defining layer 119 may be configured to increase the distance between the edge of the pixel electrode 210 and the common electrode 230 located on the pixel electrode 210 to prevent arcing, etc., from being generated at the edge of the pixel electrode 210. The pixel defining layer 119 may be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, or phenolic resin, etc., by a method such as spin coating, etc.

[0110] The pixel defining layer 119 may include an organic insulating material. Alternatively, the pixel defining layer 119 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. Alternatively, the pixel defining layer 119 may include an organic insulating material and an inorganic insulating material. According to some embodiments, the pixel defining layer 119 may include a light-blocking material and may provide a black color. The light-blocking material may include carbon black, carbon nanotubes, a resin or paste containing a black dye, metal particles such as Ni, Al, Mo, and alloys thereof, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). When the pixel defining layer 119 includes a light-blocking material, external light reflection caused by a metal structure located under the pixel defining layer 119 may be reduced.

[0111] The intermediate layer 220 may include an organic light emitting layer. The organic light emitting layer may include an organic material including a fluorescent material or a phosphorescent material that emits red, green, blue or white light. The organic light emitting layer may be formed of a low molecular weight organic material or a polymer organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) and an electron injection layer (EIL) may be further selectively arranged under and on the organic light emitting layer. The intermediate layer 220 may be arranged corresponding to each of the plurality of pixel electrodes 210. However, the embodiment is not limited thereto, and the layers such as HTL, HIL, ETL or EIL included in the intermediate layer 220 may be formed integrally throughout the plurality of pixel electrodes 210.

[0112] The common electrode 230 may be a transparent electrode or a reflective electrode. In some embodiments, the common electrode 230 may be a transparent or semi-transparent electrode and may include a metal thin layer having a low work function and including lithium (Li), calcium (Ca), Al, silver (Ag), Mg and / or compounds thereof or a multilayer material such as lithium fluoride (LiF) / Al. In addition, in addition to the metal thin layer, the common electrode 230 may further include a plurality of materials such as ITO, IZO, ZnO or In 2 O 3The common electrode 230 may be integrally formed corresponding to the plurality of pixel electrodes 210 .

[0113] An encapsulation layer including a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer between the first and second inorganic encapsulation layers may be located on the common electrode 230 .

[0114] The first inorganic encapsulation layer and the second inorganic encapsulation layer may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which may be ZnO and / or ZnO 2 ). The organic encapsulation layer may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane (HMDSO), acrylic resin (eg, polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0115] According to some embodiments, the semiconductor pattern 1130 may include a first region TA1 having a first thickness a and a second region TA2 having a second thickness b, wherein the second thickness b is greater than the first thickness a. The semiconductor pattern 1130 may have a shape in which the first region TA1 having the first thickness a and the second region TA2 having the second thickness b are alternately connected to each other. The first thickness a may be about to about The first thickness a may be approximately The second thickness b may be approximately to about The second thickness b may be approximately

[0116] According to some embodiments, the semiconductor pattern 1130 may include crystalline silicon. Hereinafter, the grain size may be the size of the crystallized grains. The grain size of the first area TA1 of the semiconductor pattern 1130 may be greater than the grain size of the second area TA2 of the semiconductor pattern 1130. Therefore, the first area TA1 may include a grain boundary whose number is less than that of the second area TA2. According to some embodiments, the grain boundary perpendicular to the longitudinal direction of the semiconductor pattern 1130 in the first area TA1 may be provided as one or less. Therefore, the mobility of the electrons may be enhanced. According to some embodiments, the grain boundary parallel to the longitudinal direction of the semiconductor pattern 1130 in the first area TA1 may be provided as one or less. Therefore, the semiconductor pattern 1130 may be uniformly formed.

[0117] According to some embodiments, the first area TA1 may include channel regions A2 to A7 of a plurality of thin film transistors T2 to T7 except the driving thin film transistor T1, and the second area TA2 may include the driving channel region A1 of the driving thin film transistor T1.

[0118] refer to Figures 3 to 5 , the first area TA1 may include first to ninth sub-areas TN1 to TN9. The first area TA1 may include a first sub-area TN1 overlapping with the second initialization channel area A7, a second sub-area TN2 and a fourth sub-area TN4 overlapping with the first initialization channel area A4, a third sub-area TN3, a fifth sub-area TN5 and a sixth sub-area TN6 overlapping with the compensation channel area A3, a seventh sub-area TN7 overlapping with the switch channel area A2, an eighth sub-area TN8 overlapping with the operation control channel area A5, and a ninth sub-area TN9 overlapping with the emission control channel area A6. The first to ninth sub-areas TN1 to TN9 may be spaced apart from each other. The second area TA2 may be an area located between the spaced-apart first to ninth sub-areas TN1 to TN9.

[0119] That is, the switching channel region A2, the compensation channel region A3, the first initialization channel region A4, the operation control channel region A5, the emission control channel region A6 and the second initialization channel region A7 may have a first thickness a, and the driving channel region A1 may have a second thickness b, wherein the second thickness b is greater than the first thickness a.

[0120] For example, refer to Figure 5, the driving thin film transistor T1 may include a driving channel region A1 and a driving gate electrode G1, the switching thin film transistor T2 may include a switching channel region A2 and a switching gate electrode G2, and the compensation thin film transistor T3 may include a compensation channel region A3 and a compensation gate electrode G3. The thickness TH1 of the driving channel region A1 may be provided to be greater than the thickness TH2 of the switching channel region A2 and the thickness TH3 of the compensation channel region A3. The driving channel region A1 may be provided to have a second thickness b, and the switching channel region A2 and the compensation channel region A3 may be provided to have a first thickness a.

[0121] In this specification, the first thickness and the second thickness may mean not only specific values ​​but also any thickness within a certain range. For example, the driving channel region A1 having the second thickness b and the switching channel region A2 and the compensation channel region A3 having the first thickness a not only mean that the switching channel region A2 and the compensation channel region A3 have the same thickness but also mean that each of the switching channel region A2 and the compensation channel region A3 has a different thickness within a range smaller than the thickness of the driving channel region A1. In other words, one region of the semiconductor pattern 1130 having the first thickness a may mean having any value within a range smaller than the second thickness b.

[0122] Subthreshold current refers to current that flows even when a voltage that is a threshold voltage or less is applied to the gate. Subthreshold current may operate even when the thin film transistor is cut off, resulting in unexpected power consumption. The switch channel region A2, the compensation channel region A3, the first initialization channel region A4, the operation control channel region A5, the emission control channel region A6, and the second initialization channel region A7 may have a relatively small thickness, so that the subthreshold current can be reduced, the uniformity of the thin film transistor can be enhanced, and the brightness uniformity can be enhanced.

[0123] In addition, when the switch channel region A2, the compensation channel region A3, the first initialization channel region A4, the operation control channel region A5, the emission control channel region A6, and the second initialization channel region A7 include crystalline silicon, they can have a relatively large grain size, so that the mobility of electrons can be enhanced and the area of ​​the thin film transistor can be reduced. Therefore, the resolution of the display device can be enhanced. The driving channel region A1 can have a relatively large thickness, so that the driving range can be increased and sufficient grayscale can be expressed.

[0124] refer to Figure 4 and Figure 6According to some embodiments, the semiconductor pattern 1130 may include a corner portion CN and a contact portion CT. The corner portion CN of the semiconductor pattern 1130 may be a region where a portion of the semiconductor pattern 1131 extending in a first direction (e.g., x direction) and a portion of the semiconductor pattern 1130 extending in a second direction (e.g., y direction) intersect each other. The corner portion CN may be located between the spaced-apart first regions TA1. For example, the corner portion CN may be a region located between the second sub-region TN2 and the third sub-region TN3, but may include a region located between the third sub-region TN3 and the fourth sub-region TN4. The corner portion CN may correspond to the second region TA2 having a second thickness b. The corner portion CN in the semiconductor pattern 1130 may be provided to be thicker than a plurality of channel regions A2 to A7 other than the driving channel region A1.

[0125] According to some embodiments, the display device may be a flexible display device including a flexible display panel. The corner portion CN of the semiconductor pattern 1130 has a relatively thick second thickness b, so that resistance to stress applied according to deformation of the display panel can be enhanced. Accordingly, cracks can be prevented from being generated in the display device, and reliability can be ensured.

[0126] According to some embodiments, the contact portion CT may be a region of the semiconductor pattern 1130 electrically connected to a conductive pattern located on the semiconductor pattern 1130. An insulating layer may be located between the semiconductor pattern 1130 and the conductive pattern, and the insulating layer may have a contact hole through which the contact portion CT of the semiconductor pattern 1130 is exposed. The contact portion CT may overlap with the contact hole. The conductive pattern may be buried in the contact hole of the insulating layer and may be electrically connected to the semiconductor pattern 1130.

[0127] refer to Figure 3 , the conductive pattern may be at least one of the data line DL, the first and second initialization connection lines 1173a and 1173b, the power supply voltage line PL, the node connection line 1174, and the contact metal 1175. The contact hole may be provided to pass through at least a portion of the first insulating layer 111, the second insulating layer 113, the interlayer insulating layer 115, and the planarization layer 117 between the semiconductor pattern 1130 and the conductive pattern.

[0128] The data line DL may be connected to the switching source region S2 which is a part of the semiconductor pattern 1130 through the contact hole 1154. The first initialization connection line 1173a may be connected to the first initialization source region S4 which is a part of the semiconductor pattern 1130 through the contact hole 1152. The power supply voltage line PL may be connected to the operation control source region S5 which is a part of the semiconductor pattern 1130 through the contact hole 1155. The node connection line 1174 may be connected to the compensation source region S3 which is a part of the semiconductor pattern 1130 through the contact hole 1156. The contact metal 1175 may be connected to the emission control drain region D6 which is a part of the semiconductor pattern 1130 through the contact hole 1153. In this case, the contact portion CT of the semiconductor pattern 1130 may be a region overlapping with the plurality of contact holes 1152, 1153, 1154, 1155, and 1156.

[0129] According to some embodiments, the contact portion CT may be included in the second area TA2 of the semiconductor pattern 1130. The contact portion CT may have a relatively thick second thickness b so that a contact defect caused by over-etching may be prevented and yield may be improved.

[0130] Figure 7 It is schematically shown Figure 4 1, which illustrates a portion of a corner portion CN of the semiconductor pattern 1130. Stress may be concentrated on the corner portion CN of the semiconductor pattern 1130. The edge of the corner portion CN of the semiconductor pattern 1130 may be provided in an arc shape so that resistance caused by stress may be enhanced.

[0131] Among the outer side C1 and the inner side C2 of the corner portion CN, the inner side C2 may be a stress concentration point. According to some embodiments, the edge of the inner side C2 and the edge of the outer side C1 of the corner portion CN may be provided in an arc shape, and the curvature of the edge of the inner side C2 may be formed to be greater than the curvature of the edge of the outer side C1, so that cracks of the display device can be prevented.

[0132] According to some embodiments, the semiconductor pattern 1130 includes a first area TA1 having a first thickness a and a second area TA2 having a second thickness b. The second thickness b may be provided to be greater than the first thickness a. The second area TA2 having a relatively large thickness may overlap with the driving channel area A1, the corner portion CN, and the contact portion CT of the driving thin film transistor T1. The first area TA1 having a relatively small thickness may overlap with a plurality of channel areas A2 to A7 except the driving channel area A1. As described above, an area may be divided from the semiconductor pattern 1130 to control the thickness, so that the characteristics of the display device may be adjusted without increasing the area of ​​the pixel circuit.

[0133] FIG. 8A to FIG. 8Gis a cross-sectional view schematically illustrating a method of manufacturing a display device according to some embodiments. For example, a display device according to some embodiments may include a plurality of pixel circuits ( Figure 2 PC), and each of the plurality of pixel circuits PC may include a plurality of thin film transistors T1 to T7, and FIG. 8A to FIG. 8G 1 is a cross-sectional view illustrating a method of manufacturing a driving thin film transistor T1, a switching thin film transistor T2, and an emission control thin film transistor T6 among a plurality of thin film transistors T1 to T7. According to some embodiments, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, and the second initialization thin film transistor T7 may be manufactured by using the same method as the method of manufacturing the switching thin film transistor T2.

[0134] refer to FIG. 8A to FIG. 8G According to some embodiments, a method for manufacturing a display device may include: forming an amorphous material layer 106 on a substrate 101; forming a sub-pattern including a first preliminary area SA1 and a second preliminary area SA2 having different thicknesses by half-etching the amorphous material layer 106; forming a polycrystalline material layer 107 by crystallizing the sub-pattern; and forming a semiconductor pattern 1130 including a first area TA1 having a first thickness a and a second area TA2 having a second thickness b by etching the polycrystalline material layer 107.

[0135] refer to Fig. 8A and Figure 8B , a buffer layer 105 may be formed on the substrate 101, and an amorphous material layer 106 may be formed on the buffer layer 105. The amorphous material layer 106 may be an amorphous silicon layer. Subsequently, a sub-pattern may be formed by half-etching the amorphous material layer 106. The sub-pattern may be the amorphous material layer 106 divided into a first preliminary area SA1 and a second preliminary area SA2, and the first preliminary area SA1 may have a thickness smaller than that of the second preliminary area SA2. For example, the thickness of the first preliminary area SA1 may be about 1000 Å. to about And the thickness of the second preliminary area SA2 may be about to about

[0136] refer to Figure 8C and Fig.8D, the amorphous material layer 106 formed with the sub-patterns may be crystallized so that the polycrystalline material layer 107 may be formed. According to some embodiments, the polycrystalline material layer 107 may be formed by using excimer laser annealing (ELA). That is, the amorphous material layer 106 may be crystallized by laser irradiation so that the polycrystalline material layer 107 may be formed. According to some embodiments, crystallization caused by complete melting of the amorphous material may occur in the first preliminary area SA1, and crystallization caused by nearly complete melting of the amorphous material may occur in the second preliminary area SA2. To this end, in Figure 8B In the half etching, the thickness of the first preliminary area SA1 and the thickness of the second preliminary area SA2 may be adjusted in advance.

[0137] As the amorphous material is completely melted in the first preliminary area SA1, the grain size crystallized in the first preliminary area SA1 may be provided to be larger than the grain size crystallized in the second preliminary area SA2. The number of grain boundaries formed in the first preliminary area SA1 may be smaller than that formed in the second preliminary area SA2.

[0138] refer to FIG. 8E to FIG. 8G , the polycrystalline material layer 107 may be etched so that a semiconductor pattern 1130 may be formed. A region of the semiconductor pattern 1130 corresponding to the first preliminary area SA1 may be formed as a first area TA1 having a first thickness a, and a region of the semiconductor pattern 1130 corresponding to the second preliminary area SA2 may be formed as a second area TA2 having a second thickness b, wherein the second thickness b is greater than the first thickness a. FIG. 8A to FIG. 8E The semiconductor layer of the thin film transistor of the semiconductor pattern 1130 is shown, and this can also be applied to the above reference Figures 3 to 7 Described are the corner portion CN and the contact portion CT.

[0139] The semiconductor pattern 1130 may include a driving semiconductor layer AL1 of the driving thin film transistor T1, a switching semiconductor layer AL2 of the switching thin film transistor T2, and an emission control semiconductor layer AL6 of the emission control thin film transistor T6. The first area TA1 may include the switching semiconductor layer AL2 and the emission control semiconductor layer AL6, and the second area TA2 may include the driving semiconductor layer AL1. That is, the driving semiconductor layer AL1 may have a relatively thick second thickness b, and at least a portion of the switching semiconductor layer AL2 and at least a portion of the emission control semiconductor layer AL6 may have a relatively thin first thickness a. The switching channel area A2 and the emission control channel area A6 may have a first thickness a.

[0140] Subsequently, a first insulating layer 111 may be formed to cover the semiconductor pattern 1130 , and a driving gate electrode G1 , a switching gate electrode G2 , and an emission control gate electrode G6 may be formed on the first insulating layer 111 .

[0141] The driving source region S1 and the driving drain region D1 of the driving thin film transistor T1 may be formed by impurity doping. In this case, the region in the driving semiconductor layer AL1 that overlaps with the driving gate electrode G1 may be formed as the driving channel region A1. Therefore, impurities may be doped in a portion of the driving semiconductor layer AL1 by impurity doping, so that the driving semiconductor layer AL1 may be divided into the driving source region S1, the driving channel region A1, and the driving drain region D1. Similarly, the switching source region S2 and the switching drain region D2 of the switching thin film transistor T2 may be formed by impurity doping, and the emission control source region S6 and the emission control drain region D6 of the emission control thin film transistor T6 may be formed. According to some embodiments, the semiconductor layers of the remaining thin film transistors in the thin film transistor may also be doped to be divided into a source region, a channel region, and a drain region. A second insulating layer 113 may be formed to cover the gate electrode.

[0142] According to some embodiments, as described above, a display device that can display a relatively high-quality image and a method of manufacturing the display device can be provided. Of course, the scope of the embodiments according to the present disclosure is not limited by these features.

[0143] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of each feature or aspect within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope defined by the claims and their equivalents.

Claims

1. A display device, comprising: Display components; a semiconductor pattern including a first region having a first thickness and a second region having a second thickness, wherein the second thickness is greater than the first thickness; a first transistor including a first gate electrode and a first channel region as a portion of the semiconductor pattern, at least a portion of the first gate electrode overlapping the first channel region; as well as a second transistor including a second gate electrode and a second channel region as a portion of the semiconductor pattern, at least a portion of the second gate electrode overlapping the second channel region, The second region of the semiconductor pattern includes a corner portion of the semiconductor pattern.

2. The display device according to claim 1, wherein: The first transistor comprises a driving transistor, and the second transistor comprises a switching transistor, and The first channel region overlaps with the second region, and the second channel region overlaps with the first region.

3. The display device according to claim 2, wherein: The first channel region and the second channel region are integrally provided.

4. The display device according to claim 2, wherein: The semiconductor pattern includes polysilicon, and The size of crystal grains included in the first region is larger than the size of crystal grains included in the second region.

5. The display device according to claim 4, wherein: In the second channel region, the number of grain boundaries perpendicular to a longitudinal direction of the second channel region is one or less.

6. The display device according to claim 5, wherein: In the second channel region, the number of grain boundaries parallel to the longitudinal direction of the second channel region is one or less.

7. The display device according to claim 1, further comprising: an insulating layer having a contact hole through which a portion of the semiconductor pattern is exposed; as well as a conductive pattern on the insulating layer, wherein at least a portion of the conductive pattern is buried in the contact hole, Wherein, the contact hole overlaps with the second region.

8. The display device according to claim 1, wherein: An edge of the corner portion of the semiconductor pattern has an arc shape.

9. The display device according to claim 8, wherein: A curvature of an inner edge of the corner portion of the semiconductor pattern is greater than a curvature of an outer edge of the corner portion of the semiconductor pattern.

10. The display device according to any one of claims 1 to 9, wherein: The first thickness is to And the second thickness is to 11. A method for manufacturing a display device, the method comprising: forming an amorphous material layer; forming a sub-pattern by half-etching the amorphous material layer, the sub-pattern comprising a first preliminary region and a second preliminary region having different thicknesses; forming a polycrystalline material layer by crystallizing the amorphous material layer formed with the sub-patterns; forming a semiconductor pattern by etching the polycrystalline material layer, the semiconductor pattern including a first region having a first thickness and a second region having a second thickness greater than the first thickness; forming a first transistor including a first channel region and a first gate electrode; forming a second transistor including a second channel region and a second gate electrode; as well as forming a display element, The second region of the semiconductor pattern includes a corner portion of the semiconductor pattern.

12. The method according to claim 11, wherein: The semiconductor pattern includes polysilicon, and The size of crystal grains included in the first region is larger than the size of crystal grains included in the second region.

13. The method according to claim 11, wherein: The semiconductor pattern includes the first channel region and the second channel region, and The first channel region overlaps with the second region, and the second channel region overlaps with the first region.

14. The method according to claim 13, wherein: In the second channel region, the number of grain boundaries perpendicular to a longitudinal direction of the second channel region is one or less.

15. The method according to claim 13, wherein: The first transistor is configured to control an amount of current flowing from a second node connected to a power supply voltage line to the display element in response to a voltage applied to a first node.

16. The method according to claim 11, further comprising: forming an insulating layer between the semiconductor pattern and the display element, wherein a contact hole is formed in the insulating layer; as well as forming a conductive pattern on the insulating layer, at least a portion of the conductive pattern being buried in the contact hole, Wherein, the contact hole overlaps with the second region.

17. The method according to claim 11, wherein: An edge of the corner portion of the semiconductor pattern has an arc shape.

18. The method according to claim 16, wherein: A curvature of an inner edge of the corner portion of the semiconductor pattern is greater than a curvature of an outer edge of the corner portion of the semiconductor pattern.

19. The method according to claim 11, wherein: The first channel region and the second channel region are integrally provided.

20. The method according to any one of claims 11 to 19, wherein: The first thickness is to And the second thickness is to

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