Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The method of manufacturing the display device includes forming a transistor and a pixel electrode over a substrate, the pixel electrode being in the same layer as one of electrodes of the transistor; forming an adhesive layer on the pixel electrode; placing a light emitting element on the adhesive layer; forming an insulating layer to cover the transistor, the pixel electrode and the light emitting element; and forming a first bridge pattern electrically connecting the transistor to the first end of the light-emitting element and a second bridge pattern electrically connected to the second end of the light-emitting element, in which the light-emitting element is preliminarily fixed by the adhesive layer, and in which the light-emitting element is secondarily fixed by the insulating layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0091875 filed in the Korean Intellectual Property Office on July 14, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Various embodiments of the present disclosure are directed to a display device and a method of manufacturing the display device. Background Art

[0003] As interest in information display increases and as demand for using portable information media increases, demand for display devices has significantly increased, and commercialization of display devices is underway. Summary of the invention

[0004] Various embodiments of the present disclosure relate to a display device, and to a method of manufacturing the display device with improved yield.

[0005] Aspects of the present disclosure are not limited to the above-mentioned contents, and other unmentioned aspects will be clearly understood by those skilled in the art from the accompanying claims.

[0006] One or more embodiments of the present disclosure may provide a method for manufacturing a display device, the method comprising: forming a transistor and a pixel electrode above a substrate, the pixel electrode being on the same layer as one of the electrodes of the transistor; forming an adhesive layer on the pixel electrode; placing a light-emitting element on the adhesive layer; forming an insulating layer to cover the transistor, the pixel electrode, and the light-emitting element; and forming a first bridge pattern and a second bridge pattern, the first bridge pattern electrically connecting the transistor to a first end of the light-emitting element, the second bridge pattern electrically connecting to a second end of the light-emitting element, wherein the light-emitting element is preliminarily fixed by the adhesive layer, and wherein the light-emitting element is secondarily fixed by the insulating layer.

[0007] The light emitting element may include a first semiconductor layer, an emission layer, and a second semiconductor layer sequentially stacked from the second end to the first end, wherein an outer peripheral surface of each of the first semiconductor layer, the emission layer, and the second semiconductor layer is covered by an insulating layer.

[0008] The insulating layer may include an inorganic material.

[0009] The first end of the light emitting element may contact the adhesive layer, wherein the first bridge pattern contacts the pixel electrode, and wherein the first end of the light emitting element is electrically connected to the pixel electrode through the adhesive layer.

[0010] The adhesive layer may include a silver paste, wherein the step of forming the adhesive layer includes thermally curing the silver paste, and wherein the light emitting element is fixed to the pixel electrode by the cured silver paste.

[0011] The pixel electrode may include a reflective metal.

[0012] The method may further include forming an organic layer and an inorganic layer on the insulating layer, wherein a portion of the insulating layer in contact with the second end of the light emitting element is exposed from the organic layer and the inorganic layer.

[0013] The transistor may include a gate electrode above the semiconductor pattern and a back gate electrode below the semiconductor pattern and overlapping the gate electrode, wherein the pixel electrode and the back gate electrode are at the same layer.

[0014] The transistor may include a gate electrode over the semiconductor pattern, wherein the pixel electrode is at the same layer as the gate electrode.

[0015] The adhesive layer may include a photoresist, wherein the pixel electrode is electrically separated from the bottom surface of the light emitting element and the transistor.

[0016] One or more embodiments of the present disclosure may provide a display device, comprising: a transistor, which is above a substrate; a pixel electrode, which is in the same layer as one of the electrodes of the transistor; an adhesive layer, which is above the pixel electrode; a light-emitting element, which is above the adhesive layer and includes a first semiconductor layer, an emission layer, and a second semiconductor layer stacked sequentially from the second end to the first end; an insulating layer, which covers the transistor, the pixel electrode, and the light-emitting element, and covers the peripheral surfaces of the first semiconductor layer, the emission layer, and the second semiconductor layer; a first bridge pattern, which is above the insulating layer and electrically connects the transistor to the first end of the light-emitting element; and a second bridge pattern, which is above the insulating layer and electrically connected to the second end of the light-emitting element.

[0017] The first bridge pattern may contact the pixel electrode, wherein the first end of the light emitting element contacts the adhesive layer to be electrically connected to the pixel electrode.

[0018] The adhesive layer may include a silver paste, wherein the light emitting element is fixed to the pixel electrode by curing the silver paste.

[0019] The pixel electrode may include a reflective metal.

[0020] The display device may further include: an organic layer and an inorganic layer sequentially on the insulating layer, wherein a portion of the insulating layer contacting the second end of the light emitting element is exposed from the organic layer and the inorganic layer.

[0021] The transistor may include a gate electrode above the semiconductor pattern and a back gate electrode below the semiconductor pattern and overlapping the gate electrode, wherein the pixel electrode and the back gate electrode are at the same layer.

[0022] The transistor may include a gate electrode over the semiconductor pattern, wherein the pixel electrode is at the same layer as the gate electrode.

[0023] The adhesion layer may include a photoresist.

[0024] The pixel electrode may be electrically separated from a bottom surface of the light emitting element.

[0025] The light emitting element may include a flip chip type micro light emitting diode.

[0026] Details of various embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a plan view showing a display device according to one or more embodiments.

[0028] Figure 2 It is shown that the Figure 1 A circuit diagram of one or more embodiments of a pixel in a display device.

[0029] Figure 3 It is shown Figure 1 A cross-sectional view of one or more embodiments of a display device.

[0030] Figures 4 to 9 It shows the manufacturing Figure 3 A cross-sectional view of a method of displaying a device.

[0031] Fig.10 It is shown Figure 1 A cross-sectional view of one or more embodiments of a display device.

[0032] Fig.11 It is shown Figure 1 A cross-sectional view of one or more embodiments of a display device.

[0033] Figures 12 to 16 It shows the manufacturing Fig.11 A cross-sectional view of a method of displaying a device.

[0034] Fig.17 It is shown Figure 1 A cross-sectional view of one or more embodiments of a display device. DETAILED DESCRIPTION

[0035] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and their implementation methods. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Throughout the drawings and written descriptions, unless otherwise stated, the same reference numerals, symbols or combinations thereof indicate the same elements, and therefore, their repeated descriptions can be omitted.

[0036] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown here. The "can", "may" or "may not" used when describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and alternatives within the conceptual and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives are technically feasible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0037] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading is often provided in the drawings to clarify the boundaries between adjacent elements. As such, unless otherwise indicated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of an element.

[0038] Various embodiments are described herein with reference to cross-sectional views as schematic illustrations of embodiments and / or intermediate structures. As such, variations in the illustrated shapes caused by, for example, manufacturing techniques and / or tolerances are anticipated. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers, or regions, but rather include shape deviations caused by, for example, manufacturing.

[0039] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0040] For ease of explanation, spatially relative terms such as "under...", "below...", "lower part", "lower side", "under...", "above...", "upper part", and "upper side" may be used here to describe the relationship between one element or feature and another element (or elements) or feature (or features) as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as "under", "below", or "under" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "under..." and "under..." can cover both upper and lower orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used here should be interpreted accordingly. Similarly, when a first part is described as being arranged "on" a second part, this means that the first part is arranged on the upper or lower side of the second part based on the direction of gravity, without being limited to its upper side.

[0041] In addition, the phrase "in a plan view" means when a portion of an object is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting a portion of an object is viewed from the side. The term "superimposed" or "overlapping" means that the first object can be above or below or on one side of the second object, and vice versa. In addition, the term "superimposed" may include stacking, facing or facing, extending above, covering or partially covering, or any other suitable term that a person of ordinary skill in the art will understand and understand. The expression "non-superimposed" may include meanings such as "away from" or "biased" or "deviated from" and any other suitable equivalents that a person of ordinary skill in the art will understand and understand. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is placed between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0042] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may collectively represent direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, and / or capacitors, etc. When describing the embodiments, unless explicitly described as directly connected, expressions of connection indicate electrical connection, and “directly connected / directly coupled to” or “directly on” means that one component is directly connected or directly coupled to another component or directly on another component without intervening components.

[0043] In addition, in this specification, when a portion of a layer, film, region, plate, etc. is formed on another portion, the formation direction is not limited to the upper direction, but includes forming the portion on the side surface or in the lower direction. On the contrary, when a portion of a layer, film, region, plate, etc. is formed "under" another portion, this not only includes the case where the portion is "directly below" another portion, but also includes the case where there is further another portion between the portion and the other portion. At the same time, other expressions describing the relationship between components, such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or intermediate layers may also be present.

[0044] For the purposes of this disclosure, expressions such as "at least one of ... " or "any one of ... " or "one or more of ... " modify the entire list of elements when following a list of elements, without modifying the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one of the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ as examples) or any variation thereof. Similarly, expressions such as "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" can include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding / following a list of elements, modify the entire list of elements and not the individual elements of the list.

[0045] It will be understood that, although the terms "first", "second", "third", etc. can be used here to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish one element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first section described below may be referred to as the second element, second component, second region, second layer or second section. The element is described as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used here to distinguish elements of different categories or sets. For simplicity, the terms "first", "second", etc. may respectively represent "first category (or first set)", "second category (or second set)", etc.

[0046] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0047] The terms used herein are only used for the purpose of describing the embodiments, and are not intended to limit the present disclosure. As used herein, unless the context clearly states otherwise, the singular forms "one" and "one (kind / person)" are also intended to include plural forms, and the plural forms are also intended to include singular forms. It will also be understood that when the terms "include", "comprise", "have" and "have" and variations thereof are used in this specification, the stated features, wholes, steps, operations, elements and / or components are specified to exist, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof are not excluded.

[0048] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order.

[0049] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms rather than terms of degree, and are intended to account for the inherent deviations of measured or calculated values ​​that would be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. As used herein, "about" or "approximately" includes the stated value and means within the acceptable deviation range of the particular value determined by those of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0051] Hereinafter, a display device according to one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0052] Figure 1 is a plan view showing a display device 10 according to one or more embodiments.

[0053] Reference Figure 1The display device 10 (or display panel) may be a device configured to display images, and may be used not only as a display screen for portable electronic devices such as mobile phones, smart phones, tablet personal computers (desktop PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs) but also as a display screen for various products such as televisions, notebooks, monitors, advertising panels, and Internet of Things (IOT) devices.

[0054] The display device 10 may be formed of a rectangular panel having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. The corresponding corners where the long side extending in the first direction DR1 and the short side extending in the second direction DR2 meet may be rounded with a corresponding curvature, or may be formed at a substantially right angle. The planar shape of the display device 10 is not limited to a rectangular shape, and may have other polygonal shapes, a circular shape, or an elliptical shape. The display device 10 (or the planar shape of the display device 10) may have an irregular shape (or may be irregular). The display device 10 may be formed to be planar, but is not limited thereto. For example, the display device 10 may include a curved surface formed in each of its left and right edges and having a constant curvature or a varying curvature. In addition, the display device 10 may be formed to be flexible so that the display device 10 may be bent, folded, or curled.

[0055] The display device 10 may include pixels PX (or sub-pixels) to display an image. The pixels PX may be arranged in a matrix in a first direction DR1 and a second direction DR2, but the present disclosure is not limited thereto. The display device 10 may further include gate lines (or scan lines) extending in the first direction DR1 and data lines extending in the second direction DR2.

[0056] Each pixel PX may include an inorganic light emitting element including an inorganic semiconductor as a light emitting element for emitting light. For example, the inorganic light emitting element may be a flip-chip type micro light emitting diode (LED), but the embodiments of the present disclosure are not limited thereto.

[0057] Figure 2 It is shown that the Figure 1 A circuit diagram of one or more embodiments of a pixel PX in a display device.

[0058] Reference Figure 2 , the pixel PX may be connected to the gate line GL, the data line DL, the first power line PL1 and the second power line PL2. In addition, the pixel PX may be further connected to at least one power line and / or signal line.

[0059] A gate signal (or scan signal) may be supplied to the gate line GL. A data signal may be supplied to the data line DL. A voltage of a first power source VDD may be applied to the first power line PL1. A voltage of a second power source VSS may be applied to the second power line PL2. The first power source VDD and the second power source VSS may have different potentials.

[0060] The pixel PX may include a light emitting element ED configured to generate light having brightness corresponding to a data signal. In addition, the pixel PX may further include a pixel circuit PC configured to drive the light emitting element ED.

[0061] The pixel circuit PC may be electrically connected to the gate line GL and the data line DL, and may be electrically connected between the first power line PL1 and the light emitting element ED.

[0062] The pixel circuit PC may include at least one transistor and at least one capacitor Cst. For example, the pixel circuit PC may include a first transistor M1, a second transistor M2, and a capacitor Cst.

[0063] The first transistor M1 may be connected between the first power line PL1 and the second node N2. The second node N2 may be a node to which the pixel circuit PC and the light emitting element ED are connected. For example, the second node N2 may be a node through which one electrode (e.g., a source electrode) of the first transistor M1 is electrically connected to the light emitting element ED. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control a driving current to be supplied to the light emitting element ED in response to a voltage of the first node N1. For example, the first transistor M1 may be a driving transistor of the pixel PX.

[0064] The second transistor M2 may be connected between the data line DL and the first node N1. A gate electrode of the second transistor M2 may be connected to the gate line GL. When a gate signal having a gate-on voltage (e.g., a logic high voltage or a high-level voltage) is supplied from the gate line GL, the second transistor M2 may be turned on to connect the data line DL with the first node N1.

[0065] During each frame period, a data signal of a corresponding frame may be supplied to the data line DL, and the data signal may be transmitted to the first node N1 through the second transistor M2 during a period in which a gate signal having a gate-on voltage is supplied. For example, the second transistor M2 may be a switching transistor configured to transmit each data signal to the inside of the pixel PX.

[0066] A first electrode of the capacitor Cst may be connected to the first node N1. A second electrode of the capacitor Cst may be connected to the second node N2. The capacitor Cst may be charged with a voltage corresponding to a data signal to be supplied to the first node N1 during each frame period.

[0067] Despite Figure 2 In the embodiment, both the first transistor M1 and the second transistor M2 included in the pixel circuit PC are described as n-type transistors, but the embodiment is not limited thereto. For example, at least one of the first transistor M1 and the second transistor M2 may be a p-type transistor. According to the embodiment, the structure and driving method of the pixel PX may be changed in various ways.

[0068] In addition, the pixel circuit PC may further include other circuit elements, such as an initialization transistor (or a sensing transistor) configured to initialize the anode electrode of the light-emitting element ED, a compensation transistor configured to compensate for the threshold voltage of the first transistor M1, an initialization transistor configured to initialize the voltage of the first node N1, an emission control transistor configured to control the period of time during which the driving current is supplied to the light-emitting element ED, and / or a boost capacitor configured to increase the voltage of the first node N1.

[0069] The light emitting element ED may emit light having a brightness corresponding to a driving current supplied thereto by the pixel circuit PC. The light emitting element ED may be connected between the first transistor M1 and the second power line PL2. The first electrode of the light emitting element ED may be connected to one electrode (or the second node N2) of the first transistor M1. The second electrode of the light emitting element ED may be connected to the second power line PL2. Here, the first electrode of the light emitting element ED may be an anode electrode, and the second electrode of the light emitting element ED may be a cathode electrode. The light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode. For example, the light emitting element ED may be a micro LED formed of an inorganic semiconductor, but is not limited thereto.

[0070] Despite Figure 2 It has been shown that the pixel PX includes only one light-emitting element ED, but the embodiments of the present disclosure are not limited thereto. For example, the pixel PX may also include at least one light-emitting element connected in parallel to the light-emitting element ED. As another example, the pixel PX may also include at least one light-emitting element connected in series to the light-emitting element ED. The number, type and / or structure of the light-emitting elements ED forming the effective light source of the pixel PX may vary according to the embodiment.

[0071] Figure 3 It is shown Figure 1 A cross-sectional view of one or more embodiments of a display device 10 is provided. Figure 3 , a cross-sectional view of the display device 10 is shown based on one pixel PX (or pixel region).

[0072] Reference Figures 1 to 3The pixel PX (or the display device 10) may include a substrate SUB, a buffer layer BF, a bottom electrode layer BML, an active layer ACTL (or an active pattern), a gate insulating layer GI, a gate layer GTL, an interlayer insulating layer ILD, a first source metal layer SDL1, a first via layer VIA1 (or a first organic layer), a second source metal layer SDL2, a second via layer VIA2 (or a second organic layer), a third source metal layer SDL3 and a passivation layer PVX (or an inorganic layer).

[0073] In one or more embodiments of the present disclosure, unless otherwise specified, “components are disposed and / or formed on the same layer” may mean that the components are formed by the same process, and “components are disposed and / or formed on different layers” may mean that the components are formed by different processes.

[0074] The substrate SUB (or substrate layer) may be a substrate substrate or a substrate component for supporting the display device 10. The substrate SUB may be a rigid substrate made of glass. Alternatively, the substrate SUB may be a flexible substrate that is bendable, foldable, or rollable, etc. In this case, the substrate SUB may include an insulating material such as a polymer resin (e.g., polyimide (PI)).

[0075] The substrate SUB may include an emission region and a non-emission region based on a single pixel PX. In a plan view, a light emitting element ED is provided in the emission region, and a thin film transistor TFT (or transistor), a signal line (e.g., a data line DL), and power lines PL1 and PL2 are positioned in the non-emission region. The thin film transistor TFT, the signal line, and the power lines PL1 and PL2 are not positioned in the emission region.

[0076] The bottom electrode layer BML may be positioned on the substrate SUB. The bottom electrode layer BML may include a bottom gate electrode BGE (or a back gate electrode or a bottom electrode). The bottom gate electrode BGE may overlap the active layer ACTL (or the channel CH of the thin film transistor TFT) in the third direction DR3. The bottom gate electrode BGE may block light irradiated onto the active layer ACTL in the third direction DR3, thereby alleviating or improving characteristic changes of the thin film transistor TFT otherwise caused by exposure to light.

[0077] In one or more embodiments, the bottom electrode layer BML may further include a pixel electrode ELT. The pixel electrode ELT may be an anode electrode. The pixel electrode ELT may be positioned at the same layer as one of the electrodes of the thin film transistor TFT. In one or more embodiments, the pixel electrode ELT may be positioned at the same layer as the bottom gate electrode BGE of the thin film transistor TFT.

[0078] The bottom electrode layer BML may include a conductive material. For example, the conductive material may include copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), chromium (Cr), gold (Au), and / or alloys thereof, and may be formed as a single layer or multiple layers.

[0079] In one or more embodiments, the bottom electrode layer BML may include a conductive material with high reflectivity. For example, the bottom electrode layer BML may include a metal such as silver (Ag), copper (Cu) or aluminum (Al), or may include an alloy containing aluminum (Al), nickel (Ni) or lanthanum (La), etc. However, the present disclosure is not limited thereto, and the bottom electrode layer BML may also include a transparent conductive material. For example, the bottom electrode layer BML may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO) and / or indium tin zinc oxide (ITZO). In one or more embodiments, the bottom electrode layer BML may be provided as a structure formed by stacking one or more transparent conductive material layers and one or more metal layers with high reflectivity on each other, or may be formed as a single layer including a transparent conductive material layer and a metal layer. For example, the bottom electrode layer BML may include a metal material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy or a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0080] The buffer layer BF (or buffer film) may be positioned on the substrate SUB. The buffer layer BF may reduce or prevent the penetration of air or water. The buffer layer BF may be an inorganic insulating layer including an inorganic material. For example, the inorganic material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and metal oxides such as aluminum oxide (AlO x )) at least one of.

[0081] The buffer layer BF may cover the bottom electrode layer BML except for at least a portion of the pixel electrode ELT. The buffer layer BF may include or define an opening through which the pixel electrode ELT is exposed.

[0082] An adhesive layer PST (or temporary adhesive layer) may be positioned on the pixel electrode ELT. The adhesive layer PST may fix or bond the light emitting element ED to the pixel electrode ELT.

[0083] In one or more embodiments, the adhesive layer PST may include silver paste. For example, the silver paste may include silver nanoparticles mixed in a resin such as an acrylic resin or an epoxy resin. The adhesive layer PST including the silver paste may electrically connect the light emitting element ED to the pixel electrode ELT. However, the adhesive layer PST is not limited to the above-described embodiments. For example, in addition to silver, the adhesive layer PST may also include conductive particles such as copper and nickel. As another example, the adhesive layer PST may not include conductive particles and may include an insulating material such as a photoresist.

[0084] For reference, in order to bond the light emitting element ED to the pixel electrode ELT, a method such as an ACF bonding method using an anisotropic conductive film (ACF) or a eutectic bonding method may be used. However, in the case of the ACF bonding method, if pressure is applied to the light emitting element ED (and the ACF) to bond the light emitting element ED to the pixel electrode ELT, conductive balls (or particles) in the ACF may be displaced outward from the region between the light emitting element ED and the pixel electrode ELT, thus potentially causing improper connection between the light emitting element ED and the pixel electrode ELT.

[0085] The eutectic bonding method is a relatively low temperature bonding technology that involves applying pressure and heat to a metal film (e.g., copper, tin, gold, or lead, etc.) having a relatively low melting point (ranging from about 200°C to about 500°C). However, even though it is considered a low temperature process, a process temperature of at least about 180°C is appropriate. Depending on the materials and processes of the components in the display device 10, the eutectic bonding method that properly uses a process temperature of about 180°C may not be applicable. In addition, considering the bonding strength between the pixel electrode ELT and the light emitting element ED, the type of metal film may be limited.

[0086] The silver paste may have adhesive properties when cured, and the curing conditions of the silver paste may be about 12 hours at about 25° C. or about 30 minutes at about 100° C. In other words, the light emitting element ED may be bonded to the pixel electrode ELT at a lower process temperature. The adhesive strength of the silver paste alone (e.g., ranging from about 70 kgf / cm 2 To about 80kgf / cm 2 ) may not be sufficient to allow the light emitting element ED to withstand the cleaning process (e.g., at about 120 kgf / cm 2 In view of this, the light emitting element ED can be reliably fixed by covering the light emitting element ED with the interlayer insulating layer ILD to be described below. The adhesive strength of the silver paste may be sufficient to maintain the fixed state of the light emitting element ED during the deposition process of the interlayer insulating layer ILD. In other words, the light emitting element ED can be temporarily fixed or bonded by the silver paste, and thereafter, the light emitting element ED can be reliably fixed by the interlayer insulating layer ILD.

[0087] The light emitting element ED may include a first semiconductor layer 11, an emission layer 12 (or an active layer), a second semiconductor layer 13, and an element electrode layer 14. The first semiconductor layer 11 may be a second end of the light emitting element ED, and the element electrode layer 14 may be a first end of the light emitting element ED. The first semiconductor layer 11, the emission layer 12, the second semiconductor layer 13, and the element electrode layer 14 may be sequentially stacked from the second end to the first end in one direction.

[0088] The first semiconductor layer 11 may be doped with a first conductive type dopant. The first conductive type may refer to an n-type. The first conductive type dopant may include Si, Ge, Sn, etc. In other words, the first semiconductor layer 11 may include an n-type semiconductor. For example, the first semiconductor layer 11 may include n-GaN doped with n-type Si.

[0089] The second semiconductor layer 13 may be positioned at a position spaced apart from the first semiconductor layer 11, and the emission layer 12 is disposed between the second semiconductor layer 13 and the first semiconductor layer 11. The second semiconductor layer 13 may be doped with a second conductive type dopant. The second conductive type may refer to a p-type. The second conductive type dopant may include Mg, Zn, Ca, Sr, Ba, and the like. In other words, the second semiconductor layer 13 may include a p-type semiconductor. For example, the second semiconductor layer 13 may include p-GaN doped with p-type Mg.

[0090] Although each of the first semiconductor layer 11 and the second semiconductor layer 13 is formed as a single layer, the embodiments of the present disclosure are not limited thereto. For example, depending on the material included in the emission layer 12, at least one of the first semiconductor layer 11 and the second semiconductor layer 13 may include a greater number of layers, such as a cap layer or a tensile strain barrier reduction (TSBR) layer.

[0091] The emission layer 12 may be positioned between the first semiconductor layer 11 and the second semiconductor layer 13. The emission layer 12 may include a material having a single quantum well structure or a multi-quantum well structure. The emission layer 12 may emit light by recombination of electron-hole pairs in response to an electrical signal applied through the first semiconductor layer 11 and the second semiconductor layer 13. For example, in the case where the emission layer 12 emits light in a blue band, the emission layer 12 may include a material such as AlGaN or AlGaInN, but the embodiments of the present disclosure are not limited thereto.

[0092] In an embodiment, according to the wavelength band of light to be emitted, emission layer 12 may have a structure formed by alternately stacking a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap, and may include semiconductor materials of Group III to Group V. Light emitted from emission layer 12 is not limited to light in the blue wavelength band, and may be light in the red or green wavelength band in some cases.

[0093] The light emitted from the emission layer 12 may be emitted through the side surfaces of the light emitting element ED in addition to the opposite ends of the light emitting element ED. The light output direction of the light emitted from the emission layer 12 is not limited to a specific direction.

[0094] The opposite ends of the light emitting element ED are electrically connected to external electrodes (e.g., pixel electrodes ELT) to apply electrical signals to the first semiconductor layer 11 and the second semiconductor layer 13. The element electrode layer 14 may be positioned between the second semiconductor layer 13 and the corresponding external electrode (e.g., the corresponding pixel electrode ELT) to reduce resistance. The element electrode layer 14 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and ITZO (indium tin zinc oxide). In one or more embodiments, the element electrode layer 14 may include a semiconductor material doped with an n-type or p-type dopant.

[0095] The element electrode layer 14 may be positioned below the second semiconductor layer 13 , but the embodiments of the present disclosure are not limited thereto. For example, a separate element electrode layer may be further positioned on the first semiconductor layer 11 .

[0096] The element electrode layer 14 (or the first end) of the light emitting element ED may contact the adhesive layer PST, and may be electrically connected to the pixel electrode ELT through the adhesive layer PST.

[0097] The active layer ACTL may be positioned on the buffer layer BF. The active layer ACTL may include a silicon semiconductor such as a polycrystalline silicon semiconductor, a single crystal silicon semiconductor, a low temperature polycrystalline silicon semiconductor, and an amorphous silicon semiconductor, or may include an oxide semiconductor.

[0098] The active layer ACTL may include a channel CH of the thin film transistor TFT, a first electrode SE and a second electrode DE. Here, the thin film transistor TFT is included in Figure 2 A transistor in a pixel circuit PC of a thin film transistor TFT. For example, the thin film transistor TFT may correspond to the first transistor M1. The channel CH of the thin film transistor TFT may refer to a region overlapping with the gate electrode GE of the thin film transistor TFT in the third direction DR3. The first electrode SE of the thin film transistor TFT may be positioned on one side of the channel CH, and the second electrode DE may be positioned on the other side of the channel CH. The first electrode SE and the second electrode DE of the thin film transistor TFT may refer to a region not overlapping with the gate electrode GE in the third direction DR3. The channel CH of the thin film transistor TFT may be an intrinsic semiconductor as an undoped semiconductor pattern. The first electrode SE and the second electrode DE of the thin film transistor TFT may be a semiconductor pattern doped with impurities.

[0099] The gate insulating layer GI may be positioned on the active layer ACTL and the buffer layer BF. The gate insulating layer GI may be an insulating layer including an inorganic material.

[0100] The gate layer GTL may be positioned on the gate insulating layer GI. The gate layer GTL may include a conductive material and may be formed as a single layer or multiple layers. The gate layer GTL may include a gate electrode GE of the thin film transistor TFT, a first capacitor electrode CE1, and a second power line PL2.

[0101] The interlayer insulating layer ILD (or insulating layer) may be positioned on the gate layer GTL. The interlayer insulating layer ILD may be an insulating layer including an inorganic material. The interlayer insulating layer ILD may be formed as a single layer or multiple layers. The interlayer insulating layer ILD may cover the thin film transistor TFT, the pixel electrode ELT, and the light emitting element ED.

[0102] In one or more embodiments, the interlayer insulating layer ILD may directly cover the peripheral surface (or side surface) of the light emitting element ED. The interlayer insulating layer ILD may reduce or prevent the possibility of a short circuit between the light emitting element ED and an adjacent component. In addition, the interlayer insulating layer ILD may reduce or minimize surface defects of the light emitting element LD, thereby improving the efficiency and service life of the light emitting element LD. During the etching process in the process of manufacturing the light emitting element ED, surface defects may occur on the surface of the semiconductor layer exposed to the etchant at the outermost edge. Surface defects may cause leakage of electrons injected into the semiconductor layer or may cause capture of holes, thereby hindering recombination between electrons and holes, thereby reducing the light efficiency of the light emitting element ED. In the case where the interlayer insulating layer ILD is directly positioned or formed on the side surface of the light emitting element ED, the side surface of the light emitting element ED may have a surface treatment effect.

[0103] For reference, in the case where the light emitting element ED is manufactured separately from the display device 10, an insulating layer (or a passivation layer) is formed on the outer peripheral surface of the light emitting element ED during the process of manufacturing the light emitting element ED to reduce or minimize surface defects. In the present disclosure, the interlayer insulating layer ILD is used as an insulating layer of the light emitting element ED, and a separate insulating layer does not need to be formed on the light emitting element ED during the process of manufacturing the light emitting element ED. Therefore, the manufacturing cost of the light emitting element ED and the display device 10 including the light emitting element ED can be reduced.

[0104] The first source metal layer SDL1 may be positioned on the interlayer insulating layer ILD. The first source metal layer SDL1 may include a conductive material, and may be formed as a single layer or a multi-layer.

[0105] The first source metal layer SDL1 may include a first bridge pattern BRP1, a second bridge pattern BRP2, a second capacitor electrode CE2, and a data line DL. The first bridge pattern BRP1 may contact the first electrode SE (or the second electrode DE) of the thin film transistor TFT through a contact hole passing through the interlayer insulating layer ILD, or may be connected to the first electrode SE (or the second electrode DE) of the thin film transistor TFT through a contact hole passing through the interlayer insulating layer ILD. In addition, the first bridge pattern BRP1 may contact the pixel electrode ELT through a contact hole passing through the interlayer insulating layer ILD, or may be connected to the pixel electrode ELT through a contact hole passing through the interlayer insulating layer ILD.

[0106] The second bridge pattern BRP2 may be connected to the first semiconductor layer 11 of the light emitting element ED through a contact hole passing through the interlayer insulating layer ILD. In addition, the second bridge pattern BRP2 may be connected to the second power line PL2 through a contact hole passing through the interlayer insulating layer ILD.

[0107] The second capacitor electrode CE2 may form a capacitor Cst (refer to Figure 2 ). The data line DL can be a reference Figure 2 Describe the data line DL.

[0108] The first via layer VIA1 (also referred to as the first planarization layer) may be positioned on the first source metal layer SDL1. The first via layer VIA1 may planarize the step surface caused by the bottom electrode layer BML, the active layer ACTL, the gate layer GTL and / or the first source metal layer SDL1. The first via layer VIA1 may be an insulating layer including an organic material. For example, the organic material may include an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, etc. In one or more embodiments, the first via layer VIA1 may not cover the light emitting element ED (or the area corresponding to the light emitting element ED).

[0109] The second source metal layer SDL2 may be positioned on the first via layer VIA1. The second source metal layer SDL2 may include a conductive material, and may be formed as a single layer or a multi-layer.

[0110] The second source metal layer SDL2 may include a third bridge pattern BRP3 and a signal line SL. The third bridge pattern BRP3 may be connected to the second electrode DE of the thin film transistor TFT through a contact hole passing through the first via layer VIA1. The signal line SL may be a reference Figure 2 The gate line GL is described, or may include the gate line GL.

[0111] The second via layer VIA2 (also referred to as the second planarization layer) may be positioned on the second source metal layer SDL2. The second via layer VIA2 may be an insulating layer including an organic material. In one or more embodiments, the second via layer VIA2 may not cover at least a portion of the light emitting element ED (or a region corresponding to the light emitting element ED). In other words, the second via layer VIA2 may include or define an opening corresponding to the light emitting element ED.

[0112] The third source metal layer SDL3 may be positioned on the second via layer VIA2. The third source metal layer SDL3 may include a conductive material, and may be formed as a single layer or a multi-layer.

[0113] The third source metal layer SDL3 may include a first power line PL1. The first power line PL1 may contact the third bridge pattern BRP3 through a contact hole passing through the second via layer VIA2, or may be connected to the third bridge pattern BRP3 through a contact hole passing through the second via layer VIA2. The first power line PL1 may be connected to the second electrode DE of the thin film transistor TFT through the third bridge pattern BRP3.

[0114] The passivation layer PVX may be positioned on the third source metal layer SDL3. The passivation layer PVX may be an insulating layer including an inorganic material. In one or more embodiments, the passivation layer PVX may not cover at least a portion of the light emitting element ED (or a region corresponding to the light emitting element ED).

[0115] In the case where a plurality of insulating layers are disposed on the light emitting element ED, reflection of light between the insulating layers may result in a reduction in the light output efficiency of the display device 10. Therefore, in consideration of the light output efficiency, the second via layer VIA2 and the passivation layer PVX may not cover the light emitting element ED (or the region corresponding to the light emitting element ED). However, the present disclosure is not limited to the foregoing example, and the second via layer VIA2 and the passivation layer PVX may cover the light emitting element ED (or the region corresponding to the light emitting element ED).

[0116] In one or more embodiments, the light conversion pattern may be positioned or disposed in the opening of the second via layer VIA2 (or on the light emitting element ED). For example, the light conversion pattern may use color conversion particles (or quantum dots) to change or convert the wavelength (or color) of light emitted from the light emitting element ED.

[0117] As described above, the pixel electrode ELT may be positioned at the same layer as the bottom gate electrode BGE which is one electrode of the thin film transistor TFT. The light emitting element ED may be temporarily fixed (or preliminarily fixed) or bonded to the pixel electrode ELT by the adhesive layer PST. The interlayer insulating layer ILD may directly cover the light emitting element ED, thereby completely (or secondarily) fixing the light emitting element ED in place. Because the light emitting element ED is fixed in place by the adhesive layer PST and the interlayer insulating layer ILD, the light emitting element ED may be fixed or bonded to the pixel electrode ELT only by a low temperature process, without the need for a high temperature process and / or a pressing process. Therefore, damage to the components of the display device 10 caused by a high temperature process may be reduced or prevented, thereby improving the yield of the display device 10.

[0118] In addition, the interlayer insulating layer ILD directly covers the outer peripheral surface (or side surface) of the light emitting element ED, thereby reducing or minimizing surface defects of the light emitting element ED. Therefore, during the manufacturing process of the light emitting element ED, there is no need to form a separate insulating layer (e.g., an insulating layer designed to reduce or minimize surface defects) on the light emitting element ED. Therefore, the manufacturing cost of the light emitting element ED and the display device 10 including the light emitting element ED can be reduced.

[0119] Figures 4 to 9 It shows the manufacturing Figure 3 A cross-sectional view of a method of displaying device 10.

[0120] Reference Figures 3 to 9 , a thin film transistor TFT and a pixel electrode ELT may be formed on the substrate SUB.

[0121] like Figure 4 As shown in , a bottom electrode layer BML including a bottom gate electrode BGE and a pixel electrode ELT may be formed on a substrate SUB. The bottom electrode layer BML or the pixel electrode ELT may include a conductive material having a high reflectivity, such as silver (Ag), copper (Cu) and / or aluminum (Al). A buffer layer BF may be formed to cover the bottom electrode layer BML. An active layer ACTL may be positioned on the buffer layer BF to overlap with the bottom gate electrode BGE. A gate insulating layer GI may be positioned on the active layer ACTL. A gate layer GTL may be positioned on the gate insulating layer GI. For example, the gate insulating layer GI may be positioned on the entire surface of the substrate SUB, and the gate insulating layer GI may be patterned using the gate layer GTL as a mask. Thus, the gate insulating layer GI may exist only under the first capacitor electrode CE1, the gate electrode GE, and the second power line PL2, and the first electrode SE and the second electrode DE of the active layer ACTL that do not overlap with the gate electrode GE may be doped with impurities.

[0122] Afterwards, if Figure 5As shown in , at least a portion of the buffer layer BF on the pixel electrode ELT may be removed. The pixel electrode ELT may be exposed through the opening OP of the buffer layer BF.

[0123] like Figure 6 As shown in , an adhesive layer PST may be formed on the pixel electrode ELT. In one or more embodiments, the adhesive layer PST may include a silver paste.

[0124] like Figure 7 As shown in , the light emitting element ED may be positioned or mounted on the adhesive layer PST. The element electrode layer 14 (or the first end) of the light emitting element ED may contact the adhesive layer PST. The element electrode layer 14 of the light emitting element ED may be electrically connected to the pixel electrode ELT through the adhesive layer PST including the silver paste.

[0125] For example, the light emitting element ED may be grown and formed on a semiconductor substrate such as a silicon wafer. The light emitting element ED may be directly transferred from the silicon wafer to the adhesive layer PST. The light emitting element ED may be transferred to the adhesive layer PST by an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0126] In one or more embodiments, a curing (or thermal curing) process may be performed on the adhesive layer PST including the silver paste. As described above, the curing conditions of the silver paste may be about 12 hours at about 25° C. or about 30 minutes at about 100° C., and the silver paste may be cured in consideration of the curing conditions. The cured silver paste has a thermal conductivity ranging from about 70 kgf / cm 2 To about 80kgf / cm 2 The bonding strength of the light emitting element ED is increased, thereby reducing or preventing the possibility of the light emitting element ED being removed from the pixel electrode ELT during a subsequent process. In other words, the light emitting element ED can be fixed (or temporarily fixed) or bonded to the pixel electrode ELT by the cured silver paste. The curing process can be performed before, after or during the supply of the light emitting element ED.

[0127] like Figure 8 As shown in , an interlayer insulating layer ILD may be formed or deposited to cover the gate layer GTL and the light emitting element ED. The interlayer insulating layer ILD may be formed on the entire surface of the substrate SUB. The interlayer insulating layer ILD may completely fix the light emitting element ED in place. In other words, the light emitting element ED may be preliminarily fixed on the pixel electrode ELT by the adhesive layer PST, and secondarily fixed on the pixel electrode ELT by the interlayer insulating layer ILD.

[0128] like Fig. 9As shown in , the first source metal layer SDL1 can be positioned on the interlayer insulating layer ILD. The first bridge pattern BRP1 can make contact with the first electrode SE (or the second electrode DE) of the thin film transistor TFT through a contact hole passing through the interlayer insulating layer ILD, or can be connected to the first electrode SE (or the second electrode DE) of the thin film transistor TFT through a contact hole passing through the interlayer insulating layer ILD. In addition, the first bridge pattern BRP1 can make contact with the pixel electrode ELT through a contact hole passing through the interlayer insulating layer ILD, or can be connected to the pixel electrode ELT through a contact hole passing through the interlayer insulating layer ILD. Therefore, the element electrode layer 14 (or the first end) of the light emitting element ED can be electrically connected to the thin film transistor TFT through the pixel electrode ELT and the first bridge pattern BRP1.

[0129] The second bridge pattern BRP2 may be connected to the first semiconductor layer 11 of the light emitting element ED through a contact hole passing through the interlayer insulating layer ILD. In addition, the second bridge pattern BRP2 may be connected to the second power line PL2 through a contact hole passing through the interlayer insulating layer ILD. Therefore, the first semiconductor layer 11 (or the second end) of the light emitting element ED may be electrically connected to the second power line PL2 through the second bridge pattern BRP2. The second capacitor electrode CE2 and the first capacitor electrode CE1 may form a capacitor Cst.

[0130] Thereafter, a first via layer VIA1, a second source metal layer SDL2, a second via layer VIA2, a third source metal layer SDL3, and a passivation layer PVX may be sequentially formed. As a result, a Figure 3 The display device 10 of the present invention. A portion of the interlayer insulating layer ILD contacting the upper surface (or the second end) of the light emitting element ED may be exposed from the first and second via layers VIA1 and VIA2 (or the organic layer) and the passivation layer PVX (or the inorganic layer).

[0131] As described above, the light emitting element ED may be primarily fixed (or temporarily fixed) to the pixel electrode ELT through the adhesive layer PST, and secondarily fixed to the pixel electrode ELT through the interlayer insulating layer ILD. The light emitting element ED may be fixed or bonded to the pixel electrode ELT only through a low temperature process without requiring a high temperature process and / or a pressing process.

[0132] Fig.10 It is shown Figure 1 A cross-sectional view of one or more embodiments of a display device.

[0133] Reference Figure 1 , Figure 3 and Fig.10 , except for the light emitting element ED_1, Fig.10 The structure of the display device 10_1 can be Figure 3The structure of the display device 10 is substantially the same or similar. Therefore, repeated explanation thereof will be omitted.

[0134] The light emitting element ED_1 may include a base substrate SSUB, a first semiconductor layer 11, an emission layer 12, a second semiconductor layer 13, an element electrode layer 14 (or a first contact electrode), and a contact electrode layer 15 (or a second contact electrode). The light emitting element ED_1 may be a flip chip type micro LED and may have a mesa structure.

[0135] The base substrate SSUB may be a sapphire substrate, but is not limited thereto.

[0136] The first semiconductor layer 11, the emission layer 12, the second semiconductor layer 13, and the element electrode layer 14 may be sequentially positioned on the base substrate SSUB. A portion of the first semiconductor layer 11 may be exposed from the emission layer 12. The contact electrode layer 15 may be positioned on the portion of the first semiconductor layer 11. The contact electrode layer 15 may include the same material as that of the element electrode layer 14.

[0137] The interlayer insulating layer ILD may cover the light emitting element ED_1 .

[0138] The first bridge pattern BRP1 may make contact with the element electrode layer 14 of the light emitting element ED_1 through a contact hole passing through the interlayer insulating layer ILD, or may be connected to the element electrode layer 14 of the light emitting element ED_1 through a contact hole passing through the interlayer insulating layer ILD. The first bridge pattern BRP1 may be directly connected to the element electrode layer 14 of the light emitting element ED_1 without passing through the pixel electrode ELT.

[0139] The second bridge pattern BRP2 may make contact with the contact electrode layer 15 of the light emitting element ED_1 through a contact hole passing through the interlayer insulating layer ILD, or may be connected to the contact electrode layer 15 of the light emitting element ED_1 through a contact hole passing through the interlayer insulating layer ILD. The second bridge pattern BRP2 may be directly connected to the contact electrode layer 15 of the light emitting element ED_1 without passing through the pixel electrode ELT.

[0140] In one or more embodiments, the adhesive layer PST_1 may include silver paste. However, because the base substrate SSUB is an insulator, the light emitting element ED_1 (eg, its bottom surface) may be electrically separated from the pixel electrode ELT. The pixel electrode ELT may be electrically floating. In one or more embodiments, the pixel electrode ELT may not be necessary and may be omitted.

[0141] In one or more embodiments, the pixel electrode ELT can be used as a heat sink. For example, the heat generated from the light-emitting element ED_1 can be transferred to the pixel electrode ELT through a silver paste having a relatively high thermal conductivity. The heat can be released to the outside through the pixel electrode ELT and the lower part of the substrate SUB. In the case where the pixel electrode ELT is formed on the entire surface of the substrate SUB except for the bottom gate electrode BGE, the use of the pixel electrode ELT having a flat plate shape can enhance the heat dissipation effect.

[0142] In one or more embodiments, the adhesive layer PST_1 may include an insulating material such as a photoresist. The photoresist may also have an adhesive strength at a level similar to that of the silver paste, and may fix the light emitting element ED_1 to the pixel electrode ELT. Since no electrical connection is required between the light emitting element ED_1 and the pixel electrode ELT, the adhesive layer PST_1 may omit conductive particles. In this case, the pixel electrode ELT may be used as a heat sink.

[0143] As described above, the pixel electrode ELT is electrically separated from the light emitting element ED_1 , and may function as a heat sink designed to dissipate heat generated from the light emitting element ED_1 to the outside.

[0144] Fig.11 It is shown Figure 1 A cross-sectional view of one or more embodiments of a display device.

[0145] Reference Figure 1 , Figure 3 and Fig.11 , in addition to the placement position of the pixel electrode ELT (and the corresponding placement position of the light emitting element ED), Fig.11 The display device 10_2 may be constructed in the same manner as Figure 3 The configuration of the display device 10 is substantially the same or similar. Therefore, repeated explanation thereof will be omitted.

[0146] In an embodiment, the pixel electrode ELT may be positioned at the same layer as one of the electrodes of the thin film transistor TFT.

[0147] In one or more embodiments, the pixel electrode ELT may be positioned on the buffer layer BF. The pixel electrode ELT may be positioned at the same layer as the first electrode SE (or the second electrode DE) of the thin film transistor TFT included in the active layer ACTL.

[0148] In one or more embodiments, the pixel electrode ELT may be included in the gate layer GTL. In other words, the pixel electrode ELT may be formed simultaneously or substantially simultaneously with the gate electrode GE of the thin film transistor TFT included in the gate layer GTL through the same process. In this case, the gate layer GTL including the pixel electrode ELT may include a conductive material having high reflectivity, such as silver (Ag), copper (Cu) and / or aluminum (Al).

[0149] The adhesive layer PST may be positioned on the pixel electrode ELT. The light emitting element ED may be positioned on the adhesive layer PST. The interlayer insulating layer ILD may cover the light emitting element ED.

[0150] As described above, the pixel electrode ELT may be positioned at the same layer as one of the electrodes of the thin film transistor TFT. The pixel electrode ELT may be positioned at the same layer as the gate electrode GE of the thin film transistor TFT.

[0151] Figures 12 to 16 It is shown Fig.11 A cross-sectional view of a method for manufacturing a display device 10_2.

[0152] Reference Figures 11 to 16 , a thin film transistor TFT and a pixel electrode ELT may be formed on the substrate SUB. In the following description, the description of Figures 4 to 9 The explanation of the contents is repeated in the examples.

[0153] like Fig.12 As shown in , a bottom electrode layer BML including a bottom gate electrode BGE may be formed on a substrate SUB. A buffer layer BF may be formed to cover the bottom electrode layer BML. An active layer ACTL may be positioned on the buffer layer BF to overlap with the bottom gate electrode BGE. A gate insulating layer GI may be positioned on the active layer ACTL. A gate layer GTL may be positioned on the gate insulating layer GI. The gate layer GTL may include a pixel electrode ELT. The pixel electrode ELT may include a conductive material having a relatively high reflectivity.

[0154] like Fig.13 As shown in , an adhesive layer PST may be formed on the pixel electrode ELT. In one or more embodiments, the adhesive layer PST may include a silver paste.

[0155] like Fig.14 As shown in , the light emitting element ED may be positioned or mounted on the adhesive layer PST.

[0156] Afterwards, if Fig.15As shown in , an interlayer insulating layer ILD may be formed or deposited to cover the gate layer GTL and the light emitting element ED. The interlayer insulating layer ILD may be formed on the entire surface of the substrate SUB. The interlayer insulating layer ILD may completely fix the light emitting element ED in place. In other words, the light emitting element ED may be preliminarily fixed on the pixel electrode ELT by the adhesive layer PST, and secondarily fixed on the pixel electrode ELT by the interlayer insulating layer ILD.

[0157] like Fig.16 As shown in FIG. 1 , the first source metal layer SDL1 may be positioned on the interlayer insulating layer ILD.

[0158] Thereafter, a first via layer VIA1, a second source metal layer SDL2, a second via layer VIA2, a third source metal layer SDL3, and a passivation layer PVX may be sequentially formed. As a result, a Fig.11 Display device 10_2.

[0159] Fig.17 It is shown Figure 1 A cross-sectional view of one or more embodiments of a display device.

[0160] Reference Figure 1 , Fig.10 and Fig.17 , in addition to the arrangement of the pixel electrode ELT (and the corresponding arrangement of the light emitting element ED_1), Fig.17 The display device 10_3 may be constructed with Fig.10 The configuration of the display device 10_1 is substantially the same or similar. Therefore, repeated explanation thereof will be omitted.

[0161] In addition, because Fig.17 The pixel electrode ELT and the corresponding light emitting element ED_1 are respectively Fig.11 and Fig.10 Similar, so further explanation thereof will be omitted.

[0162] The pixel electrode ELT may be included in the gate layer GTL and electrically separated from the light emitting element ED_1 , and may function as a heat sink designed to dissipate heat generated from the light emitting element ED_1 to the outside.

[0163] In a display device according to an embodiment of the present disclosure, a pixel electrode is positioned at the same layer as one of the electrodes of a transistor. The light-emitting element may be temporarily fixed (or preliminarily fixed) to the pixel electrode by an adhesive layer. The insulating layer (or interlayer insulating layer) may directly cover the light-emitting element, thereby completely (or secondarily) fixing the light-emitting element in place. The light-emitting element may be fixed in place via an adhesive layer and an insulating layer only by a low-temperature process, without the need for a high-temperature process and / or a pressing process. Therefore, damage to components in the display device caused by a high-temperature process may be reduced or prevented, thereby improving the yield of the display device.

[0164] In addition, the insulating layer can directly cover the peripheral surface (or side surface) of the light-emitting element, so the surface defects of the light-emitting element can be reduced or minimized. Therefore, during the manufacturing process of the light-emitting element, there is no need to form a separate insulating layer (e.g., an insulating layer for reducing or minimizing surface defects) on the light-emitting element. Therefore, the manufacturing cost of the light-emitting element and the display device including the light-emitting element can be reduced.

[0165] The effects of the present disclosure are not limited to the foregoing, and other various effects are expected herein.

[0166] Although the spirit and scope of the present disclosure are described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and replacements may be made herein without departing from the scope of the present disclosure as defined by the claims, and their functional equivalents will be included herein.

Claims

1. A method for manufacturing a display device, the method comprising: forming a transistor and a pixel electrode on a substrate, wherein the pixel electrode and one of the electrodes of the transistor are in the same layer; forming an adhesive layer on the pixel electrode; placing a light emitting element on the adhesive layer; forming an insulating layer to cover the transistor, the pixel electrode and the light emitting element; as well as forming a first bridge pattern and a second bridge pattern, wherein the first bridge pattern electrically connects the transistor to a first end of the light emitting element, and the second bridge pattern electrically connects the transistor to a second end of the light emitting element, wherein the light emitting element is initially fixed by the adhesive layer, and Wherein, the light emitting element is fixed secondarily via the insulating layer.

2. The method according to claim 1, wherein: The light emitting element includes a first semiconductor layer, an emission layer, and a second semiconductor layer sequentially stacked from the second end to the first end, Wherein, the outer peripheral surface of each of the first semiconductor layer, the emission layer and the second semiconductor layer is covered by the insulating layer.

3. The method according to claim 2, wherein: The insulating layer includes an inorganic material.

4. The method according to claim 1, wherein: The first end of the light emitting element contacts the adhesive layer, Wherein, the first bridge pattern contacts the pixel electrode, and Wherein, the first end of the light emitting element is electrically connected to the pixel electrode through the adhesive layer.

5. The method according to claim 4, wherein: The adhesive layer comprises silver paste, The step of forming the adhesive layer includes: thermally curing the silver paste, and Wherein, the light emitting element is fixed to the pixel electrode through a solidified silver paste.

6. The method according to claim 5, wherein: The pixel electrode includes a reflective metal.

7. The method according to claim 1, further comprising: forming an organic layer and an inorganic layer on the insulating layer, A portion of the insulating layer in contact with the second end of the light emitting element is exposed from the organic layer and the inorganic layer.

8. The method according to claim 1, wherein: The transistor includes a gate electrode above a semiconductor pattern and a back gate electrode below the semiconductor pattern and overlapping the gate electrode, and Wherein, the pixel electrode and the back gate electrode are in the same layer.

9. The method according to claim 1, wherein: The transistor includes a gate electrode over the semiconductor pattern, and Wherein, the pixel electrode and the gate electrode are in the same layer.

10. The method according to claim 1, wherein: The adhesive layer includes a photoresist, and The pixel electrode is electrically separated from the bottom surface of the light emitting element and the transistor.

11. A display device, comprising: transistors, above the substrate; A pixel electrode, which is in the same layer as one of the electrodes of the transistor; an adhesive layer, above the pixel electrode; a light emitting element, which is above the adhesive layer and includes a first semiconductor layer, an emission layer, and a second semiconductor layer sequentially stacked from the second end to the first end; an insulating layer covering the transistor, the pixel electrode and the light emitting element, and covering the outer peripheral surfaces of the first semiconductor layer, the emission layer and the second semiconductor layer; a first bridge pattern, which is above the insulating layer and electrically connects the transistor to the first end of the light emitting element; as well as The second bridge pattern is over the insulating layer and electrically connected to the second end of the light emitting element.

12. The display device according to claim 11, wherein: The first bridge pattern contacts the pixel electrode, and The first end of the light emitting element contacts the adhesive layer to be electrically connected to the pixel electrode.

13. The display device according to claim 12, wherein: The adhesive layer includes silver paste, and The light emitting element is fixed to the pixel electrode by curing the silver paste.

14. The display device according to claim 13, wherein: The pixel electrode includes a reflective metal.

15. The display device according to claim 11, further comprising: an organic layer and an inorganic layer, sequentially on the insulating layer, A portion of the insulating layer in contact with the second end of the light emitting element is exposed from the organic layer and the inorganic layer.

16. The display device according to claim 11, wherein: The transistor includes a gate electrode above a semiconductor pattern and a back gate electrode below the semiconductor pattern and overlapping the gate electrode, and Wherein, the pixel electrode and the back gate electrode are in the same layer.

17. The display device according to claim 11, wherein: The transistor includes a gate electrode on a semiconductor pattern, and Wherein, the pixel electrode and the gate electrode are in the same layer.

18. The display device according to claim 11, wherein: The adhesive layer includes photoresist.

19. The display device according to claim 18, wherein: The pixel electrode is electrically separated from a bottom surface of the light emitting element.

20. The display device according to claim 11, wherein: The light emitting element includes a flip chip type micro light emitting diode.

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