A dynamic parameter test circuit and test method for wafer

Abstract

The present disclosure provides a dynamic parameter test circuit and a test method for a wafer, wherein the test circuit may include: a power module, a routing device, an energy storage module, a companion test device, a test module and a device under test, wherein the power module is used to provide a current signal for the test circuit; the energy storage module is used to store the current signal; the routing device is used to transmit the current signal to the device under test via the energy storage module, or transmit the current signal to the device under test via the companion test device and the energy storage module; the companion test device, in a first working state, transmits the current signal back to the power module via the energy storage module and the device under test, or transmits the current signal back to the power module via the energy storage module; in a second working state, transmits the current signal back to the power module via the energy storage module, or transmits the current signal back to the power module via the energy storage module and the device under test; the test module is used to obtain the voltage and current of the device under test to test the device under test.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor characteristic testing, and in particular to a dynamic parameter testing circuit and testing method for a wafer. Background Art

[0002] At present, power semiconductor devices mainly include Metal Oxide Semiconductor Field Effect Transistor (MOSFET), bipolar transistor (BJT), diode (DIODE), SiC field effect transistor, GaN field effect transistor, insulated gate bipolar transistor (IGBT). In order to ensure the effective use of power semiconductor devices in power electronic systems, it is necessary to pre-test the intermediate products of the power semiconductor devices, i.e. wafers, to eliminate failed devices so that qualified devices can be used for subsequent packaging processes.

[0003] With the development of technological requirements, a large number of bare chips are used for the assembly of power switch modules, which requires that the DC parameters and AC parameters of the bare chip itself must meet the requirements of the power switch module. In order to improve the overall switching performance of the power switch module, it is necessary to perform matching tests on the DC parameters and AC parameters of the bare chip. However, there is a lack of corresponding testing means for the AC parameters of the wafer-level device under test, that is, the dynamic parameter test of the power semiconductor device, because the test of the dynamic parameters of the power semiconductor device requires that the stray inductance in the test main circuit is extremely small, generally required to be at least less than 50nH, otherwise the stray inductance will cause a large current, resulting in a high voltage spike generated by the high-speed switch, and the voltage spike will destroy the accuracy of the dynamic parameter test data and also pose a threat to the safety of the power semiconductor device. Summary of the invention

[0004] In view of this, the present disclosure hopes to provide a dynamic parameter test circuit and test method for a wafer, which can reduce the influence of stray inductance in the test circuit, improve the accuracy and reliability of dynamic parameter testing of the device under test, and ensure the safety of the device under test.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, the present disclosure provides a dynamic parameter test circuit for a wafer, the test circuit comprising: a power module, a path selector, an energy storage module, a companion test device, a test module and a device under test, wherein:

[0007] The power supply module is used to provide a current signal for the test circuit;

[0008] The energy storage module is used to store the current signal;

[0009] The router is used to transmit the current signal to the device under test via the energy storage module, or to transmit the current signal to the device under test via the companion device and the energy storage module;

[0010] The accompanying test device has a working state including a first working state and a second working state. In the first working state, the current signal is transmitted back to the power module via the energy storage module and the device under test, or the current signal is transmitted back to the power module via the energy storage module; in the second working state, the current signal is transmitted back to the power module via the energy storage module, or the current signal is transmitted back to the power module via the energy storage module and the device under test;

[0011] The test module is used to obtain the voltage and current of the device under test to test the device under test.

[0012] In a second aspect, the present disclosure provides a method for testing dynamic parameters of a wafer, the testing method being applied to the test circuit described in the first aspect, the testing method comprising:

[0013] Determine the driving signal according to the parameters to be tested;

[0014] Controlling the working states of the device under test and the accompanying device under test according to the driving signal, and obtaining the voltage and current of the device under test corresponding to the parameters to be tested;

[0015] The parameters to be tested are determined according to the voltage and current of the device under test, wherein the parameters to be tested include switching parameters of the wafer and parameters of a reverse recovery process.

[0016] The present disclosure provides a dynamic parameter test circuit and test method for a wafer. When testing the dynamic parameters of the wafer, the setting of the energy storage module allows for rapid release and recovery of energy, which improves the efficiency of the test in test scenarios where the device under test needs to be frequently switched on and off. More test configuration options are provided through different working states of the selector and the accompanying test device, so that the test circuit can adapt to different test requirements and conditions to accurately control the flow direction of the current signal. By controlling the precise path of the current signal, the error in the test process is reduced and the accuracy of the test results is improved. In addition, by accurately controlling the voltage and current, the dynamic parameter test of the wafer can be achieved without connecting a line between the wafer stage of the device under test and the energy storage module, which significantly reduces the influence of stray inductance in the test circuit, and can effectively avoid excessive voltage or current shocks to the device under test, thereby protecting the device under test from damage and ensuring the safety of the device under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a standard double pulse test circuit for dynamic parameter testing of a wafer;

[0018] Figure 2 This is a working principle diagram of a double-pulse dynamic parameter test;

[0019] Figure 3 This is a typical waveform diagram of a switch parameter test;

[0020] Figure 4 A schematic diagram of the module composition of a dynamic parameter test circuit for a wafer provided by the present disclosure;

[0021] Figure 5 A schematic diagram of the composition of a device under test provided by the present disclosure;

[0022] Figure 6 A schematic diagram of another device under test provided by the present disclosure;

[0023] Figure 7 A schematic diagram of an integration method of a main test device and a set of auxiliary test devices in a device under test provided by the present disclosure;

[0024] Figure 8 A schematic diagram of the composition of a companion test device provided by the present disclosure;

[0025] Fig. 9 A schematic diagram of the components of a test module and a controller provided by the present disclosure;

[0026] Fig.10 A schematic diagram of the composition of an energy storage module provided by the present disclosure;

[0027] Fig.11 A schematic diagram of the composition of a power module provided by the present disclosure;

[0028] Fig.12 A schematic diagram of the composition of a router provided by the present disclosure;

[0029] Fig.13 A schematic diagram of current signal flow for a switch parameter test of a wafer provided by the present disclosure;

[0030] Fig.14 A schematic diagram of current signal flow for another wafer switch parameter test provided by the present disclosure;

[0031] Fig.15 A waveform diagram of a switch parameter test provided by the present disclosure;

[0032] Fig.16A schematic diagram of current signal flow for parameter testing of a wafer reverse recovery process provided by the present disclosure;

[0033] Fig.17 A schematic diagram of current signal flow for parameter testing of another wafer reverse recovery process provided by the present disclosure;

[0034] Fig.18 A waveform diagram of a parameter test of a reverse recovery process of a device under test provided by the present disclosure;

[0035] Fig.19 A connection diagram of a sampling resistor provided by the present invention. DETAILED DESCRIPTION

[0036] In order to more clearly illustrate the technical solutions in the present disclosure or the prior art, the technical solutions in the present disclosure will be clearly and completely described below in conjunction with the drawings in the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0037] The terms "first" and "second" in this disclosure are used for descriptive purposes only and are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations, nor can they be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0038] See also Figure 1, which shows a schematic diagram of a standard double-pulse test circuit for dynamic parameter testing of a wafer, wherein K1 is a first switch, K2 is a second switch, C1 is a capacitor array arranged in parallel, L1 is a freewheeling inductor, RS is a sampling resistor, a first transistor Q1 is a device under test, and a third transistor Q3 is a companion device. The gate (Gate) of the first transistor Q1 controls the first transistor Q1 to be in different working states by responding to a pulse signal from an external controller. The drain (Drain) of the first transistor Q1 constitutes a semiconductor substrate, which is connected to the source (Source) of the third transistor Q3 through a wafer carrier and a cable. The source of the first transistor Q1 is connected to the second end of the capacitor array C1 through the sampling resistor RS. A special probe can be designed for this connection to minimize the distance from the probe to the second end of the capacitor array C1 to reduce the influence of stray inductance. The freewheeling inductor L1 and the third transistor Q3 are arranged in parallel, the first end of the third transistor Q3 and the first end of the freewheeling inductor L1 are connected to the first end of the capacitor array C1 through the first switch K1, the second end of the freewheeling inductor L1 and the second end of the third transistor Q3 are connected to the wafer stage, and the sampling resistor RS is connected to the source of the first transistor Q1 through a probe.

[0039] Combination Figure 1 The test circuit shown is shown in Figure 2 , which shows a working principle diagram of a dual pulse dynamic parameter test. Specifically, the dynamic parameter test of the wafer includes at least a switch parameter test, a diode reverse recovery process parameter test, and a short circuit parameter test. The present disclosure takes the test of the switch parameter and the diode reverse recovery process parameter as an example. It can be understood that the dynamic parameter test of the wafer is the dynamic parameter test of the device under test. Figure 1 In the test circuit shown in the figure, the switch parameter test is to apply two short pulse signals to the first transistor Q1 to simulate the fast switching process of the device under test in the actual circuit, and at the same time use the high-speed oscilloscope G2 to monitor and record the key dynamic parameters of the device under test during the switching process, such as Figure 3 The turn-on delay time Ton, turn-off delay time Toff, rise time Tr, fall time Tf, turn-on time Tdon and turn-off time Tdoff shown in the figure can evaluate the dynamic performance of the switching performance and transient behavior of the device under test.

[0040] The present disclosure takes a MOS tube as an example of a device under test. The MOS tube can be Si-MOS or SiC-MOS. Its working state includes an on state and an off state. Applying two short pulse signals is a gate voltage pulse. Figure 2In the test circuit shown, the first switch K1 is closed and the second switch K2 is open. The third transistor Q3 is generally selected from the same MOS tube as the first transistor Q1 and both have built-in body diodes. In this test circuit, the third transistor Q3 is always in the off state, and only uses its internal parasitic anti-parallel body diode as a freewheeling diode. The Power-IGBT is a protection switch. When the first transistor Q1 is in an abnormal state such as a short circuit, the entire main current loop is promptly shut down to avoid accidents such as tube explosion. A high-speed oscilloscope G2 with at least 3 channels monitors the gate-source voltage (VGS), drain-source voltage (VDS) and drain-source current (IDS) of the first transistor Q1 during the test.

[0041] Before testing the switching parameters of the wafer, charge the capacitor array C1 to the rated voltage. Figure 2 The test circuit shown in the figure provides energy. A high-level pulse, namely the first pulse, which can also be called the turn-on pulse, is applied to the gate of the MOS tube through an external power supply, so that it is quickly turned on from the cut-off state, and the conduction duration is T1. Figure 3 As shown, at this time, a conductive channel is formed between the drain and source of the MOS tube, and the current signal begins to flow through the first transistor Q1. After the first transistor Q1 is turned on, the gate voltage is maintained so that the current flows between the drain and the source, simulating the behavior of the first transistor Q1 in the on state. After a certain period of time, the gate voltage is reduced, that is, a second pulse is applied, which can also be called a turn-off pulse. The turn-off duration is T2, so that the first transistor Q1 is quickly turned off from the on state, and the current flows through the body diode or other freewheeling path built into the first transistor Q1. The gate voltage is suddenly increased, and the turn-on duration of the first transistor Q1 is T3. At the end of the T1 and T3 stages, it can be used to test the transient process of the first transistor Q1 turning off and its dynamic parameters. At the end of the T2 stage, it can be used to test the transient process of the first transistor Q1 turning on and its dynamic parameters.

[0042] During the entire test process, a high-speed oscilloscope G2 was used to monitor the Figure 3 The gate-source voltage (VGS) and drain-source current (IDS) shown in the figure are used to measure the switching parameters of the first transistor Q1. By analyzing the waveform captured by the high-speed oscilloscope G2, the transient behavior of the first transistor Q1 during the switching process can be obtained, including the rate of change of voltage and current as well as voltage spikes and oscillations.

[0043] In some examples, the parameters of the diode reverse recovery process are tested by first forward-conducting the body diode built into the first transistor Q1, then suddenly cutting off the current and applying a reverse voltage within a specified time, and measuring the reverse recovery time Trr, reverse recovery current Irr, and reverse recovery charge Qrr required for the body diode to recover from the forward conduction state to the reverse blocking state. These parameters characterize the dynamic characteristics and efficiency of the body diode in fast switching applications. Specifically, combined with Figure 2 The test schematic diagram shown and Figure 3 As shown in the waveform diagram, during the test process, the first transistor Q1 is always in the cut-off state, and the test process is controlled by the switching pulse of the third transistor Q3.

[0044] For the above example, in detail, the test process of the parameters of the diode reverse recovery process is: energy is stored on the capacitor array C1 to the rated voltage, the gate-source voltage (VGS) of the third transistor Q3 suddenly increases, the third transistor Q3 is turned on for a duration of T1, and the current signal in the test circuit flows to the third transistor Q3, the freewheeling inductor L1, and the second switch K2, and the current slope rises to ID Point ID1, at this time, the body diode of the first transistor Q1 is added with the reverse voltage drain-source voltage (VDS); the gate-source voltage (VGS) of the third transistor Q3 suddenly changes to low, and the third transistor Q3 is suddenly turned off. At this time, the current signal in the test circuit flows to the body diode in the first transistor Q1, the freewheeling inductor L1, and the second switch K2, and the duration is T2; the gate-source voltage (VGS) of the third transistor Q3 suddenly changes to high, and the third transistor Q3 is turned on for a duration of T3. The current signal in the test circuit flows to the third transistor Q3, the freewheeling inductor L1, and the second switch K2, and the current slope rises from slightly lower than ID1 to ID2; then, the gate-source voltage (VGS) of the third transistor Q3 becomes low, and the current signal in the test circuit flows to the first transistor Q1, the freewheeling inductor L1, and the second switch K2, and the current slope gradually decreases to 0; finally, the Power-IGBT is turned off and the test is completed. At the end of the T2 phase, the parameters of the reverse recovery process of the built-in body diode of the first transistor Q1, such as the reverse recovery time Trr, the reverse recovery current Irr and the reverse recovery charge Qrr, can be tested, and the rate of current change can be controlled by controlling the turn-off speed of the third transistor Q3.

[0045] In the present disclosure, for wafer testing equipment, a wafer stage refers to a mechanical component used to fix and move wafers. It usually refers to a part that can clamp the wafer, and may include a vacuum suction cup or other types of clamping structures to ensure that the wafer is stably fixed on the wafer stage during the test. In some examples, the wafer stage is movable, for example, translational or rotational, so that different positions on the wafer can be sent to the test area in sequence. This design enables the test equipment to test multiple chip units (Die) on the wafer within one test cycle. Therefore, if Figure 1 The wafer stage in the test circuit shown in is a moving part, so the cable cannot be shortened directly. Therefore, the test circuit between the wafer stage and the cable is difficult to optimize and the stray inductance in the test circuit far exceeds the test requirements. This is because the parasitic inductance in the test circuit is large, which generates voltage spikes, causing serious oscillations in the drive waveform, further affecting the performance of the power semiconductor device, making the waveform data inaccurate, and making the dynamic parameter test of the wafer more difficult. In addition, it will cause overvoltage damage to the power semiconductor device and cause safety hazards.

[0046] Based on this, the present disclosure provides a test circuit for dynamic parameters in the test phase between photolithography and packaging during wafer manufacturing, which is used to test the dynamic parameters of multiple MOS tubes without electrodes on the wafer. The MOS tubes are arranged in a common drain configuration, so that the test circuit can effectively evaluate the performance of the MOS tubes under actual working conditions and provide important electrical characteristic data for subsequent packaging and application. Figure 4 , which shows a schematic diagram of the module composition of a dynamic parameter test circuit 10 of a wafer provided by the present disclosure, the test circuit 10 may include: a power module 11, a path selector 12, an energy storage module 13, a companion test device 14, a test module 15 and a device under test 16, wherein the power module 11 is used to provide a current signal for the test circuit 10; the energy storage module 13 is used to store the current signal; the path selector 12 is used to transmit the current signal to the device under test 16 via the energy storage module 13, or transmit the current signal to the device under test 16 via the companion test device 14 and the energy storage module 13 ; The working state of the tested device 14 includes a first working state and a second working state. In the first working state, the current signal is transmitted back to the power module 11 via the energy storage module 13 and the tested device 16, or the current signal is transmitted back to the power module 11 via the energy storage module 13; in the second working state, the current signal is transmitted back to the power module 11 via the energy storage module 13, or the current signal is transmitted back to the power module 11 via the energy storage module 13 and the tested device 16; the test module 15 is used to obtain the voltage and current of the tested device 16 to test the tested device 16.

[0047] According to the description of the above scheme, when the dynamic parameters of the wafer are tested, the setting of the energy storage module 13 allows for rapid release and recovery of energy, which improves the efficiency of the test in the test scenario where the device under test 16 needs to be frequently switched on and off. More test configuration options are provided by the different working states of the selector 12 and the accompanying device under test 14, so that the test circuit 10 can adapt to different test requirements and conditions to accurately control the flow direction of the current signal. By controlling the precise path of the current signal, the error in the test process is reduced and the accuracy of the test results is improved. In addition, by accurately controlling the voltage and current, the dynamic parameter test of the wafer can be realized without connecting the line between the wafer carrier of the device under test and the energy storage module, which significantly reduces the influence of stray inductance in the test circuit 10, and can effectively avoid excessive voltage or current shocks to the device under test 16, thereby protecting the device under test 16 from damage and ensuring the safety of the device under test 16.

[0048] For some examples, see Figure 5 The device under test 16 may include a main test device and an auxiliary test device set arranged in series, wherein the auxiliary test device set includes one or more auxiliary test devices adjacent to and arranged in parallel with the main test device.

[0049] For example, when there is one auxiliary test device, the auxiliary test device is connected in series with the main test device. When there are multiple auxiliary test devices, the multiple auxiliary test devices are first connected in parallel and then connected in series with the main test device.

[0050] For some examples, see Figure 6 The main test device may include a first transistor Q1, wherein the first end of the first transistor Q1 is connected to the second end of the power supply module 11, the second end is connected to the second end of at least one auxiliary test device in the auxiliary test device set, and the first control end is used to control the first transistor Q1 to enter the first working state or the second working state; the auxiliary test device may include a second transistor Q2, wherein the first end of the second transistor Q2 is connected to the first end of the accompanying test device 14, the second end is connected to the second end of the first transistor Q1, and the second control end is used to control the second transistor Q2 to enter a continuously turned-on state.

[0051] Combination Figure 5 and Figure 6 The components of the device under test 16 are shown in FIG. Figure 7, the main test device and the auxiliary test device are integrated on the same semiconductor substrate. It should be noted that the drains of the first transistor Q1 and the second transistor Q2 are integrated on the same semiconductor substrate, which can be used as part of the transistor drain and has good conductivity, and the drain current can flow through the semiconductor substrate. The source of the first transistor Q1 is connected to the semiconductor substrate as shown in the figure. Figure 7 The probe indicated by the arrow in FIG. 1 is connected to the second end of the power module 11 . It is necessary to reduce the distance from the probe to the second end of the power module 11 as much as possible to reduce the influence of stray inductance.

[0052] In some examples, for dynamic parameter testing of wafers, both the tested die and the auxiliary die need to be contacted by the probe at the same time. Since each adjacent chip unit die in the wafer needs to be tested, each die will be probed once as the tested die and the auxiliary die. In order to ensure the reliability of the pressure welding process, it is generally not desirable to have too many needle marks on the wafer, so the number of probes should be reduced as much as possible, preferably only once for each die.

[0053] Based on this, for Figure 7 As shown in the figure, the selection of the first transistor Q1 and its adjacent MOS tube, i.e., the second transistor Q2, in some possible implementations, the first transistor Q1 is used as the die to be tested, and the second transistor Q2 is used as the auxiliary die. The needle positions of the die to be tested and the auxiliary die are set to be exactly the same, so that each repeated needle insertion will be at the same position and no needle marks will be added. In some examples, two auxiliary dies are selected at the adjacent position of the die to be tested, and one can be selected on each of the left and right sides of the die to be tested, or one can be selected on each of the upper and lower sides of the die to be tested. In this implementation, the wafer is tested once, and each die is needled 3 times. In some examples, three to four auxiliary dies can also be selected at the adjacent position of the die to be tested, and one auxiliary die can be selected on each of the upper, lower, left and right sides of the die to be tested, and the main circuit of the auxiliary die is connected in parallel, so that as long as any one of the three to four auxiliary dies can be turned on normally, the dynamic parameters of the die to be tested can be tested normally, and the three to four auxiliary dies and the probe circuit of the die to be tested can form a good surround, which can reduce the influence of stray inductance again. In this case, the wafer is tested once and each die is pierced with needles 4 to 5 times.

[0054] In some possible implementations, in order to increase the complexity of the probe card design, the tested die and the auxiliary die can be interchanged during the same needle insertion process, and two dies are tested at a time, and the two dies are adjacent particles. For example, multiple dies are selected for dynamic testing together, and multiple dies can be auxiliary dies to each other during the test process. Taking the example of selecting four auxiliary dies from the upper left, upper right, lower left, and lower right of the tested die for dynamic testing together, the four auxiliary dies are arranged in a grid, which can form a dynamic test circuit. For the first test, the needle is not lifted, and the circuit is switched on the probe card. The test of other dies is carried out in the same way. In this way, the needle is inserted once, the wafer stage moves once, and all four dies are tested for dynamic parameters. Among the four auxiliary dies, as long as any two are qualified dies, the dynamic parameters can be tested without omission. At the edge of the wafer, most of the dies can also be tested normally. In this way, not only are the needles inserted less, but the number of times the wafer stage moves is less, which can improve the test efficiency.

[0055] For some examples, see Figure 8 The test device 14 may include a third transistor Q3, wherein a first end of the third transistor Q3 is connected to a first end of the second transistor Q2 in the test device 16, a second end is connected to a first end of the power module 11, and a third control end is used to control the third transistor Q3 to enter a first working state or a second working state.

[0056] for Figure 8 In the example shown, specifically, the first transistor Q1, the second transistor Q2, and the third transistor Q3 can be transistors of the same type, and can be N-channel transistors or P-channel transistors, and all have built-in body diodes for conducting current when the transistor is in the second working state. The first terminal is the source of the transistor, the second terminal is the drain of the transistor, and the first control terminal, the second control terminal, and the third control terminal are all gates of the transistor. The first working state is the on state, and the second working state is the off state. The conversion of the on state and the off state of the N-channel transistor and the P-channel transistor is controlled by the controller changing the gate voltage relative to the source voltage.

[0057] For example, see Fig. 9 , high-level or low-level driving signals are applied to the first control terminal, the second control terminal and the third control terminal through the first controller, the second controller and the third controller respectively to control the first transistor Q1, the second transistor Q2 and the third transistor Q3 to be in the on state or the off state.

[0058] The present disclosure takes the first transistor Q1 as an example to specifically explain the control principle of controlling the on state or off state of the first transistor Q1 by the first controller. The first transistor Q1 is an N-channel transistor, and its control principle is: when the gate-source voltage (VGS) of the first transistor Q1 is greater than or equal to the threshold voltage (Vth), that is, when the first controller outputs a high-level drive signal, the first transistor Q1 is in the on state. Specifically, the first controller provides sufficient positive voltage to the gate of the first transistor Q1, so that VGS ≥ Vth, and there is sufficient positive voltage between the gate and the source to form a conductive channel, allowing the current signal to flow from the source to the drain, thereby turning on the first transistor Q1. When the gate-source voltage (VGS) is less than the threshold voltage (Vth), that is, when the first controller outputs a low-level drive signal, the first transistor Q1 enters the off state. At this time, there is not enough voltage to form a conductive channel, so no current signal can flow from the source to the drain. The first controller keeps the gate voltage at a value lower than Vth, thereby turning off the first transistor Q1.

[0059] Exemplarily, the first transistor Q1 is a P-channel transistor, and its control principle is: when the gate-source voltage (VGS) of the first transistor Q1 is less than or equal to a negative threshold voltage (-Vth), that is, when the first controller outputs a high-level drive signal, the first transistor Q1 is turned on. Specifically, the first controller provides enough negative voltage to the gate so that VGS≤-Vth, and there is enough negative voltage between the gate and the source to form a conductive channel, allowing the current signal to flow from the source to the drain, thereby turning on the first transistor Q1. When the gate-source voltage (VGS) is greater than the negative threshold voltage (-Vth), that is, when the first controller outputs a low-level drive signal, the first transistor Q1 enters the cut-off state. At this time, there is not enough negative voltage to form a conductive channel, so no current signal can flow from the source to the drain. The first controller keeps the gate voltage at a value higher than -Vth, thereby turning off the first transistor Q1.

[0060] In some examples, the first controller, the second controller, and the third controller may include a microcontroller, a transistor driving circuit, an operational amplifier, or other electronic circuits, and provide appropriate voltage signals as needed to control the on and off states of the transistors. This control method enables the transistors to be used as switches in digital circuits and as amplifiers or switches in analog circuits.

[0061] In some examples, the test module 15 may include a high-speed oscilloscope G2 for measuring the voltage and current of the device under test 16 .

[0062] For some examples, see Fig.10 The energy storage module 13 is used to store the current signal provided by the power module 11 or discharge to the device under test 16.

[0063] For example, Fig.10 As shown, the energy storage module 13 may include a freewheeling inductor L1.

[0064] For some examples, see Fig.11 The power module 11 may include a capacitor array C1 arranged in parallel, wherein a first end of the capacitor array C1 is connected to the energy storage module 13 through the path selector 12 , and a second end is connected to the device under test 16 .

[0065] Exemplarily, the power module 11 may also include a power management circuit, a pulse generator or a battery simulator.

[0066] For some examples, see Fig.12 The selector 12 may include a first switch K1 and a second switch K2, whose states include a closed state and an open state. The first switch K1 and the second switch K2 are arranged in parallel, and only one of the first switch K1 and the second switch K2 is in a closed state.

[0067] In some examples, the first switch K1 can be used to transmit the current signal provided by the power supply module 11 back to the power supply module 11 via the energy storage module 13, the auxiliary test device set in the device under test 16, and the main test device when the companion test device 14 is in the cut-off state. It can also be used to transmit the current signal back to the power supply module 11 via the energy storage module 13, the auxiliary test device set in the device under test 16, and the main test device when the companion test device 14 is in the cut-off state.

[0068] The second switch K2 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the energy storage module 13 when the companion test device 14 is in the on state, and can also be used to transmit the current signal provided by the energy storage module 13 back to the energy storage module 13 via the main test device and the auxiliary test device set in the device under test 16 in sequence when the companion test device 14 is in the off state.

[0069] according to Figure 5 As shown in the description, the device under test 16 may include a main test device and an auxiliary test device set, and the auxiliary test device set includes one or more auxiliary test devices adjacent to and arranged in parallel with the main test device. In the following, the main test device is a first transistor Q1, the auxiliary test device is a second transistor Q2, the accompanying test device 14 is a third transistor Q3, and the first transistor Q1, the second transistor Q2 and the third transistor Q3 are all N-channel transistors, and the number of the second transistor Q2 is one for example description.

[0070] Optionally, the switch parameters of the wafer may include a first switch parameter and a second switch parameter. Accordingly, when testing the first switch parameter of the device under test 16, the first switch K1 is in a closed state, and the companion device 14 is in a cut-off state when receiving the low-level drive signal of the third controller, and the first switch K1 can be used to transmit the current signal provided by the power module 11 through the first switch K1, and then through the energy storage module 13, the auxiliary test device set in the device under test 16, and the main test device back to the power module 11. When testing the second switch parameter of the device under test 16, the first switch K1 can also be used to transmit the current signal provided by the power module 11 through the energy storage module 13, the auxiliary test device set in the device under test 16, and the main test device back to the power module 11.

[0071] Optionally, the parameter test of the reverse recovery process of the wafer may include a first stage and a second stage, namely, a charging stage of the energy storage module 13 and a discharging stage of the energy storage module 13. In the first stage of testing the parameters of the reverse recovery process of the device under test 16, the second switch K2 is in a closed state and the accompanying device under test 14 receives a high-level driving signal from the third controller and is in a conducting state. The second switch K2 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the energy storage module 13. In the second stage of testing the parameters of the reverse recovery process of the device under test 16, the second switch K2 is in a closed state and the accompanying device under test 14 receives a low-level driving signal from the third controller and is in an off state. The second switch K2 can also be used to transmit the current signal provided by the power module 11 back to the power module 11 via the energy storage module 13, the main test device in the device under test 16, and the auxiliary test device set. When the charging stage of the energy storage module 13 is entered again from the discharging stage of the energy storage module 13, the parameters of the reverse recovery process of the device under test 16 are tested.

[0072] For the above example, in the test circuit 10 in the present disclosure, when testing the switching parameters of the device under test 16, at least one auxiliary test device in the auxiliary test device set is in the on state, the first switch K1 is closed, the main test device is in the on state, and the companion test device 14 is in the off state, so that the current signal provided by the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence via the first switch K1, the energy storage module 13, at least one auxiliary test device in the auxiliary test device set, and the main test device.

[0073] For the above examples, specifically, in the present disclosure, Fig.13As shown, when testing the first switch parameter of the device under test 16, the second controller outputs a high-level drive signal to control the second transistor Q2 to be in a continuous on state, and the first controller outputs a high-level drive signal to control the first transistor Q1 to be in an on state. At this time, the current can flow freely in both directions, which provides a feasible method for using the adjacent chip unit, that is, the second transistor Q2 to assist in testing the switch parameters. The third controller outputs a low-level drive signal to control the third transistor Q3 to be in an off state, thus forming a test circuit 10 for testing the switch parameters of the wafer. Fig.13 The arrows of the test circuit 10 shown describe the Fig.15 The current signal provided by the power module 11 is sequentially transmitted back to the power module 11 via the first switch K1, the energy storage module 13, at least one second transistor Q2 in the auxiliary test device set, and the first transistor Q1. Fig.13 In fact, the power module 11 discharges to the energy storage module 13, and the current slope of the energy storage module 13 rises from 0 to the set current limit value I1 in the T1 stage. At this time, the gate-source voltage, drain-source voltage of the first transistor Q1 in the device under test 16 and the current value in the test circuit are tested using a high-speed oscilloscope G2, an ammeter or a voltmeter.

[0074] In some examples, when testing the switching parameters of the device under test 16, the first switch K1 is closed, the main test device is in the off state, at least one auxiliary test device in the auxiliary test device set is in the on state, and the companion test device 14 is in the off state, so that the current signal provided by the power supply module 11 is transmitted back to the power supply module 11 via the first switch K1, the energy storage module 13, and the companion test device 14 in sequence.

[0075] For the above examples, specifically, see Fig.14 , which shows a current signal flow diagram of another wafer switch parameter test provided by the present disclosure. When testing the second switch parameter of the device under test 16, as shown in FIG. Fig.14 The arrows in the figure describe Fig.15 At this time, the first switch K1 is closed, and the first controller and the third controller respectively output low-level drive signals to control the first transistor Q1 and the third transistor Q3 to be in the off state, and the second controller outputs a high-level drive signal to control the second transistor Q2 to be in the continuous on state. The current signal provided by the power module 11 is transmitted back to the power module 11 via the first switch K1, the energy storage module 13, and the third transistor Q3 in sequence. Fig.14 In the process, the energy storage module 13 is actually discharging, and the current on the energy storage module 13 remains basically unchanged in the T2 stage.

[0076] In some examples, Fig.15 In the T3 phase, the current signal of the test circuit 10 flows into Fig.13 At this time, the current in the test circuit 10 does not start from 0, but starts from the set current limit value I1 and increases to I2. After the T3 stage ends, it enters the Fig.14 The current signal flows in the direction indicated by the arrow in the middle. The first transistor Q1 in the device under test 16 enters the cut-off state, and the current on the energy storage module 13 slowly decreases to 0.

[0077] It should be noted that, through Fig.13 and Fig.14 The test circuit 10 shown in the figure performs data verification after obtaining the first switch parameter and the second switch parameter to ensure that there are no errors or abnormal values. According to the test requirements and standards, the final switch parameter is obtained by calculating statistical parameters such as the average value, maximum value, and minimum value based on the first switch parameter and the second switch parameter.

[0078] Based on the above examples, Figure 3 and Fig.15 From the waveform diagram of the switching parameters shown, it can be seen that Fig.15 Compare Figure 3 The drain-source voltage on the first transistor Q1 and the current on the freewheeling inductor L1 are added to more clearly describe the change process of voltage and current, but the switching parameters such as the turn-on delay time Ton, the turn-off delay time Toff, the rise time Tr, the fall time Tf, the turn-on time Tdon and the turn-off time Tdoff are not described, wherein VGS is the change of the gate-source voltage of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; IDS is the change of the drain-source current of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; VDS is the change of the drain-source voltage of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; L1 (CURRENT) is the estimated waveform of the current change flowing through the freewheeling inductor L1.

[0079] Based on the above description, Fig.13 and Fig.14 As shown in the flow path of the current signal of the switch parameter test, the non-overlapping part of the current loop through which the main current in the test circuit 10 flows has been greatly reduced, and the non-overlapping part eliminates the circuit of the carrier stage and the cable connection part, thereby greatly reducing the influence of stray inductance of the test circuit.

[0080] It should be noted that the third transistor Q3 in the above-mentioned test circuit 10 is always in the off state, and only the parasitic anti-parallel body diode inside it is used as a freewheeling diode. The body diode can also be called a parasitic diode, which is naturally formed due to the manufacturing process of the MOS tube. It is located between the drain and the substrate of the MOS tube and is a parasitic element inside the MOS tube. In an N-channel transistor, the body diode is formed by a PN junction between the source and the drain, while in a P-channel transistor, the body diode is formed by a PN junction between the drain and the source. Its main function is to provide a current path from the drain to the source when the MOS tube is turned off. When the gate drive signal of the MOS tube is removed and the MOS tube is turned off, if there is a voltage between the drain and the source, the body diode will be turned on, allowing the current signal to flow from the drain to the source in the N-channel transistor, thereby protecting the MOS tube from the influence of voltage spikes. In switch applications, the body diode acts as a freewheeling diode to maintain the current continuity in the inductive circuit. When the MOS tube is turned off during the switching process, the energy stored in the inductor circuit is released through the body diode to provide a circuit path, preventing the current from being suddenly interrupted and generating a high-level spike, thereby ensuring the continuity of the current in the test circuit 10, which is crucial for the accuracy of the test and the safety of the device. In some examples, a higher-speed diode can be connected in parallel to the third transistor Q3 to replace the role of the body diode.

[0081] In some examples, in the first stage of testing the parameters of the reverse recovery process of the device under test 16, the second switch K2 is closed, the main test device is in the off state, at least one auxiliary test device in the auxiliary test device set is in the on state, and the companion test device 14 is in the on state, so that the current signal provided by the power module 11 is transmitted back to the second end of the power module 11 via the companion test device 14, the energy storage module 13, and the second switch K2 in sequence.

[0082] For the above examples, specifically, see Fig.16 , which shows a schematic diagram of the current signal flow of a parameter test of the reverse recovery process of a wafer provided by the present disclosure. The first transistor Q1, the second transistor Q2 in the device under test 16 and the third transistor Q3 in the accompanying device under test 14 are all built with body diodes for freewheeling. It is necessary to test their dynamic parameters, that is, the parameters of the reverse recovery process, mainly including the reverse recovery time Trr, the reverse recovery current Irr and the reverse recovery charge Qrr. It should be noted that Fig.16 With the aforementioned Fig.13 The difference is that the second switch K2 is closed, the first switch K1 is disconnected, the first controller outputs a low-level drive signal to control the first transistor Q1 to be in the off state, the second controller outputs a high-level drive signal to control the second transistor Q2 to be in the continuous on state, and the third controller outputs a high-level drive signal to control the third transistor Q3 to be in the on state. Fig.16 The arrows shown in the figure describe Fig.18 The flow direction of the current signal in the T1 phase, the current signal provided by the power module 11 is transmitted back to the second end of the power module 11 through the third transistor Q3, the energy storage module 13, and the second switch K2.

[0083] It should be noted that in Fig.16 In fact, the power module 11 discharges to the energy storage module 13, that is, the charging stage of the energy storage module 13, so that the current slope on the energy storage module 13 rises from 0 to the set current limit value I1 in the T1 stage. The body diode in the first transistor Q1 in the device under test 16 is subjected to reverse voltage. At this time, the flow direction of the current signal does not pass through the first transistor Q1 in the device under test 16, so there is no need to test the gate-source voltage, drain-source voltage of the first transistor Q1 and the current value in the test circuit 10. Accordingly, the parameters in the reverse recovery process of the first transistor Q1 are not tested.

[0084] In some examples, in the second stage of testing the parameters of the reverse recovery process of the device under test 16, the energy storage module 13 is discharged, the second switch K2 is closed, the main test device is in the off state, at least one auxiliary test device in the auxiliary test device set is in the on state, and the companion test device 14 is in the off state, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 in sequence via the main test device and at least one auxiliary test device in the auxiliary test device set.

[0085] For the above examples, specifically, see Fig.17 , which shows a current signal flow diagram of another parameter test of the reverse recovery process of a wafer provided by the present disclosure, in the discharge phase of the energy storage module 13, when testing the parameters of the reverse recovery process of the device under test 16, such as Fig.17 The arrows shown in the figure describe Fig.18 At this time, the second switch K2 is closed, the first controller outputs a low-level drive signal to control the first transistor Q1 to be in the off state, the second controller outputs a high-level drive signal to control the second transistor Q2 to be in the on state, and the third controller outputs a low-level drive signal to control the third transistor Q3 to be in the off state. The current signal provided by the first end of the energy storage module 13 is transmitted from the first transistor Q1 and at least one second transistor Q2 in the auxiliary test device set back to the second end of the energy storage module 13. Fig.17 In fact, the energy storage module 13 is discharging, and the current on the energy storage module 13 remains basically unchanged in the T2 stage. At this time, the gate-source voltage, drain-source voltage of the first transistor Q1 and the current value in the test circuit 10 are tested using a high-speed oscilloscope G2, an ammeter or a voltmeter.

[0086] In some examples, such as Fig.18 The T3 stage, and then enter Fig.16 The current signal flows in the direction indicated by the arrow. At this time, the current of the energy storage module 13 does not start from 0, but starts from the current limit value I1 and increases to I2. The current on the first transistor Q1 in the device under test 16, that is, the current reversely conducted through the diode, quickly drops from the current limit value I1 to 0; the voltage drop between the drain and source of the first transistor Q1 in the device under test 16 quickly changes from -0.7V (diode forward voltage drop) to a high level. Because the body diode of the first transistor Q1 in the device under test 16 has a reverse recovery characteristic, when the reverse voltage is applied instantaneously, the current will not drop directly from the current limit value I1 to 0, but there will be a reverse overshoot, whose amplitude, that is, the reverse recovery current is Irr, and the time width of the overshoot, that is, the reverse recovery time is Trr. These parameters can be measured with a high-speed oscilloscope G2, and the condition di / dt of the current change rate is determined by the gate drive speed of the third transistor Q3, where di / dt represents the speed of the change of the current i with time t.

[0087] like Fig.18 As shown in the waveform diagram of the parameters of the reverse recovery process of the device under test 16, it can be seen that at the moment when the T2 stage ends and the T3 stage begins, the parameters of the reverse recovery process of the diode can be used to test, wherein VGS is the change in the gate-source voltage of the third transistor Q3; IDS is the change in the drain-source current of the first transistor Q1 in the device under test 16 tested by the high-speed oscilloscope G2 in the test module 15; VDS is the change in the drain-source voltage of the first transistor Q1 in the device under test 16 tested by the high-speed oscilloscope G2 in the test module 15; L1 (CURRENT) is the estimated waveform of the current change flowing through the energy storage module 13.

[0088] It should be noted that, through Fig.17 The test circuit 10 shown in the figure obtains the parameters of the reverse recovery process of the energy storage module 13 during the discharge phase, and then performs data verification to ensure that there are no errors or abnormal values. The final parameters of the reverse recovery process are obtained according to the test requirements and standards.

[0089] Based on the above description, Fig.16 and Fig.17 As shown in the path of the current signal, the non-overlapping part of the current signal flowing in the test circuit 10 has been greatly reduced, and the non-overlapping part eliminates the circuit of the carrier stage and the cable connection part, thereby greatly reducing the influence of the stray inductance of the test circuit 10.

[0090] For some examples, see Fig.19 The test circuit 10 may further include: a sampling resistor, a first end of which is connected to the second end of the power module 11 , and a second end of which is connected to the device under test 16 .

[0091] For example, the sampling resistor may be Fig.19 The sampling resistor RS is shown in FIG.

[0092] In the present disclosure, a dynamic parameter testing method for a wafer is also provided. The testing method is applied to the above-mentioned test circuit 10, and the testing method may include: determining a driving signal according to the parameters to be tested; controlling the working states of the device under test 16 and the accompanying device under test 14 in the test circuit 10 according to the driving signal, and obtaining the voltage and current of the device under test 16 corresponding to the parameters to be tested; determining the parameters to be tested according to the voltage and current of the device under test 16, wherein the parameters to be tested include the switching parameters of the wafer and the parameters of the reverse recovery process.

[0093] For the technical solution of the above-mentioned test method, a driver is used to generate an accurate driving signal, which can be a voltage pulse or a current pulse, to control the switching action of the device under test 16, the closing and opening of the selector 12 to select the current path, and transmit the current signal from the energy storage module 13 to the device under test 16, or reversely transmit it back to the power module 11 and the switching of the accompanying device under test 14 between the first working state and the second working state, so as to cooperate with the test of the device under test 16, provide the necessary current return path or simulate different load conditions. Under different working states of each device, the current, voltage and current direction of the device under test 16 are measured to obtain the switching parameters of the device under test 16 and the parameters of the reverse recovery process. This method can comprehensively evaluate the switching parameters of the device under test 16 and the parameters of the reverse recovery process, improve the accuracy and efficiency of the test, and protect the safety of the device under test 16, providing important data for device design and performance optimization.

[0094] For the above-mentioned test method, in some examples, the selector 12 may include a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal and a third drive signal. The test method may include: controlling the first switch K1 to be closed, and controlling the main test device in the device under test 16 to be in an on state through the first drive signal; controlling at least one auxiliary test device in the auxiliary test device set in the device under test 16 to be in a continuously on state through the second drive signal; controlling the accompanying test device 14 to be in an off state through the third drive signal, so that the current signal provided by the power module 11 is transmitted back to the second end of the power module 11 in sequence via the first switch K1, the energy storage module 13, at least one auxiliary test device in the auxiliary test device set, and the main test device; obtaining the changes in voltage and current of the device under test 16, and obtaining the switching parameters of the device under test 16 according to the changes in voltage and current of the device under test 16.

[0095] For the above-mentioned test method, in some examples, the selector 12 may include a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal and a third drive signal. The test method may include: controlling the first switch K1 to be closed, and controlling the main test device in the device under test 16 to be in an off state through the first drive signal; controlling at least one auxiliary test device in the auxiliary test device set in the device under test 16 to be in a continuously on state through the second drive signal; controlling the accompanying test device 14 to be in an off state through the third drive signal, so that the current signal provided by the power module 11 is transmitted back to the power module 11 via the first switch K1, the energy storage module 13, and the accompanying test device 14 in sequence; obtaining the changes in voltage and current of the device under test 16, and obtaining the switching parameters of the device under test 16 according to the changes in voltage and current of the device under test 16.

[0096] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal and a third drive signal. The test method may include: controlling the second switch K2 to be closed, and controlling the main test device in the device under test 16 to be in an off state through the first drive signal; controlling at least one auxiliary test device in the auxiliary test device set in the device under test 16 to be in a continuously on state through the second drive signal; and controlling the accompanying test device 14 to be in an on state through the third drive signal, so that the current signal provided by the power module 11 is transmitted back to the second end of the power module 11 via the accompanying test device 14, the energy storage module 13, and the second switch K2 in sequence.

[0097] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal and a third drive signal. The test method may include: controlling the second switch K2 to be closed, and controlling the main test device in the device under test 16 to be in an off state through the first drive signal; controlling at least one auxiliary test device in the auxiliary test device set in the device under test 16 to be in a continuously on state through the second drive signal; controlling the accompanying test device 14 to be in an off state through the third drive signal, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 via the main test device and at least one auxiliary test device in the auxiliary test device set in turn; obtaining the changes in voltage and current of the device under test 16, and obtaining the parameters of the reverse recovery process of the device under test 16 according to the changes in voltage and current of the device under test 16.

[0098] For details of the dynamic parameter test method of the above wafer, please refer to the above Fig.13 , 14 , 16 and 17 are not described in detail here.

[0099] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0100] The above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present disclosure should be covered by the protection scope of the present disclosure.

Claims

1. A dynamic parameter test circuit for a wafer, characterized in that: The wafer is in the testing stage between photolithography and packaging, the wafer includes a plurality of transistors, the drains of the plurality of transistors constitute the substrate of the wafer, the test circuit includes: a power module, a path selector, an energy storage module, a companion device, a test module and a device under test, wherein: The device under test includes a main test device and an auxiliary test device set, wherein the main test device is any one of the plurality of transistors, and the auxiliary test device set is one or more transistors adjacent to and arranged in parallel with the main test device; The power supply module is used to provide a current signal for the test circuit; The energy storage module is used to store the current signal; The router is used to transmit the current signal to the device under test via the energy storage module, or to transmit the current signal to the device under test via the companion device and the energy storage module; The accompanying test device has a working state including a first working state and a second working state; Wherein, when the companion test device is in the first working state, when the main test device is turned on, the current signal is transmitted back to the power module via the energy storage module and the auxiliary test device set, the substrate of the wafer, and the main test device; or when the main test device is turned off, the body diode of the companion test device and the path selector are used to form a loop with the energy storage module; or when the main test device is turned off, the current source signal stored in the energy storage module is transmitted back to the energy storage module via the body diode of the main test device and the auxiliary test device; When the accompanying test device is in the second working state, the accompanying test device is used to transmit the current signal to the energy storage module, and transmit the current source signal back to the power module via the energy storage module; The test module is used to obtain the voltage and current of the device under test to test the device under test.

2. The test circuit according to claim 1, characterized in that: The main test device comprises: A first transistor, a first end of which is connected to the second end of the power module, a second end of which is connected to the second end of at least one auxiliary test device in the auxiliary test device set, and a first control end for controlling the first transistor to enter a first working state or a second working state; The auxiliary test device comprises: The second transistor has a first end connected to the first end of the companion test device, a second end connected to the second end of the first transistor, and a second control end used to control the second transistor to enter a continuously conducting state.

3. The test circuit according to claim 2, characterized in that: The accompanying test device comprises: The third transistor has a first end connected to the first end of the second transistor in the device under test, a second end connected to the first end of the power module, and a third control end used to control the third transistor to enter the first working state or the second working state.

4. The test circuit according to claim 2 or 3, characterized in that: The selector includes a first switch and a second switch, and the states thereof include a closed state and an open state. The first switch and the second switch are arranged in parallel, and only one of the first switch and the second switch is in a closed state; the first working state is a conducting state, and the second working state is a cut-off state, wherein: The first switch is used to transmit the current signal provided by the power supply module back to the power supply module via the energy storage module, the auxiliary test device set in the device under test and the main test device in sequence when the accompanying test device is in the cut-off state, or to transmit the current signal back to the power supply module via the energy storage module, the auxiliary test device set in the device under test and the main test device in sequence when the accompanying test device is in the cut-off state; The second switch is used to transmit the current signal provided by the power module back to the power module via the energy storage module when the accompanying test device is in the on state; or to transmit the current signal provided by the energy storage module back to the energy storage module via the main test device and the auxiliary test device set in the device under test in sequence when the accompanying test device is in the off state.

5. The test circuit according to claim 4, characterized in that: When testing the switching parameters of the device under test, at least one auxiliary test device in the auxiliary test device set is in a continuously on state, the first switch is closed, the main test device is in an on state, and the companion test device is in an off state, so that the current signal provided by the power supply module is transmitted back to the second end of the power supply module in sequence via the first switch, the energy storage module, at least one auxiliary test device in the auxiliary test device set, and the main test device.

6. The test circuit according to claim 4, characterized in that: When testing the switching parameters of the device under test, the first switch is closed, the main test device is in the off state, at least one auxiliary test device in the auxiliary test device set is in a continuously on state, and the accompanying test device is in the off state, so that the current signal provided by the power supply module is transmitted back to the first end of the power supply module via the first switch, the energy storage module, and the accompanying test device in sequence.

7. The test circuit according to claim 4, characterized in that: In the first stage of testing the parameters of the reverse recovery process of the device under test, the second switch is closed, the main test device is in the cut-off state, at least one auxiliary test device in the auxiliary test device set is in the on state, and the companion test device is in the on state, so that the current signal provided by the power module is transmitted back to the second end of the power module via the companion test device, the energy storage module, and the second switch in sequence.

8. The test circuit according to claim 7, characterized in that: In the second stage of testing the parameters of the reverse recovery process of the device under test, the energy storage module is discharged, the second switch is closed, the main test device is in the off state, at least one auxiliary test device in the auxiliary test device set is in the on state, and the companion test device is in the off state, so that the current signal provided by the first end of the energy storage module is transmitted back to the second end of the energy storage module via the main test device and at least one auxiliary test device in the auxiliary test device set in sequence.

9. The test circuit according to claim 4, characterized in that: The energy storage module is used to store the current signal provided by the power supply module when the first switch is closed; or to discharge to the device under test when the second switch is closed.

10. The test circuit according to claim 4, characterized in that: The power module comprises: A capacitor array is arranged in parallel, wherein a first end is connected to the energy storage module through the first switch, and a second end is connected to the device under test.

11. The test circuit according to claim 4, characterized in that: The test circuit further comprises: A sampling resistor has a first end connected to the second end of the power module and a second end connected to the device under test.

12. A method for testing dynamic parameters of a wafer, characterized in that: The test method is applied to the test circuit according to any one of claims 1 to 11, and the test method comprises: Determine the driving signal according to the parameters to be tested; Controlling the working states of the device under test and the accompanying device under test in the test circuit according to any one of claims 1 to 11 according to the driving signal, and obtaining the voltage and current of the device under test corresponding to the parameter to be tested; The parameters to be tested are determined according to the voltage and current of the device under test, wherein the parameters to be tested include switching parameters of the wafer and parameters of a reverse recovery process.

13. The testing method according to claim 12, characterized in that: The selector includes a first switch and a second switch, the drive signal includes a first drive signal, a second drive signal and a third drive signal; the method includes: Controlling the first switch to be closed, and controlling the main test device in the device under test to be in a conducting state through a first driving signal; Controlling at least one auxiliary test device in the set of auxiliary test devices in the device under test to be in a continuously turned-on state through the second driving signal; The auxiliary test device is controlled to be in a cut-off state by the third driving signal, so that the current signal provided by the power module is transmitted back to the second end of the power module via the first switch, the energy storage module, at least one auxiliary test device in the auxiliary test device set, and the main test device in sequence; The changes of the voltage and current of the device under test are obtained, and the switch parameters of the device under test are obtained according to the changes of the voltage and current of the device under test.

14. The testing method according to claim 12, characterized in that: The selector includes a first switch and a second switch, the drive signal includes a first drive signal, a second drive signal and a third drive signal; the method includes: Controlling the first switch to be closed, and controlling the main test device in the device under test to be in a cut-off state through a first driving signal; Controlling at least one auxiliary test device in the set of auxiliary test devices in the device under test to be in a continuously turned-on state through the second driving signal; The accompanying test device is controlled to be in a cut-off state by the third driving signal, so that the current signal provided by the power module is transmitted back to the first end of the power module via the first switch, the energy storage module, and the accompanying test device in sequence; The changes of the voltage and current of the device under test are obtained, and the switch parameters of the device under test are obtained according to the changes of the voltage and current of the device under test.

15. The testing method according to claim 12, characterized in that: The selector includes a first switch and a second switch, the drive signal includes a first drive signal, a second drive signal and a third drive signal; the method includes: Control the second switch to be closed, and control the main test device in the device under test to be in a cut-off state through the first drive signal; Controlling at least one auxiliary test device in the set of auxiliary test devices in the device under test to be in a continuously turned-on state through the second driving signal; The third driving signal is used to control the accompanying test device to be in an on state, so that the current signal provided by the power module is transmitted back to the second end of the power module via the accompanying test device, the energy storage module and the second switch in sequence.

16. The testing method according to claim 12, characterized in that: The selector includes a first switch and a second switch, the drive signal includes a first drive signal, a second drive signal and a third drive signal; the method includes: Control the second switch to be closed, and control the main test device in the device under test to be in a cut-off state through the first drive signal; Controlling at least one auxiliary test device in the set of auxiliary test devices in the device under test to be in a continuously turned-on state through the second driving signal; Controlling the accompanying test device to be in a cut-off state through the third driving signal, so that the current signal provided by the first end of the energy storage module is sequentially transmitted back to the second end of the energy storage module via the main test device and at least one auxiliary test device in the auxiliary test device set; The changes of the voltage and current of the device under test are obtained, and the parameters of the reverse recovery process of the device under test are obtained according to the changes of the voltage and current of the device under test.

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