Array substrate, display panel and display device

Abstract

Embodiments of the present application provide an array substrate, a display panel and a display device. The array substrate comprises: a plurality of data lines arranged along a first direction, a plurality of gate lines arranged along a second direction, and a plurality of sub-pixel groups surrounded by two adjacent gate lines and a data line in an insulating overlapping manner; each sub-pixel group comprises two sub-pixels; the sub-pixel group comprises: a first sub-pixel group, a second sub-pixel group and a third sub-pixel group arranged alternately along the first direction; wherein the sub-pixels in the second sub-pixel group are used to emit light of a first color; the two sub-pixels in the first sub-pixel group are used to emit light of a second color and light of a third color respectively; and the two sub-pixels in the third sub-pixel group are used to emit light of the second color and light of the third color respectively. Embodiments of the present application realize mixed and blurred light emission by arranging two sub-pixels emitting light of the first color adjacently, avoid the occurrence of vertical lines and other defects in the array substrate with double-gate design, and improve the light emission uniformity of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Related technologies propose using thin-film transistors (TFTs) integrated behind liquid crystal pixels to drive liquid crystal displays (LCDs), thereby achieving screen displays with advantages such as high brightness and high contrast. To achieve patterned light emission, pixels are generally arranged in an array. To drive and control the array of pixels, the common practice is to electrically connect them using staggered gate lines and data lines. This allows the switching of the TFTs to control the emission color of the red, green, and blue (RGB) primary color pixels in each pixel unit, thus controlling the color of the emitted light from the pixel unit. With the gradual development and relative maturity of LCD displays, demands such as cost reduction and image quality improvement are increasing. To meet these demands, related technologies have proposed various innovative designs for the array substrate in LCD displays, such as adjusting the number, arrangement, and connection methods of gate and data lines. However, these innovative designs often have unexpected drawbacks, which may adversely affect the realization of the array substrate's function and even lead to a decrease in the display performance of the array substrate.

[0003] It should be noted that the information in the background section of the invention is only used to enhance the understanding of the background of the invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This application provides an array substrate, a display panel, and a display device, which aims to achieve the emission of light from two pixel units of three primary color pixels by sequentially and alternately arranging a first sub-pixel group, a second sub-pixel group, and a third sub-pixel group. The two sub-pixels emitting the first color light are arranged adjacently between two adjacent pixel units and can achieve mixed and blurred emission, thereby cooperating with the emission of light from the sub-pixels in the first and third sub-pixel groups on both sides, each forming a pixel unit. This partially or completely solves the problem of vertical stripes on the array substrate caused by uneven brightness of the sub-pixels emitting the first color light, thereby improving the display performance of the array substrate.

[0005] In one aspect, embodiments of this application provide an array substrate, comprising:

[0006] Multiple data lines arranged along a first direction, multiple gate lines arranged along a second direction, and multiple sub-pixel groups formed by overlapping and insulating two adjacent gate lines among the multiple gate lines; each sub-pixel group includes two sub-pixels;

[0007] The sub-pixel group includes: a first sub-pixel group, a second sub-pixel group, and a third sub-pixel group arranged alternately along the first direction;

[0008] Wherein, the sub-pixels in the second sub-pixel group are used to emit a first color light; the two sub-pixels in the first sub-pixel group are used to emit a second color light and a third color light respectively; and the two sub-pixels in the third sub-pixel group are used to emit a second color light and a third color light respectively.

[0009] Optionally, two sub-pixels in each of the sub-pixel groups are arranged along the first direction;

[0010] Along the first direction, two sub-pixels in the first sub-pixel group are used to emit the second color light and the third color light in sequence, and two sub-pixels in the third sub-pixel group are used to emit the third color light and the second color light in sequence.

[0011] Optionally, the first color light includes blue light, the second color light includes red light, and the third color light includes green light.

[0012] Optionally, in the sub-pixel groups between adjacent gate lines, the sub-pixels in the first and third sub-pixel groups that emit light of the same color are electrically connected to the gate lines on the same side, respectively.

[0013] Optionally, each sub-pixel in each sub-pixel group is electrically connected to the data line on the same side of the sub-pixel group and the gate lines on both sides of the sub-pixel group.

[0014] The sub-pixel groups arranged along the second direction and located between the same set of gate lines are alternately electrically connected to the data lines on both sides, and the sub-pixel groups arranged along the first direction and located between the same set of data lines are respectively electrically connected to the data lines on the same side.

[0015] Optionally, the gate line has a set power-on timing sequence;

[0016] In the first sub-pixel group or the third sub-pixel group, the sub-pixel adjacent to the second sub-pixel group is used to electrically connect to the gate line with the relatively earlier power-on timing among the gate lines adjacent to both sides of the current sub-pixel group.

[0017] In the second sub-pixel group, the sub-pixel adjacent to the first sub-pixel group is used to electrically connect to the gate line with the relatively later power-on timing among the gate lines adjacent to both sides of the current first sub-pixel group.

[0018] Optionally, the luminous intensity of the sub-pixels in the first sub-pixel group and / or the third sub-pixel group is higher than the luminous intensity of the sub-pixels in the second sub-pixel group.

[0019] Optionally, it also includes: an integrated gate drive circuit;

[0020] The integrated gate drive circuit is used to control the power-on sequence and power-on duration of each gate line;

[0021] Along the second direction, the power-on timing of each gate line is set by the integrated gate drive circuit to increase sequentially, and the power-on time periods of two adjacent gate lines overlap, with the overlap time period of two adjacent gate lines being equal to two-thirds of the power-on duration.

[0022] Through the above embodiments, the array substrate provided in this application has the following advantages:

[0023] The array substrate provided in this application embodiment can realize the light emission of two pixel units of the three primary color pixels by sequentially and alternately arranging a first sub-pixel group, a second sub-pixel group, and a third sub-pixel group. The two sub-pixels emitting the first color light are arranged adjacently between two adjacent pixel units and can achieve mixed and blurred light emission. This, together with the light emission of the sub-pixels in the first and third sub-pixel groups on both sides, each forms a pixel unit, which partially or completely solves the problem of vertical stripes on the array substrate caused by uneven light emission brightness of the sub-pixels emitting the first color light, thereby improving the display performance of the array substrate.

[0024] In another aspect, embodiments of this application also provide a display panel, including the array substrate described in the above embodiments.

[0025] Optionally, it also includes: a color filter layer;

[0026] The color filter layer includes multiple filter units arranged in an array, and the color of the filter color resist of the multiple filter units corresponds one-to-one with the emission color of the sub-pixel.

[0027] The display panel provided in this application embodiment includes the array substrate in the above embodiment and also has all the advantages of the array substrate.

[0028] In another aspect, embodiments of this application also provide a display device, including the display panel in the above embodiments.

[0029] The display device provided in this application includes the display panel in the above embodiments and also has all the advantages of the above display panel. Attached Figure Description

[0030] The accompanying drawings are for reference and illustration only and are not intended to limit the scope of protection of this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0031] Figure 1 This illustration shows a schematic diagram of the arrangement and connection of an array substrate in one embodiment of the present application;

[0032] Figure 2 This illustration shows a schematic diagram of the effect of color mixing and light emission in one embodiment of the present application;

[0033] Figure 3 This illustration shows a schematic diagram of another color-mixing emission effect in one embodiment of the present application;

[0034] Figure 4 This illustration shows a schematic diagram of another color-mixing emission effect in one embodiment of the present application;

[0035] Figure 5 A timing diagram of gate power-on is shown in one embodiment of the present application.

[0036] Figure 6 This illustration shows a structural schematic diagram of the fabrication process of an array substrate according to one embodiment of the present application;

[0037] Figure 7 A schematic diagram of a GOA principle is shown in one embodiment provided in this application.

[0038] Explanation of reference numerals in the attached figures:

[0039] 10 - First sub-pixel group; 20 - Second sub-pixel group; 30 - Third sub-pixel group; 11 - First sub-pixel; 12 - Second sub-pixel; 13 - Third sub-pixel; 310 - Data line; 410 - Gate line; 500 - Pixel arrangement period; 101 - Substrate; 102 - First electrode; 103 - First insulating layer; 104 - Active layer; 105 - Source / drain electrode; 106 - Second insulating layer; 107 - Second electrode. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0041] In display devices such as liquid crystal displays (LCDs) and light-emitting diode (LED) displays, array substrates are used to achieve light emission. Taking an LCD as an example, each pixel unit can include a thin-film transistor and a pixel electrode, and drive signals are transmitted via data lines and scan signals via gate lines to drive the liquid crystal deflection. Exemplarily, the data lines can be connected to the source of the transistor, the gate lines can be connected to the gate of the transistor, and the pixel electrode can be connected to the drain of the transistor.

[0042] As the resolution of display panels increases, the number of data lines providing driving signals to each pixel unit also increases accordingly, leading to a rise in the performance and cost of the display driver IC that provides these driving signals. Traditional single-gate designs drive the arrayed pixel units through a combination of gate lines and data lines. To reduce the cost of the driver chip and improve its bonding yield, related technologies propose setting two gate lines between each row of pixel units extending along a first direction on the display panel, and setting data lines between every two columns of pixel units along a second direction intersecting the first direction, thereby achieving dual-gate driving. Specifically, in a single-gate array substrate, multiple single gate lines and multiple data lines can be insulated and overlapped to form multiple arrayed pixel units. The combination of gate lines and data lines can drive the emission of sub-pixels in different pixel units. In a dual-gate array substrate, multiple sets of dual gate lines and multiple data lines can be insulated and overlapped to form multiple array-arranged sub-pixel groups. Each sub-pixel group includes two sub-pixels, i.e., pixel points. The data lines drive two adjacent columns of pixel units, which can reduce the number of data lines by half, thereby reducing the performance requirements of the driver chip and thus reducing the cost of the array substrate and display panel.

[0043] Compared to gate array substrates, dual-gate array substrates double the number of gates, halving the charging time for each gate line. In array substrates with high display refresh rates such as 120Hz or 144Hz, the charging time for the gate lines is further reduced. If the charging time for each gate line is insufficient, it will lead to insufficient charge in the pixels, affecting the display performance of the array substrate. To ensure the charging rate of the gate lines, related technologies propose pre-charging the gate lines. This involves charging the gates in the previous row to enable the writing of data from the previous row to the gates in the next row, thus achieving pre-charging and increasing the charging rate of the gates.

[0044] Because subpixels emitting different colors of light have differences in luminous intensity and charging, their electrical connections to gate lines or data lines need to be configured according to their emission color. For example, in one related technology, since red and green subpixels are brighter than blue subpixels, if the red and green subpixels are not connected to the same row of gates, the charging difference can easily cause functional inconsistencies in the array substrate. Therefore, in this related technology, red and green subpixels in a dual-gate array substrate are often designed to have their gates connected to the same row to reduce the charging difference between subpixels.

[0045] However, the inventors discovered that in the aforementioned array substrate with pre-charged gates, when performing color mixing display of a specific color, differences in the pre-charge level between sub-pixels emitting the same color light may lead to differences in the luminous intensity of sub-pixels emitting the same color light, resulting in problems such as vertical lines on the displayed image and a decrease in the display performance of the array substrate. For example, in an array substrate provided by a related technology, sub-pixels can be arranged in the RGBRGBRGB... pattern along the direction of the gate line extension to achieve traditional RGB combination light emission. When performing color mixing display, since the gates of sub-pixels in each row and column may have different data written to the previous row during pre-charging, the different pre-charging levels will result in differences in the luminous intensity of sub-pixels emitting the same color light. For example, green and blue sub-pixels emit light, while red sub-pixels do not emit light, which can achieve displays such as the Windows system boot screen colors. The gates of blue or green sub-pixels distributed in each row and column may have different data written to the previous row during pre-charging. Specifically, this can manifest as follows: when the sub-pixel in the row preceding the current sub-pixel is a red sub-pixel, the written Data is at a low level, the pre-charge charge written to the current sub-pixel is insufficient, and the luminous intensity is low. When the sub-pixel in the row preceding the current sub-pixel is not a red sub-pixel, the written Data is at a high level, the pre-charge charge written to the current sub-pixel is insufficient, and the luminous intensity is high. If blue sub-pixels are not aligned with red or green sub-pixels, a situation may arise where one column of blue sub-pixels is brighter than the adjacent column, resulting in vertical stripes on the array substrate and display panel.

[0046] To address the aforementioned issues, this application provides an array substrate, a display panel, and a display device. It abandons the traditional RGBRGBRGB... pixel arrangement. In a dual-gate array substrate, a first sub-pixel group, a second sub-pixel group, and a third sub-pixel group are arranged alternately to achieve the emission of light from two pixel units of the three primary color pixels. The two sub-pixels emitting the first color light are arranged adjacent to each other between two adjacent pixel units and can achieve mixed and blurred emission. This, combined with the emission of light from the sub-pixels in the first and third sub-pixel groups on both sides, forms a pixel unit. This partially or completely solves the problem of vertical stripes on the array substrate caused by uneven brightness of the sub-pixels emitting the first color light, thereby improving the display performance of the array substrate.

[0047] The embodiments of this application will now be described with reference to the accompanying drawings.

[0048] like Figure 1 As shown, Figure 1 This illustration shows a schematic diagram of the arrangement and connection of an array substrate according to one embodiment of the present application. (Refer to...) Figure 1 This application provides an array substrate, including: multiple data lines 310 arranged along a first direction, multiple gate lines 410 arranged along a second direction, and multiple sub-pixel groups formed by overlapping and insulating two adjacent gate lines 410 with respect to the data lines 310.

[0049] Each sub-pixel group consists of two sub-pixels.

[0050] In one alternative implementation, two sub-pixels in each sub-pixel group may be arranged along a first direction.

[0051] Specifically, data line 310 can be electrically connected to the sub-pixel to provide data signals, including Figure 1 The data1, data2, etc. in the image. Gate line 410 can be electrically connected to sub-pixels to provide scan signals, including... Figure 1 gate1, gate2, etc.

[0052] The first direction intersects with the second direction. Specifically, the first direction and the second direction can be perpendicular to each other. For ease of understanding, the first direction can be defined as a direction extending laterally, and the second direction can be defined as a direction extending longitudinally.

[0053] Specifically, two adjacent gate lines 410 can be paired up to form a gate line group, and a gate line group can be set between adjacent sub-pixel groups arranged along the second direction to realize a dual-gate array substrate. The gate line group can be electrically connected to the sub-pixels on both sides.

[0054] The sub-pixel group includes: a first sub-pixel group 10, a second sub-pixel group 20, and a third sub-pixel group 30 arranged alternately along the first direction.

[0055] Among them, the sub-pixels in the second sub-pixel group 20 are used to emit the first color light.

[0056] The two sub-pixels in the first sub-pixel group are used to emit the second color light and the third color light, respectively, and the two sub-pixels in the third sub-pixel group are used to emit the second color light and the third color light, respectively.

[0057] Accordingly, the sub-pixel emitting the first color light can be the first sub-pixel 11, the sub-pixel emitting the second color light can be the second sub-pixel 12, and the sub-pixel emitting the first color light can be the third sub-pixel 13.

[0058] For example, a subpixel that emits blue light can be a blue subpixel.

[0059] Considering that sub-pixels can emit light through the combination of the three primary colors, in some optional embodiments, the first color light, the second color light, and the third color light can be one of red light, green light, and blue light, respectively. Any pixel unit may include a first sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13.

[0060] For example, if the first sub-pixel group 10, the second sub-pixel group 20, and the third sub-pixel group 30 are arranged alternately along the first direction, then the arrangement of subpixels along the first direction can be such that six subpixels from the first sub-pixel group 10, the second sub-pixel group 20, and the third sub-pixel group 30 constitute one pixel arrangement period 500. For example, the arrangement of subpixels in each pixel arrangement period 500 along the first direction can be the second subpixel 12, the third subpixel 13, the first subpixel 11, the first subpixel 11, the third subpixel 13, and the second subpixel 12.

[0061] Through the above embodiments, the first sub-pixel group 10, the second sub-pixel group 20 and the third sub-pixel group 30 arranged alternately in sequence realize the light emission of two pixel units of the three primary color pixels. The two sub-pixels emitting the first color light are arranged adjacent to each other between two adjacent pixel units and can realize mixed and blurred light emission. This, together with the light emission of the sub-pixels in the first sub-pixel group 11 and the third sub-pixel group 30 on both sides, each forms a pixel unit. This partially or completely solves the problem of vertical stripes on the array substrate caused by uneven light emission brightness of the sub-pixels emitting the first color light, thereby improving the display performance of the array substrate.

[0062] Specifically, the array substrate provided in the above embodiments can also be used to emit light in cases where only a first color light and another color light are emitted, such as emitting only the first color light and the second color light. The first color light is emitted in a mixed and blurred manner, and the second color light is also emitted in a more uniform manner after being mixed along the second direction due to the partial high-level pre-charging and the partial low-level pre-charging. This achieves regional uniform light emission, avoids display defects such as vertical lines, improves the light emission uniformity of the array substrate, and improves the display performance of the array substrate.

[0063] like Figure 2 As shown, Figure 2 A schematic diagram illustrating the effect of color mixing and emission in one embodiment of this application is shown. (Refer to...) Figure 2 This application exemplarily proposes a mixed-color emission method, in which the first sub-pixel 11 and the third sub-pixel group 30 emit light together. Since the column of first sub-pixels 11 adjacent to data2 is pre-charged with the high-level data signal of the other column of first sub-pixels 11, the emission intensity is high, indicated as "good" in the figure. Since the column of first sub-pixels 11 adjacent to data3 is pre-charged with the low-level data signal of the second sub-pixels 12 on both sides, the emission intensity is low, indicated as "poor" in the figure. The two columns of first sub-pixels 11 can achieve mixed and blurred emission, harmonizing the emission brightness. The third sub-pixel 13 is partially pre-charged with the low-level signal of the second sub-pixel 12 and partially pre-charged with the high-level signal of the first sub-pixel 11, exhibiting both "good" and "poor" emission, and showing a periodic change along the second direction. This also harmonizes the emission brightness between adjacent rows, thereby achieving visually uniform emission.

[0064] like Figure 3 As shown, Figure 3 This illustration shows a schematic diagram of another color-mixing emission effect in one embodiment of the present application. (Refer to...) Figure 3 This application exemplarily proposes another method of mixed-color light emission, in which the first sub-pixel 11 and the second sub-pixel group 20 emit light together. Since the column of first sub-pixels 11 adjacent to data2 is pre-charged with a high-level data signal from another column of first sub-pixels 11, the light emission intensity is high, indicated as "good" in the figure. The column of first sub-pixels 11 adjacent to data3 is pre-charged with high-level data signals from the second sub-pixels 12 on both sides, also resulting in high light emission intensity, indicated as "good" in the figure. Meanwhile, the second sub-pixels 12 are pre-charged with a low-level signal from the third sub-pixel 13, resulting in "poor" light emission brightness. Therefore, each pixel unit has both a "good" first sub-pixel 11 and a "poor" second sub-pixel 12, achieving uniform light emission from the array substrate.

[0065] like Figure 4 As shown, Figure 4This illustration shows a schematic diagram of another color-mixing emission effect in one embodiment of the present application. (Refer to...) Figure 4 This application exemplarily proposes another method of color mixing and light emission, in which the second sub-pixel 12 and the third sub-pixel group 30 emit light together. Since all the second sub-pixels 12 are pre-charged and written with the high-level data signal of the third sub-pixel 13, the light emission intensity is relatively high, which is indicated as "good" in the figure. The third sub-pixel 13 is partially pre-charged and written with the low-level signal of the first sub-pixel 11, and partially pre-charged and written with the high-level signal of the second sub-pixel 12, resulting in both "good" and "bad" light emission, which varies periodically along the second direction. This can also achieve the harmonization of light emission brightness between adjacent rows, thereby achieving visually uniform light emission.

[0066] When a single seed pixel emits light, such as only the first sub-pixel 11, the pre-charge writes low-level signals, resulting in low light intensity for all first sub-pixels 11, thus achieving uniform light emission.

[0067] When all sub-pixels emit light, such as the first sub-pixel 11, the third sub-pixel 13, and the second sub-pixel 12, all sub-pixels are charged and written with high-level signals, resulting in high light intensity and achieving uniform light emission.

[0068] Subpixels with relatively low luminous intensity are more conducive to achieving mixed blur luminescence. Therefore, in an optional embodiment, this application also provides an array substrate, wherein the luminous intensity of subpixels in the first subpixel group 10 and / or the third subpixel group 30 is higher than the luminous intensity of subpixels in the second subpixel group 20.

[0069] Considering that in some related technologies for three-primary-color displays, compared to red and green sub-pixels, blue sub-pixels have lower luminous intensity and are more suitable for achieving mixed and blurred luminescence, the first color light can be set to blue light. In some optional embodiments, the first color light includes blue light, the second color light includes red light, and the third color light includes green light.

[0070] The above embodiments do not limit the arrangement order of the second sub-pixel 12 and the third sub-pixel 13 in the second sub-pixel group 20 or the third sub-pixel group 30. Accordingly, the second color light and the third color light can also be set to either red or green. Therefore, in another optional embodiment, the first color light includes blue light, the second color light includes green light, and the third color light includes red light.

[0071] To further improve the display performance of the array substrate, a symmetrical pixel arrangement can be considered within a pixel arrangement cycle of 500. Therefore, in one optional embodiment, this application also provides an array substrate in which sub-pixels in each sub-pixel group are arranged along a first direction.

[0072] Along the first direction, two sub-pixels in the first sub-pixel group 10 are used to emit second color light and third color light in turn, and two sub-pixels in the third sub-pixel group 30 are used to emit third color light and second color light in turn.

[0073] Through the above embodiments, since two pixel units within a pixel arrangement period of 500 can achieve symmetrical emission of sub-pixels, for example, in the case of emitting only the first color light and the third color light in the dual-gate design, such as when the first color light includes blue light, the second color light includes red light, and the third color light includes green light, when only blue light and green light are emitted to achieve mixed color emission, the blue light can achieve mixed and blurred emission. And because the intensity of blue light is lower than that of the other two colors, the mixed blurring effect will be better. Within a pixel arrangement period of 500, the green light on both sides of the blue light can partially achieve high-level pre-charging and partially achieve low-level pre-charging. By emitting green light after mixing along the second direction, regional visual uniformity can be further achieved. This further avoids display defects such as vertical lines when the array substrate emits blue and green mixed color light, such as when displaying the colors of the Windows boot screen, and improves the uniformity of display emission.

[0074] Considering that sub-pixels of different emitting colors have different emitting intensities, in order to reduce the charging difference between sub-pixels, in an optional embodiment, this application also provides an array substrate, wherein, in the sub-pixel groups between adjacent gate lines 410, the sub-pixels in the first sub-pixel group 10 and the third sub-pixel group 30 that emit light of the same color are electrically connected to the gate lines 410 on the same side, respectively.

[0075] Through the above embodiments, sub-pixels emitting the same color light in the first sub-pixel group 10 and the third sub-pixel group 30 can be turned on by the gates in the same row, further reducing or avoiding charging differences between sub-pixels, thereby improving the light emission uniformity and display effect of the array substrate.

[0076] To further improve the light emission uniformity of the array substrate, in an optional embodiment, this application also provides an array substrate, wherein the sub-pixels in each sub-pixel group are electrically connected to the data line 310 on the same side of the sub-pixel group and the gate lines 410 on both sides of the sub-pixel group.

[0077] Sub-pixel groups arranged along the second direction and located between adjacent gate lines in the same group are alternately electrically connected to data lines on both sides, and sub-pixel groups arranged along the first direction and located between adjacent data lines in the same group are electrically connected to data lines on the same side respectively.

[0078] Among them, a set of gate lines can be two adjacent gate lines with a sub-pixel group in between, and a set of data lines can be two adjacent data lines.

[0079] Through the above embodiments, sub-pixels with the same emission color can still be arranged along the second direction. A sub-pixel in any sub-pixel group can be pre-charged when the gate of another sub-pixel is turned on to write a data signal. Since the sub-pixel groups arranged along the second direction are alternately electrically connected to the data lines 310 on both sides, and the sub-pixel groups arranged along the first direction are respectively electrically connected to the data lines 310 on the same side, one of the sub-pixels A in the second sub-pixel group 20 is affected by the lighting of another sub-pixel B. During pre-charging, a high level can be written, thereby achieving higher emission brightness. The influence of whether the sub-pixel B is lit or not by the lighting of the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 can be canceled by mixing and blurring emission with sub-pixel A. Furthermore, the pre-charging of the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 can be associated with the second sub-pixel group 20. In this case, when the sub-pixels of the second sub-pixel group 20 emit light, the light emission brightness of the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 can be guaranteed to a certain extent. Due to the symmetrical design, the light emission uniformity of the array substrate is improved.

[0080] Furthermore, for different sub-pixel group types, specific implementation methods can be included to electrically connect the sub-pixels with the gate line 410 and the data line 310, forming thin-film transistor switches at different locations:

[0081] In one alternative implementation, the gate lines have a set power-on timing.

[0082] In the first or third sub-pixel group, the sub-pixel adjacent to the second sub-pixel group is used to electrically connect to the gate line with the earlier power-on timing among the gate lines adjacent to both sides of the current sub-pixel group.

[0083] In some alternative embodiments, the gate power-on timing can be increased sequentially along the second direction.

[0084] In the second sub-pixel group, the sub-pixel adjacent to the first sub-pixel group is used to electrically connect to the gate line with the relatively later power-on timing among the gate lines adjacent to both sides of the current first sub-pixel group.

[0085] Through the above embodiments, the pre-charging of sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 that are close to the second sub-pixel group 20 in every other row can be associated with the second sub-pixel group 20. Therefore, when the sub-pixels of the second sub-pixel group 20 emit light, the brightness of the sub-pixels can be guaranteed to a certain extent. Furthermore, by combining the power-on timing of the gate lines with the gate lines that are electrically connected to the sub-pixels, and by combining the symmetrical design of the sub-pixels in a pixel arrangement cycle in the above embodiments, the uniformity of light emission of the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 can be improved, thereby improving the uniformity of light emission of the array substrate and avoiding display defects such as vertical lines.

[0086] Accordingly, in another alternative embodiment, in the first sub-pixel group 10 or the third sub-pixel group 30, the sub-pixel closest to the second sub-pixel group 20 is electrically connected to the gate line 410 located on one side of the sub-pixel along the second direction.

[0087] In the second sub-pixel group 20, the sub-pixel closest to the first sub-pixel group 10 is electrically connected to the gate line 410 on the side away from the sub-pixel along the second direction.

[0088] Through the above embodiments, the pre-charging of sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 that are close to the second sub-pixel group 20 in every other row can be associated with the second sub-pixel group 20. In this case, when the sub-pixels of the second sub-pixel group 20 emit light, the light emission brightness of the sub-pixels can be guaranteed to a certain extent. Due to the symmetrical design, the light emission uniformity of the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 is improved, thereby improving the light emission uniformity of the array substrate and avoiding display defects such as vertical lines.

[0089] like Figure 5 As shown, Figure 5 A timing diagram illustrating gate power-on in one embodiment of this application is shown. (Refer to...) Figure 5 Therefore, in one alternative embodiment, this application also provides an array substrate, which further includes an integrated gate drive circuit (GOA).

[0090] An integrated gate drive circuit is used to control the power-on sequence and power-on duration of each gate line 410.

[0091] Along the second direction, the power-on timing of each gate line 410 is set by the integrated gate drive circuit to increase sequentially, and the power-on time periods of two adjacent gate lines 410 overlap with each other, and the overlap time period of two adjacent gate lines 410 is equal to two-thirds of the power-on duration.

[0092] For example, since the number of gate lines 410 is doubled in the dual-gate design, when the gate charging frequency is set to 100Hz, the power-on time of any gate line 410 excluding pre-charging is 1H, which can be 4.6us. The power-on time including pre-charging can be 3 times 4.6us, i.e. 3H.

[0093] Each data line 310 also has a corresponding voltage level, such as V1 and V2, for writing data signals.

[0094] The above embodiments can improve the charging efficiency of the gate line 410 through pre-charging, avoiding insufficient pixel charge and ensuring the display performance of the array substrate. Furthermore, combined with the above embodiments, the differences in charging between different sub-pixels and the differences in pre-charging caused by the color mixing effects of the two sub-pixels have been mitigated to a certain extent, ensuring the uniformity of light emission from the array substrate.

[0095] This application also provides an example of GOA-driven implementation. When the Gate side adopts a GOA design, the Data signal is halved under the DualGate design, resulting in a halved Data COF on the Source side, thus reducing manufacturing costs. The 19T1C GOA architecture is used as an example to illustrate the corresponding principle. (Refer to...) Figure 7 , Figure 7 A schematic diagram illustrating the GOA principle of one embodiment provided in this application is shown. Figure 7 As shown,

[0096] When STV1 arrives, it indicates that the entire GOA has started working. Input is connected, M1 is turned on, VGH charges the PU point, and CLK1 is low at this time.

[0097] When CLK1 goes high, PU goes even higher due to the effect of capacitor C, which turns on M13 and M14, causing them to output CLK high and GOUT and GOUTC high respectively.

[0098] The output GOUT opens the gate to charge the pixels in the AA area, and the output GOUTC is then used as INPUT for the next row. This process is repeated to achieve the function of GOA (shift register).

[0099] GOUT and GOUTC are separated because GOUT is the gate that turns on the AA area, enabling the AA area to charge, while GOUTC is used as a shift register cascade signal, so that it does not affect the AA area, but only enables the GOA to work.

[0100] VDD1 and VDD2 are interleaved to control PD. When PU is low, PD can reduce noise and make PU low so as not to affect OUT. It is equivalent to two circuits interleaving to control PD (VDD2 is low when VDD1 is high, and VDD1 is low when VDD2 is high). The purpose of interleaving VDD1 and VDD2 is because TFT will be damaged if it is subjected to bias voltage (always high level).

[0101] Taking a Dual Gate array substrate with FHD (1920*1080) pixel resolution as an example, there are a total of 1080 gates. Doubling the Dual Gates results in 2160 gates. Gates 1 to 2160 of the GOA array are output sequentially in 6CLK cycles. Figure 5 As shown, the precharge time is increased by 2H, the high and low levels are each 3H, and the data signal is written for 1H.

[0102] Through the above embodiments, the array substrate provided in this application uses a dual-gate design. Based on the pixel arrangement of Z-inversion on the substrate 101 on the TFT side, a pixel arrangement period 500 is formed by three sub-pixel groups along the first direction. A pixel arrangement period 500 includes two pixel units. The first sub-pixels 11 of the two pixel units are adjacent and located in the same sub-pixel group. The mixed and blurred light emission of the first sub-pixels 11 can effectively avoid the problem of uneven brightness caused by the difference in pre-charge level, and achieve uniform light emission of the array substrate.

[0103] like Figure 6 As shown, Figure 6 This illustration shows a structural schematic diagram of the fabrication process of an array substrate according to one embodiment of the present application. (Refer to...) Figure 6 Based on the same inventive concept, embodiments of this application also provide a method for fabricating an array substrate, comprising:

[0104] Step S601: Provide a substrate 101 and fabricate a first electrode 102 on the substrate 101.

[0105] The substrate 101 can be a glass substrate.

[0106] The first electrode 102 can be a common electrode, and the material can be indium tin oxide (ITO). The common electrode can be patterned sequentially through coating, exposure, development, and wet etching, and can be a single pattern within a sub-pixel.

[0107] In step S602, a gate line 410 is fabricated on the first electrode 102, and a first insulating layer 103 is fabricated on the gate line 410.

[0108] The material of the gate line 410 may include Mo-Al-Mo, and the pattern of the gate line 410 may be formed by coating, exposure, development and wet etching in sequence. The first insulating material may include SiNx.

[0109] Specifically, the first insulating layer 103 may be a gate insulating layer.

[0110] In step S603, an active layer 104 is formed on the first insulating layer 103, and source and drain electrodes 105 are formed on the active layer 104.

[0111] Specifically, step S603 can employ a 4-mask process, involving one dry etching and one wet etching to form the source / drain electrodes 105, the channel, and the Tx line of the TFT, thereby forming the TFT.

[0112] The 4Mask process allows for the simultaneous deposition of the dielectric layer and source / drain electrodes 105. After coating with PR resist, only one masking is performed, resulting in partial exposure in the channel region. Alternatively, the source electrode can be etched first, followed by ashing exposure to reveal the channel.

[0113] Step S604: A second insulating layer 106 is formed above the source and drain electrodes 105.

[0114] The second insulating layer 106 can be an inorganic layer (PVX), which may include SiNx. Specifically, it can be obtained by exposure, development and etching. It may also have vias, including connection vias for pixel electrodes and half-vias for electrical connection between the gate or data line 310 and the sub-pixel.

[0115] Step S605: A second electrode 107 is fabricated above the second insulating layer 106.

[0116] The second electrode 107 can be a pixel electrode, which may include indium tin oxide, and can be patterned by coating, exposure, development and wet etching.

[0117] Through the above embodiments, the method for fabricating the array substrate provided in this application has the following advantages:

[0118] (1) The array substrate prepared by means of the above embodiments also has all the advantages of the array substrate in the above embodiments.

[0119] (2) The above manufacturing method can improve the light emission uniformity of the array substrate and reduce or avoid display defects such as vertical lines by changing only the arrangement and position of the sub-pixels. It has the characteristics of simplicity, efficiency and low cost, which is conducive to the large-scale manufacturing of the array substrate.

[0120] Based on the same inventive concept, this application also provides a display panel, including the array substrate in the above embodiments.

[0121] Therefore, in one alternative embodiment, this application also provides an array substrate, wherein the array substrate further includes a color filter layer.

[0122] The color filter layer consists of multiple filter units arranged in an array, and the color of the filter color resist of the multiple filter units corresponds one-to-one with the emission color of the sub-pixel.

[0123] Specifically, the color filter layer, also known as the color filter film, can include red, green, and blue color filters.

[0124] For example, a red filter color resist can correspond to a red sub-pixel.

[0125] Through the above embodiments, the color filter layer can adopt a corresponding color resist arrangement, and two pixel units are composed of six sub-pixels arranged along the first direction. Each pixel unit is also composed of RGB color resists to ensure the basic light-emitting display function of the display panel.

[0126] In one alternative example, the color filter layer can adopt an RGBBGR color resist arrangement corresponding to the arrangement of sub-pixels in the array substrate. Table 1 is a color resist arrangement table provided in an embodiment of this application. Referring to Table 1, the color resists corresponding to data lines 3101 to 3106 in the same row are RGBBGR, which can realize the emission of RGB and BGR of two pixel units respectively.

[0127]

[0128] In the embodiments of this application, the one-to-one correspondence between the color of the filter unit's filter color resist and the emission color of the sub-pixel can refer to the correspondence between the filter unit's filter color resist and the emission light path of the sub-pixel.

[0129] Furthermore, the orthogonal projection of the color filter of the filter unit onto the array substrate can overlap with the sub-pixel of the corresponding emission color.

[0130] This application also provides a display panel, including an array substrate fabricated using the method described in the above embodiments.

[0131] Based on the same inventive concept, this application also provides a display device, including the display panel in the above embodiments.

[0132] Specifically, the display panel may include an LCD display panel, and may further include a TFT-LCD display panel.

[0133] Specifically, considering that the array substrate in the above embodiments can be used to avoid display device failures in display or touch functions, thereby improving the display effect of various display products, the display device may include products such as display panels, smartwatches, mobile phones, tablets, VR device display screens, or computer monitors.

[0134] Based on the same inventive concept, this application also provides a display device, which includes the display apparatus in the above embodiments.

[0135] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0136] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0137] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0138] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0139] In this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes that element.

[0140] Finally, it should be noted that specific examples have been used in this document to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Although preferred embodiments of this application have been described, those skilled in the art, once they understand the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of this application.

Claims

1. An array substrate, characterized in that, include: Multiple data lines arranged along a first direction, multiple gate lines arranged along a second direction, and multiple sub-pixel groups formed by overlapping and insulating two adjacent gate lines among the multiple gate lines; Each sub-pixel group consists of two sub-pixels; The sub-pixel group includes: a first sub-pixel group, a second sub-pixel group, and a third sub-pixel group arranged alternately along the first direction; Wherein, the sub-pixels in the second sub-pixel group are used to emit a first color light; the two sub-pixels in the first sub-pixel group are used to emit a second color light and a third color light respectively; and the two sub-pixels in the third sub-pixel group are used to emit a second color light and a third color light respectively. The two sub-pixels in each sub-pixel group are arranged along the first direction; Along the first direction, two sub-pixels in the first sub-pixel group are used to emit the second color light and the third color light in sequence, and two sub-pixels in the third sub-pixel group are used to emit the third color light and the second color light in sequence; In the sub-pixel groups between adjacent gate lines, the sub-pixels in the first and third sub-pixel groups that emit the same color light are electrically connected to the gate lines on the same side, respectively. Each sub-pixel in each sub-pixel group is electrically connected to the data line on the same side of the sub-pixel group and the gate lines on both sides of the sub-pixel group. The sub-pixel groups arranged along the second direction and located between the same set of gate lines are alternately electrically connected to the data lines on both sides, and the sub-pixel groups arranged along the first direction and located between the same set of data lines are respectively electrically connected to the data lines on the same side.

2. The array substrate according to claim 1, characterized in that, The first color light includes blue light, the second color light includes red light, and the third color light includes green light.

3. The array substrate according to claim 1, characterized in that, The gate lines have a set power-on timing sequence; In the first sub-pixel group or the third sub-pixel group, the sub-pixel adjacent to the second sub-pixel group is used to electrically connect to the gate line with the relatively earlier power-on timing among the gate lines adjacent to both sides of the current sub-pixel group. In the second sub-pixel group, the sub-pixel adjacent to the first sub-pixel group is used to electrically connect to the gate line with the relatively later power-on timing among the gate lines adjacent to both sides of the current first sub-pixel group.

4. The array substrate according to claim 1, characterized in that, The luminous intensity of the sub-pixels in the first sub-pixel group and / or the third sub-pixel group is higher than that of the sub-pixels in the second sub-pixel group.

5. The array substrate according to any one of claims 1 to 4, characterized in that, Also includes: Integrated gate drive circuit; The integrated gate drive circuit is used to control the power-on sequence and power-on duration of each gate line; Along the second direction, the power-on timing of each gate line is set by the integrated gate drive circuit to increase sequentially, and the power-on time periods of two adjacent gate lines overlap, with the overlap time period of two adjacent gate lines being equal to two-thirds of the power-on duration.

6. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 5.

7. The display panel according to claim 6, characterized in that, Also includes: Color filter layer; The color filter layer includes multiple filter units arranged in an array, and the color of the filter color resist of the multiple filter units corresponds one-to-one with the emission color of the sub-pixel.

8. A display device, characterized in that, include: The display panel as described in any one of claims 6 to 7.

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