CPLD power-on timing automatic configuration method, device, equipment, and storage medium

Abstract

This application provides a method, apparatus, device, and storage medium for automatically configuring the power-on sequence of a CPLD. The method comprises: obtaining power-on sequence configuration information; generating Verilog code and a pin constraint description file based on the configuration information; and automatically configuring the CPLD power-on sequence based on the Verilog code and the pin constraint description file. Engineers responsible for the CPLD software program only need to provide the configuration information. The method provided in this application then generates the Verilog code and the pin constraint description file based on the configuration information, thereby automatically configuring the CPLD power-on sequence and improving configuration efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for automatically configuring a CPLD power-on sequence. Background Art

[0002] CPLD (Complex Programmable Logic Device), short for Complex PLD, is a more complex logic element than PLD. It allows users to construct digital integrated circuits with custom logic functions based on their needs. Its basic design approach uses an integrated development software platform, schematics, hardware description languages, and other methods to generate the corresponding target files. The code is then transferred to the target chip via a download cable ("in-system" programming), realizing the designed digital system.

[0003] CPLDs offer flexible programming, high integration, short design and development cycles, a wide range of applications, advanced development tools, low design and manufacturing costs, minimal hardware experience required, no testing required for standard products, strong confidentiality, and affordable pricing. They enable large-scale circuit design and are therefore widely used in product prototyping and production. CPLDs can be applied to nearly all applications requiring small-scale general-purpose digital integrated circuits. They have become an indispensable component of electronic products.

[0004] A primary application scenario for CPLDs is controlling and managing the power-on and reset signals of various modules or components in a system. However, some CPUs have specific requirements for the power-on and reset timing of various peripherals in the system. If a PCIE device is not powered on at the correct time, the CPU may not recognize the device. Using a CPLD to manage system power-on allows for continuous modification and adjustment of the power-on sequence according to actual needs until all devices are recognized by the CPU, greatly facilitating system debugging.

[0005] However, due to the large number of signals that need to be managed, repeated adjustments or additions and subtractions are often required during the debugging process. Engineers responsible for the CPLD software program often need to spend a lot of time checking and modifying, and are prone to errors. Summary of the Invention

[0006] In order to solve one of the above technical defects, the present application provides a CPLD power-on timing automatic configuration method, device, equipment, and storage medium.

[0007] In a first aspect, the present application provides a method for automatically configuring a CPLD power-on sequence, the method comprising:

[0008] Get the configuration information of the power-on sequence;

[0009] Generate Verilog code and pin constraint description file based on configuration information;

[0010] Automatically configure the CPLD power-on timing based on Verilog code and pin constraint description files.

[0011] Optionally, the configuration information includes: power-on timing description information, reset timing description information, and level conversion description information;

[0012] Generate Verilog code based on configuration information, including:

[0013] Generate three copies of Verilog code based on the configuration information;

[0014] The three Verilog codes are: a power-on timing Verilog code corresponding to the power-on timing description information, a reset timing Verilog code corresponding to the reset timing description information, and a level conversion Verilog code corresponding to the level conversion description information.

[0015] Optionally, the power-on timing description information includes: ReadySignal, power-on ready signal, power-on time node TimingPoint, power-on enable signal PowerEnableSignal, normal signal ConstantSignal, power-on completion signal PgSignal, external input CPLD reset signal RebootSignal, external input system shutdown signal ShutdownSignal, reset signal InternalReboot generated inside the CPLD, and shutdown signal InternalShutdown generated inside the CPLD.

[0016] Optionally, RebootSignal and ShutdownSignal both include: a signal name indicating whether a rising edge or a falling edge is valid, a pin number, and voltage standard information.

[0017] Optionally, the reset timing description information includes: a normal reset signal ConstantReset, a reset time node TimingPoint2T0, and a controlled reset signal ResetSignal.

[0018] Optionally, ConstantReset, TimingPoint2T0, and ResetSignal all include: a signal name, a pin number, and a voltage value.

[0019] Optionally, the power-on sequence Verilog code is encoded using a three-stage state machine;

[0020] The reset timing Verilog code is implemented using counted delay.

[0021] In a second aspect of the present application, a device for automatically configuring a CPLD power-on timing is provided, the device comprising:

[0022] Acquisition module, used to obtain the configuration information of the power-on sequence;

[0023] A generation module is used to generate Verilog code and pin constraint description files according to the configuration information obtained by the acquisition module;

[0024] The configuration module is used to automatically configure the CPLD power-on timing according to the Verilog code and pin constraint description file generated by the generation module.

[0025] In a third aspect of the present application, an electronic device is provided, comprising:

[0026] Memory;

[0027] processor; and

[0028] computer programs;

[0029] The computer program is stored in the memory and is configured to be executed by the processor to implement the method as described in the first aspect above.

[0030] In a fourth aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored; the computer program is executed by a processor to implement the method described in the first aspect above.

[0031] This application provides a method, apparatus, device, and storage medium for automatically configuring the power-on sequence of a CPLD. The method comprises: obtaining power-on sequence configuration information; generating Verilog code and a pin constraint description file based on the configuration information; and automatically configuring the CPLD power-on sequence based on the Verilog code and the pin constraint description file. Engineers responsible for the CPLD software program only need to provide the configuration information. The method provided in this application then generates the Verilog code and the pin constraint description file based on the configuration information, thereby automatically configuring the CPLD power-on sequence and improving configuration efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0033] Figure 1 A flowchart of a method for automatically configuring a CPLD power-on sequence according to an embodiment of the present application is provided;

[0034] Figure 2 A schematic diagram of an implementation architecture of a method for automatically configuring a CPLD power-on sequence according to an embodiment of the present application;

[0035] Figure 3 A schematic diagram of a power-on timing table provided in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of a reset timing table provided in an embodiment of the present application;

[0037] Figure 5 A schematic diagram of file import provided in an embodiment of the present application;

[0038] Figure 6 A schematic diagram of information import provided in an embodiment of the present application;

[0039] Figure 7 A code generation schematic diagram provided in an embodiment of the present application;

[0040] Figure 8 A schematic diagram of a Verilog code structure provided in an embodiment of the present application;

[0041] Figure 9 A schematic diagram of the structure of a CPLD power-on timing automatic configuration device provided in an embodiment of the present application;

[0042] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0044] In the process of implementing this application, the inventors found that due to the large number of signals that need to be managed, repeated adjustments or increases and decreases in requirements are often required during the debugging process. Engineers responsible for the CPLD software program often need to spend a lot of time checking and modifying, and are prone to errors.

[0045] To address the above issues, the present application provides a method, apparatus, device, and storage medium for automatically configuring the power-on sequence of a CPLD. The method comprises: obtaining power-on sequence configuration information; generating Verilog code and a pin constraint description file based on the configuration information; and automatically configuring the CPLD power-on sequence based on the Verilog code and the pin constraint description file. Engineers responsible for the CPLD software program only need to provide the configuration information. The method provided in the present application then generates the Verilog code and the pin constraint description file based on the configuration information, thereby automatically configuring the CPLD power-on sequence and improving configuration efficiency.

[0046] See also Figure 1 This embodiment provides a method for automatically configuring the power-on sequence of a CPLD. The method is performed as follows:

[0047] 101. Obtain configuration information of the power-on sequence.

[0048] The configuration information of this step can be an Excel template created by the hardware engineer's usage habits. The Excel template will write and describe the standardized power-on reset timing. Therefore, the implementation architecture of the CPLD power-on timing automatic configuration method provided in this embodiment is as follows: Figure 2 As shown, hardware engineers use the habit of creating an Excel template. The CPLD power-on timing automatic configuration method provided in this embodiment will obtain the Excel template, standardize the writing and description of the power-on reset timing, and input it into the script software to generate Verilog code.

[0049] Configuration information can include power-on timing description information, reset timing description information, and level conversion description information. For example, the Excel spreadsheet is divided into three pages, each page using a similar style and format to describe the power-on and reset timing requirements and level conversion requirements.

[0050] The power-on timing description information includes but is not limited to the following: ReadySignal, power-on ready signal, TimingPoint (power-on time node), PowerEnableSignal (power-on enable signal), ConstantSignal (normal signal), PgSignal (power-on completion signal), RebootSignal (externally input CPLD reset signal), ShutdownSignal (externally input system shutdown signal), InternalReboot (reset signal generated internally by CPLD), InternalShutdown (shutdown signal generated internally by CPLD).

[0051] a) Power-on ready signal, when it jumps to the specified level, it means that the power-on process can be started;

[0052] b) TimingPoint: The power-on time node, which is arranged after the current node until the power-on enable signal before the next node is the signal that will enable the current node;

[0053] c)PowerEnableSignal: Power-on enable signal, which is enabled after the power-on process reaches the corresponding time node

[0054] d) ConstantSignal: Normal signal. After the CPLD is powered on, the signal will be pulled high or low and will not change thereafter.

[0055] e) PgSignal: Power-on completion signal, indicating that the power-on enable of the corresponding time node is completed;

[0056] f)RebootSignal: external input CPLD reset signal;

[0057] g)ShutdownSignal: external input system shutdown signal;

[0058] h) InternalReboot: reset signal generated inside the CPLD;

[0059] i) InternalShutdown: The shutdown signal generated inside the CPLD.

[0060] The information required to fill in each content is different, such as Figure 3 shown.

[0061] Among them, RebootSignal and ShutdownSignal both include: a signal name indicating whether the rising edge / falling edge is valid, a pin number, and voltage standard information.

[0062] External input / output signals (i.e., RebootSignal and ShutdownSignal) require not only the rising / falling edge validity and signal name, but also the pin number and voltage standard information. This is not required for internal signals or information.

[0063] Reset timing description information, including: ConstantReset (normal reset signal), TimingPoint2T0 (reset time node), ResetSignal (controlled reset signal).

[0064] a) ConstantReset: Normal reset signal, the corresponding signal is pulled high / low immediately after the CPLD is powered on;

[0065] b) TimingPoint2T0: reset time node, which starts from the power-on time;

[0066] c)ResetSignal: The reset signal that needs to be controlled will be released at the corresponding time node;

[0067] Among them, ConstantReset, TimingPoint2T0, and ResetSignal all include: signal name, pin number, and voltage value. Figure 4 As shown, each information also needs to fill in the signal name, pin number, voltage value, etc.

[0068] In actual applications, in addition to the above information, the configuration information may also include other configuration information such as level conversion and pin constraints according to actual needs.

[0069] In specific implementation, step 101 can be Figure 5 The interface shown reads an Excel spreadsheet. Use the File->Import Excel function to obtain the Excel spreadsheet, read the contents of the Excel spreadsheet, and obtain the power-on sequence configuration information.

[0070] In addition, a modification function can be provided to facilitate the modification of some information, such as Figure 6 As shown, after obtaining the contents in the Excel table, the configuration information will be displayed in the interface, and the information can be checked and modified here.

[0071] 102. Generate Verilog code and pin constraint description file according to the configuration information.

[0072] Among them, the Verilog code is generated according to the configuration information, including:

[0073] Generate three copies of Verilog code based on the configuration information.

[0074] The three Verilog codes are: a power-on timing Verilog code corresponding to the power-on timing description information, a reset timing Verilog code corresponding to the reset timing description information, and a level conversion Verilog code corresponding to the level conversion description information.

[0075] The power-on sequence Verilog code is coded using a three-stage state machine.

[0076] The reset timing Verilog code is implemented using counted delay.

[0077] After the configuration information is obtained in step 101, a corresponding Verilog implementation code that can be directly synthesized and a pin constraint description file can be obtained in step 102.

[0078] The power-on sequence Verilog code uses a three-stage state machine encoding to implement the functional requirement of controlling the power-on enable signal one by one at each time node in the power-on sequence.

[0079] The reset timing Verilog code uses a simpler counting delay implementation method to meet the control requirements of the reset signal.

[0080] In specific implementation, it can be achieved through Figure 7 The Export function shown in the figure determines the corresponding code output options and generates Verilog code. The module function block diagram of the generated power-on reset timing management module Verilog code is as follows: Figure 8 As shown, the power-on timing management module is generated by the Generate Power-on Timing Management Module option, the reset timing management module is generated by the Generate Reset Management Module option, and the clock frequency division module and the reset signal detection module are inherent and optional modules.

[0081] Finally, a power-on reset timing control code library can be formed, which will include Verilog code and pin constraint description files, etc.

[0082] 103. Automatically configure the CPLD power-on timing according to the Verilog code and pin constraint description file.

[0083] For example, import the Verilog code and pin constraint description file into the compiler to generate a bitstream file for burning onto the board.

[0084] The CPLD power-on sequence automatic configuration method provided in this embodiment automatically generates a basic code framework for the power-on, reset, and restart functions, and fills in the power-on reset signal, in response to the characteristics of the CPLD power-on function, which has relatively simple requirements, relatively fixed code architecture, high work repetitiveness, and relatively high time consumption. This method shortens the code writing cycle, reduces repetition, and reduces workload.

[0085] The CPLD power-on timing automatic configuration method provided in this embodiment is scalable. In addition to realizing functions such as power-on reset, it can also subsequently add code generation functions for simple functions such as level conversion, or generate pin constraint files.

[0086] The CPLD power-on timing automatic configuration method provided in this embodiment uses a unified table to standardize the way hardware engineers describe power-on and reset signals and their timing, thereby improving the communication efficiency between hardware engineers and digital circuit engineers.

[0087] The CPLD power-on timing automatic configuration method provided in this embodiment can describe the power-on and reset timing in a table format and style that is close to the usage habits and actual needs of hardware engineers, thereby lowering the learning threshold and having strong practicality.

[0088] The CPLD power-on timing automatic configuration method provided in this embodiment can generate Verilog code in one click. The operation is simple and easy to learn, and the generation process is simple and intuitive, and the operation can be learned in a short time.

[0089] The code structure generated by the CPLD power-on timing automatic configuration method provided in this embodiment is simple and clear, easy to read, and has good scalability, which makes it easy for digital circuit engineers to modify the code based on the generated code according to the actual needs of the project.

[0090] The Verilog code generated by the CPLD power-on timing automatic configuration method provided in this embodiment can directly replace the files in the library. It only takes a few simple steps to repackage and use it directly in the project.

[0091] The CPLD power-on sequence automatic configuration method provided in this embodiment is a method that uses QT to write script software to generate the basic code framework for power-on, reset, and restart functions, and fill in the power-on reset signal. This method can shorten the code writing cycle and reduce repetitive and simple work. It enables FPGA engineers to generate a power-on project for hardware testing in the shortest time possible, and also allows engineers to focus on the specific functional requirements of the project.

[0092] The CPLD power-on timing automatic configuration method provided in this embodiment can automatically generate a Verilog code with a power-on reset management function that can be directly compiled by extracting information from an input power-on reset timing information table.

[0093] The CPLD power-on sequence automatic configuration method provided in this embodiment can meet the power-on reset management requirements of different projects, and the generated code has high scalability, and the code can be modified according to special requirements.

[0094] The code generated by the CPLD power-on sequence automatic configuration method provided in this embodiment divides power-on and reset management into two modules for management, thereby reducing the complexity of the code and improving the readability and scalability of the code.

[0095] The method for automatically configuring the CPLD power-on sequence provided in this embodiment proposes a method of filling power-on reset information into a table and then having software read the table content to generate code, which conforms to the working habits of hardware engineers and digital circuit engineers and reduces learning costs.

[0096] The CPLD power-on sequence automatic configuration method provided in this embodiment has strong scalability, and the function of generating codes for other functional modules can be added later.

[0097] This embodiment provides a method for automatically configuring the power-on sequence of a CPLD. The method obtains power-on sequence configuration information; generates Verilog code and a pin constraint description file based on the configuration information; and automatically configures the CPLD power-on sequence based on the Verilog code and the pin constraint description file. The engineer responsible for the CPLD software program only needs to provide the configuration information. The method provided in this embodiment generates the Verilog code and the pin constraint description file based on the configuration information, thereby automatically configuring the CPLD power-on sequence and improving configuration efficiency.

[0098] Based on the same inventive concept of the CPLD power-on timing automatic configuration method, this embodiment provides a CPLD power-on timing automatic configuration device, see Figure 9 , the device comprises:

[0099] The acquisition module 901 is used to acquire configuration information of the power-on sequence.

[0100] The generating module 902 is used to generate Verilog code and pin constraint description files according to the configuration information obtained by the obtaining module 901 .

[0101] The configuration module 903 is used to automatically configure the CPLD power-on timing according to the Verilog code and pin constraint description file generated by the generation module 902.

[0102] The configuration information includes: power-on timing description information, reset timing description information and level conversion description information.

[0103] Generate Verilog code based on configuration information, including:

[0104] Generate three copies of Verilog code based on the configuration information.

[0105] The three Verilog codes are: a power-on timing Verilog code corresponding to the power-on timing description information, a reset timing Verilog code corresponding to the reset timing description information, and a level conversion Verilog code corresponding to the level conversion description information.

[0106] Among them, the power-on timing description information includes: ReadySignal, power-on ready signal, power-on time node TimingPoint, power-on enable signal PowerEnableSignal, normal signal ConstantSignal, power-on completion signal PgSignal, external input CPLD reset signal RebootSignal, external input system shutdown signal ShutdownSignal, CPLD internal reset signal InternalReboot, CPLD internal shutdown signal InternalShutdown.

[0107] Among them, RebootSignal and ShutdownSignal both include: a signal name indicating whether the rising edge / falling edge is valid, a pin number, and voltage standard information.

[0108] The reset timing description information includes: a normal reset signal ConstantReset, a reset time node TimingPoint2T0, and a controlled reset signal ResetSignal.

[0109] Among them, ConstantReset, TimingPoint2T0, and ResetSignal all include: signal name, pin number, and voltage value.

[0110] Among them, the power-on sequence Verilog code adopts three-stage state machine encoding.

[0111] The reset timing Verilog code is implemented using counted delay.

[0112] The device provided in this embodiment obtains power-on sequence configuration information; generates Verilog code and a pin constraint description file based on the configuration information; and automatically configures the CPLD power-on sequence based on the Verilog code and the pin constraint description file. The engineer responsible for the CPLD software program only needs to provide the configuration information, and the device provided in this application can generate the Verilog code and the pin constraint description file based on the configuration information, thereby automatically configuring the CPLD power-on sequence and improving configuration efficiency.

[0113] Based on the same inventive concept of the CPLD power-on timing automatic configuration method, this embodiment provides an electronic device, such as Figure 10 As shown, it includes: a memory 1001, a processor 1002, and a computer program.

[0114] The computer program is stored in the memory 1001 and is configured to be executed by the processor 1002 to implement the above-mentioned CPLD power-on timing automatic configuration method.

[0115] Specifically,

[0116] Get the configuration information of the power-on sequence.

[0117] Generate Verilog code and pin constraint description files based on the configuration information.

[0118] Automatically configure the CPLD power-on timing based on Verilog code and pin constraint description files.

[0119] Optionally, the configuration information includes: power-on timing description information, reset timing description information and level conversion description information.

[0120] Generate Verilog code based on configuration information, including:

[0121] Generate three copies of Verilog code based on the configuration information.

[0122] The three Verilog codes are: a power-on timing Verilog code corresponding to the power-on timing description information, a reset timing Verilog code corresponding to the reset timing description information, and a level conversion Verilog code corresponding to the level conversion description information.

[0123] Optionally, the power-on timing description information includes: ReadySignal, power-on ready signal, power-on time node TimingPoint, power-on enable signal PowerEnableSignal, normal signal ConstantSignal, power-on completion signal PgSignal, external input CPLD reset signal RebootSignal, external input system shutdown signal ShutdownSignal, reset signal InternalReboot generated inside the CPLD, and shutdown signal InternalShutdown generated inside the CPLD.

[0124] Optionally, RebootSignal and ShutdownSignal both include: a signal name indicating whether a rising edge or a falling edge is valid, a pin number, and voltage standard information.

[0125] Optionally, the reset timing description information includes: a normal reset signal ConstantReset, a reset time node TimingPoint2T0, and a controlled reset signal ResetSignal.

[0126] Optionally, ConstantReset, TimingPoint2T0, and ResetSignal all include: a signal name, a pin number, and a voltage value.

[0127] Optionally, the power-on sequence Verilog code is encoded using a three-stage state machine.

[0128] The reset timing Verilog code is implemented using counted delay.

[0129] In the electronic device provided by this embodiment, a computer program is executed by a processor to generate Verilog code and a pin constraint description file according to configuration information, thereby realizing automatic configuration of the CPLD power-on timing and improving configuration efficiency.

[0130] Based on the same inventive concept of the CPLD power-on timing automatic configuration method, this embodiment provides a computer-readable storage medium having a computer program stored thereon. The computer program is executed by a processor to implement the above-mentioned CPLD power-on timing automatic configuration method.

[0131] Specifically,

[0132] Get the configuration information of the power-on sequence.

[0133] Generate Verilog code and pin constraint description files based on the configuration information.

[0134] Automatically configure the CPLD power-on timing based on Verilog code and pin constraint description files.

[0135] Optionally, the configuration information includes: power-on timing description information, reset timing description information and level conversion description information.

[0136] Generate Verilog code based on configuration information, including:

[0137] Generate three copies of Verilog code based on the configuration information.

[0138] The three Verilog codes are: a power-on timing Verilog code corresponding to the power-on timing description information, a reset timing Verilog code corresponding to the reset timing description information, and a level conversion Verilog code corresponding to the level conversion description information.

[0139] Optionally, the power-on timing description information includes: ReadySignal, power-on ready signal, power-on time node TimingPoint, power-on enable signal PowerEnableSignal, normal signal ConstantSignal, power-on completion signal PgSignal, external input CPLD reset signal RebootSignal, external input system shutdown signal ShutdownSignal, reset signal InternalReboot generated inside the CPLD, and shutdown signal InternalShutdown generated inside the CPLD.

[0140] Optionally, RebootSignal and ShutdownSignal both include: a signal name indicating whether a rising edge or a falling edge is valid, a pin number, and voltage standard information.

[0141] Optionally, the reset timing description information includes: a normal reset signal ConstantReset, a reset time node TimingPoint2T0, and a controlled reset signal ResetSignal.

[0142] Optionally, ConstantReset, TimingPoint2T0, and ResetSignal all include: a signal name, a pin number, and a voltage value.

[0143] Optionally, the power-on sequence Verilog code is encoded using a three-stage state machine.

[0144] The reset timing Verilog code is implemented using counted delay.

[0145] The computer-readable storage medium provided in this embodiment has a computer program on it that is executed by a processor to generate Verilog code and a pin constraint description file according to configuration information, thereby realizing automatic configuration of the CPLD power-on timing and improving configuration efficiency.

[0146] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiment of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal translation scripting language JavaScript, etc.

[0147] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0148] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0149] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0150] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0151] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for automatically configuring a CPLD power-on sequence, characterized in that: The method comprises: Get the configuration information of the power-on sequence; Generate Verilog code and pin constraint description file according to the configuration information; Automatically configure the CPLD power-on timing according to the Verilog code and the pin constraint description file; The configuration information includes: power-on timing description information, reset timing description information and level conversion description information; Generating Verilog code according to the configuration information includes: Generate three copies of Verilog code according to the configuration information; The three Verilog codes are: a power-on timing Verilog code corresponding to the power-on timing description information, a reset timing Verilog code corresponding to the reset timing description information, and a level conversion Verilog code corresponding to the level conversion description information.

2. The method according to claim 1, characterized in that The power-on timing description information includes: ReadySignal, power-on ready signal, power-on time node TimingPoint, power-on enable signal PowerEnableSignal, normal signal ConstantSignal, power-on completion signal PgSignal, external input CPLD reset signal RebootSignal, external input system shutdown signal ShutdownSignal, reset signal InternalReboot generated inside the CPLD, and shutdown signal InternalShutdown generated inside the CPLD.

3. The method according to claim 2, characterized in that The RebootSignal and ShutdownSignal both include: a signal name indicating whether the rising edge / falling edge is valid, a pin number, and voltage standard information.

4. The method according to claim 1, wherein The reset timing description information includes: a normal reset signal ConstantReset, a reset time node TimingPoint2T0, and a controlled reset signal ResetSignal.

5. The method according to claim 4, characterized in that The ConstantReset, TimingPoint2T0, and ResetSignal all include: signal name, pin number, and voltage value.

6. The method according to claim 1, characterized in that The power-on sequence Verilog code is encoded using a three-stage state machine; The reset timing Verilog code adopts a counting delay implementation method.

7. An electronic device, characterized in that: include: Memory; processor; as well as computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that A computer program is stored thereon; the computer program is executed by a processor to implement the method according to any one of claims 1 to 6.

Images