GPU task scheduling method and device, electronic equipment, storage medium and program product

Abstract

The invention relates to a GPU task scheduling method and device, electronic equipment, a storage medium and a program product. The GPU comprises a plurality of groups of module control circuits, and the plurality of groups of module control circuits are used for connecting a plurality of calculation modules in the GPU; the method is applied to a scheduler of the GPU, and the scheduler is arranged at the front end of the GPU. The method comprises the following steps: in response to a received to-be-processed task issued by a driving program, analyzing the to-be-processed task to obtain a task analysis result of the to-be-processed task; obtaining load information of the plurality of calculation modules through the module control circuits corresponding to the plurality of calculation modules; determining a target calculation module from the plurality of calculation modules according to the task analysis result and the load information; and issuing the to-be-processed task to the target calculation module through a module control circuit corresponding to the target calculation module.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a GPU task scheduling method, a GPU task scheduling device, an electronic device, a computer-readable storage medium, and a computer program product. Background Art

[0002] GPU (Graphics Processing Unit) is a processor specially designed for graphics rendering and image processing. It is the core component of the graphics card and is responsible for outputting display graphics. Similar to the CPU, the GPU also has computing power, but it is more focused on performing complex mathematical and geometric calculations, which are necessary for graphics rendering. Therefore, the GPU has more powerful parallel processing capabilities and can accelerate application scenarios such as image rendering, physical simulation, and deep learning. The GPU contains various fixed pipelines as well as various programmable computing modules.

[0003] In the design of modern GPUs, the application of schedulers and front-end designs significantly simplifies the driver writing process and improves the efficiency of hardware use. However, as the scale of GPU chips continues to expand and the chip design cycle continues to shorten, chip scalability design has gradually become an important consideration.

[0004] Currently, the scheduling strategy still has significant deficiencies in cooperating with modular design to achieve scalability. Specifically, every time a GPU chip adopts a modular stacking design, the front-end design often needs to be readjusted to adapt to the scheduling requirements after different modules are stacked, because the scheduling strategy is not well matched with the modular design. This frequent adjustment not only increases the complexity of driver software writing, but also prolongs the development cycle. Summary of the invention

[0005] The present invention provides a technical solution for GPU task scheduling.

[0006] According to one aspect of the present disclosure, a task scheduling method for a GPU is provided, wherein the GPU comprises a plurality of groups of module control circuits, and the plurality of groups of module control circuits are used to connect a plurality of computing modules in the GPU; the method is applied to a scheduler of the GPU, and the scheduler is arranged at a front end of the GPU; the method comprises:

[0007] In response to receiving the pending task sent by the driver, parsing the pending task to obtain a task parsing result of the pending task;

[0008] Obtaining load information of the multiple computing modules through module control circuits corresponding to the multiple computing modules;

[0009] Determine a target computing module from the plurality of computing modules according to the task analysis result and the load information;

[0010] The task to be processed is sent to the target computing module through a module control circuit corresponding to the target computing module.

[0011] In a possible implementation, the method further includes:

[0012] Obtaining configuration information of a computing module in the GPU;

[0013] According to the configuration information, an upper limit number of computing modules supported by the scheduler is configured.

[0014] In a possible implementation, the method further includes:

[0015] Deleting or reconnecting to zero the module control circuits in the GPU that are not connected to the computing modules;

[0016] and / or,

[0017] The module control circuits of the GPU that are not connected to the computing modules are left unconnected and marked as unavailable.

[0018] In a possible implementation, the method further includes:

[0019] In response to the GPU being powered on and initialized, obtaining a usability test result of a computing module in the GPU;

[0020] According to the availability test result, unavailable computing modules in the GPU are shielded.

[0021] In one possible implementation,

[0022] The obtaining load information of the plurality of computing modules through the module control circuits corresponding to the plurality of computing modules comprises: obtaining load information of the available computing modules through the module control circuits corresponding to the available computing modules in the GPU;

[0023] Determining a target computing module from the multiple computing modules according to the task analysis result and the load information includes: determining a target computing module from the available computing modules according to the task analysis result and the load information.

[0024] In one possible implementation,

[0025] The determining, from the plurality of computing modules, a target computing module according to the task analysis result and the load information, comprises: dividing the task to be processed according to the task analysis result to obtain at least two subtasks corresponding to the task to be processed; determining, from the plurality of computing modules, a target computing module corresponding to the at least two subtasks according to the load information;

[0026] The sending the to-be-processed task to the target computing module through a module control circuit corresponding to the target computing module includes: sending the subtasks to the target computing module in parallel through a module control circuit corresponding to the target computing module.

[0027] In a possible implementation, the scheduler schedules different tasks to be processed based on a preset dynamic load balancing strategy;

[0028] The preset dynamic load balancing strategy includes at least one of the following: a dynamic load balancing strategy based on priority, a dynamic load balancing strategy based on time slices, and a dynamic load balancing strategy based on resource isolation;

[0029] Wherein, the priority-based dynamic load balancing strategy includes allocating computing resources to tasks with higher priority to be processed first;

[0030] The time slice-based dynamic load balancing strategy includes allocating a corresponding time slice to each task to be processed, and switching to the next task to be processed when the time slice corresponding to any task to be processed is exhausted;

[0031] The dynamic load balancing strategy based on resource isolation includes allocating independent computing resources to different users or tasks to be processed.

[0032] According to one aspect of the present disclosure, a task scheduling device for a GPU is provided, wherein the GPU comprises a plurality of groups of module control circuits, wherein the plurality of groups of module control circuits are used to connect a plurality of computing modules in the GPU; the device is applied to a scheduler of the GPU, and the scheduler is arranged at a front end of the GPU; the device comprises:

[0033] The parsing module is used for parsing the pending tasks in response to receiving the pending tasks sent by the driver, and obtaining the task parsing results of the pending tasks;

[0034] A first obtaining module, configured to obtain load information of the plurality of computing modules through module control circuits corresponding to the plurality of computing modules;

[0035] A determination module, configured to determine a target computing module from the plurality of computing modules according to the task analysis result and the load information;

[0036] The sending module is used to send the to-be-processed task to the target computing module through the module control circuit corresponding to the target computing module.

[0037] In a possible implementation manner, the device further includes:

[0038] A second obtaining module is used to obtain configuration information of a computing module in the GPU;

[0039] A configuration module is used to configure the upper limit number of computing modules supported by the scheduler according to the configuration information.

[0040] In a possible implementation manner, the device further includes a disconnected computing module processing module, and the disconnected computing module processing module is configured to:

[0041] Deleting or reconnecting to zero the module control circuits in the GPU that are not connected to the computing modules;

[0042] and / or,

[0043] The module control circuits of the GPU that are not connected to the computing modules are left unconnected and marked as unavailable.

[0044] In a possible implementation manner, the device further includes:

[0045] A third obtaining module is used to obtain the availability test result of the computing module in the GPU in response to the power-on initialization of the GPU;

[0046] A shielding module is used to shield unavailable computing modules in the GPU according to the availability test result.

[0047] In one possible implementation,

[0048] The first obtaining module is used to: obtain the load information of the available computing modules in the GPU through the module control circuit corresponding to the available computing modules;

[0049] The determination module is used to determine a target computing module from the available computing modules according to the task analysis result and the load information.

[0050] In one possible implementation,

[0051] The determination module is used to: divide the task to be processed according to the task analysis result to obtain at least two subtasks corresponding to the task to be processed; and determine the target computing modules corresponding to the at least two subtasks from the multiple computing modules according to the load information;

[0052] The sending module is used to send the subtasks to the target computing module in parallel through the module control circuit corresponding to the target computing module.

[0053] In a possible implementation, the scheduler schedules different tasks to be processed based on a preset dynamic load balancing strategy;

[0054] The preset dynamic load balancing strategy includes at least one of the following: a dynamic load balancing strategy based on priority, a dynamic load balancing strategy based on time slices, and a dynamic load balancing strategy based on resource isolation;

[0055] Wherein, the priority-based dynamic load balancing strategy includes allocating computing resources to tasks with higher priority to be processed first;

[0056] The time slice-based dynamic load balancing strategy includes allocating a corresponding time slice to each task to be processed, and switching to the next task to be processed when the time slice corresponding to any task to be processed is exhausted;

[0057] The dynamic load balancing strategy based on resource isolation includes allocating independent computing resources to different users or tasks to be processed.

[0058] According to one aspect of the present disclosure, an electronic device is provided, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0059] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0060] According to one aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0061] In the disclosed embodiment, the GPU includes multiple groups of module control circuits, which are used to connect multiple computing modules in the GPU. The scheduler set at the front end of the GPU responds to the task to be processed sent by the driver, parses the task to be processed, obtains the task parsing result of the task to be processed, obtains the load information of the multiple computing modules through the module control circuits corresponding to the multiple computing modules, determines the target computing module from the multiple computing modules according to the task parsing result and the load information, and sends the task to be processed to the target computing module through the module control circuit corresponding to the target computing module, thereby realizing dynamic load balancing in the scheduler of the GPU, which can more effectively improve the utilization rate of the computing modules of the GPU. In the disclosed embodiment, the task allocation can be dynamically adjusted according to the real-time load conditions of each computing module, so that the computing resources of the GPU are fully utilized, thereby improving the overall computing efficiency.

[0062] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

[0063] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0065] Figure 1 A flowchart of a GPU task scheduling method provided by an embodiment of the present disclosure is shown.

[0066] Figure 2 A schematic diagram of a GPU pre-scheduling design provided by an embodiment of the present disclosure is shown.

[0067] Figure 3 A block diagram of a task scheduling device for a GPU provided in an embodiment of the present disclosure is shown.

[0068] Figure 4 A block diagram of an electronic device 1900 provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0069] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0070] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0071] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0072] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0073] The disclosed embodiment provides a task scheduling method for a GPU, wherein the GPU includes a plurality of groups of module control circuits, wherein the plurality of groups of module control circuits are used to connect a plurality of computing modules in the GPU, and the method is applied to a scheduler of the GPU, and the scheduler is arranged at the front end of the GPU. In response to receiving a task to be processed issued by a driver, the task to be processed is parsed to obtain a task parsing result of the task to be processed, and the load information of the plurality of computing modules is obtained through the module control circuits corresponding to the plurality of computing modules. According to the task parsing result and the load information, a target computing module is determined from the plurality of computing modules, and the module control circuit corresponding to the target computing module is used to issue the task to be processed to the target computing module, thereby realizing dynamic load balancing in the scheduler of the GPU, and being able to more effectively improve the utilization rate of the computing modules of the GPU. In the disclosed embodiment, the task allocation can be dynamically adjusted according to the real-time load conditions of each computing module, so that the computing resources of the GPU are fully utilized, thereby improving the overall computing efficiency.

[0074] In addition, in the disclosed embodiment, the scheduler is set at the front end, that is, dynamic load balancing is implemented in the front end, thereby making the driver software development process simpler. This design reduces the workload of adapting to different chip sizes. GPU chips of different sizes of the same generation architecture can use the same set of chip design codes of the scheduling front end and the same set of driver software codes, thereby saving development time for R&D personnel and reducing the complexity of development and maintenance.

[0075] Furthermore, the embodiments of the present disclosure use modular design to make the GPU chip design highly scalable, so that GPU chips of different sizes can be flexibly customized according to application scenarios, thereby expanding the use scenarios of the GPU chips.

[0076] The following is a detailed description of the GPU task scheduling method provided by the embodiments of the present disclosure in conjunction with the accompanying drawings.

[0077] Figure 1 A flowchart of a task scheduling method for a GPU provided in an embodiment of the present disclosure is shown. In one possible implementation, the execution subject of the task scheduling method for the GPU may be a task scheduling device of the GPU. For example, the task scheduling method for the GPU may be executed by a terminal device or a server or other electronic device. Among them, the terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device or a wearable device, etc. In some possible implementations, the task scheduling method for the GPU may be implemented by a processor calling computer-readable instructions stored in a memory. In an embodiment of the present disclosure, the GPU includes a plurality of groups of module control circuits, and the plurality of groups of module control circuits are used to connect a plurality of computing modules in the GPU; the method is applied to a scheduler of the GPU, and the scheduler is arranged at the front end of the GPU. As Figure 1 As shown, the GPU task scheduling method includes steps S11 to S14.

[0078] In step S11, in response to receiving the to-be-processed task sent by the driver, the to-be-processed task is parsed to obtain a task parsing result of the to-be-processed task.

[0079] In step S12, load information of the multiple computing modules is obtained through module control circuits corresponding to the multiple computing modules.

[0080] In step S13, a target computing module is determined from the multiple computing modules according to the task analysis result and the load information.

[0081] In step S14, the task to be processed is sent to the target computing module through the module control circuit corresponding to the target computing module.

[0082] In the disclosed embodiments, the scheduler may represent a component in the GPU that is responsible for managing and allocating tasks to computing modules. The core functions of the scheduler may include processing interdependencies and priorities between tasks, so that system resources are reasonably allocated and effectively utilized, thereby improving the overall performance and response speed of the system.

[0083] In the disclosed embodiment, the front end may represent a driver software-oriented encapsulation of hardware functions, which may be understood as an interface between the driver program and the GPU hardware, and is used to simplify the writing of the driver program and improve the efficiency of the use of hardware resources.

[0084] In the disclosed embodiments, the GPU may adopt a modular stacking design, that is, the GPU may be composed of multiple computing modules, each of which may contain a certain number of computing cores. By increasing or decreasing the number of computing modules, GPUs of different sizes and performances may be designed to meet different market demands and application scenarios. For example, in order to manufacture a high-performance GPU, more computing modules may be stacked on the GPU chip; while for applications with limited power consumption and space (such as mobile devices), fewer computing modules may be used.

[0085] In the disclosed embodiment, the GPU includes multiple groups of module control circuits, wherein the module control circuit may represent a circuit for controlling a computing module. The module control circuit may be arranged outside or inside the scheduler, which is not limited here. The module control circuit may serve as a communication interface between the scheduler and the computing module, and may be responsible for sending tasks to the computing module, obtaining load information of the computing module, and so on.

[0086] In a possible implementation, the number of module control circuits reserved in the general design phase of the GPU is greater than or equal to the number of module control circuits reserved in the implementation design phase of the GPU.

[0087] In this implementation, the number of module control circuits in the GPU during the general design stage and the integrated design stage of the GPU may be greater than or equal to the number of module control circuits reserved during the implementation design stage of the GPU. For example, during the general design stage of the GPU, 128 groups of module control circuits may be reserved in the GPU. Of course, the number of module control circuits reserved in the GPU may be adjusted according to the specific GPU architecture and is not limited here.

[0088] For example, during the implementation design phase, if a high-performance, large-scale GPU needs to be designed, a modular approach can be used to configure 128 computing modules in the GPU, and 128 sets of module control circuits can be retained. The control signals and status signals of the computing modules can be connected to the module control circuits. In this way, all computing modules can be managed and controlled by the scheduler. The scheduler can query the operating status of each computing module in real time, and use a dynamic load balancing algorithm to optimize the computing load of the GPU to achieve balanced task distribution for each computing module.

[0089] For example, during the implementation design phase, when designing a miniaturized GPU for an in-vehicle system or mobile device, 16 computing modules can be configured modularly, and the 16 computing modules can be connected to 16 groups of module control circuits respectively. In this case, in addition to these 16 groups of module control circuits, other module control circuits can be deleted or connected to 0, or can remain inactive and marked as unavailable to adapt to the performance requirements and power consumption limitations of different products. Through this flexible modular design, GPUs of appropriate sizes can be customized for different application scenarios while maintaining efficient task scheduling and management.

[0090] Of course, different numbers of module control circuits may be reserved for different application scenarios during the general design phase, which is not limited here.

[0091] In this implementation, a sufficient number of module control circuits are reserved in the general design stage of the GPU, so that during the implementation design stage of the GPU, no matter how many module control circuits are chosen to be retained, the scheduling front end can adapt and work normally. This design idea enhances the flexibility of chip design, allowing the GPU to be modularly stacked and expanded according to different needs and scenarios, thereby meeting a wider range of application needs. By adopting a scalable design, the development and verification cycle of various scale models in GPU chip design can be reduced. In this way, the process from design to productization is more efficient, which helps to shorten the time to market.

[0092] In one possible implementation, any module control circuit is connected to at most one computing module. By adopting this implementation, the connection between each module control circuit and the computing module can be made clearer and simpler. Each module control circuit focuses on managing the computing module connected to it, without having to deal with the complex interactions of multiple computing modules, thereby improving the stability and reliability of the system. In addition, since each module control circuit is only connected to one computing module, the system is more flexible in resource allocation and task scheduling. The scheduler can dynamically assign tasks to computing modules with lighter loads according to the real-time load conditions of each computing module, thereby achieving load balancing and improving the overall performance of the system. In addition, this design method also helps to reduce the power consumption of the system. Since each module control circuit is only responsible for one computing module, the power consumption of the computing module can be accurately controlled to avoid unnecessary energy waste. This is particularly important for mobile devices or low-power application scenarios.

[0093] In other possible implementations, the module control circuit and the computing module may also be in a one-to-many or many-to-one relationship, which is not limited here.

[0094] In a possible implementation, the method further includes: obtaining configuration information of a computing module in the GPU; and configuring an upper limit number of computing modules supported by the scheduler according to the configuration information.

[0095] In this implementation, during the design phase of the GPU, the configuration information of the computing modules in the GPU can be obtained. The configuration information of the computing modules may include the number, type, performance, etc. of the computing modules, which are not limited here. Based on the configuration information of the computing modules, the upper limit of the number of computing modules supported by the scheduler can be configured so that the scheduler will not be unable to manage all the computing modules due to too low configuration. By adopting this implementation, it is possible to adapt to different computing module configurations and improve the flexibility and adaptability of the GPU.

[0096] In this implementation, each computing module can also be correctly and effectively connected to the scheduler by checking and adjusting the design. In addition to the physical connection, the scheduler is also logically configured correctly to manage and schedule these computing modules. This means that the scheduler needs to understand and identify each computing module connected to it and be able to schedule these computing modules to work as needed.

[0097] In one possible implementation, the method further includes: deleting or connecting to zero the module control circuit in the GPU that is not connected to the computing module; and / or leaving the module control circuit in the GPU that is not connected to the computing module empty and marking it as unavailable.

[0098] As an example of this implementation, the module control circuit that is not connected to the computing module in the GPU may be deleted or connected to zero.

[0099] In one example, the module control circuits that are not connected to the computing modules in the GPU can be deleted. In this example, if it is determined that these module control circuits that are not connected to the computing modules are not necessary for the overall function of the GPU, or their existence may cause resource waste or performance degradation, these module control circuits can be completely deleted from the design.

[0100] In another example, for the module control circuit of the GPU that is not connected to the computing module, a connect-0 processing can be performed, that is, the module control circuit that is not connected to the computing module is set to a default or invalid state so that the module control circuit that is not connected to the computing module does not interfere with other parts of the GPU.

[0101] In this example, by deleting the module control circuit that is not connected to the computing module, unnecessary hardware components can be reduced, and the hardware resources originally occupied by these module control circuits can be released, so that the GPU can use these resources more efficiently. By performing a 0-processing on the module control circuit that is not connected to the computing module, it can be temporarily placed in an invalid state without deleting the module control circuit that is not connected to the computing module, thereby avoiding a comprehensive modification of the design and additional verification work. In addition, by deleting or 0-processing the module control circuit that is not connected to the computing module, the power consumption and heat generation of the GPU can be reduced, thereby improving its performance and stability. In addition, the optimized design may reduce data transmission delays and errors, and further improve computing efficiency. In addition, cleaning up the unconnected module control circuit can make the design of the GPU more concise and clear, reduce the complexity of the design and the possibility of errors, and also facilitate subsequent maintenance and upgrade work.

[0102] As another example of this implementation, the module control circuit of the GPU that is not connected to the computing module may be left idle and marked as unavailable.

[0103] Among them, hanging can refer to removing the module control circuits that are not connected to the computing module from the normal workflow, so that they do not participate in any data transmission tasks. This can be achieved by modifying the internal connection or configuration of the GPU. In this implementation, in addition to hanging the module control circuits that are not connected to the computing module, these module control circuits can also be marked as unavailable in the configuration information or internal state of the GPU. In this way, whether it is the GPU scheduler or other management modules, they can recognize that these module control circuits are in an inactive state and will not try to use them.

[0104] The module control circuit that is not connected to the computing module may generate an erroneous output or an interference signal due to various reasons (such as circuit failure, external noise, etc.). In this implementation, by hanging the module control circuit that is not connected to the computing module in the GPU and marking it as unavailable, the errors and interference caused by these potential problems can be reduced, and the stability and reliability of the GPU can be improved. In addition, by marking the module control circuit that is not connected to the computing module as unavailable, the scheduler and other management modules of the GPU can manage the resources of the GPU more simply. They do not need to consider the existence of these unavailable module control circuits, thereby simplifying the process of resource allocation and task scheduling. Furthermore, hanging the module control circuit that is not connected to the computing module and marking it as unavailable does not mean that these module control circuits are permanently deleted or discarded. In future GPU upgrades or expansions, if it is necessary to add new computing modules or reuse these module control circuits, the hanging state can be easily released and reconfigured.

[0105] In one possible implementation, after the GPU chip is manufactured, that is, after the tape-out is completed, the defective computing modules can be shielded through the configuration logic of the scheduler according to the actual test results of the computing modules, so that the GPU can avoid using those defective modules that may cause errors or performance degradation when working, thereby improving the overall performance and stability of the GPU. As an example of this implementation, after the GPU tape-out is completed, a series of tests can be performed to evaluate the performance and accuracy of each computing module. If a computing module is found to have defects, such as calculation errors, response delays, or stability problems, these defective computing modules can be removed from the list of available resources or marked as unavailable according to the test results and configuration logic.

[0106] In a possible implementation, the method further includes: in response to power-on initialization of the GPU, obtaining availability test results of computing modules in the GPU; and shielding unavailable computing modules in the GPU according to the availability test results.

[0107] In this implementation, the GPU can be initialized after power-on, wherein the initialization may involve resetting and initializing various modules and components inside the GPU so that they are in a correct working state. After the GPU is powered on and initialized, the availability test can be performed on each computing module in the GPU to obtain the availability test results of each computing module. According to the availability test results of each computing module in the GPU, the unavailable computing modules can be shielded, thereby avoiding the assignment of tasks to computing modules that are defective or malfunctioning. Therefore, by shielding the unavailable computing modules, the stability and accuracy of the overall calculation can be improved. Moreover, by adopting this implementation, it is helpful to control costs and improve the yield of products, thereby improving product quality.

[0108] In the disclosed embodiment, the scheduler may parse the task data packet in response to receiving the pending task sent by the driver, and obtain the task parsing result of the pending task. The task parsing result of the pending task may include the scale information, type information, etc. of the pending task, which is not limited here. The scale information of the pending task may include the calculation amount, memory requirement, etc. of the pending task. In addition, the scheduler may be equivalent to receiving the pending task sent by the driver, and obtaining the load information of each computing module through the module control circuit corresponding to each computing module. The load information may include the utilization rate of the computing module, the memory occupancy rate, the number of tasks currently processed, etc. These indicators may reflect the current working state of the computing module and the ability to process new tasks. After obtaining the load information of each computing module, the scheduler may determine the target computing module from each computing module in combination with the task parsing result according to the preset dynamic load balancing strategy, and send the pending task to the target computing module through the module control circuit corresponding to the target computing module. The target computing module may represent the computing module that is most suitable for executing the current pending task, which usually has enough idle resources to process the new task and meets the performance, accuracy or other requirements of the task.

[0109] In a possible implementation, obtaining the load information of the multiple computing modules through the module control circuits corresponding to the multiple computing modules includes: obtaining the load information of the available computing modules through the module control circuits corresponding to the available computing modules in the GPU; determining the target computing module from the multiple computing modules according to the task analysis result and the load information includes: determining the target computing module from the available computing modules according to the task analysis result and the load information. In this implementation, the scheduler can determine the target computing module from the available computing modules, thereby improving the efficiency of determining the target computing module.

[0110] In a possible implementation, determining a target computing module from the multiple computing modules based on the task analysis result and the load information includes: dividing the task to be processed according to the task analysis result to obtain at least two subtasks corresponding to the task to be processed; determining the target computing module corresponding to the at least two subtasks from the multiple computing modules according to the load information; and sending the task to be processed to the target computing module through a module control circuit corresponding to the target computing module includes: sending the subtasks to the target computing module in parallel through a module control circuit corresponding to the target computing module.

[0111] In this implementation, a more complex task to be processed can be decomposed into multiple smaller, independently executable subtasks so that these subtasks can be executed in parallel on different computing modules. Through parallel computing, computing resources can be fully utilized, computing time can be shortened, and overall performance can be improved.

[0112] For example, in general computing, tasks that can be executed in the same computing module can be divided into a group according to the workgroup parameter. In this way, tasks in each group can be executed in parallel, and tasks in different groups can be assigned to different computing modules. By grouping tasks based on the workgroup parameter, tasks can be reasonably allocated on the computing modules to avoid resource waste and performance bottlenecks. Among them, a workgroup can represent a group of tasks or threads that can be executed in parallel in the same computing module.

[0113] In graphics rendering, the entire rendering window can be divided into tiles, and each tile corresponds to a part of the rendering task. The shader tasks associated with these tiles (i.e., shader tasks in graphics rendering) can be dispatched to different computing modules for processing. Since the rendering tasks of different tiles can be executed independently, by assigning them to different computing modules, parallel processing of graphics rendering can be achieved, thereby improving rendering speed and efficiency. Among them, in graphics rendering, a tile can refer to a small, regular area of ​​the rendering window.

[0114] In this implementation, efficient execution of computing tasks is achieved by adopting means such as task division, parallel scheduling, and dynamic load balancing. This not only improves the utilization of computing resources, but also significantly improves the overall computing performance, providing strong support for various complex computing tasks.

[0115] In one possible implementation, the scheduler schedules different pending tasks based on a preset dynamic load balancing strategy; wherein the preset dynamic load balancing strategy includes at least one of the following: a priority-based dynamic load balancing strategy, a time slice-based dynamic load balancing strategy, and a resource isolation-based dynamic load balancing strategy; wherein the priority-based dynamic load balancing strategy includes preferentially allocating computing resources to pending tasks with higher priorities; the time slice-based dynamic load balancing strategy includes allocating corresponding time slices to each pending task, and switching to the next pending task when the time slice corresponding to any pending task is exhausted; the resource isolation-based dynamic load balancing strategy includes allocating independent computing resources to different users or pending tasks.

[0116] In this implementation, the scheduler can implement at least one dynamic load balancing algorithm through firmware or dedicated circuits, and determine whether a new task can be scheduled or whether the context of an existing task needs to be switched based on the load information of the computing module obtained. Since the firmware can be modified, the dynamic load balancing strategy can be adjusted according to the actual application scenario requirements.

[0117] As an example of this implementation, the preset dynamic load balancing strategy may include a priority-based dynamic load balancing strategy. In this example, computing resources may be allocated according to the priority of the task. If there are idle computing modules, high-priority tasks may be preferentially allocated to these computing modules. However, when all computing modules are in a non-idle state, the scheduler may query the currently running tasks. If it is found that low-priority tasks are being executed, context switching may be performed to schedule high-priority tasks to these computing modules so that high-priority tasks can be executed as quickly as possible and produce results.

[0118] As an example of this implementation, the preset dynamic load balancing strategy may include a dynamic load balancing strategy based on time slices. The dynamic load balancing strategy based on time slices can be implemented by accurately counting and calculating the running time of each computing module when processing a specific task group. When the running time of a task of an application reaches its preset time slice, these tasks will be switched out of the computing module, and tasks of other applications will be scheduled in. In this way, each application can evenly and efficiently use the resources of the computing module within the time slice, avoiding excessive concentration or idleness of computing resources.

[0119] As an example of this implementation, the preset dynamic load balancing strategy may include a dynamic load balancing strategy based on resource isolation. In a virtualized or container-isolated environment, a dynamic load balancing strategy based on resource isolation may be adopted. That is, corresponding computing resources may be dynamically allocated to different users. If the quota resources of a user's computing module are exhausted, the scheduler may limit its use of other computing modules so that each user can only use its allocated resources, thereby achieving effective isolation of resources and dynamic load balancing scheduling.

[0120] In this implementation, through the comprehensive use of priority-based dynamic load balancing strategy, time slice-based dynamic load balancing strategy, and resource isolation-based dynamic load balancing strategy, computing resources can be managed more intelligently and efficiently to meet the needs of different tasks and applications, thereby making the entire system run stably and efficiently.

[0121] In a possible implementation, the computing module can feed back the various resource usage of the computing module itself to the scheduler according to the requirements of the scheduling algorithm. That is, the computing module not only executes tasks, but also collects and reports its own resource usage in real time or regularly, such as usage rate, memory usage, temperature, power consumption, etc. These resource usage information is crucial for the scheduler, because it needs to evaluate the load of the computing module based on this information to make reasonable task allocation decisions. Feedback on resource usage helps the scheduler understand the working status and capabilities of each computing module. For example, if the usage rate of a computing module is already very high, the scheduler may avoid assigning more computing-intensive tasks to the computing module to avoid overload or performance degradation. On the contrary, if the resource usage of a computing module is relatively loose, the scheduler may be more inclined to assign new tasks to it. In a possible implementation, any computing module can respond to the completion of any task and feed back task completion information to the scheduler. In this implementation, when the task is completed, the computing module can inform the scheduler by interruption or status feedback. Among them, interruption is a hardware-level communication mechanism used to notify the system that an event has occurred. In this implementation, the computing module can trigger an interrupt when the task is completed to inform the scheduler that the task has been completed. Status feedback can be a software-level communication method. The computing module tells the scheduler the status of the task by updating its status information or sending a message. Through this feedback mechanism, the scheduler can know which computing modules are idle, so that new tasks can be assigned to these computing modules.

[0122] The GPU task scheduling method provided in the embodiments of the present disclosure can be applied to technical fields such as GPU, scheduler, front end, dynamic load balancing, and chip scalable design, and is not limited here.

[0123] The following describes a specific application scenario to illustrate the GPU task scheduling method provided by the embodiment of the present disclosure. Figure 2 A schematic diagram of a GPU pre-scheduling design provided by an embodiment of the present disclosure is shown. Figure 2 As shown, the scheduler is arranged at the front end of the GPU. The GPU includes multiple groups of module control circuits, and the module control circuits are used to connect the computing modules.

[0124] 1. Design stage

[0125] 1. General design stage

[0126] In the general design stage of the GPU, a sufficient number of module control circuits may be reserved in the GPU, for example, 128 groups of module control circuits may be reserved in the GPU.

[0127] 2. Landing design stage

[0128] During the implementation design phase of the GPU, the upper limit of the number of computing modules supported by the scheduler can be configured according to the number of computing modules in the GPU, and the module control circuits that are not connected to the computing modules can be deleted or connected to zero.

[0129] 2. Configuration Phase

[0130] In response to the GPU power-on initialization, the availability test results of the computing modules in the GPU are obtained, and according to the availability test results, the unavailable computing modules in the GPU are shielded. The module control circuits of the GPU that are not connected to the available computing modules can also be left unconnected and marked as unavailable.

[0131] 3. Task Scheduling Phase

[0132] After the driver sends multiple pending tasks to the scheduler, the scheduler can decide how to allocate these pending tasks to the computing modules in the GPU based on a series of rules and strategies to ensure maximum resource utilization and efficient execution of tasks.

[0133] First, the scheduler can parse the task data packets of each pending task separately to obtain the scale information of the pending task, such as the amount of calculation, memory requirements, etc. Then, the scheduler can query the currently available computing modules and determine the priority and running weight of each pending task according to the scheduling algorithm logic. Among them, the priority and running weight can be determined based on the urgency, importance, size or other business rules of the task.

[0134] The scheduler can send pending tasks to currently idle computing modules according to the priority and running weight of the pending tasks. Among them, the idle computing modules may refer to computing modules that currently have no tasks to execute or whose task queues are not full. If all computing modules are busy and there are additional pending tasks that cannot be sent immediately, the scheduler can put these pending tasks into the waiting queue. When a new computing module becomes idle, the scheduler can send the pending tasks again according to the priority of the pending tasks in the waiting queue. This ensures that high-priority pending tasks are executed first. The scheduler can continuously monitor the usage of computing modules to ensure that the GPU computing module usage rate is as high as possible to avoid resource waste.

[0135] If the new and old tasks have different priorities, and the old task has a higher priority or the two have the same priority, the scheduler can send the new task directly to the idle computing module, and wait for the old task to complete before sending the remaining part of the new task to the idle computing module. If the priority of the new task is higher than that of the old task, the scheduler can take some additional measures, such as pausing or switching out some of the old tasks from the computing module to release enough resources to meet the needs of the new task. Once the high-priority new task is completed, the scheduler can try to context switch the old task on the computing module to restore its previous running state.

[0136] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0137] In addition, the present disclosure also provides a GPU task scheduling device, an electronic device, a computer-readable storage medium, and a computer program product, all of which can be used to implement any GPU task scheduling method provided by the present disclosure. The corresponding technical solutions and technical effects can be found in the corresponding records in the method part and will not be repeated here.

[0138] Figure 3 A block diagram of a task scheduling device for a GPU provided by an embodiment of the present disclosure is shown. The GPU includes multiple groups of module control circuits, and the multiple groups of module control circuits are used to connect multiple computing modules in the GPU; the device is applied to the scheduler of the GPU, and the scheduler is set at the front end of the GPU. Figure 3 As shown, the task scheduling device of the GPU includes:

[0139] The parsing module 31 is used for parsing the pending tasks in response to receiving the pending tasks sent by the driver, and obtaining the task parsing results of the pending tasks;

[0140] A first obtaining module 32, configured to obtain load information of the plurality of computing modules through module control circuits corresponding to the plurality of computing modules;

[0141] A determination module 33, configured to determine a target computing module from the plurality of computing modules according to the task analysis result and the load information;

[0142] The sending module 34 is used to send the to-be-processed task to the target computing module through the module control circuit corresponding to the target computing module.

[0143] In a possible implementation manner, the device further includes:

[0144] A second obtaining module is used to obtain configuration information of a computing module in the GPU;

[0145] A configuration module is used to configure the upper limit number of computing modules supported by the scheduler according to the configuration information.

[0146] In a possible implementation manner, the device further includes a disconnected computing module processing module, and the disconnected computing module processing module is configured to:

[0147] Deleting or reconnecting to zero the module control circuits in the GPU that are not connected to the computing modules;

[0148] and / or,

[0149] The module control circuits of the GPU that are not connected to the computing modules are left unconnected and marked as unavailable.

[0150] In a possible implementation manner, the device further includes:

[0151] A third obtaining module is used to obtain the availability test result of the computing module in the GPU in response to the power-on initialization of the GPU;

[0152] A shielding module is used to shield unavailable computing modules in the GPU according to the availability test result.

[0153] In one possible implementation,

[0154] The first obtaining module 32 is used to: obtain the load information of the available computing modules in the GPU through the module control circuit corresponding to the available computing modules;

[0155] The determination module 33 is used to determine a target computing module from the available computing modules according to the task analysis result and the load information.

[0156] In one possible implementation,

[0157] The determination module 33 is used to: divide the task to be processed according to the task analysis result to obtain at least two subtasks corresponding to the task to be processed; and determine the target computing modules corresponding to the at least two subtasks from the multiple computing modules according to the load information;

[0158] The sending module 34 is used to send the subtasks to the target computing module in parallel through the module control circuit corresponding to the target computing module.

[0159] In a possible implementation, the scheduler schedules different tasks to be processed based on a preset dynamic load balancing strategy;

[0160] The preset dynamic load balancing strategy includes at least one of the following: a dynamic load balancing strategy based on priority, a dynamic load balancing strategy based on time slices, and a dynamic load balancing strategy based on resource isolation;

[0161] Wherein, the priority-based dynamic load balancing strategy includes allocating computing resources to tasks with higher priority to be processed first;

[0162] The time slice-based dynamic load balancing strategy includes allocating a corresponding time slice to each task to be processed, and switching to the next task to be processed when the time slice corresponding to any task to be processed is exhausted;

[0163] The dynamic load balancing strategy based on resource isolation includes allocating independent computing resources to different users or tasks to be processed.

[0164] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. Its specific implementation and technical effects can refer to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0165] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium may be a non-volatile computer-readable storage medium, or may be a volatile computer-readable storage medium.

[0166] The embodiment of the present disclosure further provides a computer program, including a computer-readable code. When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the above method.

[0167] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0168] An embodiment of the present disclosure also provides an electronic device, comprising: one or more processors; and a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0169] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0170] Figure 4 1 is a block diagram of an electronic device 1900 provided in an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal. Figure 4 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0171] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (MacOS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0172] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0173] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0174] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0175] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0176] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0177] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0178] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0179] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0180] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0181] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0182] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0183] If the technical solution of the embodiments of the present disclosure involves personal information, the product using the technical solution of the embodiments of the present disclosure has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of the embodiments of the present disclosure involves sensitive personal information, the product using the technical solution of the embodiments of the present disclosure has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the requirement of "explicit consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to collect his or her personal information; or on the device for processing personal information, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0184] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A GPU task scheduling method, characterized in that: The GPU includes multiple groups of module control circuits, and the multiple groups of module control circuits are used to connect multiple computing modules in the GPU; The method is applied to a scheduler of the GPU, and the scheduler is arranged at a front end of the GPU; the method comprises: In response to receiving the pending task sent by the driver, parsing the pending task to obtain a task parsing result of the pending task; Obtaining load information of the multiple computing modules through module control circuits corresponding to the multiple computing modules; Determine a target computing module from the plurality of computing modules according to the task analysis result and the load information; The task to be processed is sent to the target computing module through a module control circuit corresponding to the target computing module.

2. The method according to claim 1, characterized in that The method further comprises: Obtaining configuration information of a computing module in the GPU; According to the configuration information, an upper limit number of computing modules supported by the scheduler is configured.

3. The method according to claim 1, characterized in that The method further comprises: Deleting or reconnecting to zero the module control circuits in the GPU that are not connected to the computing modules; and / or, The module control circuits of the GPU that are not connected to the computing modules are left unconnected and marked as unavailable.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: In response to the GPU being powered on and initialized, obtaining a usability test result of a computing module in the GPU; According to the availability test result, unavailable computing modules in the GPU are shielded.

5. The method according to claim 4, characterized in that The obtaining load information of the plurality of computing modules through the module control circuits corresponding to the plurality of computing modules comprises: obtaining load information of the available computing modules through the module control circuits corresponding to the available computing modules in the GPU; Determining a target computing module from the multiple computing modules according to the task analysis result and the load information includes: determining a target computing module from the available computing modules according to the task analysis result and the load information.

6. The method according to any one of claims 1 to 3, characterized in that: The determining, from the plurality of computing modules, a target computing module according to the task analysis result and the load information, comprises: dividing the task to be processed according to the task analysis result to obtain at least two subtasks corresponding to the task to be processed; determining, from the plurality of computing modules, a target computing module corresponding to the at least two subtasks according to the load information; The sending the to-be-processed task to the target computing module through a module control circuit corresponding to the target computing module includes: sending the subtasks to the target computing module in parallel through a module control circuit corresponding to the target computing module.

7. The method according to any one of claims 1 to 3, characterized in that The scheduler schedules different tasks to be processed based on a preset dynamic load balancing strategy; The preset dynamic load balancing strategy includes at least one of the following: a dynamic load balancing strategy based on priority, a dynamic load balancing strategy based on time slices, and a dynamic load balancing strategy based on resource isolation; Wherein, the priority-based dynamic load balancing strategy includes allocating computing resources to tasks with higher priority to be processed first; The time slice-based dynamic load balancing strategy includes allocating a corresponding time slice to each task to be processed, and switching to the next task to be processed when the time slice corresponding to any task to be processed is exhausted; The dynamic load balancing strategy based on resource isolation includes allocating independent computing resources to different users or tasks to be processed.

8. A task scheduling device for a GPU, characterized in that: The GPU includes multiple groups of module control circuits, and the multiple groups of module control circuits are used to connect multiple computing modules in the GPU; The device is applied to the scheduler of the GPU, and the scheduler is arranged at the front end of the GPU; the device comprises: The parsing module is used for parsing the pending tasks in response to receiving the pending tasks sent by the driver, and obtaining the task parsing results of the pending tasks; A first obtaining module, configured to obtain load information of the plurality of computing modules through module control circuits corresponding to the plurality of computing modules; A determination module, configured to determine a target computing module from the plurality of computing modules according to the task analysis result and the load information; The sending module is used to send the to-be-processed task to the target computing module through the module control circuit corresponding to the target computing module.

9. An electronic device, characterized in that: include: one or more processors; a memory for storing executable instructions; The one or more processors are configured to call the executable instructions stored in the memory to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

11. A computer program product comprising computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, characterized in that: When the computer readable code is executed in an electronic device, a processor in the electronic device executes the method according to any one of claims 1 to 7.

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