Interface adaptation circuit for VCU entrance detection equipment

Abstract

The invention discloses an interface adaptation circuit for VCU entrance detection equipment. The interface adaptation circuit comprises a power supply selection circuit module, a driving mode selection circuit module, an input driving circuit module, an output driving circuit module and a logic operation circuit module. According to the interface adaptation circuit provided by the invention, adaptation to various hard wire interfaces with different functions, different transmission directions and different driving modes of the VCU is realized through configuration, and when a new interface requirement is needed or the requirement is changed, direct response can be realized, so that a large amount of manpower, material resources and time cost are saved.

Description

Technical Field

[0001] The present invention relates to the technical field of vehicle detection, and in particular to an interface adapter circuit for a VCU entrance detection device. Background Art

[0002] As a detection tool, the VCU entrance detection device needs to simulate various hardware signals and bus interfaces of the vehicle, connect with the input and output interfaces and various bus interfaces of the VCU, and detect whether the various interface functions of the VCU are normal through program control. For different models of VCU, the types and quantities of interfaces they have are different. Even for interfaces of the same functional type, their driving voltages and driving modes may not be the same. Most of the existing VCU entrance detection devices have one interface corresponding to the requirements of a VCU hard-wired interface. For the new interface function requirements of new VCU models or the changes in the interface requirements of the original VCU, the original products cannot be reused or replaced, and new entrance detection equipment can only be redesigned and produced, which requires a lot of manpower, resources and time costs. For different functional interfaces of different vehicles, there may be two signal directions of input or output, and the signal standard voltage may be 24V, 12V, 5V, etc. At the same time, for different vehicle signals, there may be two driving modes of high side and low side. Summary of the invention

[0003] Based on the above technical problems, the present invention proposes an interface adapter circuit for a VCU entrance detection device, which can adapt to a variety of possible functional interfaces after software configuration. The specific technical solution is as follows.

[0004] An interface adapter circuit for a VCU entrance detection device, arranged between a VCU hard-line input and output interface and an entrance detection device control circuit, comprises: A power selection circuit module: selects the voltage generated by the power circuit and provides the selected voltage path to the input drive circuit module and the output drive circuit module; A driving mode selection circuit module: comprising an input driving selection circuit submodule and an output driving selection circuit submodule, which respectively select the driving modes of the input driving circuit and the output driving circuit; Input drive circuit module: converts the input signal level state and converts the input signal into a signal that can be received by the MCU; Output drive circuit module: converts the signal output by MCU into a signal recognizable by VCU, has a certain current driving capability and meets the voltage requirements; Logic operation circuit module: provides control signal logic state and realizes system logic operation and communication functions.

[0005] Specifically, the power selection circuit module includes multiple groups of power gating circuits and a group of input power enabling circuits, and each group of the power gating circuits includes: NPN transistors, PMOS transistors, voltage limiting resistors, diodes, current limiting resistors 1 and 2; the voltage limiting resistors are connected between the G pole and the S pole of the PMOS transistor; the current limiting resistor 1 is respectively connected to the G pole of the PMOS transistor and the C pole of the NPN transistor; the current limiting resistor 2 is respectively connected to the B pole of the NPN transistor and an output pin of the logic operation circuit module; the E pole of the NPN transistor is grounded; the S pole of the PMOS transistor is connected to the nth driving power supply, the D pole is connected to the anode of the diode, and the cathode of the diode is connected to the S pole of the 4th PMOS transistor of the output driving circuit module.

[0006] Specifically, the NPN transistor, PMOS transistor, voltage limiting resistor, diode, current limiting resistor 1 and current limiting resistor 2 all include the 1st to nth ones, where n is the power gating circuit serial number and the maximum is the number of selectable driving power supplies.

[0007] Specifically, the input power enabling circuit includes a 9th NPN transistor, a 5th PMOS transistor, a 4th voltage limiting resistor, a 5th diode, a 17th current limiting resistor and an 18th current limiting resistor; wherein the 4th voltage limiting resistor is connected between the G pole and the S pole of the 5th PMOS transistor; the 17th current limiting resistor is respectively connected to the G pole of the 5th PMOS transistor and the C pole of the 9th NPN transistor; the 18th current limiting resistor is respectively connected to the B pole of the 9th NPN transistor and the 5th output pin of the logic operation circuit; the E pole of the 9th NPN transistor is grounded; the S pole of the 5th PMOS transistor is connected to the anode of the 3rd diode, and the D pole is connected to the anode of the 5th diode; the cathode of the 5th diode is connected to the second input pin of the first optocoupler in the input drive circuit module.

[0008] Specifically, the input drive selection circuit submodule includes a 4th NPN transistor and a 7th current limiting resistor; the C pole of the 4th NPN transistor is connected to the second input pin of the first optocoupler in the input drive circuit, and the E pole is grounded; the two ends of the 7th current limiting resistor are respectively connected to the 6th output pin of the logic operation circuit module and the B pole of the 4th NPN transistor.

[0009] Specifically, the output drive selection circuit submodule includes a 1st PNP transistor, a 2nd PNP transistor, a 5th NPN transistor, a 6th NPN transistor, a 1st voltage-dividing resistor, a 2nd voltage-dividing resistor, a 3rd voltage-dividing resistor, a 4th voltage-dividing resistor, a 7th current-limiting resistor, an 8th current-limiting resistor, a 9th current-limiting resistor, and a 10th current-limiting resistor.

[0010] Specifically, the E pole of the first PNP transistor is connected to the S pole of the fourth PMOS transistor of the output drive circuit, and the C pole is connected to the G pole of the fourth PMOS transistor; the two ends of the first voltage-dividing resistor are respectively connected to the S pole of the fourth PMOS transistor of the output drive circuit and the C pole of the fifth NPN transistor; the two ends of the second voltage-dividing resistor are respectively connected to the E pole of the fifth NPN transistor and the ground; the two ends of the seventh current-limiting resistor are respectively connected to the B pole of the first PNP transistor and the C pole of the fifth NPN transistor; the two ends of the eighth current-limiting resistor are respectively connected to the B pole of the fifth NPN transistor and the ground; The 7th output pin of the logic operation circuit is connected; the E pole of the 2nd PNP transistor is connected to the system power supply, and the C pole is connected to the 1st pin of the 5th voltage-dividing resistor in the output drive circuit; the two ends of the 3rd voltage-dividing resistor are respectively connected to the system power supply and the C pole of the 6th NPN transistor; the two ends of the 4th voltage-dividing resistor are respectively connected to the E pole of the 6th NPN transistor and the ground; the two ends of the 9th current-limiting resistor are respectively connected to the B pole of the 2nd PNP transistor and the C pole of the 6th NPN transistor; the two ends of the 10th current-limiting resistor are respectively connected to the B pole of the 6th NPN transistor and the 7th output pin of the logic operation circuit.

[0011] Specifically, the input drive circuit module includes a first optocoupler, an 11th current limiting resistor, a 12th current limiting resistor and a first filter capacitor, wherein the two ends of the 11th current limiting resistor are respectively connected to the IO signal of the VCU and the first input pin of the first optocoupler; the two ends of the first filter capacitor are respectively connected to the IO signal of the VCU and the second input pin of the first optocoupler; the output power pin of the first optocoupler is connected to the system power supply; the two ends of the 12th current limiting resistor are respectively connected to the first output pin of the first optocoupler and the first input pin of the logic operation circuit.

[0012] Specifically, the output drive circuit module includes a 1st NMOS transistor, a 4th PMOS transistor, a 7th NPN transistor, an 8th NPN transistor, a 5th voltage-dividing resistor, a 6th voltage-dividing resistor, a 7th voltage-dividing resistor, an 8th voltage-dividing resistor, a 13th current-limiting resistor, a 14th current-limiting resistor, a 15th current-limiting resistor, a 16th current-limiting resistor and a 4th diode, wherein the D pole of the 1st NMOS transistor is connected to the IO signal of the VCU, and the S pole is connected to the ground; the C pole of the 7th NPN transistor is connected to the G pole of the 1st NMOS transistor and the 2nd foot of the 5th voltage-dividing resistor, and the E pole is connected to the ground; the two ends of the 6th voltage-dividing resistor are respectively connected to the G pole of the 1st NMOS transistor and the ground; the two ends of the 13th current-limiting resistor are respectively connected to the B pole of the 7th NPN transistor and the ground; the two ends of the 14th current-limiting resistor are respectively connected to the B pole of the 7th NPN transistor and the first output pin of the logic operation circuit; The D pole of the PMOS transistor is connected to the anode of the 4th diode; the cathode of the 4th diode is connected to the IO signal of the VCU; the two ends of the 7th voltage-dividing resistor are respectively connected to the S pole and the G pole of the 4th PMOS transistor; the two ends of the 8th voltage-dividing resistor are respectively connected to the G pole of the 4th PMOS transistor and the C pole of the 8th NPN transistor; the E pole of the 8th NPN transistor is connected to the ground; the two ends of the 15th current-limiting resistor are respectively connected to the B pole of the 8th NPN transistor and the ground; the two ends of the 16th current-limiting resistor are respectively connected to the B pole of the 8th NPN transistor and the first output pin of the MCU circuit.

[0013] Specifically, the logic operation circuit module includes a first processor, and the second to seventh output pins of the first processor are respectively connected to the control pins of each circuit module.

[0014] Beneficial effects of the invention: The invention proposes an interface adapter circuit for a VCU entrance detection device, which can be configured to adapt to the hard-wired interfaces of various VCU functions, different transmission directions, and different driving modes. When new interface requirements or changes in requirements are needed, they can be directly responded to, thereby saving a lot of manpower, material resources, and time costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of an interface adapter circuit module for a VCU entrance detection device according to the present invention; Figure 2 It is a preferred interface adaptation circuit diagram for a VCU entrance detection device in an embodiment of the present invention; Figure 3 It is a diagram of device interface relationships in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described with reference to the accompanying drawings.

[0017] The present invention proposes an interface adapter circuit for a VCU entrance detection device, such as Figure 1 As shown, the interface adapter circuit serves as a hard-wired interface of the VCU entry detection device, connected to the hard-wired IO interface of the VCU; through logical control, it can achieve matching of different directions, different driving voltages, and different driving modes of the hardware interface signal, so that it can cope with changes in the VCU entry function or configuration without changing the hardware, and can use the same entry detection device to match various hard-wired interface requirements of different VCUs.

[0018] In this embodiment, the interface adapter circuit includes: a power selection circuit, a drive mode selection circuit (1), a drive mode selection circuit (2), an input drive circuit, an output drive circuit and a logic operation circuit. In this embodiment, the power selection circuit selects three optional power supplies (power supply 1, power supply 2 and power supply 3), selects the power supply voltage required for the VCU interface circuit according to the signal logic (C101) output by the logic operation circuit, and provides the selected power supply voltage (P101) path to the input and output drive circuits; the drive mode selection circuit (1) selects the drive mode of the input drive circuit according to the logic control signal (C102) provided by the logic operation circuit, whether it is a high-side drive or a low-side drive; the drive mode selection circuit (2) selects the output drive circuit according to the logic control signal (C104) provided by the logic operation circuit. The driving mode of the driving circuit is high-side driving or low-side driving; the input driving circuit is used to convert the input signal level state and convert the input signal (S104) into a signal (S101) that can be received by the logic operation circuit; the output driving circuit is used to convert the signal (S102) output by the logic operation circuit into a signal (S103) that can be recognized by the VCU, has a certain current driving capability and meets the voltage requirements; the logic operation circuit is used to receive and analyze the input signal logic and the digital signal required by the output interface, and according to the configuration, provide control signals to the various circuit parts, thereby realizing the selection of the circuit interface working mode.

[0019] Figure 2 is a preferred circuit diagram of the interface adapter circuit for the VCU entrance detection device proposed by the present invention. The interface adapter circuit serves as a hard-wire connection interface of the VCU entrance detection device and is connected to the hard-wire input and output signals of the VCU; Figure 2As shown in , S1 is the signal interface. The VCU entry detection device provides three selectable power supply voltages for the hard-wired interface: VDD_1, VDD_2, and VDD_3; at the same time, the working power supply of the logic circuit part of the device is VCC. The interface adapter circuit includes a power selection circuit, a drive mode selection circuit (1), a drive mode selection circuit (2), an input drive circuit, an output drive circuit, and a logic operation circuit. The following is a detailed description of each module: In this preferred embodiment, the power selection circuit uses three groups of power gating circuits. Among them, the first (1) NPN transistor uses transistor Q4, the first (1) PMOS transistor uses MOS transistor Q1, the first (1) voltage limiting resistor uses resistor R1, the first (1) diode uses diode D1, the first (1) current limiting resistor and the second (1) current limiting resistor use resistors R4 and R7 respectively. Among them, the resistor R1 is connected between the G pole and the S pole of the transistor Q1; the resistor R4 is connected between the G pole of the transistor Q1 and the C pole of the transistor Q4; the resistor R7 is connected between the B pole of the transistor Q4 and the second output pin OUT2 of the logic operation circuit U1; the E pole of the transistor Q4 is grounded; the S pole of the transistor Q1 is connected to the driving power supply VDD_1, and the D pole is connected to the anode of the diode D1; the cathode of the diode D1 is connected to the power supply network marked as VDD. When OUT2 of the logic operation circuit U1 outputs a high level, the MOS tube Q1 is turned on, and the power supply VDD_1 is enabled to the power supply VDD; when OUT2 outputs a low level, the power supply VDD is disconnected from VDD_1.

[0020] The first (2) NPN transistor uses transistor Q5, the first (2) PMOS transistor uses MOS transistor Q2, the first (2) voltage limiting resistor uses resistor R2, the first (2) diode uses diode D2, the first (2) current limiting resistor and the second (2) current limiting resistor use resistors R5 and R8 respectively. The resistor R2 is connected between the G pole and the S pole of the transistor Q2; the resistor R5 is connected between the G pole of the transistor Q2 and the C pole of the transistor Q5; the resistor R8 is connected between the B pole of the transistor Q5 and the third output pin OUT3 of the logic operation circuit U1; the E pole of the transistor Q5 is grounded; the S pole of the transistor Q2 is connected to the driving power supply VDD_2, and the D pole is connected to the anode of the diode D2; the cathode of the diode D2 is connected to the power supply network marked as VDD. When OUT3 of the logic operation circuit U1 outputs a high level, the MOS tube Q2 is turned on, and the power supply VDD_2 is enabled to the power supply VDD; when OUT3 outputs a low level, the power supply VDD is disconnected from VDD_2.

[0021] The first (3) NPN transistor uses transistor Q6, the first (3) PMOS transistor uses MOS transistor Q3, the first (3) voltage limiting resistor uses resistor R3, the first (3) diode uses diode D3, the first (3) current limiting resistor and the second (3) current limiting resistor use resistors R6 and R9 respectively. The resistor R3 is connected between the G pole and the S pole of the transistor Q3; the resistor R6 is connected between the G pole of the transistor Q3 and the C pole of the transistor Q6; the resistor R9 is connected between the B pole of the transistor Q6 and the fourth output pin OUT4 of the logic operation circuit U1; the E pole of the transistor Q6 is grounded; the S pole of the transistor Q3 is connected to the driving power supply VDD_3, and the D pole is connected to the anode of the diode D3; the cathode of the diode D3 is connected to the power supply network marked as VDD. When OUT4 of the logic operation circuit U1 outputs a high level, the MOS tube Q3 is turned on, and the power supply VDD_3 is enabled to the power supply VDD; when OUT4 outputs a low level, the power supply VDD is disconnected from VDD_3.

[0022] In the input power enabling circuit, the 9th NPN transistor uses transistor Q17, the 5th PMOS transistor uses transistor Q16, the 4th voltage limiting resistor uses resistor R29, the 5th diode uses diode D6, the 17th current limiting resistor and the 18th current limiting resistor use resistor R30 and resistor R31 respectively. Among them, the resistor 29 is connected between the G pole and the S pole of the transistor Q16; the resistor R30 is connected between the G pole of the transistor Q16 and the C pole of the transistor Q17; the resistor R31 is connected between the B pole of the transistor Q17 and the 5th output pin OUT5 of the logic operation circuit U1; the E pole of the transistor Q17 is grounded; the S pole of the transistor Q16 is connected to the power supply network VDD, and the D pole is connected to the anode of the diode D6; the cathode of the diode D6 is connected to the power supply network marked as VDD_IN. When OUT5 of the logic operation circuit U1 outputs a high level, the MOS tube Q16 is turned on, and the power supply VDD is enabled to the power supply VDD_IN; when OUT5 outputs a low level, the power supply VDD is disconnected from VDD_IN.

[0023] In the drive mode selection circuit (1), the 4th NPN transistor is Q7, and the 7th current limiting resistor is R12. The C pole of the transistor Q7 is connected to the second input pin of the first optical coupler U3 in the input drive circuit, and the E pole is grounded; the two ends of the resistor R12 are respectively connected to the 6th output pin OUT6 of the logic operation circuit U1 and the B pole of the transistor Q7. When OUT6 of the logic operation circuit U1 outputs a high level, the transistor Q7 is turned on; when OUT6 outputs a low level, the transistor Q7 is turned off.

[0024] In the drive mode selection circuit (2), the first PNP transistor is Q9, the second PNP transistor is Q12, the fifth NPN transistor is Q10, the sixth NPN transistor is Q13, the first voltage-dividing resistor is R14, the second voltage-dividing resistor is R18, the third voltage-dividing resistor is R21, the fourth voltage-dividing resistor is R25, the seventh current-limiting resistor is R15, the eighth current-limiting resistor is R16, the ninth current-limiting resistor is R22, and the tenth current-limiting resistor is R23. Among them, the E pole of the transistor Q9 is connected to the S pole of the 4th PMOS transistor Q8 of the output drive circuit, and the C pole is connected to the G pole of the 4th PMOS transistor Q8; the two ends of the resistor R14 are respectively connected to the S pole of the transistor Q8 and the C pole of the transistor Q10; the two ends of the resistor R18 are respectively connected to the E pole of the transistor Q10 and the ground; the two ends of the resistor R15 are respectively connected to the B pole of the transistor Q9 and the C pole of the transistor Q10; the two ends of the resistor R16 are respectively connected to the B pole of the transistor Q10 and the 7th output pin OUT7 of the logic operation circuit U1. The E pole of transistor Q12 is connected to the system power supply VCC, and the C pole is connected to the 1st pin of the 5th voltage-dividing resistor R24 ​​in the output drive circuit; the two ends of resistor R21 are respectively connected to the system power supply VCC and the C pole of transistor Q13; the two ends of resistor R25 are respectively connected to the E pole of transistor Q13 and the ground; the two ends of resistor R22 are respectively connected to the B pole of transistor Q12 and the C pole of transistor Q13; the two ends of resistor R23 are respectively connected to the B pole of transistor Q13 and the 7th output pin OUT7 of the logic operation circuit U1. When the OUT7 pin of U1 outputs a high level, transistors Q10 and Q13 are turned on, and when the OUT7 pin outputs a low level, transistors Q10 and Q13 are turned off.

[0025] In the input drive circuit, the first optocoupler is U3, the 11th current limiting resistor is R10, the 12th current limiting resistor is R11, and the first filter capacitor is C1. Among them, the two ends of the resistor R10 are respectively connected to the IO signal S1 of the VCU and the first input pin of the optocoupler U3; the two ends of the capacitor C1 are respectively connected to the IO signal S1 of the VCU and the second input pin of the optocoupler U3; the output power pin of the optocoupler U3 is connected to the system power supply VCC; the two ends of the resistor R11 are respectively connected to the first output pin of the optocoupler U3 and the first input pin IO_IN of the logic operation circuit U1.

[0026] In the output driving circuit, the 1st NMOS transistor is Q14, the 4th PMOS transistor is Q8, the 7th NPN transistor is Q15, the 8th NPN transistor is Q11, the 5th voltage-dividing resistor is R24, the 6th voltage-dividing resistor is R27, the 7th voltage-dividing resistor is R13, the 8th voltage-dividing resistor is R17, the 13th current-limiting resistor is R28, the 14th current-limiting resistor is R26, the 15th current-limiting resistor is R20, the 16th current-limiting resistor is R19, and the 4th diode is D4. Among them, the D pole of the transistor Q14 is connected to the IO signal S1 of the VCU, and the S pole is connected to the ground; the C pole of the transistor Q15 is connected to the G pole of the transistor Q14 and the 2nd pin of the resistor R24, and the E pole is connected to the ground; the two ends of the resistor R27 are respectively connected to the G pole of the transistor Q14 and the ground; the two ends of the resistor R28 are respectively connected to the B pole of the transistor Q15 and the ground; the two ends of the resistor R26 are respectively connected to the B pole of the transistor Q15 and the first output pin IO_OUT of the logic operation circuit U1. The D pole of transistor Q8 is connected to the anode of diode D4; the cathode of diode D4 is connected to the IO signal S1 of VCU; the two ends of resistor R13 are respectively connected to the S pole and G pole of transistor Q8; the two ends of resistor R17 are respectively connected to the G pole of transistor Q8 and the C pole of transistor Q11; the E pole of transistor Q11 is connected to the ground; the two ends of resistor R20 are respectively connected to the B pole of transistor Q11 and the ground; the two ends of resistor R19 are respectively connected to the B pole of transistor Q11 and the first output pin IO_OUT of the logic operation circuit U1. When the IO_OUT pin of U1 outputs a high level, transistors Q11 and Q15 are turned on; when the IO_OUT output is a low level, transistors Q11 and Q15 are turned off.

[0027] In the logic operation circuit, the first processor is U1, and the preferred embodiment uses MCU, whose power supply is the system power supply VCC. Among them, the first input pin IO_IN of the processor U1 is used to receive and analyze the logic state of the signal output by the VCU; the first output pin IO_OUT of U1 is used to provide and output the logic state required by the VCU; the second, third, fourth, fifth, sixth, and seventh output pins (OUT2, OUT3, OUT4, OUT5, OUT6, and OUT7, respectively) are connected to the above control signals respectively.

[0028] Figure 3This is a diagram of the device interface relationship in actual use. It should be noted that the VCU entry detection device processor can be the same device as the logic operation processor, or it can be a different logic operation device. If it is the same device, the logic state of each output pin of the above-mentioned logic operation processor can be directly controlled by program configuration according to the actual application; if it is a different device, it is necessary to transmit the required control logic to the logic operation processor through other communication means, and then the logic operation processor generates and outputs the logic state of each output pin. In view of the fact that this part of the content is not related to the hardware of the present invention, it is only explained here without further details.

[0029] Next, combine Figure 2 , Figure 3 As shown, the implementation logic of this interface adapter circuit in practical applications is explained.

[0030] In actual applications, the hardwire interface that the VCU entry detection device may encounter is a random combination of the following states: Signal working voltage, in this embodiment, there are three optional voltages; Signal direction (for the VCU entry detection device), in this embodiment, the signal can be an input or output signal; Signal driving mode: in this embodiment, the signal can be high-side driving or low-side driving.

[0031] Since the logic setting of the operating voltage is independent of the signal direction and the driving mode, it is assumed in the following description that the power supply voltage VDD_1 is selected. For the cases of VDD_2 and VDD_3, since the processing logic is consistent, the description is not repeated.

[0032] For the case where the signal direction (for VCU entrance detection equipment) is input and the signal driving mode is high-side driving: The OUT2 pin of the processor U1 outputs a low level, the OUT3 and OUT4 pins output a low level, the OUT5 pin outputs a low level, the OUT6 pin outputs a high level, the OUT7 pin outputs a high level, and the IO_OUT pin outputs a high level. Because the OUT2, OUT3, and OUT4 pins of the processor U1 are at a low level, the transistors Q4, Q5, and Q6 are all in the cut-off state, so the voltage across the resistors R1, R2, and R3 is zero, so that the transistors Q1, Q2, and Q3 are all in the cut-off state; the power supply network VDD is not connected to VDD_1, VDD_2, and VDD_3. Because the OUT5 pin of the processor U1 is at a low level, the transistor Q17 is in the cut-off state, so the voltage across the resistor R29 is zero, so that the transistor Q16 is in the cut-off state, and the power supply network VDD_IN is not connected to the power supply network VDD. Because the OUT6 pin of the processor U1 is at a high level, the transistor Q7 is in the on state, so the second input pin of the optocoupler U3 is connected to the ground. Because VDD is not connected to any power supply network, transistor Q8 is in the off state regardless of the state of transistor Q11; because the IO_OUT pin of processor U1 is at a high level, transistor Q15 is in the on state, so the voltage across the G pole and S pole of transistor Q14 is zero, so transistor Q14 is in the off state. At the same time, due to the presence of diode D4, signal S1 is prevented from being fed back to the power supply network VDD, and the output drive circuit has no effect on signal S1 at this time. Therefore, when the S1 signal input is at a high level, current flows between the first and second input pins of the optocoupler U3, so that the third and fourth pins of the optocoupler U3 are turned on, and the input pin IO_IN of the processor U1 can receive a high level; when the S1 signal input is at a low level, no current flows between the first and second input pins of the optocoupler U3, so that the third and fourth pins of the optocoupler U3 are not turned on, and the input pin IO_IN of the processor U1 can receive a low level.

[0033] 2. For the case where the signal direction (for VCU entry detection equipment) is input and the signal driving mode is low-side driving: The OUT2 pin of the processor U1 outputs a high level, the OUT3 and OUT4 pins output a low level, the OUT5 pin outputs a high level, the OUT6 pin outputs a low level, the OUT7 pin outputs a high level, and the IO_OUT pin outputs a high level. Because the OUT2 pin of the processor U1 is at a high level, the transistor Q4 is in the on state, so the voltage across the resistor R1 is not zero, so the transistor Q1 is in the on state; the power supply network VDD is connected to VDD_1. Because the OUT3 and OUT4 pins of the processor U1 are at a low level, the transistors Q5 and Q6 are in the off state, so the voltage across the resistors R2 and R3 is zero, so the transistors Q2 and Q3 are in the off state; the power supply network VDD is not connected to VDD_2 and VDD_3. Because the OUT5 pin of the processor U1 is at a high level, the transistor Q17 is in the on state, so the voltage across the resistor R29 is not zero, so the transistor Q16 is in the on state, and the power supply network VDD_IN is connected to the power supply network VDD. Because the OUT6 pin of the processor U1 is at a low level, the transistor Q7 is in the cut-off state, so the second input pin of the optocoupler U3 is disconnected from the ground. Because the OUT7 pin of the processor U1 outputs a high level, the transistor Q10 is in the on state, so the voltage across the resistor R14 is not zero, so the transistor Q9 is in the on state, so the voltage across the resistor R13 is zero, and the transistor Q8 is in the cut-off state; because the IO_OUT pin of the processor U1 is at a high level, the transistor Q15 is in the on state, so the voltage across the G pole and the S pole of the transistor Q14 is zero, so the transistor Q14 is in the cut-off state. At the same time, due to the presence of the diode D4, the signal S1 is prevented from being fed back to the power supply network VDD, and at this time, the output drive circuit has no effect on the signal S1. Therefore, when the S1 signal inputs a logic low signal, current flows between the first and second input pins of the optocoupler U3, so that the third and fourth pins of the optocoupler U3 are turned on, and the input pin IO_IN of the processor U1 can receive a high-level signal; when the S1 signal inputs a logic high signal, no current flows between the first and second input pins of the optocoupler U3, so that the third and fourth pins of the optocoupler U3 are not turned on, and the input pin IO_IN of the processor U1 can receive a low-level signal. Through the operation of the processor U1, the state of the input signal can be effectively identified.

[0034] 3. For the case where the signal direction (for VCU entry detection equipment) is output and the signal driving mode is high-side driving: The OUT2 pin of the processor U1 outputs a high level, the OUT3 and OUT4 pins output a low level, the OUT5 pin outputs a low level, the OUT6 pin outputs a low level, and the OUT7 pin outputs a low level. Because the OUT2 pin of the processor U1 is at a high level, the transistor Q4 is in the on state, so the voltage across the resistor R1 is not zero, so the transistor Q1 is in the on state; the power supply network VDD is connected to VDD_1. Because the OUT3 and OUT4 pins of the processor U1 are at a low level, the transistors Q5 and Q6 are in the off state, so the voltage across the resistors R2 and R3 is zero, so the transistors Q2 and Q3 are in the off state; the power supply network VDD is not connected to VDD_2 and VDD_3. Because the OUT5 pin of the processor U1 is at a low level, the transistor Q17 is in the off state, so the voltage across the resistor R29 is zero, so the transistor Q16 is in the off state, and the power supply network VDD_IN is not connected to the power supply network VDD. Because the OUT6 pin of the processor U1 is at a low level, the transistor Q7 is in the cut-off state, so the second input pin of the optocoupler U3 is disconnected from the ground. At this time, the second input pin of the optocoupler U3 is disconnected from the resistor network VDD_IN and the ground, so the input drive circuit has no effect on the output signal. Because the OUT7 pin of the processor U1 outputs a low level, the transistor Q13 is in the cut-off state, so the voltage across the resistor R21 is zero, and the transistor Q12 is in the cut-off state, so no matter what the output state of the IO_OUT pin of the operator U1 is, the G pole voltage of the transistor Q14 is zero, that is, the transistor Q14 is in the cut-off state. Because the OUT7 pin of the processor U1 outputs a low level, the transistor Q10 is in the cut-off state, so the voltage across the resistor R14 is zero, and the transistor Q9 is in the cut-off state; therefore, when the IO_OUT pin of the processor U1 outputs a high level, the transistor Q11 is in the on state, at which time the voltage across the resistor R13 is not zero, the transistor Q8 is in the on state, and the VDD voltage is output to the signal S1; when the IO_OUT pin of the processor U1 outputs a low level, the transistor Q11 is in the cut-off state, at which time the voltage across the resistor R13 is zero, the transistor Q8 is in the cut-off state, and at this time the signal S1 has no driving source, so it is a logic low signal.

[0035] 4. For the case where the signal direction (for VCU entry detection equipment) is output and the signal driving mode is high-side driving: The OUT2 pin of the processor U1 outputs a high level, the OUT3 and OUT4 pins output a low level, the OUT5 pin outputs a low level, the OUT6 pin outputs a low level, and the OUT7 pin outputs a high level. Because the OUT2 pin of the processor U1 is at a high level, the transistor Q4 is in the on state, so the voltage across the resistor R1 is not zero, so the transistor Q1 is in the on state; the power supply network VDD is connected to VDD_1. Because the OUT3 and OUT4 pins of the processor U1 are at a low level, the transistors Q5 and Q6 are in the off state, so the voltage across the resistors R2 and R3 is zero, so the transistors Q2 and Q3 are in the off state; the power supply network VDD is not connected to VDD_2 and VDD_3. Because the OUT5 pin of the processor U1 is at a low level, the transistor Q17 is in the off state, so the voltage across the resistor R29 is zero, so the transistor Q16 is in the off state, and the power supply network VDD_IN is not connected to the power supply network VDD. Because the OUT6 pin of the processor U1 is at a low level, the transistor Q7 is in the cut-off state, so the second input pin of the optocoupler U3 is disconnected from the ground. At this time, the second input pin of the optocoupler U3 is disconnected from the resistor network VDD_IN and the ground, so the input drive circuit has no effect on the output signal. Because the OUT7 pin of the processor U1 outputs a high level, the transistor Q10 is in the on state, so the voltage across the resistor R14 is not zero, so that the transistor Q9 is in the on state, and the voltage across the G pole and the S pole of the transistor Q8 is zero. At this time, regardless of the output state of the IO_OUT pin of the processor U1, the transistor Q8 is in the cut-off state. Because the OUT7 pin of the processor U1 outputs a high level, the transistor Q13 is in the on state, so the voltage across the resistor R21 is not zero, and the transistor Q12 is in the on state. At this time, when the IO_OUT pin of the processor U1 outputs a high level, the transistor Q15 is in the on state, the transistor Q14 is in the off state, and the signal S1 is disconnected from the ground, which can be regarded as an output high level state; when the IO_OUT pin of the processor U1 outputs a low level, the transistor Q15 is in the off state, and since the transistor Q12 is turned on, the voltage between the G pole and the S pole of the transistor Q14 is not zero, so that the transistor Q14 is in the on state, and the signal S1 is connected to the ground, which can be regarded as an output low level state; Finally, it should be noted that in some other embodiments of "An Interface Adapter Circuit for VCU Entrance Detection Device", since there may be multiple interface adapter circuits, a shift register circuit can be used to expand the processor IO control interface to achieve control of the logic circuit instead of direct control by the processor pin.

[0036] The present invention has shown and described the basic principles and main features of the present invention and the advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. An interface adapter circuit for a VCU entrance detection device, arranged between a VCU hard-line input and output interface and an entrance detection device control circuit, characterized in that: include: A power selection circuit module: selects the voltage generated by the power circuit and provides the selected voltage path to the input drive circuit module and the output drive circuit module; A driving mode selection circuit module: comprising an input driving selection circuit submodule and an output driving selection circuit submodule, which respectively select the driving modes of the input driving circuit and the output driving circuit; Input drive circuit module: converts the input signal level state and converts the input signal into a signal that can be received by the MCU; Output drive circuit module: converts the signal output by MCU into a signal recognizable by VCU, has a certain current driving capability and meets the voltage requirements; Logic operation circuit module: provides control signal logic state and realizes system logic operation and communication functions.

2. The interface adapter circuit for VCU entrance detection equipment according to claim 1, characterized in that: The power selection circuit module includes multiple groups of power gating circuits and a group of input power enabling circuits, and each group of the power gating circuits includes: NPN transistors, PMOS transistors, voltage limiting resistors, diodes, current limiting resistors 1 and 2; the voltage limiting resistors are connected between the G pole and the S pole of the PMOS transistor; the current limiting resistor 1 is respectively connected to the G pole of the PMOS transistor and the C pole of the NPN transistor; the current limiting resistor 2 is respectively connected to the B pole of the NPN transistor and an output pin of the logic operation circuit module; the E pole of the NPN transistor is grounded; the S pole of the PMOS transistor is connected to the nth driving power supply, the D pole is connected to the anode of the diode, and the cathode of the diode is connected to the S pole of the 4th PMOS transistor of the output driving circuit module.

3. The interface adapter circuit for VCU entrance detection equipment according to claim 2, characterized in that: The NPN transistor, PMOS transistor, voltage limiting resistor, diode, current limiting resistor 1 and current limiting resistor 2 all include the 1st to nth ones, where n is the power supply gating circuit serial number and the maximum is the number of selectable driving power supplies.

4. The interface adapter circuit for VCU entrance detection equipment according to claim 3, characterized in that: The input power enabling circuit includes a 9th NPN transistor, a 5th PMOS transistor, a 4th voltage limiting resistor, a 5th diode, a 17th current limiting resistor and an 18th current limiting resistor; wherein the 4th voltage limiting resistor is connected between the G pole and the S pole of the 5th PMOS transistor; the 17th current limiting resistor is respectively connected to the G pole of the 5th PMOS transistor and the C pole of the 9th NPN transistor; the 18th current limiting resistor is respectively connected to the B pole of the 9th NPN transistor and the 5th output pin of the logic operation circuit; the E pole of the 9th NPN transistor is grounded; the S pole of the 5th PMOS transistor is connected to the anode of the 3rd diode, and the D pole is connected to the anode of the 5th diode; the cathode of the 5th diode is connected to the second input pin of the first optocoupler in the input drive circuit module.

5. The interface adapter circuit for VCU entrance detection equipment according to claim 1, characterized in that: The input drive selection circuit submodule includes a 4th NPN transistor and a 7th current limiting resistor; the C pole of the 4th NPN transistor is connected to the second input pin of the first optocoupler in the input drive circuit, and the E pole is grounded; the two ends of the 7th current limiting resistor are respectively connected to the 6th output pin of the logic operation circuit module and the B pole of the 4th NPN transistor.

6. The interface adapter circuit for VCU entrance detection equipment according to claim 1, characterized in that: The output drive selection circuit submodule includes a first PNP transistor, a second PNP transistor, a fifth NPN transistor, a sixth NPN transistor, a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, a fourth voltage-dividing resistor, a seventh current-limiting resistor, an eighth current-limiting resistor, a ninth current-limiting resistor, and a tenth current-limiting resistor.

7. The interface adapter circuit for VCU entrance detection equipment according to claim 6, characterized in that: The E pole of the first PNP transistor is connected to the S pole of the fourth PMOS transistor of the output drive circuit, and the C pole is connected to the G pole of the fourth PMOS transistor; the two ends of the first voltage-dividing resistor are respectively connected to the S pole of the fourth PMOS transistor of the output drive circuit and the C pole of the fifth NPN transistor; the two ends of the second voltage-dividing resistor are respectively connected to the E pole of the fifth NPN transistor and the ground; the two ends of the seventh current-limiting resistor are respectively connected to the B pole of the first PNP transistor and the C pole of the fifth NPN transistor; the two ends of the eighth current-limiting resistor are respectively connected to the B pole of the fifth NPN transistor and the ground of the logic The 7th output pin of the logic operation circuit is connected; the E pole of the 2nd PNP transistor is connected to the system power supply, and the C pole is connected to the 1st pin of the 5th voltage-dividing resistor in the output drive circuit; the two ends of the 3rd voltage-dividing resistor are respectively connected to the system power supply and the C pole of the 6th NPN transistor; the two ends of the 4th voltage-dividing resistor are respectively connected to the E pole of the 6th NPN transistor and the ground; the two ends of the 9th current-limiting resistor are respectively connected to the B pole of the 2nd PNP transistor and the C pole of the 6th NPN transistor; the two ends of the 10th current-limiting resistor are respectively connected to the B pole of the 6th NPN transistor and the 7th output pin of the logic operation circuit.

8. The interface adapter circuit for VCU entrance detection equipment according to claim 1, characterized in that: The input drive circuit module includes a first optocoupler, an 11th current limiting resistor, a 12th current limiting resistor and a first filter capacitor, wherein both ends of the 11th current limiting resistor are respectively connected to the IO signal of the VCU and the first input pin of the first optocoupler; both ends of the first filter capacitor are respectively connected to the IO signal of the VCU and the second input pin of the first optocoupler; the output power pin of the first optocoupler is connected to the system power supply; and both ends of the 12th current limiting resistor are respectively connected to the first output pin of the first optocoupler and the first input pin of the logic operation circuit.

9. The interface adapter circuit for VCU entrance detection equipment according to claim 1, characterized in that: The output drive circuit module includes a 1st NMOS transistor, a 4th PMOS transistor, a 7th NPN transistor, an 8th NPN transistor, a 5th voltage-dividing resistor, a 6th voltage-dividing resistor, a 7th voltage-dividing resistor, an 8th voltage-dividing resistor, a 13th current-limiting resistor, a 14th current-limiting resistor, a 15th current-limiting resistor, a 16th current-limiting resistor and a 4th diode, wherein the D pole of the 1st NMOS transistor is connected to the IO signal of the VCU, and the S pole is connected to the ground; the C pole of the 7th NPN transistor is connected to the G pole of the 1st NMOS transistor and the 2nd foot of the 5th voltage-dividing resistor, and the E pole is connected to the ground; the two ends of the 6th voltage-dividing resistor are respectively connected to the G pole of the 1st NMOS transistor and the ground; the two ends of the 13th current-limiting resistor are respectively connected to the B pole of the 7th NPN transistor and the ground; the two ends of the 14th current-limiting resistor are respectively connected to the B pole of the 7th NPN transistor and the first output pin of the logic operation circuit; The D pole of the PMOS transistor is connected to the anode of the 4th diode; the cathode of the 4th diode is connected to the IO signal of the VCU; the two ends of the 7th voltage-dividing resistor are respectively connected to the S pole and the G pole of the 4th PMOS transistor; the two ends of the 8th voltage-dividing resistor are respectively connected to the G pole of the 4th PMOS transistor and the C pole of the 8th NPN transistor; the E pole of the 8th NPN transistor is connected to the ground; the two ends of the 15th current-limiting resistor are respectively connected to the B pole of the 8th NPN transistor and the ground; the two ends of the 16th current-limiting resistor are respectively connected to the B pole of the 8th NPN transistor and the first output pin of the MCU circuit.

10. The interface adapter circuit for VCU entrance detection equipment according to claim 1, characterized in that: The logic operation circuit module includes a first processor, and the second to seventh output pins of the first processor are respectively connected to the control pins of each circuit module.

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