Processor simulation verification method and device, medium and product
By setting up the UVM verification platform and writing the RISC-V behavior model in the processor verification, the transplantability and efficiency of the existing technologies medium-level language behavior models were solved, and more efficient simulation verification and function coverage records were achieved.
Patent Information
- Application Number
- CN202411702909.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-01-21
AI Technical Summary
During the verification process of existing processors, the behavioral model of high-level languages cannot be uniformly packaged with mainstream hardware verification components, which reduces the reusability and portability of the verification environment, and frequently communicates through the DPI interface, reducing the running speed of the verification environment. and efficiency.
Establish a UVM verification platform, the RISC-V behavior model of the target processor based on the UVM platform, and build a functional coverage record component, simulation verification through the RISC-V behavior model, and directly communicate with the UVM verification platform to avoid through the DPI interface.
Improved the migrating and reusedability of the RISC-V behavior model, improved the rate and efficiency of the verification process, and provided quantitative verification progress information through functional coverage to record components.
Smart Images
Figure CN119337788A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of simulation verification technology, and in particular to a processor simulation verification method, device, medium and product. Background Art
[0002] In the verification process of existing processors, high-level languages such as C / C++ are used to model the processor behavior. Then, through means such as DPI, the processor behavior model built in the high-level language is connected to the RTL verification platform to ensure the correctness and integrity of the processor behavior.
[0003] However, the behavioral models of high-level languages cannot be uniformly packaged with mainstream hardware verification components, such as the UVM verification platform, which reduces the reusability and portability of the verification environment. In addition, the behavioral models of high-level languages frequently communicate with the hardware verification environment through the DPI interface, which also reduces the operating speed and efficiency of the verification environment. Summary of the invention
[0004] In view of the deficiencies in the prior art, the present invention provides a processor simulation verification method, device, medium and product, which solve the problems in the prior art of poor portability and reusability of behavioral models of high-level languages and reduced operating speed and efficiency of the verification environment.
[0005] According to an embodiment of the present invention, a processor simulation verification method includes:
[0006] Build UVM verification platform;
[0007] Write a RISC-V behavior model of the target processor based on the UVM verification platform, and build a functional coverage recording component;
[0008] The RISC-V behavior model is used for simulation verification, and the functional coverage information of the simulation verification is recorded by the functional coverage recording component.
[0009] Optionally, writing a RISC-V behavior model of a target processor based on the UVM verification platform includes:
[0010] Based on the data types provided by the UVM platform, set the base class of the instruction descriptor;
[0011] Defining the basic elements required to describe the construction of RISC-V instructions in the base class of the instruction descriptor;
[0012] Construct N RISC-V instructions based on the basic elements.
[0013] Optionally, the N RISC-V instructions include verification instructions and recording instructions.
[0014] Optionally, after constructing N RISC-V instructions according to the basic elements, the method further includes:
[0015] Set the recognition method of each RISC-V instruction, the impact of each RISC-V instruction execution result on PC, the impact of each RISC-V instruction execution result on IO access, and the impact of each RISC-V instruction execution result on internal registers.
[0016] Optionally, simulation verification is performed using the RISC-V behavior model, and functional coverage information of the simulation verification is recorded, including:
[0017] Instantiating the RISC-V behavior model on the UVM verification platform to obtain an intelligent agent;
[0018] Predicting the execution results of N RISC-V instructions by the agent;
[0019] Among them, when the nth RISC-V instruction is confirmed to be executed, the function coverage sampling function corresponding to the instruction function is called in the function coverage recording component to record the function coverage information, and the instruction execution result is predicted, and the predicted result is written into the result prediction queue. The comparison result prediction queue is used for comparison with the actual sampling information queue.
[0020] Optionally, before predicting the instruction execution results of N RISC-V instructions by the agent, the method further comprises:
[0021] Acquiring processor information required to predict the execution result of the instruction based on the intelligent agent;
[0022] The processor information includes the clock and reset information and interrupt interface information of the target processor, as well as the PC value of the target processor and the register value inside the target processor.
[0023] Optionally, predicting the instruction execution result and writing the predicted result into the result prediction queue includes:
[0024] If the corresponding element in the prediction information queue and the actual sampling information queue of the virtual interface are both non-empty, compare the first element;
[0025] If the information matches, the correct information will be reported based on the current verbosity setting. If the information does not match, the error information will be reported.
[0026] A second aspect provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the processor simulation verification method as described above when executing the computer program.
[0027] A third aspect provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the processor simulation verification method as described above.
[0028] A fourth aspect provides a computer program product, comprising a computer program, which implements the processor simulation verification method as described above when executed by a processor.
[0029] Compared with the prior art, the present invention has the following beneficial effects: firstly, a UVM verification platform is built, and then the RISC-V behavior model of the target processor is written using the hardware description and hardware verification language provided by the UVM verification platform, so that simulation verification can be performed through the RISC-V behavior model. Therefore, the RISC-V behavior model can be conveniently encapsulated into the verification environment together with other components of the hardware verification platform, thereby enhancing the portability and reusability of the RISC-V behavior model; in addition, the RISC-V behavior model can communicate with the UVM verification platform without passing through a DPI interface, thereby improving the speed and efficiency of the verification process; and, the present invention adopts a function coverage recording component constructed by hardware description and hardware verification language, which can directly provide quantitative information of the verification progress in the verification environment. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic diagram of the implementation flow of a processor simulation verification method according to an embodiment of the present invention;
[0031] Figure 2 A schematic diagram of a process of checking the instruction execution integrity of a RISC-V behavior model according to an embodiment of the present invention;
[0032] Figure 3 A schematic diagram of the structure of a processor simulation verification device according to an embodiment of the present invention;
[0033] Figure 4 Schematic diagram of the structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0034] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.
[0035] like Figure 1 As shown, the embodiment of the present invention provides a processor simulation verification method, including but not limited to the following steps:
[0036] S1. Build UVM (Universal Verification Methodology) verification platform;
[0037] S2, write the RISC-V behavior model of the target processor based on the UVM verification platform, and build a functional coverage recording component;
[0038] S3. Perform simulation verification through the RISC-V behavior model, and record the functional coverage information of the simulation verification through the functional coverage recording component.
[0039] For the above-mentioned step S2, RISC-V is an open source instruction set architecture based on the reduced instruction set (RISC) principle. The embodiment of the present invention uses the UVM verification platform that is built, so as to write the RISC-V behavior model based on the hardware description and hardware verification language provided by the UVM verification platform. Then, the RISC-V behavior model can be encapsulated together with other components of the hardware verification platform to obtain the ability to be transferred to other verification environments, thereby enhancing the portability and reusability of the RISC-V behavior model; and the RISC-V behavior model built based on the UVM verification platform does not need to communicate through the DPI interface, and can greatly improve the rate and efficiency of the verification process.
[0040] In one embodiment, the implementation of step S2 includes:
[0041] Based on the data types provided by the UVM platform, set the base class of the instruction descriptor;
[0042] Defining the basic elements required to describe the construction of RISC-V instructions in the base class of the instruction descriptor;
[0043] Construct N RISC-V instructions based on the basic elements.
[0044] Exemplarily, the base class of the instruction descriptor describes the basic elements required for a RISC-V instruction, including: instruction encoding, instruction mnemonics, instruction register parameters, IO parameters, etc.
[0045] In a specific application, N RISC-V instructions are obtained by expanding the base class of the instruction descriptor after the base class of the instruction descriptor is defined, thereby automatically collecting and constructing all legal instruction description units registered in the instruction pool. Among them, the base class of the instruction descriptor also includes all basic elements defined in the base class of the instruction descriptor. Exemplarily, the N RISC-V instructions include verification instructions and recording instructions.
[0046] In addition, when constructing specific RISC-V instructions, the RISC-V instructions also need to implement multiple functional functions. Therefore, after constructing N RISC-V instructions according to the basic elements, the following is also included:
[0047] Set the recognition method of each RISC-V instruction, the impact of each RISC-V instruction execution result on PC, the impact of each RISC-V instruction execution result on IO access, and the impact of each RISC-V instruction execution result on internal registers.
[0048] The above are all functional descriptions of instructions, and in a better implementation method, the functional description of instructions adopts a distributed management mode. A single instruction is registered in the corresponding instruction pool in the instruction descriptor. The instructions registered in the instruction pool are automatically constructed at the same time as the instruction pool is constructed, which is convenient for customized addition, deletion, and modification of the relevant functional description of a single instruction according to the implementation of the current processor.
[0049] Exemplarily, the functional description of the above instruction is implemented by the following function:
[0050] 1. The instruction identification method: the current instruction can be uniquely selected or excluded according to the input instruction code;
[0051] 2. The impact of the instruction execution result on the PC: When a function is called, the PC value after the instruction is executed is predicted based on the current internal state of the processor and the instruction encoding;
[0052] 3. The impact of the instruction execution result on IO access: When calling a function, the IO transmission generated by the instruction execution is predicted based on the current internal state of the processor and the instruction encoding (for IO load operation instructions, only the relevant command information of the load operation is predicted, and the readback data information is not predicted)
[0053] 4. The impact of the instruction execution result on the internal registers: When calling a function, based on the current internal state of the processor and combined with the instruction encoding, predict the impact of the instruction execution on the internal registers (whether to update the GPR and CSR, and what the result of the update operation is)
[0054] 5. Other effects of the instruction execution result: According to the specific implementation of the RISC-V processor, customize the expected function of the operation result of relevant special instructions, such as cache flush, atomic instruction operation, etc.;
[0055] Regarding the above step S3, since the functional coverage recording component constructed by the hardware description and hardware verification language is adopted in the above step S2, the verification environment can directly provide quantitative information of the verification progress.
[0056] In one embodiment, the implementation of step S3 includes:
[0057] Instantiating the RISC-V behavior model on the UVM verification platform to obtain an intelligent agent;
[0058] Predicting the execution results of N RISC-V instructions by the agent;
[0059] Among them, when the nth RISC-V instruction is confirmed to be executed, the function coverage sampling function corresponding to the instruction function is called in the function coverage recording component to record the function coverage information, and the instruction execution result is predicted, and the predicted result is written into the result prediction queue. The comparison result prediction queue is used for comparison with the actual sampling information queue.
[0060] It can be understood that the function coverage sampling function corresponding to the instruction function means that when a RISC-V instruction is confirmed to be executed, the sampling function required for sampling the function implemented by this RISC-V instruction is called, so as to obtain the relevant sample value of the function coverage of the function implemented by this RISC-V instruction, that is, the function coverage information.
[0061] Before predicting the execution results of N RISC-V instructions by the agent, the method includes:
[0062] Acquiring processor information required to predict the execution result of the instruction based on the intelligent agent;
[0063] The processor information includes the clock and reset information and interrupt interface information of the target processor, as well as the PC value of the target processor and the register value inside the target processor.
[0064] It should be noted that the method for obtaining the processor information required for predicting the instruction execution result based on the intelligent agent is: obtaining the processor information required for predicting the instruction execution result from the design of the RISC-V processor through the UVM virtual interface method. Wherein, the UVM virtual interface represents the virtual interface provided by the UVM platform.
[0065] The embodiment of the present invention also describes the implementation of predicting the instruction execution result and writing the predicted result into the result prediction queue when the nth RISC-V instruction is confirmed to be executed, including:
[0066] Predicting the instruction execution result according to the processor information in the RISC-V behavior model, and writing the predicted result into a result prediction queue with the same category according to the category of the processor information;
[0067] The result prediction queue of each category is used to compare with the actual sampling information queue. When the processor information in the result prediction queue is different from the processor information in the actual sampling information queue, the correct information of the information comparison is reported. If not, the information comparison error information is reported; wherein the actual sampling information queue is obtained by sampling the processor information of the target processor by the UVM verification platform.
[0068] In specific applications, the processor information in the RISC-V behavior model includes multiple categories such as the PC value of the processor running, the register value inside the processor, and interface information. Therefore, the result prediction queue corresponds to multiple categories such as PC information queue, REG information queue, and IO information queue. Similarly, the processor information of the target processor also corresponds to multiple categories including PC, REG, IO, etc., and the actual sampling information queue corresponds to multiple categories such as PC information queue, REG information queue, and IO information queue. The result prediction queue of each category above is used to compare with the actual sampling information queue, that is, the PC information queue of the result prediction queue is compared with the PC information queue of the actual sampling information queue, the REG information queue of the result prediction queue is compared with the REG information queue of the actual sampling information queue, and the IO information queue of the result prediction queue is compared with the IO information queue of the actual sampling information queue.
[0069] like Figure 2 As shown, for example, taking the addition instruction add as an example, the RISC-V behavior model checks the instruction execution integrity as follows:
[0070] 1. The UVM verification platform captures the instruction information input and sends the collected instruction information to the intelligent agent of the RISC-V behavior model;
[0071] 2. The agent passes the instruction information to the instruction pool, which includes N RISC-V instructions;
[0072] 3. Query which RISC-V instruction the currently input instruction information is. If the query fails or multiple instructions are reported to match, an error is reported. Otherwise, the execution result of the RISC-V instruction corresponding to the instruction information is predicted;
[0073] 4. When the current instruction, that is, the RISC-V instruction corresponding to the instruction information is confirmed to be executed, the function coverage sampling function corresponding to the instruction function is called in the function coverage recording component to record the function coverage information. Then, the processor information (PC, REG, IO, etc.) in the RISC-V behavior model predicts the instruction execution result and writes the prediction result into the result prediction queue (PC information queue, REG information queue, IO information queue, etc.);
[0074] 5. When the elements in the result prediction queue and the actual sampling information queue of the UVM verification platform are not empty, compare the first element. If the information matches, report the correct information of the information comparison. If the information does not match, report the error information of the information comparison.
[0075] 6. The above steps 1 to 5 are all executed by pipeline operation, that is, after the execution result of step 1 is passed to step 2, the continued execution of step 1 is not blocked, so that the instructions are collected in a loop and the execution results of the instructions are judged, thereby achieving the function of predicting and checking the instruction results.
[0076] Through the above steps S1 to S3, the embodiment of the present invention first builds a UVM verification platform, and then uses the hardware description and hardware verification language provided by the UVM verification platform to write the RISC-V behavior model of the target processor, so that simulation verification can be performed through the RISC-V behavior model. Therefore, the RISC-V behavior model can be conveniently encapsulated into the verification environment together with other components of the hardware verification platform, which enhances the portability and reusability of the RISC-V behavior model; in addition, the RISC-V behavior model can communicate with the UVM verification platform without passing through the DPI interface, which improves the speed and efficiency of the verification process; and the functional coverage recording component constructed by the present invention using the hardware description and hardware verification language can directly verify the environment to provide quantitative information of the verification progress.
[0077] like Figure 3 As shown, the embodiment of the present invention further provides a processor simulation verification device 30, comprising:
[0078] UVM verification platform building module 31, used for building UVM verification platform;
[0079] A model building module 32 is used to write a RISC-V behavior model of a target processor based on the UVM verification platform and to build a functional coverage recording component;
[0080] The simulation verification module 33 is used to perform simulation verification through the RISC-V behavior model, and record the functional coverage information of the simulation verification through the functional coverage recording component.
[0081] Therefore, the processor simulation verification device provided in the embodiment of the present invention can execute the processor simulation verification method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.
[0082] Figure 4A schematic diagram of the structure of an electronic device 40 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.
[0083] like Figure 4 As shown, the electronic device 40 includes at least one processor 41, and a memory connected to the at least one processor 41, such as a read-only memory (ROM) 42, a random access memory (RAM) 43, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 41 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 42 or the computer program loaded from the storage unit 48 to the random access memory (RAM) 43. In the RAM 43, various programs and data required for the operation of the electronic device 40 can also be stored. The processor 41, the ROM 42, and the RAM 43 are connected to each other through a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.
[0084] A number of components in the electronic device 40 are connected to the I / O interface 45, including: an input unit 46, such as a keyboard, a mouse, etc.; an output unit 47, such as various types of displays, speakers, etc.; a storage unit 48, such as a disk, an optical disk, etc.; and a communication unit 49, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 49 allows the electronic device 40 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.
[0085] The processor 41 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 41 performs the various methods and processes described above, such as a processor simulation verification method.
[0086] In some embodiments, the data processing method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 40 via the ROM 42 and / or the communication unit 49. When the computer program is loaded into the RAM 43 and executed by the processor 41, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the processor 41 may be configured to perform the data processing method in any other appropriate manner (e.g., by means of firmware).
[0087] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
[0088] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.
[0089] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0090] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).
[0091] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.
[0092] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.
[0093] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0094] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A processor simulation verification method, characterized in that: include: Build UVM verification platform; Write a RISC-V behavior model of the target processor based on the UVM verification platform, and build a functional coverage recording component; The RISC-V behavior model is used for simulation verification, and the functional coverage information of the simulation verification is recorded by the functional coverage recording component.
2. The processor simulation verification method according to claim 1, characterized in that: The RISC-V behavior model of the target processor is written based on the UVM verification platform, including: Based on the data types provided by the UVM platform, set the base class of the instruction descriptor; Defining the basic elements required to describe the construction of RISC-V instructions in the base class of the instruction descriptor; Construct N RISC-V instructions based on the basic elements.
3. The processor simulation verification method according to claim 2, characterized in that: The N RISC-V instructions include verification instructions and recording instructions.
4. The processor simulation verification method according to claim 2, characterized in that: After constructing N RISC-V instructions according to the basic elements, it also includes: Set the recognition method of each RISC-V instruction, the impact of each RISC-V instruction execution result on PC, the impact of each RISC-V instruction execution result on IO access, and the impact of each RISC-V instruction execution result on internal registers.
5. The processor simulation verification method according to any one of claims 1 to 4, characterized in that: The RISC-V behavior model is used for simulation verification, and the functional coverage information of the simulation verification is recorded, including: Instantiating the RISC-V behavior model on the UVM verification platform to obtain an intelligent agent; Predicting the execution results of N RISC-V instructions by the agent; Among them, when the nth RISC-V instruction is confirmed to be executed, the function coverage sampling function corresponding to the instruction function is called in the function coverage recording component to record the function coverage information, and the instruction execution result is predicted, and the predicted result is written into the result prediction queue. The comparison result prediction queue is used for comparison with the actual sampling information queue.
6. The processor simulation verification method according to claim 5, characterized in that: Before predicting the instruction execution results of N RISC-V instructions by the agent, it includes: Acquiring processor information required to predict the execution result of the instruction based on the intelligent agent; The processor information includes the clock and reset information and interrupt interface information of the target processor, as well as the PC value of the target processor and the register value inside the target processor.
7. The processor simulation verification method according to claim 6, characterized in that: Predict the instruction execution result and write the prediction result into the result prediction queue, including: Predicting the instruction execution result according to the processor information in the RISC-V behavior model, and writing the predicted result into a result prediction queue with the same category according to the category of the processor information; The result prediction queue of each category is used to compare with the actual sampling information queue. When the processor information in the result prediction queue is different from the processor information in the actual sampling information queue, the correct information of the information comparison is reported. If not, the information comparison error information is reported; wherein the actual sampling information queue is obtained by sampling the processor information of the target processor by the UVM verification platform.
8. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the processor simulation verification method as claimed in any one of claims 1 to 7 when executing the computer program.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the processor simulation verification method as claimed in any one of claims 1 to 7 is implemented.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the processor simulation verification method according to any one of claims 1 to 7 is implemented.