A bidirectional aggregation computing accelerator and system for GCN

Abstract

This invention discloses a bidirectional aggregation computation accelerator for graph convolutional networks (GCNs), relating to the field of graph convolutional network technology. It includes a preprocessing algorithm, CPU, DDR, controller, bidirectional connection aggregation computation array, connection edge data buffer, sliding data table, node data buffer, feature matrix buffer, conflict data buffer, and aggregation result buffer. The CPU configures the size of the bidirectional aggregation computation array and the number of rows for data sliding. The preprocessing algorithm determines whether data sliding is necessary and records this in the sliding data table. The preprocessing algorithm schedules the product results and writes them to the aggregation result buffer. This invention reduces decoding complexity by using simple sliding data information and slides the computation results to the corresponding computation units, reducing hardware resource consumption. It effectively solves the problem of uneven load distribution among computation units caused by uneven distribution of connection edge data, significantly improving the utilization rate of computation units and exhibiting better configurability and versatility.

Description

Technical Field

[0001] This invention relates to the field of graph convolutional network technology, and more specifically, to a bidirectional aggregation computing accelerator and system for GCN. Background Technology

[0002] In recent years, with the rapid development of artificial intelligence and big data technologies, Graph Convolutional Networks (GCNs), as an emerging deep learning method, have demonstrated outstanding capabilities in modeling and learning graph-structured data, and have achieved breakthroughs in multiple application areas such as social network analysis, bioinformatics, and recommender systems. With continuous technological advancements and the ongoing expansion of application scenarios, the application prospects of GCNs will become even broader.

[0003] In real-world graph datasets, graphs typically exhibit irregular structures, leading to uneven node distribution and irregular adjacency matrices. The sparsity of the feature matrix varies across different datasets; for example, the feature matrix of the Core dataset is highly sparse, while that of the Reddit dataset is dense. Therefore, GCN requires sparse-to-sparse or sparse-to-dense matrix multiplication when performing node aggregation. This large-scale and irregular computational pattern presents significant challenges to hardware architecture.

[0004] Currently, traditional hardware architectures are poorly adapted to irregular computing needs, which can easily lead to a waste of computing resources and low computing efficiency. On the other hand, architectures with high computing efficiency often require complex software scheduling or hardware design, which is not conducive to subsequent system integration and layout routing. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies, such as the poor adaptability of traditional hardware structures to irregular computing needs, which easily leads to the waste of computing resources and low computing efficiency, while high computing efficiency architectures often require complex software scheduling or hardware design, which is not conducive to subsequent system integration and layout routing. This invention provides a bidirectional aggregation computing accelerator for GCN.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] A bidirectional aggregation computing accelerator for GCN includes: a CPU, a preprocessing algorithm, DDR, a controller, a bidirectional connection aggregation computing array, a connection edge data buffer, a sliding data table, a node data buffer, a feature matrix buffer, a conflict data buffer, and an aggregation result buffer;

[0008] The CPU configures the size of the bidirectional aggregation computing array and the number of rows of data sliding, and determines whether each connection edge data needs to be slidable through the preprocessing algorithm. The preprocessing algorithm schedules the product results in the bidirectional connection aggregation computing array and obtains the sliding data table based on the result of the preprocessing algorithm.

[0009] The CPU configures the controller and initiates read and write operations on the DDR. The controller reads the node information of the connection edge data buffer and controls the data flow direction of the corresponding data of the node data buffer and the feature matrix buffer in each computing unit of the bidirectional connection aggregation computing array according to the information in the sliding data table. The conflict data buffer is used to store redundant connection edge data in the node that cannot be slidable.

[0010] After the calculation is completed, the calculation unit sends an end signal, and the calculation result is written to the aggregation result buffer.

[0011] As a preferred embodiment, the preprocessing algorithm includes the following steps:

[0012] Initialize by creating a fixed list of boxes, an empty sequence to store numbers that cannot be placed in a box, and state parameters for all boxes;

[0013] Input a sequence of numbers and iterate through it, count the number of times each number appears, and split the input sequence of numbers into sequences of the first and subsequent occurrences.

[0014] Iterate through the first occurrence of the number sequence. If the box corresponding to the number is empty, put the corresponding number in it and set the state parameter of the box.

[0015] Iterate through the sequence of numbers that do not appear for the first time. For each number, first check the box before the corresponding box with an index greater than 1. If the previous box is empty, put the number in and update the state parameter of the corresponding box. If the previous box is not empty, check the box after the corresponding box with an index less than the total number of boxes. If the next box is empty, put the number in and update the state parameter of the corresponding box. If the next box is not empty either, add the number to the empty sequence.

[0016] Iterate through all boxes and update the state parameters of empty boxes;

[0017] The output includes the state parameters of each box and the sequence of numbers that cannot be placed into the box.

[0018] As a preferred embodiment, the sliding data table includes connection edge data, sliding information configuration, and valid value flag. The sliding information configuration indicates that the product result does not need to slide, or slides up or down. The valid value flag indicates whether the value of the second multiplier in the product result is valid.

[0019] As a preferred embodiment, the preprocessing algorithm schedules the product results in the bidirectional join aggregation calculation array and obtains the sliding data table based on the result determined by the preprocessing algorithm, specifically including:

[0020] When a node has only one connected edge data, the corresponding feature data in the feature matrix buffer is written into the computing unit of the node;

[0021] When a node has multiple connection edge data, the feature data corresponding to the first occurrence of the connection edge is written into the calculation unit of the node, and the neighboring nodes of the node are traversed to see if they have connection edge data. If the neighboring node has no connection edge data, the feature data corresponding to the connection edge that does not occur for the first time is written into the calculation unit of the neighboring node, and the result is written into the sliding data table. If the neighboring node has connection edge data, the extra connection edge data is stored in the conflict data buffer. The results of the above operations are recorded by the sliding data table.

[0022] As a preferred embodiment, after the calculation is completed, the calculation unit issues an end signal and writes the calculation result into the aggregation result buffer, specifically as follows:

[0023] After the calculation is completed, the calculation unit sends an end signal and writes the calculation result into the aggregation result buffer. If a node has redundant connection edge data and cannot perform data sliding, the redundant connection edge data is stored in the conflict data buffer.

[0024] As a preferred embodiment, the bidirectional interconnected aggregation computing array consists of several rows of computing units, and each row of computing units is connected to adjacent uplink computing units and downlink computing units by a network.

[0025] As a preferred embodiment, the calculation unit includes 5 input signals and 3 output signals. The input signals are m1, m2, mr1, mr2 and the sliding information configuration, respectively. The output signals are ps1, ps2 and outAggrData, respectively. m1 and m2 are two values ​​that are multiplied in the calculation unit. mr1 and mr2 are the product data from the adjacent previous row and the adjacent next row, respectively, which are used for accumulation in this calculation unit. ps1 and ps2 are the product results output by this calculation unit, which are sent to the calculation units of the adjacent previous row and the adjacent next row for accumulation.

[0026] Of the five input signals and three output signals, except for the sliding information configuration, the remaining input signals and output signals all include payload and valid. The payload represents the value itself, and the valid is used to mark whether the value is valid.

[0027] As a preferred embodiment, the aggregation calculation process within the computing unit includes:

[0028] First, determine whether to multiply based on the validity of m1 and m2. If both signals are valid, the value is sent to the multiplier. The input sliding information configuration is used as the control signal for the product result, which controls whether the product result is output to ps1, ps2 or sent to the adder.

[0029] If the output is sent to an external adder, the valid value of the corresponding ps1 or ps2 is set to high level; otherwise, it is set to low level.

[0030] Next, determine whether the input signals mr1 and mr2 are valid. If only one signal is valid, add the product result to that signal. If both are valid, add the product result to both input signals.

[0031] Each computing unit has a built-in register reg, which is used to temporarily store the result of multiplication and addition. When the calculation result data of the next slice arrives, the data in reg is added to the data. When the end signal is pulled high, the data in reg is output, indicating that the aggregation calculation of the node has been completed.

[0032] As a preferred embodiment, the number of rows in the bidirectional connection aggregation computing array is equal to the number of target nodes configured, and the number of columns is equal to the dimension of the feature matrix.

[0033] To achieve the objective of the invention, another aspect of the present invention provides a bidirectional aggregation computing acceleration system for GCN, which applies the bidirectional aggregation computing accelerator for GCN described above. The system includes:

[0034] The algorithm module includes a preprocessing algorithm to determine whether each connection edge data of each slice needs to be slid.

[0035] The data storage module includes DDR, node data buffer, sliding data table, connection edge data buffer, feature matrix buffer, conflict data buffer, and aggregation result buffer, which are used for storing various types of data;

[0036] The aggregation computing module includes a bidirectional connection aggregation computing array, which includes several rows of computing units for performing bidirectional aggregation computing.

[0037] The controller module includes a controller. The controller first controls the reading and writing of DDR, moving off-chip data to the on-chip buffer. Secondly, the controller controls the data of the sliding data table, node data buffer, and feature matrix buffer to be transmitted to the computing array according to the information of the connection edge data buffer. The controller also controls the storage of conflicting data in the conflicting data buffer.

[0038] The configuration module, including a CPU, is used to configure the size of the bidirectional interconnected aggregation computing array and the number of rows of data sliding, run the preprocessing algorithm, configure the controller module, and initiate read and write operations to the DDR.

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0040] This invention addresses the problem of uneven load distribution among computing units caused by uneven distribution of connection edge data and irregular calculations. On the software side, a preprocessing algorithm is used to determine whether each connection edge data needs to slide, and the determination result is recorded in a sliding data table. On the hardware side, node data buffer data is loaded into the computing unit, and the corresponding feature matrix buffer data is written into the corresponding computing unit according to the sliding data table, controlling the sliding data flow of the product result. The simple sliding data information reduces the complexity of decoding, enabling the hardware to quickly determine data scheduling, significantly improving the utilization and computational efficiency of the computing units in the computing array. The size of the computing array and the number of sliding rows are configurable, offering better configurability and versatility. Attached Figure Description

[0041] Figure 1 This is an overall framework diagram of a bidirectional aggregation computing accelerator for GCN according to this application;

[0042] Figure 2 This is a schematic diagram of the sliding data table of Embodiment 1 of this application;

[0043] Figure 3 This is a flowchart of the preprocessing algorithm in this application;

[0044] Figure 4 This is an interface signal diagram of a single computing unit in Embodiment 1 of this application;

[0045] Figure 5 This is an internal circuit design diagram of a single computing unit according to Embodiment 1 of this application;

[0046] Figure 6 This is a structural diagram of the bidirectional interconnected aggregation computing array of Embodiment 1 of this application;

[0047] Figure 7 This is a schematic diagram of a computational example of a bidirectional aggregation computing array according to Embodiment 2 of this application. Detailed Implementation

[0048] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0049] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0050] Example 1

[0051] Embodiment 1 of this application provides a bidirectional aggregation computing accelerator for GCN, comprising:

[0052] CPU, preprocessing algorithm, DDR, controller, bidirectional connection aggregation computing array, connection edge data buffer, sliding data table, node data buffer, feature matrix buffer, conflict data buffer, and aggregation result buffer;

[0053] The CPU configures the size of the bidirectional aggregation computing array and the number of rows of data sliding, and uses a preprocessing algorithm to determine whether each connection edge data needs to be slid. The preprocessing algorithm schedules the product results in the bidirectional connection aggregation computing array and obtains the sliding data table based on the results of the preprocessing algorithm.

[0054] The CPU configures the controller and initiates read and write operations on the DDR. The controller reads the node information of the connection edge data buffer and controls the data flow of the corresponding data in the node data buffer and feature matrix buffer in each computing unit of the bidirectional connection aggregation computing array according to the information in the sliding data table. The conflict data buffer is used to store redundant connection edge data in the node that cannot be slid.

[0055] After the calculation is completed, the calculation unit sends an end signal and writes the calculation result to the aggregation result buffer.

[0056] The technical solution described above in Example 1 of the present invention will now be fully described in conjunction with the accompanying drawings. For ease of explanation, PE (process element) in the drawings represents the computing unit connected to the network in the bidirectional aggregate computing array.

[0057] Please see Figure 1The entire accelerator comprises a CPU, Double Data Rate Synchronous Dynamic Random Access Memory (DDR), a sliding data table obtained through a preprocessing algorithm, node data buffers, edge data buffers, feature matrix buffers, a controller, a bidirectional connection aggregation computing array, a conflict data buffer, and an aggregation result buffer. The CPU first configures the computing array size and the number of sliding rows. Then, it uses an intelligent preprocessing algorithm to determine whether each edge data in each slice needs to be slid. The sliding data table records the algorithm's traversal results, and the controller is configured via the AXI bus, initiating read and write operations to the DDR. Since graph data is typically very large, the DDR is used for storing large amounts of data, including node data buffers, edge data buffers, feature matrix buffers, conflict data buffers, aggregation result buffers, and the preprocessed sliding data table. The controller reads the node information from the edge data buffers, controls the writing of corresponding data from the node buffer and feature matrix buffer into the multiply-accumulate unit array, and writes it into the corresponding computing units according to the configuration information in the sliding data table, thereby controlling the data flow of each computing unit in the computing array. After the calculation is completed, the calculation unit sends an end signal and writes the calculation result into the aggregation result buffer. If a node has redundant connection edge data and cannot perform data sliding, the redundant connection edge data is stored in the conflict data buffer.

[0058] Please see Figure 2 , Figure 2 This is a sliding information table preprocessed by the CPU using an intelligent preprocessing algorithm. The hardware controls the sliding data flow based on the information in the table. Here, `config` represents the connection edge data; for example, [1, r1, 3] represents node 1 and node 3 connected by relation r1. `isOrNo` is the sliding information configuration, indicating whether the product data needs to slide: 0 means the data does not slide and is sent to the adder, 1 means the data slides downwards, and 2 means the data slides upwards. `m2.valid` is the valid value flag, indicating whether the value of the second multiplier is valid. For example, if node 4 has no connected nodes, the value multiplied by node 4 is invalid.

[0059] Please see Figure 3 , Figure 3 The process of preprocessing for intelligent preprocessing algorithms.

[0060] Step 1: Initialization: Create a fixed number of boxes and an empty sequence to store numbers that cannot be placed in boxes, as well as the state parameters of all boxes; Step 2: Data Preprocessing and Classification: Traverse the input sequence, count the occurrences of numbers, and split the input sequence into sequences of numbers appearing for the first time and sequences of numbers appearing for the last time; Step 3: Processing the Sequence of Numbers Appearing for the First Time: Traverse the sequence of numbers appearing for the first time. If the corresponding box is empty, place the number in it and set the box's state parameters; Step 4: Processing the Sequence of Numbers Appearing for the Last Time: Traverse the sequence of numbers appearing for the last time. For each number, first check the box preceding the corresponding box (if the number is greater than 1). If the preceding box is empty... If the box is empty, insert a number and update the box state: isorNO = 2 and m2Valid = 1. If the previous box is not empty, check the next box with the corresponding number (if the number is less than the total number of boxes). If the next box is empty, insert a number and update the box state parameters: isorNO = 2 and m2Valid = 1. If the next box is not empty, add the number to the empty sequence. Step 5: Handle empty boxes and missing numbers: Iterate through all boxes. For empty boxes, set m2Valid to False. Step 6: Output the results: Output the state of each box, the sequence of numbers that cannot be inserted into the box, and the state parameters of each box.

[0061] Please see Figure 4 For a single computational unit (PE), there are 5 input signals and 3 output signals. Except for the sliding information configuration, the other signals are composed of payload and valid. The payload represents the value itself, and the valid is used to mark whether the value is valid. m1 and m2 are two values ​​that are fed into the PE for multiplication; mr1 and mr2 are the product data from the adjacent previous row and the adjacent next row, respectively, used for accumulation in this PE; ps1 and ps2 are the product results of this PE, which are sent to the PEs of the adjacent previous row and the adjacent next row for accumulation.

[0062] Please see Figure 5 , attached Figure 5This is the internal circuit design diagram of a single PE. The specific calculation process within the calculation unit is as follows: First, it determines whether to multiply based on the validity of m1 and m2. If both signals are valid, the value is sent to the multiplier. The input sliding information isOrNo serves as the control signal for the product result, controlling whether the product result is output to ps1, ps2, or sent to the adder. If output to the outside, the validity value of the corresponding ps is set to high; otherwise, it is set to low. Next, it checks whether the validity of input signals mr1 and mr2 is valid. If only one signal is valid, the product result is added to it; if both are valid, the product result is added to both input signals. Each PE has a built-in register (reg) to temporarily store the result of the multiplication and addition calculation. When the calculation result data of the next slice arrives, the data in reg is added to that data. When the end signal goes high, the data in reg is output, indicating that the aggregation calculation of this node has been completed.

[0063] Please see Figure 6 The size of the bidirectional multiply-accumulate array depends on the CPU configuration, as shown in the attached diagram. Figure 6 The number of rows represents the number of target nodes configured, and the number of columns represents the dimension of the feature matrix. When the end signal goes high, the reg data of each PE is output, and the values ​​of each PE are concatenated and fed into a FIFO (First-In-First-Out, an important data structure used to store and transmit data in a data stream). Furthermore, the parameters for bidirectional connections of each PE can also be configured, meaning that the data sliding of each PE can be configured to slide up or down N rows.

[0064] Example 2

[0065] Please see Figure 7 This embodiment 2 further explains the computational process implementation of the bidirectional aggregation computing array based on the accelerator of embodiment 1, including:

[0066] according to Figure 7 The information in the adjacency matrix in the left-middle diagram is used to calculate the data flow direction of each PE in the array. Figure 7 As shown in the middle right figure, for the data set [2,r3,4], the calculation is performed in the row PE of node 3, and the result of the multiplication is sent to the row PE of node 2 for accumulation; for the data set [6,r6,5], the calculation is performed in the row PE of node 5, and the result of the multiplication is sent to the row PE of node 6 for accumulation; node 4 has no connected data, so there is no related calculation operation.

[0067] The other technical details and steps of this embodiment 2 are the same as those of embodiment 1, and will not be repeated here.

[0068] Example 3

[0069] This embodiment 3 also provides a bidirectional aggregation computing acceleration system for GCN, which applies a bidirectional aggregation computing accelerator for GCN provided in embodiment 1. The system includes the following modules:

[0070] The algorithm module includes a preprocessing algorithm to determine whether each connection edge data of each slice needs to be slid.

[0071] The data storage module includes DDR, node data buffer, sliding data table, connection edge data buffer, feature matrix buffer, conflict data buffer, and aggregation result buffer, which are used for storing various types of data;

[0072] The aggregation computing module includes a bidirectional connection aggregation computing array, which includes several rows of computing units for performing bidirectional aggregation computing.

[0073] The controller module includes a controller. The controller first controls the reading and writing of DDR, moving off-chip data to the on-chip buffer. Secondly, the controller controls the data of the sliding data table, node data buffer, and feature matrix buffer to be transmitted to the computing array according to the information of the connection edge data buffer. The controller also controls the storage of conflicting data in the conflicting data buffer.

[0074] The configuration module, including the CPU, is used to configure the size of the bidirectional interconnected aggregation computing array and the number of rows of data sliding, run the preprocessing algorithm, configure the controller module, and initiate read and write operations to the DDR.

[0075] Other technical details and implementation steps of this embodiment 3 are the same as those of embodiment 1, and will not be repeated here.

[0076] As can be seen from the above embodiments, the present invention effectively solves the problem of uneven load on each computing unit caused by uneven distribution of connection edge data, and significantly improves the utilization rate of computing units in the computing array. The simple sliding data information reduces the complexity of decoding, enabling the hardware to quickly determine the scheduling of data and slide the calculation results to the corresponding computing units, thereby reducing the consumption of hardware resources. The size of the computing array and the number of sliding rows can be configured to meet the multiplication and addition operation requirements of a node corresponding to multiple connection edge data, and has better configurability and versatility.

[0077] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A bidirectional aggregation computing accelerator for GCN, characterized in that, include: The algorithm module includes a preprocessing algorithm to determine whether each connection edge data of each slice needs to be slid. The data storage module includes DDR, node data buffer, sliding data table, connection edge data buffer, feature matrix buffer, conflict data buffer, and aggregation result buffer, which are used for storing various types of data; The aggregation computing module includes a bidirectional connection aggregation computing array, which includes several rows of computing units for performing bidirectional aggregation computing. The controller module includes a controller. The controller first controls the reading and writing of DDR, moving off-chip data to the on-chip buffer. Secondly, the controller controls the data of the sliding data table, node data buffer, and feature matrix buffer to be transmitted to the computing array according to the information of the connection edge data buffer. The controller also controls the storage of conflicting data in the conflicting data buffer. The configuration module, including the CPU, is used to configure the size of the bidirectional connection aggregation computing array and the number of rows of data sliding, run the preprocessing algorithm, configure the controller module, and initiate read and write operations to the DDR. The CPU configures the size of the bidirectional connection aggregation computing array and the number of rows of data sliding, and determines whether each connection edge data needs to be slidable through the preprocessing algorithm. The preprocessing algorithm schedules the product results in the bidirectional connection aggregation computing array and obtains the sliding data table based on the result of the preprocessing algorithm. The CPU configures the controller and initiates read and write operations on the DDR. The controller reads the node information of the connection edge data buffer and controls the data flow direction of the corresponding data of the node data buffer and the feature matrix buffer in each computing unit of the bidirectional connection aggregation computing array according to the information in the sliding data table. The conflict data buffer is used to store redundant connection edge data in the node that cannot be slidable. After the calculation is completed, the calculation unit sends an end signal, and the calculation result is written to the aggregation result buffer.

2. The bidirectional aggregation computing accelerator for GCN according to claim 1, characterized in that, The preprocessing algorithm includes the following steps: Initialize by creating a fixed list of boxes, an empty sequence to store numbers that cannot be placed in a box, and state parameters for all boxes; Input a sequence of numbers and iterate through it, count the number of times each number appears, and split the input sequence of numbers into sequences of the first and subsequent occurrences. Iterate through the first occurrence of the number sequence. If the box corresponding to the number is empty, put the corresponding number in it and set the state parameter of the box. Iterate through the sequence of numbers that do not appear for the first time. For each number, first check the box before the corresponding box with an index greater than 1. If the previous box is empty, put the number in and update the state parameter of the corresponding box. If the previous box is not empty, check the box after the corresponding box with an index less than the total number of boxes. If the next box is empty, put the number in and update the state parameter of the corresponding box. If the next box is not empty either, add the number to the empty sequence. Iterate through all boxes and update the state parameters of empty boxes; The output includes the state parameters of each box and the sequence of numbers that cannot be placed into the box.

3. A bidirectional aggregation computing accelerator for GCN according to claim 2, characterized in that, The sliding data table includes connection edge data, sliding information configuration, and valid value flag. The sliding information configuration indicates that the product result does not need to slide, or slides up or down. The valid value flag indicates whether the value of the second multiplier in the product result is valid.

4. A bidirectional aggregation computing accelerator for GCN according to claim 1, characterized in that, The preprocessing algorithm schedules the product results in the bidirectional join aggregation calculation array and obtains the sliding data table based on the result of the preprocessing algorithm, specifically including: When a node has only one connected edge data, the corresponding feature data in the feature matrix buffer is written into the computing unit of the node; When a node has multiple connection edge data, the feature data corresponding to the first occurrence of the connection edge is written into the calculation unit of the node, and the neighboring nodes of the node are traversed to see if they have connection edge data. If the neighboring node has no connection edge data, the feature data corresponding to the connection edge that does not occur for the first time is written into the calculation unit of the neighboring node, and the result is written into the sliding data table; if the neighboring node has connection edge data, the extra connection edge data is stored in the conflict data buffer.

5. A bidirectional aggregation computing accelerator for GCN according to claim 1, characterized in that, After the calculation is completed, the calculation unit issues an end signal, and the calculation result is written to the aggregation result buffer, specifically: After the calculation is completed, the calculation unit sends an end signal, and the calculation result is written into the aggregation result buffer. If a node has redundant connection edge data and its product result cannot be slid to other calculation units, the redundant connection edge data is stored in the conflict data buffer.

6. A bidirectional aggregation computing accelerator for GCN according to claim 3, characterized in that, The bidirectional interconnected aggregation computing array consists of several rows of computing units, and each row of computing units is connected to adjacent uplink computing units and downlink computing units by a network.

7. A bidirectional aggregation computing accelerator for GCN according to claim 6, characterized in that, The calculation unit includes 5 input signals and 3 output signals. The input signals are m1, m2, mr1, mr2 and the sliding information configuration, respectively. The output signals are ps1, ps2 and outAggrData, respectively. m1 and m2 are two values ​​that are multiplied in the calculation unit. mr1 and mr2 are the product data from the adjacent previous row and the adjacent next row, respectively, which are used for accumulation in this calculation unit. ps1 and ps2 are the product results output by this calculation unit, which are sent to the calculation units of the adjacent previous row and the adjacent next row for accumulation. Of the five input signals and three output signals, except for the sliding information configuration, the remaining input signals and output signals all include payload and valid. The payload represents the value itself, and the valid is used to mark whether the value is valid.

8. A bidirectional aggregation computing accelerator for GCN according to claim 7, characterized in that, The aggregation calculation process within the computing unit includes: First, determine whether to multiply based on the validity of m1 and m2. If both signals are valid, the value is sent to the multiplier. The input sliding information configuration is used as the control signal for the product result, which controls whether the product result is output to ps1, ps2 or sent to the adder. If the output is sent to an external adder, the valid value of the corresponding ps1 or ps2 is set to high level; otherwise, it is set to low level. Next, determine whether the input signals mr1 and mr2 are valid. If only one signal is valid, add the product result to that signal. If both are valid, add the product result to both input signals. Each computing unit has a built-in register reg, which is used to temporarily store the result of multiplication and addition. When the calculation result data of the next slice arrives, the data in reg is added to the data. When the end signal is pulled high, the data in reg is output, indicating that the aggregation calculation of the node has been completed.

9. A bidirectional aggregation computing accelerator for GCN according to claim 1, characterized in that, The number of rows in the bidirectional connection aggregation computing array is the number of configured target nodes, and the number of columns is the dimension of the feature matrix.

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