Pixel circuit and driving method thereof, display panel and display device

Abstract

The invention provides a pixel circuit and a driving method thereof, a display panel and a display device, and the pixel circuit comprises a driving sub-circuit which comprises a driving transistor, is electrically connected between a first node and a second node, and is configured to generate a driving current from a first power signal end to a light-emitting unit, the first light-emitting control sub-circuit is electrically connected to the second node, the anode of the light-emitting unit and a first light-emitting control end, and is configured to transmit a driving current to the anode based on a signal of the first light-emitting control end and drive the light-emitting unit to emit light; and the driving unit is electrically connected to the first power signal end, the second power signal end, the second light-emitting control end and the anode, and is configured to transmit a first power signal of the first power signal end to the anode and drive the light-emitting unit to emit light based on a signal of the second light-emitting control end. According to the embodiment provided by the invention, the width of the PWM black bar is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] In the field of display technology, in order to achieve better frequency conversion effects, a pixel architecture based on an oxide process is currently generally adopted. This architecture involves multiple reset periods, resulting in a wider invalid level period for light control and a longer black bar width for PWM (Pulse-Width Modulation). Summary of the invention

[0003] In order to solve at least one of the above problems, the present disclosure provides a pixel circuit according to a first aspect, comprising: a driving subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, and a light-emitting unit.

[0004] The driving subcircuit includes a driving transistor electrically connected between the first node and the second node, and configured to generate a driving current from the first power signal terminal to the light emitting unit,

[0005] The first light-emitting control subcircuit is electrically connected to the second node, the anode of the light-emitting unit and the first light-emitting control terminal, and is configured to transmit the driving current to the anode based on the signal of the first light-emitting control terminal and drive the light-emitting unit to emit light,

[0006] The second light-emitting control subcircuit is electrically connected to the first power signal terminal, the second power signal terminal, the second light-emitting control terminal and the anode, and is configured to transmit the first power signal of the first power signal terminal to the anode and drive the light-emitting unit to emit light based on the signal of the second light-emitting control terminal.

[0007] Optionally, the second light emitting control subcircuit includes: a first transistor, a second transistor and a third transistor,

[0008] The first transistor has a first electrode electrically connected to the third node, a second electrode electrically connected to the anode, and a control electrode electrically connected to the second light emitting control terminal.

[0009] The first electrode of the second transistor is electrically connected to the second power signal terminal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second light emitting control terminal.

[0010] A first electrode and a control electrode of the third transistor are electrically connected to the first power signal terminal, and a second electrode is electrically connected to the third node.

[0011] Optionally, the first transistor and the third transistor are N-type transistors, and the second transistor is a P-type transistor.

[0012] Optionally, the polarity of the effective level of the second light emitting control terminal is opposite to the polarity of the effective level of the first light emitting control terminal.

[0013] The signal connected to the second light-emitting control terminal is a signal connected to the first light-emitting control terminal delayed by a plurality of Hs, where H is the time for the signal connected to the first light-emitting control terminal to scan a row of light-emitting units.

[0014] Optionally, the pixel circuit further includes: a compensation subcircuit and a writing subcircuit,

[0015] The writing subcircuit is electrically connected to the first node, the data signal terminal and the data control terminal, and is configured to transmit the data signal connected to the data signal terminal to the first node based on the signal of the data control terminal.

[0016] The compensation subcircuit is electrically connected to the second node, a fourth node corresponding to the control electrode of the driving transistor and the compensation control terminal, and is configured to electrically connect the second node and the fourth node based on a signal of the compensation control terminal.

[0017] Optionally, the pixel circuit further includes: a first reset subcircuit and a second reset subcircuit,

[0018] The first reset subcircuit is electrically connected to the first reset signal terminal, the second node, and the second reset control terminal, and is configured to transmit the signal of the first reset signal terminal to the second node based on the signal of the first reset control terminal.

[0019] The second reset subcircuit is electrically connected to the second reset signal terminal, the anode, and the second reset control terminal, and is configured to transmit the signal of the second reset signal terminal to the anode based on the signal of the second reset control terminal.

[0020] Optionally, the pixel circuit further includes: a third reset subcircuit electrically connected to the third reset signal terminal, the first node and the third reset control terminal, and configured to transmit the signal of the third reset signal terminal to the first node based on the signal of the third reset control terminal.

[0021] Optionally, the first light emitting control subcircuit includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the second node, a second electrode is electrically connected to the anode, and a control electrode is electrically connected to the first light emitting control terminal.

[0022] The compensation sub-circuit includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the second node, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the compensation control terminal.

[0023] The writing sub-circuit includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the data signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the data control terminal.

[0024] The pixel circuit further includes a first capacitor, a first electrode of the first capacitor is electrically connected to the first power signal terminal, and a second electrode of the first capacitor is electrically connected to the fourth node.

[0025] Optionally, the pixel circuit also includes a third light-emitting control subcircuit, which includes a seventh transistor, a first electrode of the seventh transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the third light-emitting control terminal.

[0026] A second aspect of the present disclosure provides a display panel, comprising the pixel circuit described above.

[0027] A third aspect of the present disclosure provides a display device, comprising the display panel described above.

[0028] A fourth aspect of the present disclosure provides a driving method of the pixel circuit as described above, comprising:

[0029] In the first light-emitting stage, the second light-emitting control subcircuit transmits the first power signal of the first power signal terminal to the anode and drives the light-emitting unit to emit light based on the signal of the second light-emitting control terminal being at an effective level, and the first light-emitting control subcircuit disconnects the second node from the anode based on the signal of the first light-emitting control terminal being at an invalid level.

[0030] In the second light emitting stage, the first light emitting control subcircuit transmits the driving current from the second node to the anode based on the signal at the first light emitting control terminal being at an effective level, and drives the light emitting unit to emit light.

[0031] The beneficial effects of the present disclosure are as follows:

[0032] In response to the existing problems, the present disclosure develops a pixel circuit and a driving method thereof, a display panel, and a display device. By providing a second light-emitting control subcircuit, and the second light-emitting control subcircuit provides a path for the flow of driving current independent of the driving subcircuit, the voltage provided by the first power supply signal is used to emit light during a period when the driving current is not provided to the light-emitting unit, thereby reducing the time width of the black bar of the light-emitting unit, thereby reducing flicker, improving the eye protection effect certification value of the stroboscopic visibility measure (SVM), and thus improving the user experience of the display product. The display product has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 An exemplary circuit schematic diagram of a pixel circuit according to the related art is shown;

[0035] Figure 2 An exemplary timing diagram showing key ports of the related art;

[0036] Figure 3 A schematic block diagram of a pixel circuit according to an embodiment of the present disclosure is shown;

[0037] Figure 4 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

[0038] Figure 5 A signal timing diagram of key ports of a pixel circuit according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] In order to more clearly illustrate the present disclosure, the present disclosure is further described below in conjunction with preferred embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present disclosure.

[0040] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate a quantitative limitation, but rather indicate the existence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. In addition, in the present disclosure, the electrical connection can be a direct connection or a connection separated by a certain conductive transistor.

[0041] The transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and drain. In the embodiment of the present disclosure, in order to distinguish the source and drain of the transistor, when the transistor is an N-type transistor, the drain is called the first pole, the source is called the second pole, and the gate is called the control pole. When the gate inputs a high level, the source and drain are turned on. In addition, when the gate and the source are both at a high level with equal potential, the source and drain are not turned on. When the transistor is a P-type transistor, the source is called the first pole, the drain is called the second pole, and the gate is called the control pole. When the gate inputs a low level, the source and drain are turned on. In addition, when the gate and the drain are both at a high level with equal potential, the source and drain are not turned on.

[0042] A pixel circuit based on an oxide process means that the pixel circuit contains a low-temperature polycrystalline silicon oxide (LTPO) transistor. In other words, the pixel circuit contains both N-type transistors and P-type transistors. Figure 1 The typical structure of a pixel circuit currently based on oxide technology is shown in FIG. Figure 1 As shown, the pixel circuit includes a circuit structure of 8 transistors T11-T18 and 1 capacitor C1 driving the light-emitting unit D1. In this circuit, only when the signal terminal EM is at an effective level, can the driving current generated by the transistor T13 as a driving transistor be provided to the light-emitting unit D1 and drive it to emit light. However, since there is at least one N-type transistor in the circuit, the transistors therein require different effective levels for driving, and multiple nodes have reset requirements, more groups of gate drive signals are required to provide scanning signals for the transistors. For example, Figure 1 The circuit shown in FIG. 1 requires five groups of gate drive circuits to provide signals to the control terminals EM, H-out, G-out, P-out, and E-out, respectively, and requires multiple resets of nodes N1 to N4. Figure 2 As shown in the figure, this results in a very long period of time when the control terminal EM is at an invalid level, usually more than 32 hours. This is much longer than the conventional 10 to 12 hours of the EM invalid level period of the pixel circuit of the conventional LTPS technology. As a result, a longer black bar time is caused that can be recognized by the naked eye, resulting in obvious flickering visually, so that the SVM eye protection index value deteriorates, the eye protection effect deteriorates, and the visual experience is significantly affected.

[0043] In order to achieve at least one of the above purposes, refer to Figure 3 As shown, an embodiment of the present disclosure provides a pixel circuit, comprising: a driving subcircuit 10, a first light-emitting control subcircuit 20, a second light-emitting control subcircuit 30, and a light-emitting unit 40, wherein:

[0044] The driving sub-circuit 10 includes a driving transistor, which is electrically connected between the first node N1 and the second node N2 and is configured to generate a driving current from the first power signal terminal VDD to the light emitting unit 40.

[0045] The first light-emitting control subcircuit 20 is electrically connected to the second node N2, the anode of the light-emitting unit 40 and the first light-emitting control terminal EM, and is configured to transmit a driving current to the anode based on a signal of the first light-emitting control terminal EM and drive the light-emitting unit 40 to emit light.

[0046] The second light-emitting control subcircuit EM+3 is electrically connected to the first power signal terminal VDD, the second power signal terminal VSS, the second light-emitting control terminal EM+3 and the anode, and is configured to transmit the first power signal of the first power signal terminal VDD to the anode and drive the light-emitting unit 40 to emit light based on the signal of the second light-emitting control terminal EM+3.

[0047] In this embodiment, a second light-emitting control subcircuit is provided, and the second light-emitting control subcircuit provides a path for the flow of driving current independent of the driving subcircuit, so that light is emitted by utilizing the voltage provided by the first power supply signal during a period when the driving current is not provided to the light-emitting unit, thereby reducing the time width of the black bar of the light-emitting unit, thereby reducing flicker, improving the SVM eye protection effect certification value, and thereby enhancing the user experience of the display product.

[0048] In order to explain in detail the structure and functional advantages of the pixel circuit in the embodiment of the present disclosure, a specific circuit structure is described in detail below in combination with specific examples.

[0049] In a specific example, refer to Figure 4 As shown, the pixel circuit includes: a driving subcircuit 10 , a first light emitting control subcircuit 20 , a second light emitting control subcircuit 30 , and a light emitting unit 40 .

[0050] Specifically, the light-emitting unit 40 may be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro light-emitting diode (Micro LED). In the embodiments of the present disclosure, any light-emitting element that can emit light under a driving current and can emit light when a certain amplitude of a power supply voltage is provided by the anode may be used. The light-emitting element is represented by D. In addition, although Figure 4A light emitting element D is shown in the figure, but it is for illustration only. The light emitting unit 40 may also include a plurality of light emitting elements connected in series. When the plurality of light emitting elements are connected in series, the anode of the light emitting element at the first position of the light emitting elements connected in series represents the anode of the light emitting unit 40.

[0051] Continue to refer to Figure 4 As shown, the driving subcircuit 10 includes a driving transistor DTFT. The driving subcircuit 10 is electrically connected between a first node N1 and a second node N2, and is configured to generate a driving current from the first power signal terminal VDD to the light emitting unit 40. Specifically, the cathode of the light emitting unit 40 is electrically connected to the power terminal VSS. In essence, the driving subcircuit 10 is used to generate a driving current that flows from the first power signal terminal VDD through the first node N1 and the second node N2 and finally to the power terminal VSS via the light emitting unit 40. The driving current is a current that is directly generated by the driving transistor DTFT and flows in the path from the first power signal terminal VDD to the power terminal VSS to cause the light emitting unit 40 to emit light.

[0052] Specifically, the first electrode of the driving transistor DTFT is electrically connected to the first node N1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to Figure 4 The fourth node N4 in the transistor is configured to generate a driving current based on a signal of the control electrode.

[0053] Continue to refer to Figure 4 As shown, the first light-emitting control subcircuit 20 is electrically connected to the second node N2, the anode of the light-emitting unit 40 and the first light-emitting control terminal EM, and is configured to transmit the driving current to the anode based on the signal of the first light-emitting control terminal EM and drive the light-emitting unit 40 to emit light. That is, when the signal of the first light-emitting control terminal EM is at an effective level, a light-emitting path of the branch where the driving transistor DTFT is located is formed.

[0054] In particular, in the embodiment of the present disclosure, the pixel circuit further includes a second control subcircuit 30, which is electrically connected between the first power signal terminal VDD and the anode of the light-emitting unit 40, and is specifically electrically connected to the first power signal terminal VDD, the second power signal terminal VGH, the second light-emitting control terminal EM+3 and the anode, and is configured to transmit the first power signal of the first power signal terminal VDD to the anode and drive the light-emitting unit 40 to emit light based on the signal of the second light-emitting control terminal EM+3. Figure 4 In the embodiment, the first light emitting control sub-circuit 20 and the second light emitting control sub-circuit 30 are both electrically connected to the anode and intersect to form a fifth node N5.

[0055] Through this arrangement, a new light-emitting control path is added outside the path where the driving subcircuit 10 is located. Through this arrangement, it is controlled by the second light-emitting control terminal EM+3, and can provide the voltage of the first power signal terminal VDD to the anode of the light-emitting unit 40 in response to the signal of the second light-emitting control terminal EM+3, so that the light-emitting unit 40 is driven to emit light by using the first power signal terminal VDD as the power supply terminal. Furthermore, during the time period when the path where the driving subcircuit is located does not form a light-emitting path, the light-emitting path where the second light-emitting control subcircuit is located is used to emit light, thereby achieving the effect of shortening the time length of displaying the black bar, thereby improving the SFM eye protection index, avoiding flickering that can be detected by users, and improving the display effect.

[0056] Specifically, refer to Figure 4 As shown, the second light-emitting control subcircuit 30 includes: a first transistor T1, a second transistor T2 and a third transistor T3. Among them, the first electrode of the first transistor T1 is electrically connected to the third node N3, the second electrode is electrically connected to the anode, and the control electrode is electrically connected to the second light-emitting control terminal EM+3, the first electrode of the second transistor T2 is electrically connected to the second power signal terminal VGH, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the second light-emitting control terminal EM+3. The first electrode and the control electrode of the third transistor T3 are electrically connected to the first power signal terminal VDD, and the second electrode is electrically connected to the third node N3.

[0057] In the embodiments of the present disclosure, referring to Figure 4 In the structure shown, when the second transistor T2 and the third transistor T3 are turned on at the same time, a short circuit is formed from the first power signal terminal VDD to the second light-emitting control terminal EM+3. When the first transistor T1 and the third transistor T3 are both turned on and the second transistor T2 is turned off, the voltage of the first power signal terminal VDD can be provided to the fifth node N5 and drive the light-emitting unit 40 to emit light. In other words, by setting the connection relationship of the third transistor T3 to enable it to be turned on, and setting the coordination of the first transistor T1 and the second transistor T2, the first transistor T1 is turned on and the second transistor T2 is turned off during the time period when the light-emitting time of the light-emitting unit 40 needs to be increased, and vice versa, the first transistor T1 is turned off and the second transistor T2 is turned on.

[0058] In this case, the conductivity types of the first transistor T1 and the second transistor T2 are opposite. Optionally, the first transistor T1 and the third transistor T3 are transistors of the same type, and are N-type transistors, and the second transistor T2 is a P-type transistor.

[0059] By setting the third transistor T3 as an N-type transistor in the case of conducting coordination, the signal end of the first power signal end VDD can be used to provide a control signal to the third transistor T3, so that the third transistor T3 forms a normally open tube, which reduces the number of signal lines and reduces the control difficulty.

[0060] In addition, in the embodiment of the present disclosure, the polarity of the effective level of the second light-emitting control terminal EM+3 is opposite to the polarity of the effective level of the first light-emitting control terminal EM, and the signal connected to the second light-emitting control terminal EM+3 is a signal connected to the first light-emitting control terminal EM delayed by multiple Hs, where H is the time for the signal connected to the first light-emitting control terminal to scan a row of light-emitting units.

[0061] In the embodiment of the present disclosure, the polarity of the effective level of the second light-emitting control terminal EM+3 refers to the polarity of the level that enables the second light-emitting control sub-circuit 30 to drive the light-emitting unit 40 to emit light. For example, specifically to the circuit, the effective level represents the signal polarity that can turn on the first transistor T1; similarly, the polarity of the effective level of the first light-emitting control terminal EM refers to the polarity of the level that enables the first light-emitting control sub-circuit 20 to drive the light-emitting unit 40 to emit light.

[0062] Specifically, the first light emitting control subcircuit 20 may include a fourth transistor T4, a first electrode of the fourth transistor T4 being electrically connected to the second node N2, a second electrode being electrically connected to the anode, and a control electrode being electrically connected to the first light emitting control terminal EM. When the first transistor T1 is an N-type transistor, the fourth transistor T4 is a P-type transistor.

[0063] Through this arrangement, the same group of gate driving circuits for controlling light control can be used to provide signals to the first light control terminal EM and the second light control terminal EM+3, and the effect of increasing the light-emitting time of the light-emitting unit 40 by using the second light control terminal EM+3 in a path outside the light-emitting path where the driving sub-circuit 10 is located is met. That is, the embodiment of the present disclosure only needs to add three transistors without adding peripheral control circuits, which is conducive to narrow frame design. The specific implementation method will be further described below in conjunction with the timing diagram, and will not be repeated here.

[0064] Optionally, continue to refer to Figure 4 As shown, the pixel circuit further includes a compensation subcircuit 50 and a writing subcircuit 60 .

[0065] Among them, the compensation subcircuit 50 is electrically connected to the second node N2, the fourth node N4 corresponding to the control electrode of the driving transistor DTFT and the compensation control terminal E-out, and is configured to electrically connect the second node N2 and the fourth node N4 based on the signal of the compensation control terminal E-out.

[0066] The write sub-circuit 60 is electrically connected to the first node N1, the data signal terminal Data and the data control terminal G-out, and is configured to transmit the data signal connected to the data signal terminal Data to the first node N1 based on the signal of the data control terminal G-out.

[0067] Specifically, the compensation sub-circuit 50 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected to the second node N2, a second electrode is electrically connected to the fourth node N4, and a control electrode is electrically connected to the compensation control terminal E-out. When the signal connected to the compensation control terminal E-out is at an effective level, the fifth transistor T5 is turned on, and the second node N2 and the fourth node N4 are turned on.

[0068] The writing sub-circuit 60 includes a sixth transistor T6, a first electrode of the sixth transistor T6 is electrically connected to the data signal terminal Data, a second electrode is electrically connected to the first node N1, and a control electrode is electrically connected to the data control terminal G-out. When the signal connected to the data control terminal G-out is at an effective level, the sixth transistor T6 is turned on, and the first node N1 and the data signal terminal Data are turned on, so that the signal of the data signal terminal Data is transmitted to the first node N1.

[0069] In addition, refer to Figure 4 As shown in the figure, the pixel circuit may further include: a first capacitor C1, a first electrode of the first capacitor C1 is electrically connected to the first power signal terminal VDD, and a second electrode is electrically connected to the fourth node N4. In this example, the first capacitor C1 is used to maintain the potential of the fourth node N4 to ensure that after the writing sub-circuit 60 writes the data signal of the data signal terminal Data into the fourth node N4, it can be compensated based on its potential holding ability and the driving transistor DTFT can be continuously turned on during the stage in which the driving transistor DTFT generates a driving current to drive the light-emitting unit 40 to emit light.

[0070] Optionally, refer to Figure 4 As shown, the pixel circuit further includes: a third light emitting control subcircuit 70. The third light emitting control subcircuit 70 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is electrically connected to the first power signal terminal VDD, a second electrode is electrically connected to the first node N1, and a control electrode is electrically connected to the third light emitting control terminal. In this example, the signal received by the third light emitting control terminal is the same as the signal received by the first control terminal, so Figure 4 The same symbol "EM" is used to identify them.

[0071] Those skilled in the art should understand that, if necessary, the signals of the two can also be different, and the specific setting method depends on the actual functions of the third light-emitting control subcircuit 70 and the first light-emitting control subcircuit 20 in the pixel circuit. For example, if the two have the function of conducting in other time periods in addition to controlling the flow of the driving current of the path where the driving subcircuit 10 is located, they may need to be controlled separately, which will not be described in detail here.

[0072] Optionally, continue to refer to Figure 4 As shown, the pixel circuit further includes: a first reset subcircuit 81 and a second reset subcircuit 82 .

[0073] Among them, the first reset sub-circuit 81 is electrically connected to the first reset signal terminal Vint1, the second node N2 and the second reset control terminal P-out, and is configured to transmit the signal of the first reset signal terminal Vint1 to the second node N2 based on the signal of the first reset control terminal P-out, so as to use the signal of the first reset signal terminal Vint1 to reset the second electrode of the driving transistor DTFT corresponding to the second node N2.

[0074] Specifically, the first reset sub-circuit 81 includes an eighth transistor T8, a first electrode of the eighth transistor T8 is electrically connected to the first reset signal terminal Vint1, a second electrode is electrically connected to the second node N2, and a control electrode is electrically connected to the first reset control terminal P-out. When the signal of the first reset control terminal P-out is at a valid level, the seventh transistor T7 is turned on to transmit the signal of the first reset signal terminal Vint1 to the second node.

[0075] The second reset sub-circuit 82 is electrically connected to the second reset signal terminal Vint2, the anode and the second reset control terminal H-out, and is configured to transmit the signal of the second reset signal terminal Vint2 to the anode based on the signal of the second reset control terminal H-out, so as to reset the potential corresponding to the anode using the signal of the second reset signal terminal Vint2.

[0076] The first reset sub-circuit 82 includes a ninth transistor T9, a first electrode of the ninth transistor T9 is electrically connected to the second reset signal terminal Vint2, a second electrode is electrically connected to the anode of the light-emitting unit 40, that is, the fourth node N4, and a control electrode is electrically connected to the second reset control terminal H-out. When the signal of the second reset control terminal H-out is at a valid level, the ninth transistor T9 is turned on to transmit the signal of the second reset signal terminal Vint2 to the anode of the light-emitting unit 40.

[0077] Optionally, continue to refer to Figure 4 As shown, the pixel circuit further includes: a third reset subcircuit 83. The third reset subcircuit 83 is electrically connected to the third reset signal terminal Vint3, the first node N1 and the third reset control terminal H-out, and is configured to transmit the signal of the third reset signal terminal Vint3 to the first node N1 based on the signal of the third reset control terminal H-out. In this example, the third reset control terminal receives the same signal as the second reset control terminal, and is therefore represented by the same reference numeral "H-out". However, those skilled in the art should understand that the present disclosure is not intended to be limited thereto, and in actual applications, the two can also be controlled by different signals.

[0078] Specifically, the third reset subcircuit 83 may include a tenth transistor T10, a first electrode of the tenth transistor T10 is electrically connected to the third reset signal terminal Vint3, a second electrode is electrically connected to the first node N1, and a control electrode is electrically connected to the third reset control terminal H-out. When the signal of the third reset control terminal H-out is at a valid level, the tenth transistor T10 is turned on, and the signal of the third reset signal terminal Vint3 is transmitted to the first node N1 to reset the potential of the first node N1.

[0079] It should be noted that although the pixel circuit given above includes Figure 4 The compensation sub-circuit 50, the writing sub-circuit 60, and the third light-emitting control sub-circuit 70 constitute a first light-emitting path, and Figure 4 The first, second and third reset subcircuits 81, 82 and 83 are shown electrically connected to the second node N2, the fifth node N5 (ie, the anode of the light emitting unit 40) and the first node N1, respectively, but the present disclosure is not limited thereto.

[0080] In other words, as long as it includes a first light-emitting path and a second light-emitting path, and the first light-emitting path uses a driving subcircuit composed of a driving transistor DTFT to generate a driving current and uses a signal based on a control terminal (i.e., the first light-emitting control terminal) to transmit the driving current to the light-emitting unit for light emission, the second light-emitting path is independent of the first light-emitting path, and can thus emit light by transmitting the voltage of the first light-emitting power signal terminal VDD to the anode of the light-emitting unit on the basis of control.

[0081] More specifically, the circuit structure constituting the first light emitting path is not limited to Figure 4 For example, on the basis that the pixel circuit includes a driving subcircuit and a first light-emitting control subcircuit, the position of the writing subcircuit can be changed, and the form of writing the data signal through the writing subcircuit can also be changed; for another example, the structural form of the compensation subcircuit can be changed, and it can be an internal compensation subcircuit that is performed simultaneously with the writing of the data signal, or it can be an internal compensation subcircuit that is performed separately from the writing of the data signal, and even the pixel subcircuit can also be in the form of external compensation, or a circuit structure in which internal compensation and external compensation are performed simultaneously.

[0082] In addition, the structure of the reset subcircuit for resetting each node in the pixel circuit may also be not limited to Figure 4 For example, the following description can be used to understand Figure 4In the structure, the first reset subcircuit can reset the fourth node N4 and the third node N3 at the same time, but it is not limited to this. The pixel circuit can also add a reset subcircuit to reset the fourth node N1 alone, or when the position of the first light-emitting path of the pixel circuit is adjusted, the position of the reset subcircuit may also be adjusted accordingly.

[0083] In conclusion, pixel circuits formed by other variant circuit structures except the driving subcircuit 10, the first light-emitting control subcircuit 20 and the second light-emitting control subcircuit 30 are all protected by the present disclosure.

[0084] In order to further understand the structure and function of the pixel circuit of the embodiment of the present disclosure, Figure 4 As an example, refer to the circuit structure shown in Figure 5 The timing diagram within one frame of image time shown describes the working principle of the pixel circuit of the embodiment of the present disclosure in each time period.

[0085] It should be noted that, in this example, the fifth transistor T5, the first transistor T1 and the third transistor T3 are N-type transistors, and the other transistors are all P-type transistors. In addition, for ease of understanding, except that the data signal connected to the data signal terminal Data is represented as Vdata, the potentials of other ports are represented by the corresponding port names. Of course, the type of the fifth transistor T5 is only exemplary and can be changed as needed. Similarly, the types of other transistors can also be changed as needed.

[0086] It should also be noted that, in this example, the first light-emitting control terminal, the second light-emitting control terminal and the third light-emitting control terminal are provided with signals by the same group of gate driving circuits, and the first light-emitting control terminal and the third light-emitting control terminal are connected to the scanning signal of the same row and thus are connected to the same signal, which is represented by "EM"; the signal connected to the second light-emitting control terminal is a scanning signal that is 6H apart from the scanning signal of the first light-emitting control terminal and the third light-emitting control terminal EM, and is represented by "EM+3". "EM+1" represents a scanning signal that is delayed by 2H compared to the signal of "EM", for example, the port of "EM+1" is a scanning signal that is delayed by two rows compared to the signal represented by "EM", "EM+2" represents a scanning signal that is delayed by 4H compared to the signal represented by "EM", and the signal connected to the second light-emitting control terminal EM+3 is delayed by 6H compared to the signal represented by "EM". Of course, this is only exemplary, and the present disclosure is not limited to this, and the second light-emitting control terminal EM+3 can be separated from the first light-emitting control terminal EM by more Hs.

[0087] Reference Figure 5 As shown, the process of the pixel circuit driving the light emitting unit 40 to emit light includes a first stage T1 of being off and a second stage T2 of being on, and the second stage T2 includes a first light emitting stage t1 and a second light emitting stage t2.

[0088] In the first stage T1, the signals connected to the second reset control terminal and the third reset control terminal H-out have a low level period, the signals connected to the first light-emitting control terminal and the third light-emitting control terminal EM are high level, the signal connected to the first reset control terminal P-out is high level, the signal connected to the write control terminal G-out is high level, and the signal connected to the compensation control terminal E-out is low level. The duration of the first stage T1 is 6H, and the second light-emitting control terminal EM+3 is always low level in this stage.

[0089] Therefore, in the first light-emitting path, the ninth transistor T9 in the second reset subcircuit 82 and the tenth transistor T10 in the third reset subcircuit 83 are turned on, and the other transistors are turned off. The second node N2 is reset by the signal of the second reset signal terminal vint2, and the first node N1 is reset by the signal of the third reset signal terminal vint3. In the second light-emitting path, the first transistor T1 is turned off, the second transistor T2 and the third transistor T3 are turned on, and the signal of the first power supply signal terminal VDD cannot be provided to the fifth node N5.

[0090] Therefore, in the first stage T1 , the light emitting unit 40 does not emit light.

[0091] In the first light-emitting stage t1 and the second light-emitting stage t2 in the second stage T2, Figure 5 The dotted lines in the figure indicate the schematic start and end time edges of the signal change.

[0092] In the first light emitting stage t1 , the signals connected to the first light emitting control terminal and the third light emitting control terminal EM are always at high level, so the driving current generated by the driving transistor DTFT cannot form a path from the first power signal terminal VDD to the anode of the light emitting unit 40 .

[0093] However, at this time, the signal connected to the second light-emitting control terminal EM+3 begins to become a high level, so the first transistor T1 is turned on, the second transistor T2 is turned off, and the third transistor T3 is a normally open tube, so that the second light-emitting control subcircuit 30 provides the voltage of the first power signal terminal VDD to the anode of the light-emitting unit 40, and uses the voltage of the first power signal terminal VDD to power the light-emitting unit 40 to emit light.

[0094] Continue to refer to Figure 5 As shown, in the first light-emitting stage t1, the signal connected to the compensation control terminal E-out first changes to a high level, and at the same time, the signal connected to the first reset control terminal P-out changes to a low level, so that the fifth transistor T5 and the eighth transistor T8 are turned on at the same time, and the signal of the first reset signal terminal Vint1 is used to reset the fourth node N4 and the second node N2 corresponding to the driving transistor DTFT.

[0095] Subsequently, after the signal connected to the first reset control terminal P-out becomes high level and during the period when the compensation control terminal E-out still maintains high level, the signal of the write control terminal G-out becomes effective level, i.e. low level. Thus, the sixth transistor T6 of the write subcircuit 60 is turned on, and the data signal Vdata of the data signal terminal Data is transmitted to the first node N1. At the same time, the fifth transistor T5 of the compensation subcircuit 50 is turned on and the driving transistor DTFT is turned on under the action of the first capacitor C1, and the data signal Vdata is transmitted to the fourth node N4 and charged to the control electrode of the driving transistor DTFT. When the potential of the driving transistor DTFT is charged to the potential difference between the gate and the source Vgs=Vth, the charging stops. At this time, the fourth node N4 corresponding to the driving transistor DTFT is positioned as: Vg=Vdata+Vth.

[0096] It can be seen that during the time period when the second light-emitting path formed by the second light-emitting control sub-circuit 30 drives the light-emitting unit 40 to emit light, the first light-emitting path where the driving sub-circuit 10 is located independently and normally performs processes such as reset, data writing and threshold compensation, and the existence of the second light-emitting control sub-circuit 30 does not affect the normal working process of another light-emitting path.

[0097] It should be noted that in the first light-emitting stage t1, the timing of each signal port in the first light-emitting path is not limited to Figure 5 As shown, or in other words, the first stage T1 and the first light-emitting stage t1 as a whole constitute all the reset, data writing and threshold compensation processes in the first light-emitting path before light emission. Except that the light-emitting control signal formed by the light-emitting path is always at an invalid level, the timing changes of the signal ports of the first light-emitting path related processes can be changed according to actual needs. For example, in the first light-emitting stage t1, the compensation control terminal E-out is Figure 5 By this arrangement, the fifth transistor T5 can be turned on once in advance, so that the first node N1 and the second node N2 of the driving transistor DTFT can be reset to a high voltage in advance by using the signal stored in the first capacitor C1, thereby improving the residual image and the display effect.

[0098] In the second light-emitting stage t2, the signals connected to the first light-emitting control terminal and the third light-emitting control terminal EM are both at a valid level, i.e., a low level, and the fourth transistor T4 of the first light-emitting control subcircuit 20 and the seventh transistor T7 of the third light-emitting control subcircuit are both turned on, so that the driving current generated by the driving transistor DTFT is provided from the first power signal terminal VDD to the anode of the light-emitting unit 40 to form a light-emitting path.

[0099] During the first 6H period of the second light-emitting stage t2, the second light-emitting control terminal EM+3 has not yet reached the period of becoming a low level, thereby maintaining a 6H high level period. During this 6H period, in the second light-emitting control sub-circuit 30, the first transistor T1 is turned on, the second transistor T2 is turned off, and the third transistor T3 is a normally open tube, so that the third light-emitting control sub-circuit 30 provides the voltage of the first power signal terminal VDD to the anode of the light-emitting unit 40, and uses the voltage of the first power signal terminal VDD to power the light-emitting unit 40 to emit light, so that during this 6H period, the two light-emitting paths simultaneously supply power to the light-emitting unit 40 to drive it to emit light.

[0100] Afterwards, when the signal of the second light-emitting control terminal EM+3 begins to become an invalid level, that is, a low level, the first transistor T1 is turned off, the second transistor T2 and the third transistor T3 are turned on, so that the light-emitting path stops supplying power to the light-emitting unit 40, and the pixel circuit only emits light under the grayscale driving current provided by the data signal in the path where the driving sub-circuit 10 is located. At this time, the driving circuit Id = k × (Vgs-Vth) 2 =k×(Vgs+VSS) 2 , where k represents the gain parameter of the driving transistor.

[0101] It can be seen that through the arrangement of the embodiment of the present disclosure, a light-emitting path independent of the light-emitting path where the driving transistor DTFT is located is added by utilizing the second light-emitting control subcircuit 30, so that the path can control the light-emitting unit in advance without affecting the data writing of the driving current, the threshold compensation of the driving transistor and the resetting of the related nodes, thereby significantly reducing the black bar time of the light-emitting control, reducing the flicker of the display product, and improving the flicker index SVM, thereby improving the eye protection effect of the display product, especially the display product with a high refresh rate, and improving the user experience.

[0102] A second aspect of the present disclosure provides a display panel including the pixel circuit of an embodiment of the present disclosure.

[0103] In this embodiment, by including the above-mentioned pixel circuit, the black bar time length of the display panel can be reduced with a simple circuit layout, and the flicker index SVM can be improved, thereby improving the eye protection effect of the display product, especially the display product with a high refresh rate, and providing a higher display quality.

[0104] The third aspect of the present disclosure provides a display device, including the display panel of the embodiment of the present disclosure. The display device can be a display product or component including any of the above display panels, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc., which is not limited in the present embodiment.

[0105] The specific structure and function of the above display panel and the pixel circuit included in the display panel have been described in detail in the above embodiments and will not be repeated here.

[0106] In this embodiment, by providing the above-mentioned pixel circuit in the display panel, the black bar time length of the display panel can be reduced with a simple circuit layout, and the flicker index SVM can be improved, thereby improving the eye protection effect of the display product, especially the display product with a high refresh rate, and providing a higher display quality.

[0107] A fourth aspect of the present disclosure provides a driving method of a pixel circuit using an embodiment of the present disclosure, comprising:

[0108] In the first light-emitting stage, the second light-emitting control subcircuit transmits the first power signal of the first power signal terminal to the anode and drives the light-emitting unit to emit light based on the signal of the second light-emitting control terminal being at a valid level, and the first light-emitting control subcircuit disconnects the second node from the anode based on the signal of the first light-emitting control terminal being at an invalid level.

[0109] In the second light-emitting stage, the first light-emitting control subcircuit transmits the driving current from the second node to the anode based on the signal of the first light-emitting control terminal being at a valid level, and drives the light-emitting unit to emit light.

[0110] The above method can provide two independently controlled first light-emitting stages and second light-emitting control stages, so that an independent light-emitting path can be formed in advance during the data writing, compensation, resetting and other stages required for the driving current, thereby reducing the black bar time length of the display panel and improving the flicker index SVM, thereby improving the eye protection effect of display products, especially high refresh rate display products, and providing higher display quality.

[0111] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not limitations on the implementation methods of the present disclosure. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A pixel circuit, characterized in that: include: a driving subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, and a light-emitting unit, The driving subcircuit includes a driving transistor electrically connected between a first node and a second node, and configured to generate a driving current from a first power signal terminal to the light emitting unit, The first light-emitting control subcircuit is electrically connected to the second node, the anode of the light-emitting unit and the first light-emitting control terminal, and is configured to transmit the driving current to the anode and drive the light-emitting unit to emit light based on the signal of the first light-emitting control terminal, The second light-emitting control subcircuit is electrically connected to the first power signal terminal, the second power signal terminal, the second light-emitting control terminal and the anode, and is configured to transmit the first power signal of the first power signal terminal to the anode and drive the light-emitting unit to emit light based on the signal of the second light-emitting control terminal.

2. The pixel circuit according to claim 1, characterized in that: The second light emitting control subcircuit comprises: a first transistor, a second transistor and a third transistor, The first electrode of the first transistor is electrically connected to the third node, the second electrode is electrically connected to the anode, and the control electrode is electrically connected to the second light emitting control terminal. The first electrode of the second transistor is electrically connected to the second power signal terminal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second light emitting control terminal. The first electrode and the control electrode of the third transistor are electrically connected to the first power signal terminal, and the second electrode is electrically connected to the third node.

3. The pixel circuit according to claim 2, characterized in that: The first transistor and the third transistor are N-type transistors, and the second transistor is a P-type transistor.

4. The pixel circuit according to claim 1, characterized in that: The polarity of the effective level of the second light emitting control terminal is opposite to the polarity of the effective level of the first light emitting control terminal. The signal received by the second light-emitting control terminal is a signal received by the first light-emitting control terminal delayed by a plurality of Hs, where H is the time for the signal received by the first light-emitting control terminal to scan a row of light-emitting units.

5. The pixel circuit according to claim 1, characterized in that: Also includes: Compensation subcircuit and write subcircuit, The compensation subcircuit is electrically connected to the second node, a fourth node corresponding to the control electrode of the driving transistor, and a compensation control terminal, and is configured to electrically connect the second node and the fourth node based on a signal of the compensation control terminal. The write subcircuit is electrically connected to the first node, the data signal terminal and the data control terminal, and is configured to transmit the data signal connected to the data signal terminal to the first node based on the signal of the data control terminal.

6. The pixel circuit according to claim 1, characterized in that: Also includes: a first reset subcircuit and a second reset subcircuit, The first reset subcircuit is electrically connected to the first reset signal terminal, the second node, and a second reset control terminal, and is configured to transmit a signal from the first reset signal terminal to the second node based on a signal from the first reset control terminal. The second reset subcircuit is electrically connected to the second reset signal terminal, the anode, and a second reset control terminal, and is configured to transmit a signal from the second reset signal terminal to the anode based on a signal from the second reset control terminal.

7. The pixel circuit according to claim 6, characterized in that: Also includes: The third reset sub-circuit is electrically connected to the third reset signal terminal, the first node and the third reset control terminal, and is configured to transmit the signal of the third reset signal terminal to the first node based on the signal of the third reset control terminal.

8. The pixel circuit according to claim 5, characterized in that: The first light emission control subcircuit includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the second node, a second electrode is electrically connected to the anode, and a control electrode is electrically connected to the first light emission control terminal. The compensation sub-circuit comprises a fifth transistor, a first electrode of the fifth transistor is electrically connected to the second node, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the compensation control terminal. The writing sub-circuit comprises a sixth transistor, a first electrode of the sixth transistor is electrically connected to the data signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the data control terminal. The pixel circuit further includes a first capacitor, wherein a first electrode of the first capacitor is electrically connected to the first power signal terminal, and a second electrode of the first capacitor is electrically connected to the fourth node.

9. The pixel circuit according to claim 1, characterized in that: Also includes: A third light-emitting control subcircuit includes a seventh transistor, a first electrode of the seventh transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to a third light-emitting control terminal.

10. A display panel, characterized in that: The method comprises a pixel circuit as claimed in any one of claims 1 to 9.

11. A display device, characterized in that: Comprising the display panel as claimed in claim 10.

12. A driving method for a pixel circuit according to any one of claims 1 to 9, characterized in that: include: In the first light-emitting stage, the second light-emitting control subcircuit transmits the first power signal of the first power signal terminal to the anode and drives the light-emitting unit to emit light based on the signal of the second light-emitting control terminal being at a valid level, and the first light-emitting control subcircuit disconnects the second node from the anode based on the signal of the first light-emitting control terminal being at an invalid level. In the second light-emitting stage, the first light-emitting control subcircuit transmits the driving current from the second node to the anode based on the signal of the first light-emitting control terminal being at a valid level, and drives the light-emitting unit to emit light.

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