Controller, segment code liquid crystal display device and display module state detection method

Abstract

The present disclosure provides a controller, a segment code liquid crystal display device and a state detection method of a display module. The controller is adapted to drive a display module having a plurality of pixels, and includes a signal generation circuit and an abnormality detection circuit. The signal generation circuit is coupled to the display module and generates a plurality of control signals for driving the plurality of pixels based on a power signal, wherein the signal generation circuit outputs the control signals having a test waveform in a test mode. The abnormality detection circuit receives the power signal and is configured to detect a change in the power signal in response to the test waveform in the test mode to generate a detection value corresponding to a pixel under test.

Description

Technical Field

[0001] This disclosure relates to a detection technique for a display device, and more particularly to a method for detecting the status of a controller, a segment liquid crystal display device, and a display module. Background Technology

[0002] A segment LCD is a type of patterned liquid crystal display commonly used as the display interface for electronic devices such as air conditioner remote controls, electronic blood pressure monitors, and electronic calculators. The display mechanism of a segment LCD primarily involves controlling the pixels / segments in the display module through the control of a shared signal (COM signal) and a segment signal (SEG signal) to display different patterns and numbers.

[0003] The connection interface of the display module of a segment LCD is usually arranged according to the pin arrangement for receiving SEG and COM signals. The controller connects to the display module through the connection interface and sends control signals to drive the display module to display images.

[0004] A common anomaly in these types of display modules is the potential for short circuits between pins or between pins and external circuitry, causing malfunctions in segment LCD displays. Therefore, the manufacturing process requires inspecting individual pixels / segments for abnormalities in the displayed image / numbers. Common methods for this inspection include visual inspection or using I / O controls to adjust the pins under test to high / low levels, using signal states to confirm the presence of short circuits on each pin.

[0005] While manual inspection can provide a more intuitive way to confirm whether each pixel / field can be displayed correctly, this method is very time-consuming. Furthermore, manual inspection may fail to detect abnormalities due to distraction or fatigue, making it difficult to improve overall efficiency and inspection accuracy.

[0006] On the other hand, in detection methods that use I / O control to determine the high / low level of the pin under test, the main method is to check if other pins have the same high / low level to determine if the pin under test is short-circuited. If the same high / low level is detected on other pins as on the pin under test, it indicates a short circuit. While this method can detect basic short circuits, it cannot determine the severity of the short circuit. Sometimes, although a short circuit occurs between pins, the equivalent impedance at both ends is large enough that no abnormality is displayed. In some applications, this situation does not need to be classified as an abnormal condition that needs to be filtered out. However, with the I / O control detection method described above, any short circuit will be filtered out as abnormal, thus unnecessarily increasing manufacturing costs. Summary of the Invention

[0007] This disclosure proposes a status detection method for a controller, a segment LCD display device, and a display module, which can detect the degree of short circuit between pins and avoid filtering out pixels that can be displayed normally.

[0008] This disclosure provides a controller suitable for driving a display module having multiple pixels, wherein the controller includes a signal generation circuit and an anomaly detection circuit. The signal generation circuit is coupled to the display module and generates multiple control signals for driving the multiple pixels based on a power supply signal, wherein the signal generation circuit outputs control signals having test waveforms in a test mode. The anomaly detection circuit receives the power supply signal and is used to detect changes in the power supply signal in response to the test waveform in the test mode to generate a detection value corresponding to a pixel under test among the multiple pixels.

[0009] This disclosure provides a segment LCD display device, including a segment LCD module and a controller. The segment LCD module has multiple display fields, each display field having two pins. The controller is coupled to the multiple pins and is used to generate multiple control signals based on a power supply signal and output them to the multiple pins respectively to drive the segment LCD module. In test mode, the controller outputs a control signal with a test waveform and detects changes in the power supply signal in response to the test waveform to generate a detection value indicating the short-circuit degree of the corresponding display field.

[0010] This disclosure provides a state detection method for a display module, comprising the following steps: sending a first control signal having a first test waveform to one of a plurality of pins of the display module, and sending a second control signal having a second test waveform to another of the plurality of pins of the display module, wherein the one pin and the other pin correspond to a pixel to be tested in the display module; detecting a power supply signal used to generate the control signal; and generating a detection value corresponding to the pixel to be tested based on the change in the power supply signal.

[0011] Based on the above, the controller, segment LCD display device, and display module status detection method of this disclosure can more accurately detect the actual short circuit degree and abnormal conditions of the pins corresponding to each pixel of the display module. This allows backend applications to more accurately assess the availability of the display module according to the required application scenario, thereby avoiding the excessive screening of modules with slight short circuits that do not affect the display, which would unnecessarily increase manufacturing costs. Alternatively, it can prevent the failure to screen out minor short circuits in applications requiring high reliability, thus avoiding unexpected product reliability risks. Furthermore, some embodiments of this disclosure can set the test mode functions and operations on existing LCD drivers without any additional output setting modifications or the addition of additional circuitry, effectively reducing the design and manufacturing costs of circuit modifications. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure;

[0013] Figure 2 This is a schematic diagram of a controller according to an embodiment of the present disclosure;

[0014] Figure 3 This is a schematic diagram of the signal timing of a controller in test mode according to an embodiment of the present disclosure; and

[0015] Figure 4 This is a schematic diagram of the signal timing of the controller in test mode according to another embodiment of the present disclosure;

[0016] Figure 5 This is a flowchart illustrating the steps of a state detection method for a display module according to an embodiment of the present disclosure; and

[0017] Figure 6 This is a flowchart illustrating the steps of a state detection method for a display module according to another embodiment of the present disclosure. Detailed Implementation

[0018] This disclosure proposes a novel method for detecting the state of a controller, a segment-type liquid crystal display device, and a display module to address the problems mentioned in the background art. To make the features and advantages of this disclosure more apparent, specific embodiments of the invention are described in detail below with reference to the accompanying drawings. The following description contains specific information relating to exemplary embodiments in this disclosure. The accompanying drawings and detailed description are exemplary embodiments only. However, this disclosure is not limited to these exemplary embodiments. Other variations and embodiments of this disclosure will occur to those skilled in the art. Unless otherwise stated, the same or corresponding components in the drawings are indicated by the same or corresponding reference numerals. Furthermore, the drawings and illustrations in this disclosure are generally not drawn to scale and are not intended to correspond to actual relative dimensions.

[0019] In all descriptions relating to specific numerical values ​​in this disclosure, although not explicitly stated, the terms "approximately" or "substantially" are included, meaning that these specific numerical values ​​encompass a possible range of numerical error to characterize potential unintended effects and deviations in process or material selection. This range of numerical error may include numerical changes that do not significantly alter the material's structure, properties, or effects, for example, a deviation of 0% to 10%, which is clear to those skilled in the art.

[0020] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure. Please refer to... Figure 1The display device 10 includes a display module LCM and a controller 100 for driving the display module LCM. This disclosure does not limit the category / type of the display device 10 and its display module LCM. In some embodiments, the display device 10 may be an electronic device with display functionality, such as the display interface of an electronic watch, electronic clock, or remote control. In some embodiments, the display module LCM may be a liquid crystal display (LCD) module or a segment LCD module. When the display module LCM is an LCD module, the display device 10 may also be called a liquid crystal display device; similarly, when the display module LCM is a segment LCD module, the display device 10 may be called a segment LCD device.

[0021] In this embodiment, the display module LCM is an example of a segment LCD module with multiple pins. The multiple pins may be, for example, n+1 pins P_COM0 to P_COMn for receiving COM signals, and m+1 pins P_SEG1 to P_SEGm for receiving SEG signals, where m and n are natural numbers and can be selected according to the actual design.

[0022] Specifically, the display module (LCM) includes multiple pixels. Each pixel receives a COM signal and a SEG signal through two corresponding pins. Since some or all of the multiple pixels can share the COM signal, the number of pins used to receive the COM signal can be less than the number of pixels. On the other hand, each pixel receives a corresponding SEG signal, so the number of pins used to receive the SEG signal can be one-to-one with the number of pixels, but this disclosure is not limited thereto. In the application of segment LCD devices, each pixel can refer to a corresponding display field.

[0023] The controller 100 is coupled to pins P_COM0~P_COMn and P_SEG0~P_SEGm of the display module LCM, and is used to generate multiple control signals Sc_0~Sc_x as LCD driving signals (i.e., the COM signal and SEG signal) based on a power supply signal. These signals are then provided to the pixels within the display module LCM through the corresponding pins P_COM0~P_COMn and P_SEG0~P_SEGm to drive the display module LCM. In this embodiment, the control signals Sc_0~Sc_x can have a one-to-one correspondence with pins P_COM0~P_COMn and P_SEG0~P_SEGm. That is, when driving the display module LCM, control signal Sc_0 is the COM0 signal provided to pin P_COM0, control signal Sc_1 is the COM1 signal provided to pin P_COM1, and so on; therefore, the number of control signals x will be less than or equal to m+n+2. However, this disclosure is not limited to this.

[0024] Taking a segment LCD display device that displays "8" as an example, it may include 7 display segments. Therefore, the display module LCM may include one pin P_COM0 (i.e., n=0) for receiving COM signals and 7 pins P_SEG0 to P_SEG6 (i.e., m=6) for receiving SEG signals. Each SEG signal pin P_SEG0 to P_SEG6 is paired with the COM signal pin P_COM0 to form two corresponding pins of a display segment to receive control signals Sc_0 to Sc_7 issued by the controller 100. Among them, the control signal Sc_0 is the COM signal provided to the pin P_COM0, the control signal Sc_1 is the SEG signal provided to the pin P_SEG0, the control signal Sc_2 is the SEG signal provided to the pin P_SEG1, and so on.

[0025] Example configuration of controller 100 is as follows Figure 2 As shown, where Figure 2 This is a schematic diagram of a controller according to an embodiment of the present disclosure. Please also refer to... Figure 1 and Figure 2 In addition to driving the display module LCM, the controller 100 of this embodiment can also output control signals with corresponding test waveforms to each pin P_COM0 to P_SEGm of the display module LCM in test mode TM to detect each pixel / display field in the display module LCM, and can output detection values ​​indicating the short circuit degree / type of each pixel / display field.

[0026] Specifically, the controller 100 may include a signal generation circuit 110, an anomaly detection circuit 120, and a power supply circuit 130. In addition to generating control signals Sc_0 to Sc_x as LCD driving signals when driving the display module LCM, the signal generation circuit 110 can also generate control signals Sc_0 to Sc_x with test waveforms WF1 and WF2 based on the power signal VLCD in test mode TM, and output the control signals Sc_0 to Sc_x to the corresponding pins, thereby sequentially testing the short-circuit degree of each pixel.

[0027] For example, Figure 2This example illustrates the signal output state during the testing of pixel Pab. The signal generation circuit 110 outputs a first control signal Sc_a with test waveform WF1 and a second control signal Sc_b with test waveform WF2 to the corresponding two pins of pixel Pab. This enables pixel Pab in response to the first control signal Sc_a and the second control signal Sc_b, while simultaneously disabling the pixels corresponding to the other pins in response to the received control signals. The resulting detection value reflects the short-circuit degree of pixel Pab. After completing the detection of pixel Pab, the signal generation circuit 110 can select the two pins corresponding to the next pixel to output control signals with test waveforms WF1 and WF2 to continue detecting the next pixel. The original first control signal Sc_a / second control signal Sc_b with test waveforms WF1 / WF2 is then switched to a control signal that disables the corresponding pixel Pab. The testing of other pixels can be performed similarly.

[0028] For example, if the two pins corresponding to pixel Pab are pin P_COM0 and pin P_SEG0, then the signal generation circuit 110 will output a control signal Sc_0 with test waveform WF1 to pin P_COM0, and a control signal with test waveform WF2 to pin P_SEG0; other pins P_COM1~P_COMn and P_SEG1~P_SEGm will receive control signals that will not enable the pixels corresponding to pins P_COM1~P_COMn and P_SEG1~P_SEGm. When pixel Pab completes detection, the signal generation circuit 110 will switch to outputting a control signal with test waveform WF2 to pin P_SEG1 to enable the pixels corresponding to pins P_COM0 and P_SEG1 to be tested, while pin P_SEG0 will receive a control signal that disables pixel Pab.

[0029] In other words, the signal generation circuit 110 outputs a first control signal (such as Sc_a) with test waveform WF1 and a second control signal (such as Sc_b) with test waveform WF2 to the corresponding two pins of the pixel under test (such as Pab) in the display module LCM in test mode TM, so that the anomaly detection circuit 120 generates a detection value CTV corresponding to the pixel under test.

[0030] It should be noted that the short circuit refers to an unintended electrical connection between a pixel-related line / pin and surrounding lines / components / pins, such that the pixel's line / pin can be considered electrically connected to surrounding lines / components / pins through a short-circuit impedance, causing leakage current through the short-circuit resistor. The degree / situation of the short circuit refers to the magnitude of the short-circuit impedance and / or leakage current. A more severe short circuit indicates a larger leakage current and a smaller short-circuit impedance, while a milder short circuit indicates a smaller leakage current and a larger short-circuit impedance.

[0031] In some embodiments, the test waveforms WF1 and WF2 can be square waves that are opposite in phase, forming an AC signal to enable the corresponding pixel under test.

[0032] In some embodiments, the test waveforms WF1 and WF2 can be waveforms conforming to the LCD driving signal format; that is, the LCD driving signal can be directly used as the test signal. Specifically, the waveform conforming to the LCD driving signal format can be a step signal waveform with multiple (e.g., at least three) different voltage levels in one cycle, and each voltage level conforms to the output voltage under the LCD driving signal format. In other words, the voltage difference between the test waveforms WF1 and WF2 can form a periodic multi-order AC square wave that can drive LCD pixels. Specific examples of the controller 100 detecting under different test waveforms WF1 and WF2 will be further described in subsequent embodiments.

[0033] Since the controller 100 can use test waveforms WF1 and WF2 that conform to the LCD drive signal format for detection, the hardware of the signal generation circuit 110 can be implemented using a general LCD driver architecture without the need for additional hardware configuration.

[0034] The anomaly detection circuit 120 can receive the power supply signal VLCD and is used to detect changes in the power supply signal VLCD in response to test waveforms WF1 and WF2 in test mode TM, so as to generate detection values ​​CTV corresponding to each pin P_COM0 to P_SEGm.

[0035] Specifically, when the controller 100 sends a first control signal Sc_a and a second control signal Sc_b with test waveforms WF1 and WF2 to the corresponding pins to enable the pixel under test Pab, the state of the pixel under test Pab is similar to that in the driving mode. Therefore, the power signal VLCD will respond to the operating current of the pixel under test Pab and have a charging and discharging waveform similar to that in the driving mode.

[0036] When there is no short circuit in the lines / pins of the pixel under test (Pab), the load current caused by the basic power consumption is very small, resulting in a relatively gentle pull-down (i.e., a small slope) in the voltage level of the power supply signal VLCD, and a relatively quick recovery to the steady-state voltage during charging. Conversely, when a short circuit occurs in the lines / pins of the pixel under test (Pab), the short circuit path causes additional leakage current, causing the voltage level of the power supply signal VLCD to be pulled down rapidly (i.e., a large slope). The larger the leakage current, the faster the voltage level of the power supply signal VLCD is pulled down. In addition, the short-circuit resistance also prolongs the time it takes for the power supply circuit 130 to recharge the voltage level of the power supply signal VLCD to the steady-state voltage.

[0037] In other words, the magnitude of the change in the power supply signal VLCD is related to the leakage current / short-circuit resistance, which is also related to the degree of short circuit of the pin being tested.

[0038] The controller 100 in this embodiment utilizes the aforementioned voltage level variation characteristics to obtain a detection value CTV that reflects the short-circuit degree of the pins P_COM0 to P_SEGm and / or traces related to the detected pixel. In other words, the controller 100 in this embodiment can output control signals Sc_0 to Sc_x with test waveforms WF1 and WF2 in test mode TM, and detect the power supply signal VLCD in response to changes in test waveforms WF1 and WF2 to generate a detection value CTV indicating the short-circuit degree of the pixel under test, Pab.

[0039] The detected value CTV can be a numerical value that indicates the degree of short circuit of the test pin in a proportional relationship. It can be, for example, a count value, a voltage value, or other types of numerical values, depending on the actual implementation of the fault detection circuit.

[0040] It should be noted that the short circuit described in this disclosure is not limited to the absence of any impedance or negligible impedance at the two short-circuited pins / components / lines along their short-circuit path. Any short circuit may be considered a short circuit as described in this disclosure if the two pins / components can be equivalently connected via an impedance path, and the leakage current caused by that impedance path is identifiable as greater than the load current caused by the base power dissipation. For example, a short-circuit impedance of 5 ohms, 50 ohms, 500 ohms, or 5000 ohms between two pins can be considered a short circuit in this disclosure, differing only in the degree of short circuit.

[0041] In some embodiments, the anomaly detection circuit 120 may include a voltage detection unit 122 and a counting unit 124. The voltage detection unit 122 is used to detect the voltage level of the power supply signal VLCD in test mode TM to generate trigger signals St1 and St2. The counting unit 124 is coupled to the voltage detection unit 122 and is used to count in response to the trigger signals St1 and St2, and generate a detection value CTV accordingly.

[0042] More specifically, the voltage detection unit 122 can generate a first trigger signal St1 to trigger the counting unit 124 to start counting when the voltage level of the power signal VLCD exceeds a first voltage Vt1 (either by dropping from a high voltage to below the first voltage Vt1 or by increasing from a low voltage to above the first voltage Vt1). Conversely, when the voltage level of the power signal VLCD exceeds a second voltage Vt2 (either by dropping from a high voltage to below the second voltage Vt2 or by increasing from a low voltage to above the second voltage Vt2), the counting unit 124 can generate a second trigger signal St2 to trigger the counting unit 124 to stop counting. In other words, the counting unit 124 starts counting in response to the first trigger signal St1 and stops counting in response to the second trigger signal St2. The voltage detection unit 122 may generate a first trigger signal St1 when the voltage level of the power signal VLCD starts to drop from the steady-state voltage, or when the voltage level of the power signal VLCD reaches the trough voltage. In addition, the voltage detection unit 122 may generate a second trigger signal St2 when the voltage level of the power signal VLCD reaches the trough voltage, or when the voltage level of the power signal VLCD returns to the steady-state voltage.

[0043] In other words, the detection value CTV generated by the counting unit 124 can be the count value of the time required for the voltage level of the counting power supply signal VLCD to drop from the steady-state voltage to the trough voltage, the count value of the time required for the voltage level to rise back to the steady-state voltage from the trough voltage, or the count value of the time required for the voltage level to drop from the steady-state voltage to the trough voltage and then rise back to the steady-state voltage. This disclosure is not limited to these.

[0044] Similar to what was previously described, since the time required for the voltage level of the power signal VLCD to drop from a steady-state voltage to a trough voltage and then rise back to a steady-state voltage is related to the leakage current / short-circuit impedance of the pixel under test, and the leakage current / short-circuit impedance is related to the degree of short circuit, the count value obtained by the counting unit 124 can be used as the detection value CTV indicating the degree of short circuit. In other words, in this embodiment, the anomaly detection circuit 120 reflects the magnitude of the change in the voltage level of the power signal VLCD by counting the time it takes for the voltage level of the power signal VLCD to change, and uses this as the detection value CTV indicating the degree of short circuit.

[0045] The power supply circuit 130 is coupled to the signal generation circuit 110 and the fault detection circuit 120, and is used to generate a power signal VLCD to provide to the signal generation circuit 110 and the fault detection circuit 120. In practical applications, depending on the driving voltage required by the display module LCM, the power supply circuit 130 can be implemented using an architecture such as a charge pump, an internal analog voltage source, or an external voltage source, but this disclosure is not limited to this.

[0046] In the manner described above, the controller 100 of this disclosure can more accurately detect the actual short circuit degree of the pins P_COM0 to P_SEGm corresponding to each pixel of the display module LCM. This allows backend applications to more accurately assess the availability of the display module LCM according to the application scenario, avoiding the over-screening of modules with slight short circuits that do not affect the display in some applications, thus avoiding unnecessary increases in manufacturing costs; or avoiding the failure to screen out minor short circuits in some applications requiring high reliability, thus avoiding unexpected product reliability risks.

[0047] Furthermore, compared to traditional detection methods, the controller 100 disclosed herein does not require the use of input / output ports (I / O ports) for detection. Instead, it can use signal output conforming to the LCD drive signal format, combined with the detection of power supply signal changes to determine short circuit conditions. This allows the detection mechanism to be directly integrated into the LCD drive control circuit without additional hardware development costs.

[0048] It should be noted that the test mode TM can be a mode that is enabled by user operation and differs from the normal driving situation. Any controller that has the function and / or operation to controllably enable the detection of the short-circuit degree of the LCM pins can be considered to include the test mode, or all operations under the test mode. In other words, even if the characteristics of the controller 100 described in this disclosure cannot be directly observed in the appearance of a display device, it does not necessarily mean that the controller included in the display device does not fall within the scope of the claims of this disclosure. In fact, as long as it can be discovered / verified through any testing method or reverse engineering means (including non-standard usage methods indicated by the display device) that the controller included in the display device possesses the test mode, or operates under a test mode that conforms to the scope of the claims of this disclosure, the controller can be considered to fall within the scope of the claims of this disclosure.

[0049] The following pairings Figure 3 and Figure 4 The signal timing will be used to further illustrate the operation of the controller in test mode, where... Figure 3 In accordance with Figure 2 A schematic diagram of the signal timing of the controller in test mode according to one embodiment; and Figure 4 In accordance with Figure 2 A signal timing diagram of the controller in test mode in another embodiment.

[0050] Please refer to Figure 2 and Figure 3 ,in Figure 3The timing of the signal when the rendering controller 100 tests the pixel Pab of the display module LCM is taken as an example. In this embodiment, the signal generation circuit 110 sends a first control signal Sc_a with a periodic square wave waveform and a second control signal Sc_b with a waveform that is inversely phase to the first control signal Sc_a (i.e., the phase difference between the two signals is 180 degrees) to the pixel Pab under test. The first control signal Sc_a may be, for example, a signal sent to the COM pin of the pixel Pab, and the second control signal Sc_b may be, for example, a signal sent to the SEG pin of the pixel Pab, but this disclosure is not limited thereto.

[0051] Furthermore, the signal generation circuit 110 can send a control signal with the same / in-phase waveform as one of the first control signal Sc_a and the second control signal Sc_b to other pins (or at least some of the other pins) of the display module LCM to disable non-tested pixels. For example, when the first control signal Sc_a and the second control signal Sc_b are respectively given to the COM pin and SEG pin of pixel Pab, the signal generation circuit 110 can send a control signal with the same waveform as the first control signal Sc_a to other SEG pins that share the COM signal with pixel Pab to disable other non-tested pixels.

[0052] During the period when pixel Pab is enabled in response to the first control signal Sc_a and the second control signal Sc_b, the power signal VLCD will repeatedly charge and discharge within a certain voltage range (such as the range between voltage levels VL and VH) in response to the workload of pixel Pab, so as to maintain a roughly stable power supply.

[0053] Under normal conditions where the related pins / lines of pixel Pab are not short-circuited, the time for the power signal VLCDn to discharge from voltage level VH to voltage level VL is Tfn, and the time for it to recharge from voltage level VL to voltage level VH is Trn. Therefore, a complete charge and discharge period Tn is the discharge period Tfn plus the charging period Trn.

[0054] In some embodiments, when a short circuit occurs on the associated pin / line of pixel Pab, the additional leakage current causes the power supply signal VLCDf to be rapidly pulled down from voltage level VH to voltage level VL, resulting in a shorter discharge period Tff than the normal discharge period Tfn. On the other hand, since a short circuit may introduce unexpected impedance, this series impedance will lengthen the charging time for power supply VLCDf to return from voltage level VL to voltage level VH. Therefore, the charging period Tf under short-circuit conditions will be longer than the normal charging period Trn. Consequently, when a short circuit occurs on the associated pin / line of pixel Pab, a complete charge / discharge period Tf of the power supply signal VLCDf will be longer than the normal charge / discharge period Tn.

[0055] Therefore, counting the ratios Tfn / Tff during charging, Trn / Trf during discharging, or Tn / Tf during charging and discharging can all be used to identify whether a short circuit has occurred. Furthermore, depending on the specifications of the product under test, different identification conditions can be selected for detection to improve accuracy. For example, counting the ratios Tfn / Tff during discharging is more suitable for low-load applications, while counting the ratios Trn / Trf during charging is more suitable for high-load or short-circuit impedance applications, but this disclosure is not limited to these methods.

[0056] Please refer to Figure 2 and Figure 4 ,in Figure 4 Taking the signal timing of the display controller 100 testing the pixel Pab of the display module LCM as an example, in this embodiment, the signal generation circuit 110 sends a first control signal Sc_a and a second control signal Sc_b with waveforms similar to or the same as conventional LCD driving signals to the pixel Pab under test. The conventional LCD driving signal can be similar to a periodic multi-order square wave with multiple voltage levels such as V0 to V4, as shown in the figure.

[0057] In this embodiment, the first control signal Sc_a may be, for example, a signal sent to the COM pin of pixel Pab, and the second control signal Sc_b may be, for example, a signal sent to the SEG pin of pixel Pab, but this disclosure is not limited thereto. The first control signal Sc_a and the second control signal Sc_b will form an AC voltage difference VSEGab on pixel Pab to enable pixel Pab, wherein the maximum value of the voltage difference VSEGab is the voltage level VP, which may be, for example, twice the difference between voltage levels V4 and V1.

[0058] In addition, in some embodiments, the signal generation circuit 110 may send a control signal with a fixed voltage level (e.g., ground level) to other pins (or at least some of the other pins) of the display module LCM to disable non-tested pixels.

[0059] In other embodiments, the signal generation circuit 110 may also be similar to that described above. Figure 3 In this embodiment, a third control signal having the same / in-phase waveform as one of the first control signal Sc_a and the second control signal Sc_b is sent to other pins (or at least some of the other pins) of the display module LCM to disable non-tested pixels. In other words, for non-tested pixels, the control signal received by their corresponding pins can be of different forms, as long as the voltage difference between the corresponding pins is insufficient to enable the non-tested pixel.

[0060] During the period when pixel Pab is enabled in response to the first control signal Sc_a and the second control signal Sc_b, the changes in the power supply signal VLCDn in the normal state and the power supply signal VLCDf in the abnormal state (i.e., the state where a short circuit has occurred) will be similar to those described above. Figure 3 In this embodiment, the discharge period Tff under abnormal conditions will be less than the discharge period Tfn under normal conditions, the charging period Trf under abnormal conditions will be greater than the charging period Trn under normal conditions, and the complete charge and discharge period Tf under abnormal conditions will be greater than the complete charge and discharge period Tn under normal conditions. Therefore, a counting method similar to the above can be used to determine whether the pins and lines connected to the currently tested pixel Pab are abnormal.

[0061] Compared to Figure 3 In this embodiment, since the waveform of the LCD driving signal is directly used as the test waveform, no additional output setting modification or additional circuitry is required for the signal generation circuit 110. The test can be achieved simply by sending the corresponding test waveforms to the pixel under test Pab in the test order. This allows the function and operation of the test mode to be easily implemented on the existing LCD driver, effectively reducing the design and manufacturing costs of circuit modification.

[0062] Figure 5 This is a flowchart illustrating the steps of a state detection method for a display module according to an embodiment of this disclosure. Please refer to... Figure 5 The state detection method in this embodiment can be applied to the above-described... Figures 1 to 4In the display device and its controller described in the embodiment, the state detection method includes: in a test mode (such as TM), sending a first control signal (such as Sc_a) with a first test waveform (such as WF1) to one of the pins of the display module (such as LCM), and sending a second control signal (such as Sc_b) with a second test waveform (such as WF2) to another pin of the display module (step S110), wherein the one pin and the other pin are two pins corresponding to a pixel under test (such as Pab) in the display module.

[0063] Next, the power supply signal (e.g., VLCD) used to generate the control signal is detected (step S120), and a detection value (e.g., CTV) corresponding to the pixel under test is generated based on the change in the power supply signal (step S130). The change in the power supply signal can be at least one of the charging period, discharging period, and charge / discharge period of the power supply signal. The detection value can represent whether a short circuit has occurred in the related pins / lines of the pixel under test and the severity of the short circuit.

[0064] More specifically, the steps of the state detection method in some specific test scenarios can be as follows: Figure 6 As shown, where Figure 6 This is a flowchart illustrating the steps of a state detection method for a display module according to another embodiment of the present disclosure.

[0065] Please refer to Figure 6 In this embodiment, before conducting actual testing, engineers can first test the same batch of display modules that are confirmed to be in normal condition, obtain the detection value of the display modules that are in normal condition as the screening value (step S210), and use this screening value as the judgment standard for subsequent tests.

[0066] After obtaining the screening value, the controller can send a first control signal with a first test waveform and a second control signal with a second test waveform to a group of pins defined as detection pins in the display module (step S220) to enable the pixel under test. Step S220 is similar to step S110 in the aforementioned embodiment and can be referred to the above. Figures 1 to 5 The relevant descriptions of the embodiments will be provided and will not be repeated here.

[0067] Additionally, the controller can send a third control signal with a third test waveform to some or all of the remaining pins (step S230) to disable other non-tested pixels. Depending on the test waveform used in step S220, the third test waveform can be the same as one of the first and second test waveforms, or a fixed voltage level, but this disclosure is not limited thereto. Step S230 can also refer to the above description. Figures 1 to 5The relevant descriptions of the embodiments will be provided and will not be repeated here.

[0068] Next, the controller detects the power signal used to generate the control signal (step S240), counts the change time of the power signal to generate a detection value (step S250), and then determines whether the currently detected pixel is abnormal by comparing the detection value and the filter value (step S260). The change time of the power signal can be at least one of the charging period, discharging period, and charge / discharge period of the power signal, and this disclosure is not limited thereto.

[0069] If the currently detected pixel is determined to be abnormal in step S260, the controller can further output the detection result and related detection value (step S270); conversely, if the currently detected pixel is determined to be normal in step S260, the controller can further determine whether the corresponding pins of all pixels have been tested (step S280).

[0070] If any pixels have not yet been tested, the controller selects a set of pins corresponding to one untested pixel as detection pins (step S290) and returns to step S220 to perform testing and obtain detection values. On the other hand, if it is determined in step S280 that all pixels have completed testing, the controller will end the testing process and leave the testing mode.

[0071] It should be noted here that, Figure 6 The steps described above are merely an illustrative example of this disclosure. Those skilled in the art can modify the above steps without affecting the testing objective, based on the description. For example, in some embodiments, the controller may omit step S260 and output the detection result to the engineer for judgment regardless of whether the detected value exceeds the screening value. In other words, any test method that enables a specific pixel under test of the display module by outputting a specific test waveform and disables other non-test pixels, and then generates an indication of the degree of abnormality of the related pins / circuits of the pixel under test by detecting changes in the power supply signal, falls within the scope of this application and is intended to be protected.

[0072] This disclosure is not limited to the embodiments described above, and various modifications can be made within the scope shown in the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included within the technical scope of this disclosure. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

[0073] In summary, the controller, segment LCD display device, and display module status detection method disclosed herein can more accurately detect the actual short circuit degree and abnormal conditions of the pins corresponding to each pixel of the display module. This allows backend applications to more accurately assess the availability of the display module according to the required application scenarios, thereby avoiding the excessive filtering out of modules with slight short circuits that do not affect the display, thus preventing unnecessary increases in manufacturing costs. Alternatively, it can prevent unintended product reliability risks caused by the failure to filter out minor short circuits in applications requiring high reliability. Furthermore, some embodiments of this disclosure can set the test mode functions and operations on existing LCD drivers without any additional output setting modifications or the addition of additional circuitry, effectively reducing the design and manufacturing costs of circuit modifications.

Claims

1. A controller adapted to drive a display module having a plurality of pixels, characterized in that, The controller comprises: a signal generating circuit coupled to the display module and configured to generate a plurality of control signals for driving the pixels based on a power signal, wherein the signal generating circuit outputs control signals having a test waveform in a test mode; and an abnormality detection circuit configured to receive the power signal and to detect a change in the power signal in response to the test waveform in the test mode to generate a detection value corresponding to a pixel under test among the pixels.

2. The controller of claim 1, wherein, Each of the pixels has two pins to receive the control signals, the control signals including a first control signal having a first test waveform and a second control signal having a second test waveform; the signal generating circuit is configured to output the first control signal and the second control signal to the two pins of the pixel under test in the test mode to cause the abnormality detection circuit to generate the detection value corresponding to the pixel under test.

3. The controller of claim 2, wherein, The control signals further include a third control signal having a third test waveform; the signal generating circuit is configured to output the third control signal to pins of at least some of the pixels other than the pixel under test in the test mode, wherein the third test waveform is different from at least one of the first test waveform and the second test waveform.

4. The controller of claim 2, wherein, The detection value is indicative of a degree of short circuit of the pins of the pixel under test in a proportional relationship.

5. The controller of claim 2, wherein, A voltage difference between the first test waveform and the second test waveform constitutes a periodic multi-step alternating square wave.

6. The controller of claim 2, wherein, The first test waveform and the second test waveform are periodic square waves that are mutually inverted.

7. The controller of claim 1, wherein, The abnormality detection circuit comprises: a voltage detection unit configured to detect a voltage level of the power signal in the test mode to generate a trigger signal; and a counting unit coupled to the voltage detection unit and configured to count in response to the trigger signal and to generate the detection value accordingly, wherein the counting unit counts at least one of a falling period and a rising period of the voltage level of the power signal as the detection value.

8. A segment code liquid crystal display device, characterized by comprising: It comprises: a segment code liquid crystal display module having a plurality of display fields, wherein each of the display fields has two pins; and a controller coupled to the pins and configured to generate a plurality of control signals based on a power signal and to output the control signals to the pins respectively to drive the segment code liquid crystal display module, wherein the controller outputs control signals having a test waveform in a test mode and detects a change in the power signal in response to the test waveform to generate a detection value indicative of a degree of short circuit of one of the display fields. The controller comprises:

9. The segment code liquid crystal display device according to claim 8, wherein a signal generating circuit configured to receive the power signal to generate the control signals; a voltage detection unit configured to detect a voltage level of the power signal in the test mode to generate a trigger signal; and a counting unit coupled to the voltage detection unit and configured to count in response to the trigger signal and to generate the detection value accordingly. It comprises:

10. A method of detecting a state of a display module, characterized by, ​ sending a first control signal having a first test waveform to one of a plurality of pins of a display module, and sending a second control signal having a second test waveform to another of the plurality of pins of the display module, wherein the one and the another of the plurality of pins correspond to a pixel under test of the display module; detecting a power signal used to generate the first and second control signals; and generating a detection value corresponding to the pixel under test according to a variation of the power signal.

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