Gate driving circuit, display panel and display device

Abstract

The application discloses a gate driving circuit, comprising N cascaded starting stage gate driving units, wherein the Nth starting stage gate driving unit comprises an Nth virtual starting circuit and an Nth starting active stage gate driving circuit; the Nth starting active stage gate driving circuit comprises a pull-up control unit, a pull-up unit and a pull-down unit; the Nth virtual starting circuit is connected with a starting signal and the pull-up control unit, the pull-up control unit and the pull-down unit are connected with gate signal points respectively, and the pull-up unit and the pull-down unit are connected with an Nth horizontal scanning line respectively; the Nth virtual starting circuit is used for providing a starting voltage for the pull-up control unit, so that the working voltage periods of the gate signal points of each gate driving unit are consistent. The application provides the starting voltage for the pull-up control unit through the virtual starting circuit, so that the working voltage periods of the gate signal points of each gate driving unit are consistent, and the problem of panel display abnormality is solved.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal display technology, and in particular to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] With the development of LCD screens, more and more LCD panels are adopting a narrow bezel design, using GOA (Gate Driver on Array) circuits instead of IC (integrated circuit) circuits to drive horizontal scan lines, thereby reducing costs and making the resulting products more suitable for bezel-less display panels.

[0003] The GOA (Gateway Oriented Array) circuit integrates the gate row scan drive circuit onto a thin-film transistor array substrate. By scanning the gate, all thin-film transistors electrically connected to that horizontal scan line are turned on, allowing signal voltages on the data lines to be written to the pixels. When the GOA circuit starts, a signal is needed to provide an initial voltage to the starting GOA circuit for normal operation. However, this may cause some nodes in the initial active stage to have different voltage periods than other stages, potentially leading to display abnormalities during long-term use or in harsh environments. Summary of the Invention

[0004] In view of at least some of the problems and deficiencies in the prior art, embodiments of the present invention disclose a gate driving circuit, a display panel, and a display device to solve the problem that the node voltage of the initial effective stage GOA in the existing GOA circuit is different from the node voltage of other stages GOA, resulting in abnormal display.

[0005] On one hand, an embodiment of the present invention provides a gate driving circuit, for example, comprising a plurality of cascaded gate driving units, each of which is configured to drive a scan line. The plurality of cascaded gate driving units include N cascaded start-level gate driving units and a plurality of non-start-active-level gate driving units cascaded with the Nth-level start-level gate driving unit. The Nth-level start-level gate driving unit includes an Nth-level virtual start circuit and an Nth-level start-active-level gate driving circuit. The Nth-level start-active-level gate driving circuit includes a pull-up control unit, a pull-up unit, and a pull-down unit. The Nth-level virtual start circuit is connected to a start signal and is connected to the pull-up control unit. The pull-up control unit is connected to a gate signal point, and the pull-down unit is connected to the gate signal point and the Nth-level horizontal scan line. The pull-up unit is connected to the Nth-level horizontal scan line. The Nth-level virtual start circuit provides a start voltage to the pull-up control unit so that the operating voltage period of the gate signal point of each cascaded gate driving unit is consistent.

[0006] This invention addresses the problem of abnormal panel display by adding a virtual start circuit before the pull-up control unit in the initial effective stage gate drive unit. The virtual start circuit provides a start voltage to the pull-up control unit, thereby ensuring that the operating voltage cycle of the gate signal point of each cascaded gate drive unit is consistent with each other.

[0007] In one embodiment of the present invention, the Nth-level virtual start circuit includes a virtual pull-up unit and a virtual pull-down unit. Each of the virtual pull-up unit and the virtual pull-down unit includes at least one transistor. The at least one transistor in the virtual pull-up unit is connected to the start signal and the timing signal, and is connected to the pull-up control unit. The at least one transistor in the virtual pull-down unit is connected to the (N+n)th-level horizontal scan line and the pull-up control unit, where n ≥ 1. The timing signal includes m lines, where n is a positive integer and n = m / 2, and N is a positive integer and 1 ≤ N ≤ m / 2.

[0008] In one embodiment of the present invention, the starting voltage includes a virtual stage transfer voltage and a virtual scan voltage.

[0009] In one embodiment of the present invention, the virtual pull-up unit includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the start signal, the second terminal of the first transistor is connected to a timing signal, and the third terminal of the first transistor is connected to a virtual stage signal transmission point and is used to output the virtual stage transmission voltage to the pull-up control unit. The first terminal of the second transistor is connected to the virtual stage signal transmission point, the second terminal of the second transistor is connected to the first transistor, and the third terminal of the second transistor is connected to a virtual scan signal point and is used to output the virtual scan voltage to the pull-up control unit.

[0010] In one embodiment of the present invention, the virtual pull-down unit includes a third transistor and a fourth transistor. The first terminal of the third transistor is connected to the N+n level horizontal scan line, the second terminal of the third transistor is connected to the virtual level signal transmission point, and the third terminal of the third transistor is connected to a negative voltage. The first terminal of the fourth transistor is connected to the N+n level horizontal scan line, the second terminal of the fourth transistor is connected to the virtual scan signal point, and the third terminal of the fourth transistor is connected to a negative voltage.

[0011] In one embodiment of the present invention, the first end of the pull-up control unit is connected to the virtual stage signal point, the second end of the pull-up control unit is connected to the virtual scan signal point, and the third end of the pull-up control unit is connected to the gate signal point.

[0012] In one embodiment of the present invention, during the time period when the start signal and the timing signal connected to the virtual pull-up unit are both at the second voltage H2, the Nth stage virtual start circuit outputs the virtual stage transfer voltage and the virtual scan voltage, and the voltage of the gate signal point changes from a low voltage H0 to a first voltage H1, wherein H0

[0013] In one embodiment of the present invention, during the time period when the start signal connected to the virtual pull-up unit is the second voltage H2 and the timing signal connected to the virtual pull-up unit is the low voltage H0, the voltage of the gate signal point changes from the first voltage H1 to the third voltage H3, and the voltage of the Nth level horizontal scan line is the second voltage H2, so that the virtual stage voltage and the virtual scan voltage are pulled down to the low voltage H0, wherein H0

[0014] On the other hand, embodiments of the present invention provide a display panel, including, for example, the gate driving circuit as described above.

[0015] In another aspect, embodiments of the present invention provide a display device, such as a display panel as described above.

[0016] ​​As can be seen from the above, the above-mentioned technical features of the present invention can have one or more of the following beneficial effects: The gate driving circuit provided in the embodiments of the present invention adds a virtual start circuit before the pull-up control unit in the starting effective stage gate driving unit. The virtual start circuit is used to provide a start voltage to the pull-up control unit, so that the working voltage cycle of the gate signal point of each cascaded gate driving unit is consistent with each other, thereby solving the problem of abnormal panel display. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the operation of a conventional gate drive circuit with 12 timing signals (CK) in related technologies.

[0019] Figure 2 According to Figure 1 This diagram illustrates the input signal voltage waveform, the voltage waveform of the working node in the circuit, and the output voltage waveform during actual operation of a traditional gate drive circuit.

[0020] Figure 3 This is a schematic diagram of an exemplary circuit module for the Nth stage start-up gate drive unit provided in an embodiment of the present invention.

[0021] Figure 4 for Figure 3 A schematic diagram of an exemplary circuit module for the Nth level virtual start circuit.

[0022] Figure 5 for Figure 3 A schematic diagram of an exemplary circuit module for the Nth-stage start-up effective gate drive circuit.

[0023] Figure 6 This is a schematic diagram of the input signal voltage waveform, node voltage waveform, and output voltage waveform of the gate drive circuit provided in the embodiment of the present invention during actual operation. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] The directional terms used in the embodiments of this invention, such as "up," "down," "front," "back," "left," "right," "inner," "outer," and "side," are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of the invention, and not for limiting the invention. For ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown, but the invention is not limited thereto. When a component, such as a layer, film, region, or substrate, is referred to as "on" another component, the component may be directly on the other component, or there may be an intermediate component. Furthermore, in the specification, "on" means located above or below the target component, and does not necessarily mean located on top based on gravity.

[0027] Furthermore, the division of multiple embodiments in this invention is merely for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0028] First, in one embodiment of the present invention, see... Figure 1 , Figure 1 This is a schematic diagram of the operation of a conventional gate drive circuit with 12 timing signals CK in related technologies. For example, the timing signal CK refers to a timing signal line capable of generating the timing signal CK, which is connected to the timing drive circuit of the display panel. The 12 timing signals CK can be understood as having 12 timing signal lines, each generating one timing signal CK. Further... Figure 1 In the diagram, the red line represents the stage transfer signal STN required for the gate drive circuit to operate. The stage transfer signals ST1 to ST6 in the first six gate drive units are provided by the start signal STV, which in turn provides the start voltage to the pull-up control units in the first six gate drive units. Figure 1In this process, starting from the 7th stage gate drive unit, the starting voltage required in its pull-up control unit is generated by the associated previous stage gate drive unit. At the same time, the scan voltage G7 output by the 7th stage gate drive unit serves as a start voltage for the pull-down unit of the 1st stage gate drive unit, enabling it to pull down the G1 voltage of the 1st stage gate drive unit to a negative voltage.

[0029] As stated above, Figure 2 According to Figure 1 This diagram illustrates the gate drive circuit's cascading relationship, including the actual input operating voltage waveform, the operating node voltage waveform, and the output voltage waveform. Figure 2 It can be seen that the start signal STV provides the start voltage to the pull-up control unit of the first 6 gate drive units. Taking the first gate drive unit corresponding to CK1 as an example, the start signal STV is switched to the second voltage H2 at time t1. The voltage Q1 at the gate signal point of the first gate drive unit is switched from the H0 level to the first voltage H1. During the time period t1 to t2, the voltage Q1 at the gate signal point of the first gate drive unit remains at the H1 level. During the time period t2 to t3, CK1 is the second voltage H2. At this time, the voltage Q1 at the gate signal point of the first gate drive unit is pulled up to the third voltage H3. At the same time, the scan voltage G1 output by the first gate drive unit is also the second voltage H2.

[0030] Since the starting voltage of the pull-up control unit is generated by the associated preceding gate drive unit starting from the 7th gate drive unit, the voltage Q at the gate signal point of the last stage of the gate drive unit from the 7th gate drive unit up to the last stage of the gate drive unit has the same duration as the output scan voltage G of its corresponding gate drive unit during the holding time of voltage H1. When the starting signal STV is switched to high level at time t1, Q2 to Q6 also switch from H0 to the first voltage H1. When their corresponding stage CK is not switched to high level, they all maintain the first voltage H1. Therefore, it can be seen that the holding time of Q2 to Q6 at voltage H1 is longer than the holding time of other stage Qn nodes at high level H1. G2 to G6 follow the same pattern. When CK2 to CK6 switch to the second voltage H2, G2 to G6 output the second voltage H2, and sequentially turn on the scan lines.

[0031] That is, within each frame, Q2 to Q6 maintain the H1 voltage for a longer time than in other rows. This long-term repeated voltage drop cycle makes the electrical characteristics of the gate drive circuit more prone to drift, which in turn leads to abnormal output of the gate drive circuit.

[0032] To address the aforementioned technical problems, embodiments of the present invention provide a gate driving circuit, which includes, for example, multiple cascaded gate driving units, wherein each gate driving unit is configured to drive a scan line. Specifically, the multiple cascaded gate driving units include N cascaded start-level gate driving units and multiple non-start-active-level gate driving units cascaded with the Nth start-level gate driving unit. For example, in the multiple cascaded gate driving units, the first to Nth level gate driving units are start-level gate driving units, and the (N+1)th level gate driving unit and subsequent gate driving units are non-start-active-level gate driving units. For example, the number of N is consistent with the number of timing signals CK, and the timing signals CK are connected to the timing driving circuit of the display panel.

[0033] Figure 3 For example, here is an exemplary circuit module diagram of the Nth-level start-up gate driving unit. Specifically, the Nth-level start-up gate driving unit 10 includes: an Nth-level virtual start circuit 100 and an Nth-level start-effective gate driving circuit 11. The Nth-level start-effective gate driving circuit 11 includes a pull-up control unit 200, a pull-up unit 300, and a pull-down unit 400. The Nth-level virtual start circuit 100 is connected to the start signal STV and is also connected to the pull-up control unit 200, which is connected to the gate signal point Q(N). The pull-down unit 400 connects the gate signal point Q(N) and the Nth-level horizontal scan line G(N), and the pull-up unit 300 connects to the Nth-level horizontal scan line G(N). For example, the voltage at the gate signal point Q(N) is defined as the node voltage QN, and the voltage at the Nth-level horizontal scan line G(N) is defined as the scan voltage GN. The virtual start circuit 100 is used to provide a start voltage to the pull-up control unit so that the operating voltage period of the gate signal point of each cascaded gate drive unit is consistent. For example, the start voltage includes a virtual cascade voltage and a virtual scan voltage.

[0034] This invention addresses the problem of abnormal panel display by adding a virtual start circuit before the pull-up control unit in the initial effective stage gate drive unit. The virtual start circuit provides a start voltage to the pull-up control unit, thereby ensuring that the operating voltage cycle of the gate signal point of each cascaded gate drive unit is consistent with each other.

[0035] Furthermore, the Nth-level virtual start circuit 100 includes a virtual pull-up unit 110 and a virtual pull-down unit 120, each of which includes at least one transistor. See also... Figure 4 , Figure 4For example, this is a schematic diagram of an exemplary circuit module of the Nth-level virtual start circuit 100. The virtual pull-up unit 110 includes a first transistor T1 and a second transistor T2. The first terminal (e.g., the gate terminal) of the first transistor T1 is connected to the start signal STV, the second terminal (e.g., the source terminal) of the first transistor T1 is connected to the timing signal CK, and the third terminal (e.g., the drain terminal) of the first transistor T1 is connected to a virtual stage transmission signal point (e.g., dummy STN in the figure) and is used to output the virtual stage transmission voltage to the gate terminal of the pull-up control unit 200 as the gate voltage of the pull-up control unit 200. The virtual stage transmission voltage is, for example, the stage transmission voltage output via the Nth-level virtual start circuit 100. The first terminal (e.g., the gate terminal) of the second transistor T2 is connected to the virtual stage transmission signal point, the second terminal (e.g., the source terminal) of the second transistor T2 is connected to the first transistor, and the third terminal (e.g., the drain terminal) of the second transistor T2 is connected to a virtual scan signal point (e.g., dummy GN in the figure) and is used to output the virtual scan voltage to the source terminal of the pull-up control unit 200 as the source voltage of the pull-up control unit 200. The virtual scan voltage is, for example, the scan voltage output via the Nth-level virtual start circuit 100.

[0036] Furthermore, see also Figure 4 The virtual pull-down unit 120 includes a third transistor T3 and a fourth transistor T4. The first terminal (e.g., the gate terminal) of the third transistor T3 is connected to the (N+n)th level horizontal scan line G(N+n), where n ≥ 1. The second terminal (e.g., the source terminal) of the third transistor T3 is connected to the virtual level signal transmission point, and the third terminal (e.g., the drain terminal) of the third transistor T3 is connected to a negative voltage VSS. The first terminal (e.g., the gate terminal) of the fourth transistor T4 is connected to the (N+n)th level horizontal scan line G(N+n). The second terminal (e.g., the source terminal) of the fourth transistor T4 is connected to the virtual scan signal point, and the third terminal (e.g., the drain terminal) of the fourth transistor T4 is connected to a negative voltage VSS, where n ≥ 1. Specifically, the timing signal CK includes m signals, where n is a positive integer and n = M / 2, and N is a positive integer and 1 ≤ N ≤ m / 2. For example, the number of N signals is m / 2, and N can be any positive integer from 1 to m / 2.

[0037] By connecting the drains of both the third transistor T3 and the fourth transistor T4 to a negative voltage VSS, when the third transistor T3 and the fourth transistor T4 are turned on, they can pull the voltages of the virtual stage transmission signal points and the virtual scan signal points to negative voltages. This reduces the impact of noise on the voltages of the virtual stage transmission signal points and the virtual scan signal points, thereby enhancing the stability of the gate voltage and source voltage of the pull-up control unit 200 in the Nth stage start-active stage gate drive unit 10. For example, when there is a voltage at the N+n stage horizontal scan line G(N+n), the third transistor T3 and the fourth transistor T4 are turned on. That is, when the timing signal CK in the N+n stage gate drive unit corresponding to the N+n stage horizontal scan line G(N+n) is switched to a high level, the third transistor T3 and the fourth transistor T4 are turned on.

[0038] Further, see Figure 5 , Figure 5 For example, this is a schematic diagram of an exemplary circuit module for a gate drive circuit for the Nth stage starting effective level. The Nth stage starting effective level gate drive circuit 11 includes a pull-up control unit 200, a pull-up unit 300, and a pull-down unit 400. The pull-up control unit 200 includes, for example, a fifth transistor T5, the first terminal (e.g., the gate terminal) of which is connected to the virtual stage signal transmission point (e.g.,...). Figure 4 in dummy STN, Figure 5 In STN-m), the second terminal (e.g., the source terminal) of the fifth transistor T5 is connected to the virtual scan signal point (e.g., Figure 4 in dummy GN, Figure 5In the above, the third terminal (e.g., the drain terminal) of the fifth transistor T5 is connected to the gate signal point Q(N). The pull-up unit 300 includes, for example, a sixth transistor T6 and a seventh transistor T7. The gate terminal of the sixth transistor T6 is connected to the gate signal point Q(N), the source terminal of the sixth transistor T6 is connected to the timing signal CK, and the drain terminal of the sixth transistor T6 outputs the stage transmission signal STN. The gate terminal of the seventh transistor T7 is connected to the gate signal point Q(N), the source terminal of the seventh transistor T7 is connected to the timing signal CK, and the drain terminal of the seventh transistor T7 is connected to the Nth level horizontal scan line G(N) and outputs the scan voltage GN. The pull-down unit 400 includes, for example, an eighth transistor T8 and a ninth transistor T9. The gate terminal of the eighth transistor T8 is connected to the N+n level horizontal scan line G(N+n), the source terminal of the eighth transistor T8 is connected to the gate signal point Q(N), and the drain terminal of the eighth transistor T8 is connected to the negative voltage VSS. The gate of the ninth transistor T9 is connected to the N+n level horizontal scan line G(N+n), the source of the ninth transistor T9 is connected to the N level horizontal scan line G(n), and the drain of the ninth transistor T9 is connected to a negative voltage VSS. Therefore, when the timing signal CK in the N+n level gate drive unit corresponding to the N+n level horizontal scan line G(N+n) is switched to a high level (i.e., there is a voltage at the N+n level horizontal scan line), the eighth transistor T8 and the ninth transistor T9 are turned on, which can pull the voltage at the gate signal point Q(N) and the voltage at the N level horizontal scan line G(N) down to the negative voltage VSS.

[0039] This invention addresses the problem of abnormal panel display by adding a virtual start circuit before the pull-up control unit in the initial effective stage gate drive unit. The virtual start circuit provides a start voltage to the pull-up control unit, thereby ensuring that the operating voltage cycle of the gate signal point of each cascaded gate drive unit is consistent with each other.

[0040] The following example uses a gate drive circuit consisting of 12 timing signals CK and 6 virtual start circuits, and compares it with the traditional gate drive circuit with 12 timing signals CK mentioned above to illustrate the solution provided by the present invention in detail.

[0041] Furthermore, the following example uses a gate drive circuit consisting of 12 timing signals CK and 6 sets of virtual start circuits. Specifically, the first 6 start-stage gate drive units each include a virtual start circuit. The gate terminal of the first transistor T1 in the virtual start circuit is connected to the start signal STV, and the source terminals of the first transistor T1 and the second transistor T2 in the virtual start circuit are connected to CK1 to CK6, respectively.

[0042] Figure 6The diagram shows the input signal voltage waveform, node voltage waveform, and output voltage waveform of the gate drive circuit provided in the embodiments of the present invention during actual operation. Figure 6 As shown, the start signal STV switches from low level H0 to the second voltage H2, and CK1 to CK6 switch from low level H0 to the second voltage H2. During the time period when the start signal STV and the timing signal CK are both at the second voltage H2, the virtual pull-up units of the six virtual start circuits output virtual stage transfer voltages ST1 (dummy ST1) to ST6 (dummy ST6) and virtual scan voltages (dummy G1) to G6 (dummy G6), respectively. The output signals are connected to the gate terminal and source terminal of the fifth transistor T5 in the associated pull-up control unit, thereby providing the start voltage to the pull-up control unit of the first six start effective stage gate drive units of the gate drive circuit.

[0043] Specifically, during the time period t1 to t2, both the dummy stage voltage ST1 and the dummy scan voltage G1 are the second voltage H2. At this time, the node voltage Q1 at the gate signal point Q(1) of the first stage start-up effective stage gate drive unit is switched from H0 to the intermediate voltage H1, where H0

[0044] During the time period t2 to t3 (i.e., the time period during which the start signal STV connected to the virtual pull-up unit of the first-stage virtual start circuit in the first-stage start-stage gate drive unit is the second voltage H2, and the timing signal CK1 connected to the virtual pull-up unit of the first-stage start-active gate drive unit is the low level H0), the voltage Q1 of the gate signal point in the first-stage start-active gate drive unit changes from the first voltage H1 to the third voltage H3, and at this time the voltage G1 of the first-stage horizontal scan line is the second voltage H2, thereby pulling the virtual stage transmission voltage ST1 (dummy ST1) and the virtual scan voltage (dummy G1) down to the low level H0 through the third transistor T3 and the fourth transistor T4 in the virtual start circuit, where H0

[0045] As shown above, Q2 to Q6 maintain the H1 level for the same duration as the voltage Qn of other row nodes, which avoids Q2 to Q6 maintaining the H1 level for longer periods than other rows within each frame. This ensures that the operating voltage periods of the gate signal points of multiple cascaded start-active stage gate drive units are consistent.

[0046] ​​In summary, the embodiments of the present invention solve the problem of abnormal panel display by adding a virtual start circuit before the pull-up control unit in the initial effective stage gate drive unit. The virtual start circuit is used to provide a start voltage to the pull-up control unit, so that the operating voltage cycle of the gate signal point of each cascaded gate drive unit is consistent with each other.

[0047] In addition, the present invention also provides a display panel, which includes, for example, the aforementioned gate driving circuit, which will not be described in detail here.

[0048] Furthermore, the present invention also provides a display device, such as the aforementioned display panel, which will not be described in detail here.

[0049] It is understood that the foregoing embodiments are merely illustrative examples of the present invention. Provided that the technical features do not conflict, the structure is not contradictory, and the purpose of the invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate driving circuit comprising a plurality of cascaded gate driving units, each of the gate driving units being configured to drive a scan line, characterized in that, The plurality of cascaded gate driving units include N cascaded start-level gate driving units and a plurality of non-start-active-level gate driving units cascaded with the Nth-level start-level gate driving unit, wherein the Nth-level start-level gate driving unit includes: an Nth-level virtual start circuit and an Nth-level start-active-level gate driving circuit; the Nth-level start-active-level gate driving circuit includes: a pull-up control unit, a pull-up unit, and a pull-down unit; The Nth-level virtual start circuit is connected to the start signal, the Nth-level virtual start circuit is connected to the pull-up control unit, the pull-up control unit is connected to the gate signal point, the pull-down unit is connected to the gate signal point and the Nth-level horizontal scan line, and the pull-up unit is connected to the Nth-level horizontal scan line; The Nth-level virtual start circuit is used to provide a start voltage for the pull-up control unit so that the operating voltage cycle of the gate signal point of each cascaded gate drive unit is consistent. The Nth level virtual start circuit includes a virtual pull-up unit and a virtual pull-down unit. Each of the virtual pull-up unit and the virtual pull-down unit includes at least one transistor. The at least one transistor in the virtual pull-up unit is connected to the start signal and the timing signal and is connected to the pull-up control unit. The at least one transistor in the virtual pull-down unit is connected to the N+n level horizontal scan line and the pull-up control unit, where n≥1. The timing signals include m signals, where n is a positive integer and n = m / 2, and N is a positive integer and 1 ≤ N ≤ m / 2.

2. The gate driving circuit as described in claim 1, characterized in that, The starting voltage includes the virtual stage transfer voltage and the virtual scan voltage.

3. The gate driving circuit as described in claim 2, characterized in that, The virtual pull-up unit includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the start signal, the second terminal of the first transistor is connected to the timing signal, and the third terminal of the first transistor is connected to the virtual stage signal transmission point and is used to output the virtual stage transmission voltage to the pull-up control unit. The first terminal of the second transistor is connected to the virtual stage signal transmission point, the second terminal of the second transistor is connected to the first transistor, and the third terminal of the second transistor is connected to the virtual scan signal point and is used to output the virtual scan voltage to the pull-up control unit.

4. The gate driving circuit as described in claim 3, characterized in that, The virtual pull-down unit includes a third transistor and a fourth transistor. The first terminal of the third transistor is connected to the N+n level horizontal scan line, the second terminal of the third transistor is connected to the virtual level signal transmission point, and the third terminal of the third transistor is connected to a negative voltage. The first terminal of the fourth transistor is connected to the N+n level horizontal scan line, the second terminal of the fourth transistor is connected to the virtual scan signal point, and the third terminal of the fourth transistor is connected to a negative voltage.

5. The gate driving circuit as described in claim 4, characterized in that, The first end of the pull-up control unit is connected to the virtual stage signal point, the second end of the pull-up control unit is connected to the virtual scan signal point, and the third end of the pull-up control unit is connected to the gate signal point.

6. The gate driving circuit as described in claim 5, characterized in that, During the time period when the start signal and the timing signal connected to the virtual pull-up unit are both at the second voltage H2, the Nth stage virtual start circuit outputs the virtual stage transfer voltage and the virtual scan voltage, and the voltage of the gate signal point changes from a low voltage H0 to a first voltage H1, wherein H0 <H1<H2。 7. The gate driving circuit as described in claim 6, characterized in that, During the time period when the start signal connected to the virtual pull-up unit is the second voltage H2 and the timing signal connected to the virtual pull-up unit is the low voltage H0, the voltage of the gate signal point changes from the first voltage H1 to the third voltage H3, and the voltage of the Nth level horizontal scan line is the second voltage H2, so that the virtual stage voltage and the virtual scan voltage are pulled down to the low voltage H0, wherein H0 <H1<H2<H3。 8. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 1-7.

9. A display device, characterized in that, Includes the display panel as described in claim 8.

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