Semiconductor device with row decoder circuit
By introducing a voltage control circuit into the main word driver circuit of the semiconductor memory device and switching the supply voltage, the problem of difficulty in reducing the transistor GIDL in the sub-word driver is solved, achieving higher energy efficiency and reduced power consumption.
Patent Information
- Application Number
- CN202410932815.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-19
- Filing Date
- 2024-07-12
- Publication Date
- 2025-01-21
AI Technical Summary
In the existing semiconductor memory devices, it is difficult to effectively reduce the transistor GIDL in the sub-word driver, especially during standby time, resulting in poor energy efficiency.
By introducing a voltage control circuit into the main word driver circuit, the supply voltage can be switched in different operating modes, thereby reducing the operating voltage of the main word line during standby time and reducing GIDL.
GIDL effectively reduces standby time, improves the energy efficiency of semiconductor memory devices, and reduces power consumption.
Smart Images
Figure CN119339764A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to semiconductor devices, and in particular, to semiconductor devices having row decoder circuits. Background Art
[0002] There are cases where a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is configured to select a word line based on a row address and a bit line based on a column address. There are cases where word lines are hierarchical with a main word line selected by a higher-order bit of a row address and a sub-word line selected by a lower-order bit of the row address. In order to reduce GIDL (Gate Induced Drain Leakage) of a transistor included in a sub-word driver, there are cases where an operating voltage lower than an operating voltage at a normal time is supplied to a main word driver driving the main word line during a standby time. Summary of the invention
[0003] On the one hand, the present disclosure provides a device comprising: a plurality of first regions arranged in a first direction, each of the plurality of first regions including a second region and a third region; a plurality of main word lines extending in a second direction intersecting the first direction and arranged in the first direction; a plurality of main word driver circuits, each of which is configured to activate an associated one of the plurality of main word lines in response to a row address signal; and a voltage control circuit configured to supply a first power supply voltage to the plurality of main word driver circuits in a first operating mode and to supply a second power supply voltage different from the first power supply voltage to the plurality of main word driver circuits in a second operating mode, wherein one or more of the plurality of main word driver circuits are arranged in the second region included in each of the plurality of first regions, and wherein the voltage control circuit is divided into a plurality of circuit portions, the plurality of circuit portions being respectively arranged in two or more third regions in two or more of the plurality of first regions.
[0004] On the other hand, the present disclosure provides an apparatus comprising: a memory cell array configured to be accessed by a plurality of main word signals; a main word circuit configured to activate one of the plurality of main word signals and arranged in a main word circuit region overlapping the memory cell array in a first direction, a sensing circuit configured to amplify read data read from the memory cell array and arranged in a sensing amplifier region overlapping the memory cell array in a second direction perpendicular to the first direction; and a voltage control circuit configured to control an operating voltage of the main word circuit, wherein a portion of the voltage control circuit is arranged in the main word circuit region so as to overlap the memory cell array in the first direction, and wherein another portion of the voltage control circuit is arranged in a gap region adjacent to the main word circuit region in the second direction and adjacent to the sensing amplifier region in the first direction so as not to overlap the memory cell array in the first direction.
[0005] On the other hand, the present disclosure provides a device comprising: a plurality of first regions arranged in a line, each of the plurality of first regions including a second region in a central area, a third region along a first side, and a fourth region along a second side opposite to the first side; a plurality of main word driver circuits, each of which is arranged in a corresponding one of the second regions of the plurality of first regions; and a voltage control circuit configured to supply a voltage to each of the plurality of main word driver circuits, the voltage control circuit being divided into a plurality of circuit portions, the plurality of circuit portions being arranged in one or more of the third and fourth regions in one or more of the plurality of first regions. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 is a schematic diagram showing the configuration of a main part of a semiconductor memory device according to an embodiment of the present disclosure;
[0007] Figure 2 is a schematic circuit diagram for explaining the functions of circuits included in a main word driver area;
[0008] Figure 3 and 4 is a circuit diagram of a level shift circuit;
[0009] Figure 5 is a circuit diagram of a main word driver circuit;
[0010] Figure 6 It is the circuit diagram of the voltage control circuit;
[0011] Figure 7 is a schematic plan view for explaining an example of the configuration of a main word driver area;
[0012] Figure 8is a schematic plan view for explaining the configuration of a unit driver area;
[0013] Fig. 9 is used to explain Figure 7 A schematic plan view of a circuit arranged in a combination area in the layout shown in FIG.
[0014] Fig.10 is a schematic plan view for explaining another example of the configuration of the main word driver area;
[0015] Fig.11 is used to explain Fig.10 A schematic plan view of the circuits arranged in the combination area in the layout shown in FIG. 1 ; and
[0016] Fig.12 is a circuit diagram of a modified driver circuit. DETAILED DESCRIPTION
[0017] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show specific aspects and various embodiments of the present disclosure by way of illustration. The detailed description provides sufficient details to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein need not be mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.
[0018] Figure 1 is a schematic diagram showing the configuration of a main part of a semiconductor memory device according to an embodiment of the present disclosure. Figure 1The semiconductor memory device shown in is a DRAM, and the semiconductor memory device includes an array area 2 including a plurality of memory cell arrays 10 and a row decoder area 4 arranged at the end of the array area 2 in the X direction. In the array area 2, a sub-word driver area 11 is disposed between the memory cell arrays 10 adjacent to each other in the X direction, and a sense amplifier area 12 is disposed between the memory cell arrays 10 adjacent to each other in the Y direction. In some examples, the X direction and the Y direction are perpendicular to each other. A plurality of sub-word drivers 13 are disposed in the sub-word driver area 11. Each of the sub-word drivers 13 activates an associated one of the sub-word lines SWL based on a sub-word selection signal FX and a main word signal MW supplied via a main word line MWL. A plurality of sense amplifiers 14 are disposed in the sense amplifier area 12. Each of the sense amplifiers 14 amplifies a potential difference appearing on a pair of bit lines BL. A memory cell MC is disposed at the intersection of the sub-word line SWL and the bit line BL. With this configuration, when data held in the memory cell MC in response to activation of the sub word line SWL is read by the bit line BL, the data read by the bit line BL is amplified by associated ones of the sense amplifiers 14 .
[0019] A row address RA is supplied to the row decoder area 4. A sub-word selection signal FX is generated based on the lower-order bits of the row address RA. A main word signal MW is generated based on the higher-order bits of the row address RA. A plurality of main word driver areas 15 are arranged in the row decoder area 4. A plurality of main word driver circuits 27 that drive the main word lines MWL are arranged in each of the main word driver areas 15. Each of the main word driver areas 15 is assigned to a plurality of memory cell arrays 10 arranged in the X direction. The width of each of the main word driver areas 15 in the Y direction is substantially the same as the width of each of the memory cell arrays 10 in the Y direction. A gap area 16 is arranged between the main word driver areas 15 adjacent to each other in the Y direction. The width of the gap area 16 in the Y direction is substantially the same as the width of the sense amplifier area 12 in the Y direction. The width of the gap area 16 in the X direction may be greater than the width of each of the main word driver areas 15 in the X direction.
[0020] Figure 2 1 is a schematic circuit diagram for explaining the functions of the circuits included in each of the main word driver regions 15. Figure 2In the example shown in FIG. 1 , the address bits X0 to X2 constituting the row address RA are supplied to the predecoder 21. The predecoder 21 generates the sub-word selection signal FX based on the address bits X0 to X2. In addition, the address bits X3 to X5 constituting the row address RA are supplied to the predecoder 22. The predecoder 22 generates the predecode signal RX543 based on the address bits X3 to X5. The predecode signal RX543 has, for example, a predecode bit RX543. <0> To RX543 <7> The 8-bit configuration is formed, and the pre-decoding signal RX543 activates the pre-decoding bit RX543 <0> To RX543 <7> The address bits X6 to X8 constituting the row address RA are supplied to the predecoder 23. The predecoder 23 generates a predecode signal RX876 based on the address bits X6 to X8. The predecode signal RX876 has, for example, <0> To RX876 <7> The 8-bit configuration is formed, and the pre-decoding signal RX876 activates the pre-decoding bit RX876 <0> To RX876 <7> The address bits X9 and X10 constituting the row address RA are supplied to the predecoder 24. The predecoder 24 generates a predecode signal RX109 based on the address bits X9 and X10. The predecode signal RX109 has, for example, <0> To RX109 <3> The 4-bit configuration is formed, and the pre-decoding signal RX109 activates the pre-decoding bit RX109 <0> To RX109 <3> Any one of. Predecode signal RX876 and predecode signal RX109 constitute predecode signal RX910. Note that it is not always necessary to decode each of address bits X6 to X8 and address bits X9 and X10 by predecoders 23 and 24, respectively, and predecode signal RX910 can be generated by a predecoder that decodes address bits X6 to X10.
[0021] The pre-decoding signal RX543 is converted into the pre-decoding signal RF543 by the level shift circuit 25. The pre-decoding signal RX610 constituting the pre-decoding signals RX876 and RX109 is converted into the pre-decoding signal RF610 by the level shift circuit 26. The pre-decoding signals RF543 and RF610 are supplied to the main word driver circuit 27. The main word driver circuit 27 activates the associated main word line MWL based on the pre-decoding signal RF543 and the pre-decoding signal RF610. The power supply potential VCCP of each of the level shift circuits 25 and 26 is supplied via the power supply line 31. The power supply potential Vccprdec of the main word driver circuit 27 is supplied via the power supply line 33. The level of the power supply potential Vccprdec is selected by the voltage control circuit 28 based on the selection signal SEL. The power supply potentials VCCP and VGIDL are supplied to the voltage control circuit 28 via the power supply lines 31 and 32, respectively, and any one of the power supply potential VCCP and the power supply potential VGIDL is supplied to the power supply line 33 based on the selection signal SEL. The power supply potential VCCP is selected at the time of normal operation. The power supply potential VGIDL is selected at the standby time. The level of the power supply potential VGIDL is lower than the level of the power supply potential VCCP, and thus the GIDL of the standby time is reduced. In addition, the power supply potential VDD2 of each of the predecoders 21 to 24 is lower than the power supply potential VCCP and the power supply potential VGIDL. The level shift circuit 25 has a function of converting the predecode signal RX543 having an amplitude of VDD2 into a predecode signal RF543 having an amplitude of VCCP or VGIDL. The level shift circuit 26 has a function of converting the predecode signal RX610 having an amplitude of VDD2 into a predecode signal RF610 having an amplitude of VCCP or VGIDL.
[0022] Figure 3 is a circuit diagram of the level shift circuit 25. Figure 3As shown in FIG. 1 , the level shift circuit 25 is composed of the pre-decoding bit RX543 <0> To RX543 <7> The eight level shift circuits 25 associated <0> To 25 <7> Level shift circuit 25 <0> The inverter circuit 41 and 42 are cascade-coupled, an N-channel MOS transistor 43, and a P-channel MOS transistor 44 are included. A control signal C1 is supplied to an input node of the inverter circuit 41. An output node of the inverter circuit 41 and an input node of the inverter circuit 42 are coupled to each other via a signal line 45. A power supply potential VCCP is supplied to a high potential side power supply node of each of the inverter circuits 41 and 42. The transistor 43 is coupled between a low potential side power supply node of the inverter circuit 41 and a power supply line 34 to which a ground potential VSS is supplied. The pre-decoding bit RX543 is supplied. <0> Supplied to the gate electrode of transistor 43. With this configuration, when the pre-decoding bit RX543 <0> When at a high level, the level shift circuit 25 is activated. <0> The inverter circuit 41 in FIG. 4 is coupled between the power supply line 31 to which the power supply potential VCCP is supplied and the signal line 45. The gate electrode of the transistor 44 is coupled to the output node of the inverter circuit 42. The level-shifted pre-decoding bit RF543 is output from the output node of the inverter circuit 42. <0> With this circuit configuration, in response to the control signal C1, the pre-decoded bit RX543 having an amplitude of VDD2 is <0> Convert to pre-decoded bits RF543 with amplitude VCCP <0> For other level shift circuits 25 <1> To 25 <7> , in addition to the pre-decode bits RX543 associated with <1> To RX543 <7> Convert to pre-decoded bits RF543 <1> To RF543 <7> In addition to the fact that each of these circuits has Figure 3 The level shift circuit 25 shown in <0> The circuit configuration of the eight level shift circuits 25 is the same as that of the <0> To 25 <7> Arranged in Figure 1 In a main word drive area 15 shown in FIG.
[0023] Figure 4 is a circuit diagram of the level shift circuit 26. Figure 4 As shown in FIG. 1 , the level shift circuit 26 is composed of 25 level shift circuits 26 <0> To 26 <24> Formation, pre-decoding bit RX876 <0> To RX876 <7> Any one of the pre-decoding bits RX109 <0> To RX109 <3> Any of them are input to the 25 level shift circuits 26 in different pairs. <0> To 26 <24> . Figure 4 Demonstrate a level shift circuit 26 Circuit configuration of level shift circuit 26 The inverter circuit 51 and 52 are cascade-coupled, N-channel MOS transistors 53 and 54, and a P-channel MOS transistor 55 are included. A control signal C2 is supplied to an input node of the inverter circuit 51. An output node of the inverter circuit 51 and an input node of the inverter circuit 52 are coupled to each other via a signal line 56. A power supply potential VCCP is supplied to a high potential side power supply node of each of the inverter circuits 51 and 52. The transistors 53 and 54 are coupled to each other in series between a low potential side power supply node of the inverter circuit 51 and a power supply line 34 to which a ground potential VSS is supplied. The associated pre-decoding bit RX543 is supplied to the power supply line 34. <j>(j is any one of 0 to 7) is supplied to the gate electrode of transistor 53. The associated pre-decoding bit RX109 <k>(k is any one of 0 to 3) is supplied to the gate electrode of transistor 54. With this configuration, when the associated pre-decoding bit RX543 <j>and associated pre-decoding bit RX109 <k>When both are at high level, the level shift circuit 26 is activated. The inverter circuit 51 in FIG. 5 is coupled between the power supply line 31 to which the power supply potential VCCP is supplied and the signal line 56. The gate electrode of the transistor 55 is coupled to the output node of the inverter circuit 52. The pre-decoding bit RF610 having the amplitude VCCP is output from the output node of the inverter circuit 52. . With this circuit configuration, when the associated pre-decode bit RX543 <j>and associated pre-decoding bit RX109 <k>When both are at high level, in response to the control signal C2, the level shift circuit 26 The associated pre-decoding bit RF610 In this way, using the pre-decoding bit RX876 <0> To RX876 <7> And pre-decoding bit RX109 <0> To R109X <3> are input to the level shift circuit 26 in different pairs <0> To 26 <24> The configuration of the level shift circuit 26 <0> To 26 <24> Activate pre-decoding bit RF610 <0> To RF610 <24> Any one of the 25 level shift circuits 26 <0> To 26 <24> Arranged in Figure 1 In a main word drive area 15 shown in FIG.
[0024] Figure 5 Main word driver circuit 27 Circuit diagram of Figure 5 As shown in FIG. 1 , the main word driver circuit 27 The eight main word driver circuits 27 _0 to 27 _7 formation, each of which receives the pre-decoded bit RF610 . Main word driver circuit 27 _0 to 27 Each of _7 is pre-decoded by RF610 And receive pre-decoding bit RX543 <0> To RX543 <7> A main word signal MW as an output from the NAND gate circuit 60 is supplied to each associated main word line MWL.
[0025] Figure 6 2 is a circuit diagram of the voltage control circuit 28. Figure 6 , the voltage control circuit 28 includes a control circuit 70 and a driver circuit 80. The control circuit 70 includes P-channel MOS transistors 71 to 74 and an N-channel MOS transistor 75. The transistors 71, 72, and 75 are coupled in series with each other between the power supply line 31 to which the power supply potential VCCP is supplied and the power supply line 34 to which the ground potential VSS is supplied. A selection signal SEL is supplied to the gate electrode of each of the transistors 71 and 75. The ground potential VSS is supplied to the gate electrode of the transistor 72 in a fixed manner. With this configuration, the transistors 71, 72, and 75 constitute an inverter circuit, and a signal SELB obtained by inverting the selection signal SEL is output from a coupling point between the transistor 72 and the transistor 75. The transistors 73 and 74 are coupled in series with each other between the power supply line 32 to which the power supply potential VGIDL is supplied and the power supply line 33 to which the power supply potential Vccprdec is supplied. The selection signal SEL is supplied to the gate electrode of each of the transistors 73 and 74. The driver circuit 80 includes P-channel MOS transistors 81 and 82. The transistors 81 and 82 are coupled in parallel with each other between the power supply line 31 to which the power supply potential VCCP is supplied and the power supply line 33 to which the power supply potential Vccprdec is supplied. The signal SELB is supplied to the gate electrode of each of the transistors 81 and 82. With this circuit configuration, when the selection signal SEL is at a high level, the transistors 81 and 82 are turned on, and the power supply potential VCCP is supplied to the power supply line 33. In this case, the power supply potential Vccprdec is at the same level as the power supply potential VCCP. At the same time, when the selection signal SEL is at a low level, the transistors 73 and 74 are turned on, and the power supply potential VGIDL is supplied to the power supply line 33. In this case, the power supply potential Vccprdec is at the same level as the power supply potential VGIDL.
[0026] Here, the transistor 72 that is always turned on is coupled in series with the transistor 71 so as to maintain a certain withstand voltage during the period in which the transistors 71 and 72 are turned on, while the transistors 71 and 72 each having the same gate length and the same array pitch as the P-channel MOS transistor used for the main word driver circuit 27 are used, and the gate length of these transistors is almost enlarged to two times by coupling these transistors in series. In addition, the transistors 73 and 74 are coupled in series with each other so as to reduce the turn-on current during the period in which the transistors 73 and 74 are turned on, while the transistors 73 and 74 each having the same gate length and the same array pitch as the P-channel MOS transistor used for the main word driver circuit 27 are used, and the gate length of these transistors is almost enlarged to two times by coupling these transistors in series.
[0027] Figure 7 1 is a schematic plan view for explaining an example of the configuration of the main word driver area 15. Figure 7 In the example shown in FIG. 1 , the main word driver area 15 is divided into 25 unit driver areas 100 to 124 arranged in the Y direction. Figure 4 The level shift circuit 26 shown in <0> To 26 <24> Any of the pre-decoding bits RF610 is respectively arranged in each of the 25 unit driver regions 100 to 124. Therefore, each of the unit driver regions 100 to 124 is represented by an associated pre-decoding bit RF610. <0> To RF610 <24> Each of the options in Figure 7 In the example shown in Figure 5 The eight main word driver circuits 27 shown in _0 to 27 _7 is arranged in each of the 23 unit driver areas 101 to 123. One main word driver circuit 27 is arranged in the unit driver area 100 located at one end of the main word driver area 15 in the Y direction. Four main word driver circuits 27 are arranged in the unit driver area 124 located at the other end of the main word driver area 15 in the Y direction. With this configuration, a total of 189 main word driver circuits 27 are arranged in one main word driver area 15. An associated main word line MWL is respectively allocated to each of the 189 main word driver circuits 27. These main word lines MWL extend in the X direction and are arranged in the Y direction.
[0028] Figure 8 is a schematic plan view for explaining the configuration of the unit driver area. Figure 8 1 and 2 show six unit driver areas 102 to 107 as an example, but other unit driver areas in the unit driver area 101 to 123 including eight main word driver circuits 27 also have the same configuration. Figure 8 , the unit driver regions 102 to 107 are shaped into rectangles. The region on one side of the unit driver regions 102 to 107 in the X direction forms a P-type region 210 in which a P-channel MOS transistor is arranged. The region on the other side of the unit driver regions 102 to 107 in the X direction forms an N-type region 220 in which an N-channel MOS transistor is arranged. The P-type region 210 includes a main region 211 in which P-channel MOS transistors constituting eight main word driver circuits 27 are arranged and a sub-region 212 in which no main word driver circuit 27 is arranged. The sub-region 212 is located at one end of the P-type region 210 in the X direction and its position in the Y direction is offset. Similarly, the N-type region 220 includes a main region 221 in which N-channel MOS transistors constituting eight main word driver circuits 27 are arranged and a sub-region 222 in which no main word driver circuit 27 is arranged. The sub-region 222 is located at the other end of the N-type region 220 in the X direction and its position in the Y direction is offset.
[0029] Here, the unit driver regions adjacent to each other in the Y direction are axially symmetric to each other with respect to the boundaries of these driver regions as the axis, so that the sub-regions 212 are integrated with each other and the sub-regions 222 are also integrated with each other. For example, the driver region 102 and the driver region 103 are axially symmetric to each other with respect to the boundary line L as the axis. With this configuration, the sub-region 212 included in the driver region 102 and the sub-region 212 included in the driver region 103 are integrated with each other, thereby forming a combination region P, in which a P-channel MOS transistor can be arranged. Similarly, the sub-region 222 included in the driver region 102 and the sub-region 222 included in the driver region 103 are integrated with each other, thereby forming a combination region N, in which an N-channel MOS transistor can be arranged. With this configuration, a pair of combination regions P and N are formed in every 16 main word driver circuits 27.
[0030] Fig. 9 is used to explain Figure 7 Schematic plan view of the circuits arranged in combination areas P and N in the layout shown in FIG. Fig. 9 In the example shown in FIG. 1 , 11 combination areas P0 to P10 and 11 combination areas N0 to N10 are formed in one main word driver area 15. Among these combination areas, eight combination areas P0 to P7 and eight combination areas N0 to N7 have arranged therein Figure 3 For example, the eight level shift circuits 25 shown in FIG. <0> The P-channel MOS transistors are arranged in the combination area P0 and constitute the level shift circuit 25 <0> The N-channel MOS transistors of are arranged in the combination area N0. Here, the combination areas P0 to P3 and the combination areas N0 to N3 are located in the cell driver areas 102 to 109, and the combination areas P4 to P7 and the combination areas N4 to N7 are located in the cell driver areas 116 to 123.
[0031] Meanwhile, the P-channel MOS transistors 71 to 74 of the transistors constituting the control circuit 70 included in the voltage control circuit 28 are arranged in the combination area P8 positioned in the unit driver areas 112 and 113. In addition, the N-channel MOS transistor 75 of the transistors constituting the control circuit 70 included in the voltage control circuit 28 is arranged in the combination area N8 positioned in the unit driver areas 112 and 113. Furthermore, the P-channel MOS transistor 81 constituting the driver circuit 80 included in the voltage control circuit 28 is arranged in the combination area P9 positioned in the unit driver areas 110 and 111. The P-channel MOS transistor 82 constituting the driver circuit 80 included in the voltage control circuit 28 is arranged in the combination area P10 positioned in the unit driver areas 114 and 115.
[0032] With this configuration, it is not necessary to arrange the voltage control circuit 28 in the gap area 16, so that the size of the gap area 16 in the X direction can be reduced. In addition, since the combination areas P9 and P10 in which the driver circuit 80 is arranged are positioned in a portion close to the center of the main word driver area 15 in the Y direction, the wiring length of the power supply line 33 that couples the driver circuit 80, the level shift circuits 25 and 26, and the main word driver circuit 27 to each other is shortened compared to the case where the driver circuit 80 is arranged in the gap area 16. Fig. 9 The state in which the power supply line 33 and the transistors 81 and 82 constituting the driver circuit 80 are coupled to each other in the combination regions P9 and P10 is shown. With this configuration, the interconnection resistance on the power supply line 33 supplying the power supply potential Vccprdec can be reduced.
[0033] Fig.10 1 is a schematic plan view for explaining another example of the configuration of the main word driver section 15. Fig.10 In the example shown in , the main word driver area 15 is divided into 22 unit driver areas 130 to 151 arranged in the Y direction. Among the unit driver areas 130 to 151, 20 unit driver areas 131 to 150 respectively have eight main word driver circuits 27 arranged therein, the unit driver area 130 positioned at one end of the main word driver area 15 in the Y direction has two main word driver circuits 27 arranged therein, and the unit driver area 151 positioned at the other end of the main word driver area 15 in the Y direction has four main word driver circuits 27 arranged therein. With this configuration, a total of 166 main word driver circuits 27 are arranged in one main word driver area 15.
[0034] Fig.11 is used to explain Fig.10 Schematic plan view of the circuits arranged in combination areas P and N in the layout shown in FIG. Fig.11 In the example shown in FIG. 1 , ten combined areas P0 to P9 and ten combined areas N0 to N9 are formed in one main word driver area 15. Among the combined areas P0 to P9 and N0 to N9, eight combined areas P0 to P7 and eight combined areas N0 to N7 respectively have arranged therein Figure 8 Here, the combination area P0 to P3 and the combination area N0 to N3 are located in the cell driver areas 131 to 138 and the combination area P4 to P7 and the combination area N4 to N7 are located in the cell driver areas 143 to 150.
[0035] Meanwhile, the P-channel MOS transistors 71 to 74 of the transistors constituting the control circuit 70 included in the voltage control circuit 28 are arranged in the combination area P8 located in the unit driver areas 141 and 142. In addition, the N-channel MOS transistor 75 of the transistors constituting the control circuit 70 included in the voltage control circuit 28 is arranged in the combination area N8 located in the unit driver areas 141 and 142. Furthermore, the P-channel MOS transistor 81 constituting the driver circuit 80 included in the voltage control circuit 28 is arranged in the combination area P9 located in the unit driver areas 139 and 140. In this example, as Fig.12 As shown in FIG. 8 , three P-channel MOS transistors 81 to 83 are coupled in parallel to the driver circuit 80. In addition, as shown in FIG. Fig.11 As shown in FIG. 8 , the transistor 82 is arranged in the gap region 16 adjacent to one side of the main word driver region 15 in the Y direction and the transistor 83 is arranged in the gap region 16 adjacent to the other side of the main word driver region 15 in the Y direction.
[0036] With this configuration, since the transistors 81 to 83 constituting the driver circuit 80 are arranged in the Y direction in a distributed manner, the wiring length of the power supply line 33 coupling the driver circuit 80, the level shift circuits 25 and 26, and the main word driver circuit 27 to each other is further shortened. Fig.11 There is shown a state in which the power supply line 33 and the transistors 81 to 83 constituting the driver circuit 80 are coupled to each other in the combination region P9 and the two gap regions 16. With this configuration, the interconnection resistance on the power supply line 33 supplying the power supply potential Vccprdec can be further reduced.
[0037] Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the embodiments and obvious modifications and equivalents thereof. In addition, it will be easy for those skilled in the art to understand other modifications within the scope of the present disclosure based on the present disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with each other to form a variation pattern of the disclosed embodiments. Therefore, it is desired that the scope of at least some of the present disclosure should not be limited by the above-mentioned specific disclosed embodiments. < / k> < / j> < / k> < / j> < / k> < / j>
Claims
1. A device comprising: a plurality of first regions arranged in a first direction, each of the plurality of first regions including a second region and a third region; a plurality of main word lines extending in a second direction crossing the first direction and arranged in the first direction; a plurality of main word driver circuits each configured to activate an associated one of the plurality of main word lines in response to a row address signal; and a voltage control circuit configured to supply a first power supply voltage to the plurality of main word driver circuits in a first operating mode and to supply a second power supply voltage different from the first power supply voltage to the plurality of main word driver circuits in a second operating mode, wherein one or more of the plurality of main word driver circuits are arranged in the second region included in each of the plurality of first regions, and wherein the voltage control circuit is divided into a plurality of circuit portions, and the plurality of circuit portions are respectively arranged in two or more third regions in two or more of the plurality of first regions.
2. The device according to claim 1, The voltage control circuit comprises: a first switch circuit coupled between a first power supply line supplied with the first power supply voltage and a third power supply line supplying an operating voltage to the plurality of main word driver circuits; a second switch circuit coupled between a second power line supplied with the second power voltage and the third power line; and a control circuit configured to control the first and second switch circuits, wherein the first switch circuit is arranged in the third region included in a first one of the plurality of first regions, and Wherein the control circuit is arranged in the third region included in a second one of the plurality of first regions. 3 . The apparatus of claim 2 , wherein the second switch circuit is arranged in the third region included in the second one of the plurality of first regions.
4. The device according to claim 3, wherein the voltage control circuit further comprises a third switch circuit coupled in parallel with the first switch circuit, and Wherein the third switch circuit is arranged in the third region included in a third one of the plurality of first regions. 5 . The apparatus of claim 4 , wherein the second one of the plurality of first regions is arranged between the first one of the plurality of first regions and the third one of the plurality of first regions in the first direction.
6. The apparatus of claim 2, further comprising: a first decoder circuit configured to decode a first portion of the row address signal to activate one of a plurality of first select signals; and a first level shift circuit configured to convert the levels of the plurality of first selection signals from a first amplitude to a second amplitude, Wherein the first level shift circuit is arranged in the third region included in a fourth one of the plurality of first regions.
7. The apparatus of claim 6, wherein the second amplitude is substantially the same as the first supply voltage.
8. The apparatus of claim 7, further comprising: a second decoder circuit configured to decode a second portion of the row address signal to activate one of a plurality of second select signals; and a second level shift circuit configured to convert the levels of the plurality of second selection signals from the first amplitude to the second amplitude, Wherein the second level shift circuit is arranged in each of the plurality of first regions.
9. The apparatus of claim 8, wherein each of the plurality of main word driver circuits is configured to activate an associated one of the plurality of main word lines when an associated one of the plurality of first select signals and an associated one of the plurality of second select signals are activated.
10. The apparatus of claim 2, further comprising: a memory cell array coupled to the plurality of main word lines and positioned so as to overlap the plurality of first regions in the second direction; and A fourth region is positioned adjacent to the plurality of first regions in the first direction so as not to overlap with the memory cell array in the second direction.
11. The apparatus of claim 10, wherein the voltage control circuit is arranged in the third region included in one or more of the plurality of first regions and is not arranged in the fourth region.
12. The device according to claim 10, wherein the voltage control circuit further comprises a third switch circuit coupled in parallel with the first switch circuit, and The third switching circuit is arranged in the fourth area.
13. The apparatus of claim 12, further comprising a fifth region positioned so as not to overlap the memory cell array in the second direction, wherein the plurality of first regions are arranged between the fourth and fifth regions in the first direction, wherein the voltage control circuit further comprises a fourth switch circuit coupled in parallel with the first and third switch circuits, and Wherein the fourth switch circuit is arranged in the fifth area.
14. An apparatus comprising: a memory cell array configured to be accessed by a plurality of main word signals; a main word circuit configured to activate one of the plurality of main word signals and arranged in a main word circuit region overlapping the memory cell array in a first direction; a sensing circuit configured to amplify read data read from the memory cell array and arranged in a sense amplifier region overlapping the memory cell array in a second direction perpendicular to the first direction; and a voltage control circuit configured to control an operating voltage of the main word circuit, wherein a portion of the voltage control circuit is arranged in the main word circuit area so as to overlap with the memory cell array in the first direction, and Another portion of the voltage control circuit is arranged in a gap region adjacent to the main word circuit region in the second direction and adjacent to the sense amplifier region in the first direction so as not to overlap with the memory cell array in the first direction.
15. The apparatus of claim 14, wherein the voltage control circuit comprises: a plurality of first power supply circuits configured to supply the operating voltage having a first level to the main word circuit; and a second power supply circuit configured to supply the operating voltage having a second level lower than the first level to the main word circuit, wherein one of the plurality of first power supply circuits is arranged in the main word circuit area, and Another one of the plurality of first power supply circuits is arranged in the gap region.
16. The device according to claim 15, wherein the voltage control circuit further comprises a control circuit configured to activate the first power circuit or the second power circuit, and The control circuit is arranged in the main word circuit area.
17. An apparatus comprising: a plurality of first regions arranged in a line, each of the plurality of first regions including a second region in a central area, a third region along a first side, and a fourth region along a second side opposite to the first side; a plurality of main word driver circuits each disposed in a corresponding one of the second regions of the plurality of first regions; and A voltage control circuit is configured to supply a voltage to each of the plurality of main word driver circuits, the voltage control circuit being divided into a plurality of circuit portions, the plurality of circuit portions being arranged in one or more of the third and fourth regions in one or more of the plurality of first regions.
18. The device according to claim 17, wherein the third region can only be used for first conductivity type transistors, and The fourth region can only be used for second conductivity type transistors.
19. The device according to claim 17, The plurality of circuit parts include: a first switch circuit configured to supply a first voltage to each of the plurality of main word driver circuits; a second switch circuit configured to supply a second voltage to each of the plurality of main word driver circuits; and a control circuit configured to control the first and second switch circuits, wherein the first switch circuit is arranged in one of the third regions, wherein the second switch circuit is arranged in another one of the third regions, wherein a portion of the control circuit is arranged in one of the fourth regions, wherein another portion of the control circuit is arranged in the other one of the third regions.
20. The apparatus of claim 19, further comprising a plurality of level shifting circuits, each of the level shifting circuits being configured to receive a first control signal having a first amplitude to generate a second control signal having a second amplitude, wherein the plurality of main word driver circuits are configured to be controlled by corresponding ones of the second control signals, and Wherein the plurality of level shifting circuits are arranged in an associated one or more of the third and fourth regions in another one or more of the plurality of first regions.