Wafer-level packaging method of slotted filling support material and chip structure

Abstract

The invention discloses a wafer-level packaging method and a chip structure of a slotted filling support material, comprising the following steps: providing a wafer-level packaging structure which comprises a first wafer, a second wafer and a connecting part for bonding the first wafer and the second wafer, a cutting channel cavity communicated with the outside is formed between at least part of adjacent connecting parts; cutting the wafer-level packaging structure to form a through groove along the thickness direction of the wafer-level packaging structure, wherein the through groove is communicated with the cutting channel cavity along the thickness direction; and the cutting channel cavity is filled with a supporting material through the through groove. The cutting channel cavity is good in supporting effect, and the wafer-level packaging structure is not prone to being broken and damaged.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging and testing, and in particular to a wafer-level packaging method and a chip structure of a slotted filling support material. Background Art

[0002] Traditional chip packaging is to fix the pre-processed and divided single chip in the packaging tube shell, connect the contacts on the chip with the electrical pins on the packaging tube shell through wire bonding technology, and finally fill it with insulating packaging materials or add a cover plate to seal it. With the development of semiconductor manufacturing technology, wafer level packaging (WLP) has been developed to improve integration and reduce chip manufacturing costs. This technology is a technology that packages and tests the entire wafer and then cuts it to obtain a single finished chip.

[0003] Wafer-level packaging technology includes wafer bonding technology. More and more semiconductor devices are beginning to use bonding to achieve the purpose of pre-bonding protection of devices, functional device stacking, etc., and bonding is often no longer 100% flat bonding, but through pre-processing of the bonding surface, a cavity structure is formed. From a simple metal bonding layer cavity of a few microns to a silicon cavity of tens or hundreds of microns, the cutting path area forms a pipeline cavity structure that runs horizontally and vertically.

[0004] The existence of such cut-way cavities has a great impact on subsequent packaging. For chip-level packaging, cutting is generally performed first, followed by chip-level packaging. In this case, only the impact of cutting needs to be considered, such as the risk of breakage and cracks in the bonding layer. For wafer-level packaging, the existence of cut-way cavities will bring more problems and troubles:

[0005] Grinding thinning and cracking: This risk mainly exists at the edge of the wafer. Since grinding is a grinding process with great pressure, the edge, which has no support structure, is very likely to cause wafer fracture.

[0006] Cutting line corrosion: Due to the existence of the pipeline cavity, the liquid of the wet process flows into the pipeline cavity, which will cause cutting line corrosion, destroy the bonding layer structure and the internal circuit of the chip, and eventually lead to serious problems such as wafer cavity explosion and chip function damage.

[0007] Cutting abnormality: When discussing the use of a wafer knife to cut Si and other materials, in order to achieve a better back collapse effect, it is necessary to select a suitable tape to adhere and support the back of the material to reduce the vibration during the cutting process and the force of pulling the cutting interface material. However, the state of the cutting cavity is exactly zero support, and the rigidity of the material is completely relied on to resist the pulling and vibration of the blade. Therefore, the size of the back collapse will be very difficult to control, and may even cause the entire material layer to break during the cutting process, or cause the crack to extend to the inside of the circuit, causing the chip to fail.

[0008] In the prior art, after wafer bonding, the glue is added to the edge to make the glue flow into the cutting path cavity to achieve the purpose of support. However, it is difficult to control the extent to which the glue is added into the cutting path. Considering that the glue cannot produce obvious volatile gas, the material usually selected will not have good fluidity, so the distance it can penetrate from the edge to the inside is limited, and most of the middle area cannot be filled with glue, so the support effect is limited. Summary of the invention

[0009] One of the purposes of the present invention is to provide a wafer-level packaging method for slotted filling with supporting materials to solve the technical problem of poor support effect of saw path cavities in the prior art.

[0010] One of the objectives of the present invention is to provide a chip structure.

[0011] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a wafer-level packaging method for slot-filled support material, comprising the following steps:

[0012] A wafer-level packaging structure is provided, the wafer-level packaging structure comprising a first wafer, a second wafer, and a connecting portion bonding the first wafer and the second wafer, wherein at least a portion of adjacent connecting portions has a cutting path cavity communicating with the outside;

[0013] A through groove is formed in the wafer-level packaging structure along the thickness direction thereof, wherein the through groove is connected to the cutting path cavity along the thickness direction;

[0014] The cutting path cavity is filled with supporting material through the through groove.

[0015] As a further improvement of an embodiment of the present invention, the through groove is filled with supporting material.

[0016] As a further improvement of an embodiment of the present invention, “providing a wafer-level packaging structure” includes the steps of:

[0017] Providing a first wafer and a second wafer, wherein the first wafer is provided with a plurality of chip modules, and at least some of the chip modules have a sealing functional area exposed to a first surface of the first wafer;

[0018] forming a connection portion on the first surface surrounding at least a portion of the outer periphery of the sealing functional area;

[0019] The connection portion and the second wafer are bonded together.

[0020] As a further improvement of an embodiment of the present invention, “bonding the connection portion to the second wafer” comprises the steps of:

[0021] The connection portion and the second wafer are connected by dielectric bonding or non-dielectric bonding, and the wafer-level packaging structure includes a bonding layer arranged between the connection portion and the second wafer.

[0022] As a further improvement of an embodiment of the present invention, “forming a through groove along the thickness direction of the wafer-level packaging structure” comprises the steps of:

[0023] The second wafer is cut and / or etched to form a through groove; the through groove can be selectively formed in the second wafer, the second wafer has a substrate and a circuit layer arranged on the substrate, the connecting portion connects the first surface and the circuit layer, and the cutting path cavity corresponds to a non-functional area of ​​the circuit layer.

[0024] As a further improvement of an embodiment of the present invention, the dicing street cavities in all regions of the first wafer are filled with supporting material.

[0025] As a further improvement of an embodiment of the present invention, the method comprises the steps of: cutting corresponding cutting path cavities to form a plurality of independent chip structures.

[0026] As a further improvement of one embodiment of the present invention, the cutting road cavity includes a plurality of transverse cutting roads that penetrate horizontally, and a plurality of longitudinal cutting roads that penetrate longitudinally, wherein the transverse and longitudinal directions are horizontal and perpendicular to each other; a plurality of the transverse cutting roads are arranged along the longitudinal direction, and a plurality of the longitudinal cutting roads are arranged along the transverse direction, and the transverse cutting roads and the longitudinal cutting roads are cross-connected.

[0027] As a further improvement of one embodiment of the present invention, the through groove includes a transverse through groove arranged corresponding to the transverse cutting path and / or a longitudinal through groove arranged corresponding to the longitudinal cutting path, and supporting material is filled into the transverse cutting path through the transverse through groove, and / or supporting material is filled into the longitudinal cutting path through the longitudinal through groove.

[0028] As a further improvement of an embodiment of the present invention, the through groove has a rectangular groove and / or an inverted trapezoidal groove which are connected and arranged along the thickness direction.

[0029] As a further improvement of an embodiment of the present invention, the through slot has a first opening close to the cutting path cavity and a second opening away from the cutting path cavity, and a size of the first opening is not greater than a size of the second opening.

[0030] As a further improvement of an embodiment of the present invention, along the thickness direction close to the cutting path cavity, the opening size of the through groove has a tendency to gradually decrease.

[0031] As a further improvement of one embodiment of the present invention, the through groove has at least a first inverted trapezoidal groove and a second inverted trapezoidal groove connected along the thickness direction, and a transition plane transitionally connecting the first inverted trapezoidal groove and the second inverted trapezoidal groove, and the transition plane is perpendicular to the thickness direction.

[0032] To achieve one of the above-mentioned objects of the invention, an embodiment of the present invention provides a chip structure, using a wafer-level packaging method of a slotted filling support material as described in any one of the above items, wherein the chip structure is formed by cutting the cutting path cavity of the wafer-level packaging structure.

[0033] Compared with the prior art, the present invention provides a wafer-level packaging method with a slotted filling supporting material. After the first wafer and the second wafer are bonded together, a through slot is formed by cutting at least one of the first wafer and the second wafer, and the supporting material is filled into the cutting path cavity through the through slot to improve the supporting effect of the cutting path cavity. During the thinning and cutting process, the wafer-level packaging structure is not easily broken or damaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The present invention relates to a wafer-level packaging method for forming a chip structure in one embodiment of the present invention.

[0035] Figure 2 FIG. 4 is a schematic plan view of a first wafer in one embodiment of the present invention.

[0036] Figure 3 1 is a plan view of a wafer-level packaging structure in one embodiment of the present invention.

[0037] Figure 4 4 is a schematic cross-sectional view of a wafer-level packaging structure in one embodiment of the present invention.

[0038] Figure 5 It is a cross-sectional schematic diagram of a wafer-level packaging structure in another embodiment of the present invention.

[0039] Figure 6 Schematic diagram of a chip structure in one embodiment of the present invention.

[0040] Figure 7 It is a cross-sectional schematic diagram of a chip structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0042] It should be noted that the term "comprises" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, the terms "first", "second", "third", "fourth", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0043] The terms "connected", "connected to" or any other variants are intended to cover various relative positions in a connection relationship, so as to include direct connection or indirect connection. Among them, the direct connection can be formed by a gas pipeline, the indirect connection can be a connection relationship established by a device such as a valve body, a sensor, etc., can be a connection relationship established by a gas circuit component such as a brake control unit, or can be a connection relationship established by any other medium such as air.

[0044] See also Figure 1 , a wafer-level packaging method for slotted filling support material provided by an embodiment of the present invention comprises the steps of:

[0045] S1: Provide a wafer-level packaging structure 2000, wherein the wafer-level packaging structure 2000 includes a first wafer 100, a second wafer 200, and a connecting portion 320 bonding the first wafer 100 and the second wafer 200, and a cutting path cavity 330 communicating with the outside is provided between at least some adjacent connecting portions 320.

[0046] The first wafer 100 can be made by semiconductor manufacturing technology, for example, forming N-type metal oxide semiconductor devices and P-type metal oxide semiconductor devices on a semiconductor substrate by deposition, etching and other processes, and forming a dielectric layer, a metal interconnection structure and a pad electrically connected to the metal interconnection on the device. The first wafer 100 can be made of third-generation semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium nitride or indium gallium.

[0047] The second wafer 200 can be made by semiconductor manufacturing technology, for example, forming N-type metal oxide semiconductor devices and P-type metal oxide semiconductor devices on a semiconductor substrate by deposition, etching and other processes, and forming dielectric layers, metal interconnect structures and pads electrically connected to the metal interconnect junctions on the devices. The second wafer 200 can be: lithium tantalate, lithium niobate, silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or other compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator and germanium on insulator, or double-sided polished silicon wafer.

[0048] One end of the connecting portion 320 is formed on the first wafer 100, and the other end is bonded to the second wafer 200 to achieve the connection between the first wafer 100 and the second wafer 200; or one end of the connecting portion 320 is formed on the second wafer 200, and the other end is bonded to the first wafer 100 to achieve the connection between the first wafer 100 and the second wafer 200.

[0049] The chip structure 1000 includes a bonding layer disposed at a connection between the connecting portion 320 and the second wafer 200 .

[0050] One end of the connection portion 320 is formed on the surface of the first wafer 100, and the other end of the connection portion 320 can be bonded to the second wafer 200 by non-medium bonding, or bonded to the second wafer 200 by medium bonding. When medium bonding is used, the bonding layer can be selected as an organic glue layer or a metal layer.

[0051] Specifically, combined Figure 2 As shown, one end of the connecting portion 320 is deposited or etched on the first wafer 100, the process is simple, and the connection is stable and firm. The other end of the connecting portion 320 is bonded to the second wafer 200 through a bonding layer, thereby realizing the connection between the first wafer 100 and the second wafer 200.

[0052] “Providing a wafer-level packaging structure 2000” further includes:

[0053] S11: providing a first wafer 100 and a second wafer 200, wherein the first wafer 100 is provided with a plurality of chip modules 30, and at least part of the chip modules 30 has a sealing functional area 310 exposed to the first surface 110 of the first wafer.

[0054] The chip module 30 includes at least one chip, and the multiple chips can be chips with the same function; or, the multiple chips include at least two chips with different functions. The chip includes at least one of a logic chip, a memory chip, a central processing unit chip, a microprocessor chip, and an analog-to-digital conversion chip, or the chip includes at least one MEMS chip of a microphone, a pressure sensor, a speed sensor, an acceleration sensor, and a filter, a sensor chip that senses one of a radio frequency signal, an infrared radiation signal, a visible light signal, an acoustic wave signal, and an electromagnetic wave signal, etc.

[0055] The chip module 30 can be only arranged on the first wafer 100, the first wafer 100 is a functional wafer, and the second wafer 200 is a cover wafer; or only arranged on the second wafer 200, the second wafer 200 is a functional wafer, and the first wafer 100 is a cover wafer; or arranged on the first wafer 100 and the second wafer 200 at the same time, the first wafer 100 and the second wafer 200 are both functional wafers and form a cover for each other; in actual applications, it can be adjusted according to packaging requirements.

[0056] In a specific embodiment, combined with Figure 2-3 As shown, the first wafer 100 is provided with the chip module 30 and is a functional wafer, and the second wafer 200 is a cover wafer.

[0057] S12: forming a connection portion 320 surrounding at least a portion of the outer periphery of the sealing functional area 310 on the first surface 110. Specifically, the connection portion 320 can be formed on the first surface 110 by etching or deposition.

[0058] The connection part 320 is annular in structure, and the cutting path cavity 330 is formed between adjacent connection parts 320. The cutting path cavity 330 is crisscrossed, and the outer end of the cutting path cavity 330 is connected to the outside. In the prior art, the cutting path cavity 330 is only filled with colloid through the edge area of ​​the outer end, and the degree of filling is not controlled. When the wafer-level packaging structure 2000 is thinned or cut, the support effect of the cutting path cavity 330 is limited.

[0059] S13: Bonding the connection part 320 and the second wafer 200 to form a wafer-level packaging structure. The "bonding the connection part 320 and the second wafer 200" includes the steps of: connecting the connection part 320 and the second wafer 200 by dielectric bonding or dielectric-free bonding, and the wafer-level packaging structure 2000 includes a bonding layer disposed between the connection part 320 and the second wafer 200.

[0060] The connection portion 320 and the second wafer 200 may be bonded by dielectric bonding, including metal dielectric bonding and organic adhesive dielectric bonding. The bonding medium is selected according to the bonding method.

[0061] In a specific implementation, the bonding layer may be a bonding glue, including the steps of: applying the bonding glue at the connection portion 320 ; the bonding glue may be directly applied to the connection portion 320 , or may be applied to the area of ​​the second wafer 200 corresponding to the connection portion 320 .

[0062] One end of the connection part 320 is etched or deposited on the first wafer 100, the process is simple and the connection is stable. The other end of the connection part 320 is connected to the second wafer 200 through a bonding layer, without the need for complex pre-treatment processes, and has low requirements for bonding equipment, saving manufacturing costs.

[0063] As described above, the first wafer 100 and the second wafer 200 are first bonded together. Due to the covering of the second wafer 200 , only the outer end of the dicing path cavity 330 is connected to the outside, rather than being completely exposed to the outside.

[0064] S2: A through groove 220 is formed along the thickness direction of the wafer-level packaging structure 2000, and the through groove 220 is connected to the scribe line cavity 330 along the thickness direction. In this way, the through groove 220 for filling glue is formed by opening the first wafer 100 and / or the second wafer 200.

[0065] S3: Filling the cutting path cavity 330 with supporting material through the through slot 220 .

[0066] In a preferred embodiment, the supporting material is at least one of photoresist, epoxy resin glue, and UV glue, and the flowing colloid is convenient for filling and has viscosity. The supporting material is solidified in the cutting path cavity 330 to form the filling portion 400 .

[0067] In a preferred embodiment, supporting materials may also be filled into the through groove 330 to strengthen the support.

[0068] In a preferred embodiment, the cutting road cavity 330 includes a plurality of transverse cutting roads 331 that penetrate horizontally, and a plurality of longitudinal cutting roads 332 that penetrate longitudinally, wherein the transverse and longitudinal directions are horizontal and perpendicular to each other; a plurality of the transverse cutting roads 331 are arranged along the longitudinal direction, and a plurality of the longitudinal cutting roads 332 are arranged along the transverse direction, and the transverse cutting roads 331 and the longitudinal cutting roads 332 are cross-connected to facilitate the flow of subsequent supporting materials.

[0069] The outer ends of the cutting path cavity 330 are connected to the outside, including the two ends of the transverse cutting path 331 being connected to the outside, and the two ends of the longitudinal cutting path 332 being connected to the outside.

[0070] In a preferred embodiment, the width of the transverse cutting road 331 and / or the longitudinal cutting road 332 ranges from 40 mm to 200 mm. Theoretically, for the first wafer 100, the second wafer 200 and the chip module 30 of different sizes, the smaller the width of the cutting road cavity 330, the better, so as to reserve more space for the chip module 30. In actual packaging applications, due to the limited process level, the width of the cutting road cavity 330 cannot be made particularly small. Common widths of the cutting road cavity 330 are 80 mm and 120 mm, which ensure the appropriate width of the cutting road cavity 330 without taking up too much space of the first wafer 100.

[0071] In a preferred embodiment, the scribe line cavity 330 further includes transverse scribe lines and longitudinal scribe lines located at the periphery of the chip module 30 in the edge region.

[0072] “Making a through groove 220 along the thickness direction in the wafer packaging structure 2000” includes the following steps:

[0073] S21: Cut and / or etch the second wafer 200 to form a through groove 220. The through groove 220 can be selectively formed in the second wafer 200 to prevent affecting the chip module of the first wafer. The second wafer 200 has a substrate and a circuit layer 210 disposed on the substrate. The connecting portion 320 connects the first surface 110 and the circuit layer 210. The cutting path cavity 330 corresponds to the non-functional area of ​​the circuit layer 210 to ensure the integrity of the functional area of ​​the circuit layer 210.

[0074] Combination Figure 4-5 As shown, the second wafer 200 can be opened by etching the substrate, and then the non-functional area of ​​the circuit layer 210 corresponding to the cutting path cavity 330 can be opened by knife cutting or laser cutting to form a through groove 220. Alternatively, the second wafer 200 is marked at the corresponding cutting path cavity 330, and the substrate and the circuit layer are opened directly by knife cutting or laser cutting to form a through groove 220.

[0075] In a preferred embodiment, the through groove 220 includes a transverse through groove arranged corresponding to the transverse cutting path 331 and / or a longitudinal through groove arranged corresponding to the longitudinal cutting path 332, and supporting material is filled into the transverse cutting path 331 through the transverse through groove, and / or supporting material is filled into the longitudinal cutting path 332 through the longitudinal through groove.

[0076] In a specific embodiment, the through groove 220 includes a transverse through groove corresponding to the transverse cutting path 331 and a longitudinal through groove corresponding to the longitudinal cutting path 332. The transverse cutting path 331 and the longitudinal cutting path 332 are both opened and filled with supporting materials respectively. The glue line of the sprayed supporting material is required to be relatively thin relative to the transverse and longitudinal cutting paths and will not overflow into the transverse and longitudinal cutting path cavities.

[0077] In a specific embodiment, the through groove 220 includes a transverse through groove corresponding to the transverse cutting path 331 and a longitudinal through groove corresponding to the longitudinal cutting path 332. However, only the transverse or longitudinal cutting path is filled, and the cutting path in the other direction is filled by the fluidity of the glue. This method is used when the glue line of the support material cannot be sprayed too thin, and the transverse or longitudinal cutting path is relatively wide, so the width of the glue line can be adapted or overflow in this direction can be allowed.

[0078] In a specific embodiment, the through groove 220 includes a horizontal through groove corresponding to the horizontal cutting road 331 or a vertical through groove corresponding to the vertical cutting road 332. Due to the characteristics of the second wafer 200 or the process capability limitation, the cutting road in a certain direction cannot be opened or the opening process may easily cause damage to the second wafer 200, while the other direction is not restricted. In this case, the filling support material only fills the cutting road in one direction, and the cutting road in the other direction is filled by the fluidity of the glue.

[0079] It can be seen that the scribe line cavities 330 in all regions of the first wafer 100 are filled with support materials to provide better support. In other words, the transverse scribe lines 331 and the longitudinal scribe lines 332 in all regions are filled with support materials.

[0080] The width of the through slot 330 is smaller than the distance between two adjacent chip modules 30 . In actual processes, the width of the through slot 330 is smaller than the width of the cutting path cavity 330 .

[0081] The through groove 330 has a rectangular groove or an inverted trapezoidal groove connected along the thickness direction. The through groove 330 can be set to a single rectangle or inverted trapezoid, or a combination of at least two shapes, but it should be satisfied that the first opening size of the through groove 220 is not larger than the second opening size, which is convenient for guiding the colloid.

[0082] The through groove 220 has a first opening close to the cutting path cavity 330 and a second opening away from the cutting path cavity 330. The size of the first opening is not larger than the size of the second opening. On the other hand, the first opening corresponds to the non-functional area of ​​the circuit layer of the second wafer. The small size of the first opening can retain more functional areas of the circuit layer of the second wafer 200.

[0083] Along the thickness direction close to the cutting path cavity 330 , the opening size of the through groove 220 has a tendency to gradually decrease. Specifically, the through groove 220 is set in an inverted trapezoidal shape. The through groove 220 has an inclined surface and has the function of guiding the fluid to ensure that the colloid gradually flows into the cutting path cavity 330 .

[0084] In a preferred embodiment, the through groove 220 at least has a first inverted trapezoidal groove 221 and a second inverted trapezoidal groove 222 connected in the thickness direction, and a transition plane 223 connecting the first inverted trapezoidal groove 221 and the second inverted trapezoidal groove 222, and the transition plane 223 is perpendicular to the thickness direction. The through groove 220 is arranged as a combination of two inverted trapezoidal grooves, which is convenient for operation during actual filling and has a good guiding and gathering effect.

[0085] S4: Cutting the corresponding dicing path cavities 330 to form a plurality of independent chip structures 1000 .

[0086] The cutting path cavity 330 is the position where the first wafer 100 and the second wafer 200 are cut to form the chip structure 1000 after the first wafer 100 and the second wafer 200 are bonded. The cutting path cavity 330 achieves the effect of dividing several chip modules 30 from each other, realizes wafer-level packaging, simplifies the process flow, and improves packaging efficiency.

[0087] It is understandable that the wafer-level packaging structure 2000 may be subjected to a thinning process before being cut to form the chip structure 1000. The back side of the first wafer 100 and / or the second wafer 200 may be subjected to a thinning process to be thinned to a suitable thickness to ensure the performance of the chip module 30 in the first wafer 100 and to reduce the packaging thickness.

[0088] When cutting the cutting path cavity 330, since a filling part 400 is formed in all the cutting path cavities 330, it has better support. On the one hand, it can prevent the wafer-level packaging structure 2000 from cracking and damage during the thinning process and the cutting process; on the other hand, when the wafer-level packaging structure 2000 undergoes a wet process, the existence of the filling part 400 can prevent liquid from flowing into the cutting path cavity, which will cause corrosion of the cutting path cavity.

[0089] Combination Figure 6-7 As shown, the chip structure 1000 includes a first substrate 10, a second substrate 20, a connection layer 32, and a chip module 30 disposed on the first substrate 10. The connection layer 32 connects the first substrate 10 and the second substrate 20, and the connection layer 32 is disposed around the periphery of the sealing functional area 31. The chip structure 1000 also includes a filling structure 40 disposed around the periphery of the connection layer 32 for protecting the chip module.

[0090] The chip structure 1000 is formed by cutting the entire wafer-level packaging structure 2000, wherein the first layer substrate 10 is formed by cutting the first wafer 100, the second layer substrate 20 is formed by cutting the second wafer 200, the filling structure 40 is formed by cutting the filling part 400, and the connecting layer 32 is formed by cutting the connecting part 320. The structure of the chip module 30 itself will not be affected, and the chip structure 1000 formed by cutting includes at least one chip module 30.

[0091] The outer circumference of the filling structure 40 is located in the same plane as the outer circumferences of the first substrate 10 and the second substrate 20. In other words, the filling structure 40 constitutes part of the outer wall of the chip structure 1000 to protect the internal structure.

[0092] A filling groove 33 is formed on the first surface 301, which is equivalent to a cutting path cavity 330 formed by cutting. The filling structure 40 is filled in the filling groove 33. The connecting layer 32 and the filling structure 40 are ring-shaped. The connecting layer 32 is arranged around the periphery of the sealing functional area 31. The filling structure 40 is further arranged around the periphery of the connecting layer 32. The connecting layer 32 serves to separate the sealing functional area 31 and the filling structure 40.

[0093] The bonding layer is bonded to the connection layer 32 and the second substrate 20 , and is further sealed between the filling groove 33 and the sealing functional area 31 , thereby further preventing the filling structure 40 from entering the sealing functional area 31 and affecting the function of the chip module.

[0094] The second wafer 200 is formed with a through groove 220 , and after cutting, the second substrate 20 will form a notch 22 . Similarly, the outer wall of the notch 22 has an inclined surface, and the end of the inclined surface away from the filling structure 40 is inclined toward the sealing functional area 31 .

[0095] The filling structure 40 is usually located between the first substrate 10 and the second substrate 20 along the thickness direction. In other embodiments, the filling structure 40 also extends into the gap 22 to provide better support and protection.

[0096] The beneficial effects of the present invention are: a wafer-level packaging method for filling a groove with supporting material after bonding has a simple process and is easy to operate, and can accurately control the position of the supporting material to be filled into the cutting path cavity 330 to form a filling portion 400 with good support; the wafer-level packaging structure is not easy to be broken or damaged during the thinning and cutting process.

[0097] It can be formed by referring to any of the technical solutions provided above, and will not be described in detail here.

[0098] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0099] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wafer-level packaging method for slotted filling support material, characterized in that: The following steps are involved: A wafer-level packaging structure is provided, the wafer-level packaging structure comprising a first wafer, a second wafer, and a connecting portion bonding the first wafer and the second wafer, wherein at least a portion of adjacent connecting portions has a cutting path cavity communicating with the outside; A through groove is formed in the wafer-level packaging structure along the thickness direction thereof, wherein the through groove is connected to the cutting path cavity along the thickness direction; The cutting path cavity is filled with supporting material through the through groove.

2. The wafer-level packaging method of claim 1, wherein: The through slot is filled with a supporting material.

3. The wafer-level packaging method of claim 1, wherein: "Providing a wafer level packaging structure" includes the steps of: Providing a first wafer and a second wafer, wherein the first wafer is provided with a plurality of chip modules, and at least some of the chip modules have a sealing functional area exposed to a first surface of the first wafer; forming a connection portion on the first surface surrounding at least a portion of the outer periphery of the sealing functional area; The connection portion and the second wafer are bonded together.

4. The wafer-level packaging method of claim 3, wherein: “Bonding the connection portion to the second wafer” comprises the steps of: The connection portion and the second wafer are connected by dielectric bonding or non-dielectric bonding, and the wafer-level packaging structure includes a bonding layer arranged between the connection portion and the second wafer.

5. The wafer-level packaging method of claim 1, wherein: “Making a through groove along the thickness direction in the wafer packaging structure” comprises the steps of: The second wafer is cut and / or etched to form a through groove; the through groove can be selectively formed in the second wafer, the second wafer has a substrate and a circuit layer arranged on the substrate, the connecting portion connects the first surface and the circuit layer, and the cutting path cavity corresponds to a non-functional area of ​​the circuit layer.

6. The wafer-level packaging method of claim 1, wherein: The scribe line cavities in all regions of the first wafer are filled with supporting material.

7. The wafer-level packaging method of claim 1, wherein: The method comprises the steps of: cutting the corresponding cutting path cavities to form a plurality of independent chip structures.

8. The wafer-level packaging method of claim 1, wherein: The cutting road cavity includes a plurality of transverse cutting roads that penetrate the wafer transversely, and a plurality of longitudinal cutting roads that penetrate the wafer longitudinally, wherein the transverse and longitudinal directions are horizontal and perpendicular to each other; a plurality of the transverse cutting roads are arranged along the longitudinal direction, and a plurality of the longitudinal cutting roads are arranged along the transverse direction, and the transverse cutting roads and the longitudinal cutting roads are cross-connected.

9. The wafer-level packaging method of claim 8, wherein: The through grooves include transverse through grooves arranged corresponding to the transverse cutting paths and / or longitudinal through grooves arranged corresponding to the longitudinal cutting paths, and the transverse cutting paths are filled with supporting material through the transverse through grooves and / or the longitudinal cutting paths are filled with supporting material through the longitudinal through grooves.

10. The wafer-level packaging method of claim 1, wherein: The through groove comprises a rectangular groove and / or an inverted trapezoidal groove which are connected and arranged along the thickness direction.

11. The wafer-level packaging method of claim 10, wherein: The through slot has a first opening close to the cutting path cavity and a second opening away from the cutting path cavity, and a size of the first opening is not greater than a size of the second opening.

12. The wafer-level packaging method of claim 10, wherein: Along the thickness direction close to the cutting path cavity, the opening size of the through slot has a tendency to gradually decrease.

13. The wafer-level packaging method of claim 10, wherein: The through groove at least comprises a first inverted trapezoidal groove and a second inverted trapezoidal groove connected in a thickness direction, and a transition plane connecting the first inverted trapezoidal groove and the second inverted trapezoidal groove, wherein the transition plane is perpendicular to the thickness direction.

14. A chip structure, using a wafer-level packaging method of the slotted filling support material according to any one of claims 1 to 13, characterized in that: The chip structure is formed by cutting the scribe line cavity through the wafer-level packaging structure.

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