Wafer level packaging method and chip structure

Abstract

The invention discloses a wafer-level packaging method and a chip structure, and the method comprises the following steps: providing a first wafer, manufacturing a supporting dam on the first wafer, and enabling the supporting dam to comprise a first supporting dam and a second supporting dam; providing a second wafer, wherein the second wafer comprises a first welding pad area; the first supporting dam is connected with the second supporting dam and a second wafer, the first supporting dam covers the first welding pad area, and the first supporting dam and the first welding pad area are mutually disconnected; cutting the first wafer along the first cutting channel, and removing the first supporting dam and the first wafer connected with the first supporting dam; damage to the first welding pad area in the packaging process is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging and testing, and in particular to a wafer-level packaging method and a chip structure. Background Art

[0002] In the prior art, a wafer-level packaging structure generally includes a transparent cover plate, a device wafer, and a support dam structure connecting the transparent cover plate and the device wafer. In order to reduce the impact on the solder pad area on the device wafer, the support dam structure is generally arranged away from the solder pad area, and the solder pad area is exposed between the transparent cover plate and the device wafer. Thus, the solder pad area may be damaged when the transparent cover plate is cut.

[0003] In the prior art, the support dam structure can also cover and connect to the solder pad area. After the transparent cover is cut, the support dam at the corresponding solder pad area is removed by etching to expose the solder pad area. In this way, the solution may also cause damage to the solder pad area during the etching process. Summary of the invention

[0004] One of the purposes of the present invention is to provide a wafer-level packaging method to solve the technical problem of damage to the pad area in the prior art.

[0005] One of the objectives of the present invention is to provide a chip structure.

[0006] To achieve one of the above-mentioned objects of the invention, an embodiment of the present invention provides a wafer-level packaging method, comprising: providing a first wafer, and manufacturing a support dam on the first wafer, wherein the support dam comprises a first support dam and a second support dam;

[0007] Providing a second wafer, wherein the second wafer includes a first pad area;

[0008] connecting the second support dam and the second wafer, wherein the first support dam covers the first pad area, and the first support dam and the first pad area are disconnected from each other;

[0009] The first wafer is cut along the first cutting line to remove the first support dam and the first wafer connected to the first support dam.

[0010] As a further improvement of an embodiment of the present invention, “fabricating a support dam on the first wafer” includes:

[0011] The support dam is formed by coating a photoresist on the surface of the first wafer and patterning the photoresist, or the support dam is formed on the surface of the first wafer by 3D printing.

[0012] As a further improvement of an embodiment of the present invention, “connecting the second support dam and the second wafer” includes:

[0013] Adhesive is applied only on the second supporting dam by screen printing, and the first wafer and the second wafer are pressed together.

[0014] As a further improvement of one embodiment of the present invention, the second wafer includes a functional area, the first pad area is arranged outside the functional area, the second support dam is surrounded by the outside of the functional area and is located between the functional area and the first pad area, and the first support dam is located outside the second support dam.

[0015] As a further improvement of an embodiment of the present invention, the first supporting dam and the second supporting dam are arranged at intervals.

[0016] As a further improvement of an embodiment of the present invention, the first cutting road is located in a region between the first supporting dam and the second supporting dam corresponding to the first wafer.

[0017] As a further improvement of an embodiment of the present invention, the method comprises the steps of: cutting the second wafer along a second cutting path to form a single chip structure.

[0018] As a further improvement of an embodiment of the present invention, the second cutting road is located in a region between the first adjacent pad regions of the second wafer.

[0019] As a further improvement of an embodiment of the present invention, “cutting the first wafer along a first cutting path” includes: cutting through the first wafer by knife cutting or laser cutting;

[0020] “Cutting the second wafer along the second scribe line” includes: cutting with a knife, cutting with a laser or etching to cut through the second wafer.

[0021] As a further improvement of one embodiment of the present invention, the steps are as follows:

[0022] Providing a substrate, and placing the chip structure on the substrate;

[0023] electrically connecting the substrate and the chip structure;

[0024] The substrate and chip structure are plastic-sealed.

[0025] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a chip structure, which is manufactured using the wafer-level packaging method in any of the above-mentioned technical solutions, and the chip structure includes a first base layer, a second base layer and a support dam connecting the first base layer and the second base layer, wherein the first base layer is formed by cutting a first wafer, and the second base layer is formed by cutting a second wafer.

[0026] Compared with the prior art, the present invention provides a wafer-level packaging method, wherein a first support dam covers a first pad area and can protect the first pad area when the first wafer is cut; the first support dam is disconnected from the first pad area, and after the first wafer is cut, the first support dam and the first wafer connected to the first support dam can be removed to expose the first pad area, without the need for additional processing steps, and the first pad area is protected from damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of a first wafer and a support dam in one embodiment of the present invention.

[0028] Figure 2 is a schematic diagram of a second wafer in one embodiment of the present invention.

[0029] Figure 3 yes Figure 1 Cross-sectional view along AA direction.

[0030] Figure 4 yes Figure 2 Cross-sectional view along direction BB.

[0031] Figure 5 It is a schematic diagram of supporting dam coating glue in one embodiment of the present invention.

[0032] Figure 6 Schematic diagram of bonding a first wafer and a second wafer in one embodiment of the present invention.

[0033] Figure 7 Schematic diagram of cutting a first wafer in one embodiment of the present invention.

[0034] Figure 8 is a schematic diagram of cutting a first wafer in another embodiment of the present invention.

[0035] Fig. 9 It is a schematic diagram after removing the first supporting dam in one embodiment of the present invention.

[0036] Fig.10 Schematic diagram of cutting the second wafer in one embodiment of the present invention.

[0037] Fig.11 Schematic diagram of a chip structure and a substrate in one embodiment of the present invention.

[0038] Fig.12 It is a schematic diagram of the chip structure and the substrate completing plastic packaging in one embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0040] It should be noted that the term "comprises" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, the terms "first", "second", "third", "fourth", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0041] The terms "connected", "connected to" or any other variants are intended to cover various relative positions in a connection relationship, so as to include direct connection or indirect connection. Among them, the direct connection can be formed by a gas pipeline, the indirect connection can be a connection relationship established by a device such as a valve body, a sensor, etc., can be a connection relationship established by a gas circuit component such as a brake control unit, or can be a connection relationship established by any other medium such as air.

[0042] See also Figure 1-2 , is a schematic diagram of a first wafer 100 and a second wafer 200 provided in an embodiment of the present invention. The present invention provides a wafer-level packaging method for the first wafer 100 and the second wafer 200.

[0043] The wafer-level packaging method comprises the steps of:

[0044] S1 : providing a first wafer 100 , and manufacturing a support dam 300 on the first wafer 100 , wherein the support dam 300 includes a first support dam 310 and a second support dam 320 .

[0045] The “fabrication of the support dam 300” includes: coating a photoresist on the surface of the first wafer 100 and patterning the photoresist to form the support dam 300. The “patterning the photoresist” includes: using a mask plate to perform exposure and development, removing part of the photoresist, retaining the photoresist actually needed, and forming the support dam 300.

[0046] Alternatively, “making the support dam 300” includes: forming the support dam 300 on the surface of the first wafer 100 by 3D printing. The operator can directly print and form the support dam 300 according to actual needs, and the process is simple.

[0047] In actual production, any of the above methods can be selected to produce the support dam 300 as needed. Figure 3 The first wafer 100 is a wafer-level transparent cover plate, the support dam 300 is made of an organic material and is formed on one surface of the first wafer 100 , and the shape of the support dam 300 is formed and manufactured according to actual needs.

[0048] S2: providing a second wafer 200, wherein the second wafer 200 comprises a first pad area 210 and a functional area 220, wherein the first pad area 210 is disposed outside the functional area 220,

[0049] In a specific embodiment, combined with Figure 4 As shown, the second wafer 200 is a device wafer, which has a plurality of functional devices and metal interconnects to form a functional area 220. The first pad area 210 is electrically connected to the functional area 220 and is also used to electrically connect to an external circuit. In other embodiments, the first pad area 210 and the functional area 220 can be located on opposite surfaces of the second wafer 200.

[0050] S3: Connect the second support dam 320 and the second wafer 200, the first support dam 310 covers the first pad area 210, and the first support dam 310 and the first pad area 210 are disconnected from each other. Figure 6 , which is equivalent to bonding the first wafer 100 and the second wafer 200,

[0051] The second support dam 320 is disposed outside the functional area 220 and between the functional area 220 and the first pad area 210 . The first support dam 310 is located outside the second support dam 320 .

[0052] Specifically, the second support dam 320 is annular to seal the functional area 220, and the first support dam 310 is located outside the second support dam 320. The first support dam 310 only covers the first solder pad area 210 but is not used to connect the first solder pad area 210. On the one hand, the first support dam 310 can shield and protect the first solder pad area 210 when cutting the first wafer 100. On the other hand, after cutting the first wafer 100, the first support dam 310 is easy to remove and is also used to protect the first solder pad area 210.

[0053] In a preferred embodiment, the first support dam 310 and the second support dam 320 are spaced apart from each other, and the area between the first support dam 310 and the second support dam 320 is an area for cutting to facilitate subsequent cutting.

[0054] The step of “connecting the second support dam 320 and the second wafer 200 ” includes: applying adhesive only on the second support dam 320 by screen printing, and pressing the first wafer 100 and the second wafer 200 together.

[0055] Combination Figure 5-6 As shown, during screen printing, the second support dam 320 is coated with adhesive, while the first support dam 310 is not coated with adhesive. In this way, after the first wafer 100 and the second wafer 200 are pressed together, the second support dam 320 is connected to the surface of the second wafer 200 through the adhesive, while the first support dam 310 only covers the surface of the second wafer 200.

[0056] S4 : cutting the first wafer 100 along the first scribe line 110 , and removing the first support dam 310 and the first wafer 100 connected to the first support dam 310 .

[0057] In a preferred embodiment, “cutting the first wafer 100 along the first cutting street 110 ” includes: cutting through the first wafer 100 by knife cutting or laser cutting.

[0058] Specifically, the first wafer 100 is a transparent cover plate, and the knife cutting method is that a circular rotary tool rotates at high speed and moves along the first cutting path 110 while rotating to cut through the first wafer 100 .

[0059] Combination Figure 7 As shown, the first cutting road 110 is located in the area between the first support dam 310 and the second support dam 320 of the first wafer 100. In this step, the surface of the second wafer 200 cannot be cut when cutting the first wafer 100. Therefore, the first support dam 310 and the second support dam 320 are arranged at intervals, and the area between the first support dam 310 and the second support dam 320 is empty, and it is only necessary to cut through the first wafer 100. The first support dam 310 covers and protects the first pad area 210, and knife cutting or laser cutting will not affect the first pad area 210.

[0060] In a preferred embodiment, the first cutting lanes 110 should be arranged in a horizontal and vertical cross pattern. After the first wafer 100 is cut, the first support dam 310 area corresponding to the first wafer 100 is disconnected from the second support dam 320 area corresponding to the first wafer 100. Since the first support dam 310 is not connected to the second wafer 200, the area corresponding to the first support dam 310 can be directly removed, thereby exposing the first pad area 210. Fig. 9 In this step, there is no need to further use etching or other methods to remove the first support dam 310 , thereby reducing the impact on the first pad area 210 .

[0061] In a preferred embodiment, the first support dam 310 simultaneously covers at least two adjacent first pad areas 210. In other words, the first support dam 310 covering two adjacent first pad areas 210 is connected as one. Figure 7In other embodiments, at least two first pad regions 210 may correspond to at least two first support dams 310, respectively. In other words, the first support dams 310 covering two adjacent first pad regions 210 are also spaced apart. Figure 8 In the process of forming the support dam 300 , different patterning operations may be performed as required to obtain an integrated first support dam 310 or separate first support dams 310 .

[0062] S5: cutting the second wafer 200 along the second dicing streets 230 to form a single chip structure.

[0063] In a preferred embodiment, “cutting the second wafer 200 along the second cutting street 230 ” includes: cutting with a knife, cutting with a laser or etching to cut through the second wafer 200 .

[0064] In a preferred embodiment, the second wafer 200 is a device wafer, and the first wafer 100 and the second wafer 200 are cut twice respectively, which can better protect the second wafer 200. Specifically, in the actual packaging process, after the first wafer 100 and the second wafer 200 are bonded and connected, there will be a cavity that crosses horizontally and vertically between the two. If the first wafer 100 and the second wafer 200 are cut at the same time, due to the existence of the cavity, cracks may be caused after the second wafer 200 is cut, and even the normal function of the chip structure may be affected.

[0065] Combination Fig.10 As shown, the second dicing lanes 230 are located between the first pad regions 210 corresponding to the adjacent first pad regions 210 of the second wafer 200 so as to cut and separate the adjacent chip structures 10 .

[0066] The present invention also protects a single chip structure 10, which is manufactured using the above-mentioned wafer-level packaging method. The chip structure 10 includes a first base layer 11, a second base layer 12, and a support dam 300 connecting the first base layer 11 and the second base layer 12. The first base layer 11 is formed by cutting the first wafer 100, and the second base layer 12 is formed by cutting the second wafer 200. The second base layer 12 includes the functional area 220 and the first pad area 210. The support dam 300 is more specifically the second support dam 320. Figure 11-12 As shown, the cut chip structure is further packaged.

[0067] S6: providing a substrate 400, placing the chip structure 10 on the substrate 400, and fixing the back surface of the second base layer 12 to the substrate 400 via an adhesive layer.

[0068] The substrate 400 and the chip structure 10 are electrically connected, and a lead wire connects the substrate 400 and the first pad area 210; a second pad area 410 is set on the first surface of the substrate 400, and the chip structure 10 is set on the first surface, and the wire connects the first pad area 210 and the second pad area 410 to achieve electrical connection between the chip structure 10 and the substrate 400.

[0069] In other embodiments, a through hole may be opened on the back side of the second base layer 12, an electrical connection column may be formed in the through hole, a solder ball connected to the electrical connection column may be arranged on the back side of the second base layer 12, and the solder ball may be welded to the substrate 400 to realize electrical connection between the chip structure 10 and the substrate 400.

[0070] The substrate 400 and the chip structure 10 are plastic-sealed, and a plastic-sealing material is filled on the first surface of the substrate 400. The plastic-sealing material covers the first pad area 210 and the second pad area 410. The plastic-sealing material can be a polymer composite material such as epoxy resin, polyimide, dry film, etc. The plastic-sealing material is formed into a plastic-sealing layer, and the plastic-sealing layer is polished to be flush with the surface of the first base layer 11 away from the second base layer 12. The plastic-sealing material provides physical support for the chip structure 10 and plays a sealing and protective role for the chip structure 10 and the substrate 400.

[0071] The beneficial effects of the present invention are: the support dam 300 includes the first support dam 310 covering the first solder pad area 210, which can protect the first solder pad area 210 when cutting the first wafer 100; in the process of connecting the support dam 300 and the second wafer 200, the first support dam 310 is not coated with glue, and only the second support dam 320 is coated with glue; in this way, the first support dam 310 is not connected to the first solder pad area 210, and after cutting the first wafer 100, the first support dam 310 can be directly removed to expose the first solder pad area 210, without the need for additional processing, and the first solder pad area 210 is protected from damage by processes such as etching.

[0072] It can be formed by referring to any of the technical solutions provided above, and will not be described in detail here.

[0073] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0074] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wafer-level packaging method, characterized in that: The following steps are involved: Providing a first wafer, and manufacturing support dams on the first wafer, wherein the support dams include a first support dam and a second support dam; Providing a second wafer, wherein the second wafer includes a first pad area; connecting the second support dam and the second wafer, wherein the first support dam covers the first pad area, and the first support dam and the first pad area are disconnected from each other; The first wafer is cut along the first cutting line to remove the first support dam and the first wafer connected to the first support dam.

2. The wafer-level packaging method according to claim 1, characterized in that: "Making a support dam on the first wafer" includes: The support dam is formed by coating a photoresist on the surface of the first wafer and patterning the photoresist, or the support dam is formed on the surface of the first wafer by 3D printing.

3. The wafer-level packaging method according to claim 1, characterized in that: “Connecting the second support dam and the second wafer” includes: Adhesive is applied only on the second supporting dam by screen printing, and the first wafer and the second wafer are pressed together.

4. The wafer-level packaging method according to claim 1, characterized in that: The second wafer includes a functional area, the first pad area is arranged outside the functional area, the second support dam is surrounded outside the functional area and located between the functional area and the first pad area, and the first support dam is located outside the second support dam.

5. The wafer-level packaging method according to claim 4, characterized in that: The first supporting dam and the second supporting dam are arranged at an interval.

6. The wafer-level packaging method according to claim 4, characterized in that: The first scribe line is located in a region of the first wafer corresponding to the first supporting dam and the second supporting dam.

7. The wafer-level packaging method according to claim 1, characterized in that: Includes steps: The second wafer is cut along second dicing streets to form a single chip structure.

8. The wafer-level packaging method according to claim 7, characterized in that: The second scribe line is located between the first pad areas adjacent to each other on the second wafer.

9. The wafer-level packaging method according to claim 7, characterized in that: “Cutting the first wafer along a first scribe line” includes: cutting with a knife or cutting with a laser to cut through the first wafer; “Cutting the second wafer along the second cutting path” includes: knife cutting, laser cutting or etching to cut through the second wafer.

10. The wafer-level packaging method according to claim 7, characterized in that: Providing a substrate, and placing the chip structure on the substrate; electrically connecting the substrate and the chip structure; The substrate and chip structure are plastic-sealed.

11. A chip structure manufactured using the wafer-level packaging method according to any one of claims 1 to 10, characterized in that: The invention comprises a first base layer, a second base layer and a support dam connecting the first base layer and the second base layer, wherein the first base layer is formed by cutting a first wafer, and the second base layer is formed by cutting a second wafer.

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