Heat dissipation in stacked memory devices and associated systems and methods

Abstract

The invention relates to heat dissipation in stacked memory devices and associated systems and methods. High bandwidth memory (HBM) devices and associated systems and methods are disclosed herein. In some embodiments, the HBM device includes a first die, a plurality of second dies carried by a signal routing region of the first die, and an active through substrate via (TSV) positioned within an footprint of the signal routing region. The active TSV extends from a first metallization layer in the first die to a second metallization layer in an uppermost memory die. The HBM device also includes a cooling network configured to deliver heat from the first die. For example, the cooling network can include a thermally conductive layer carried by a hot zone of the first die and a cooling TSV in contact with the thermally conductive layer. The thermally conductive TSV extends from the thermally conductive layer to a height at or above a top surface of the uppermost memory die.

Description

Technical Field

[0001] The present technology relates generally to vertically stacked semiconductor devices, and more particularly, to systems and methods for heat dissipation in stacked semiconductor devices. Background Art

[0002] Microelectronic devices, such as memory devices, microprocessors, and other electronic devices, typically include one or more semiconductor dies mounted to a substrate and enclosed in a protective cover. The semiconductor die includes functional features, such as memory cells, processor circuits, imager devices, interconnect circuitry, etc. To meet the demand for ever-decreasing sizes, wafers, individual semiconductor dies, and / or active components are typically manufactured in batches, singulated, and then stacked on an interposer and / or a supporting substrate, such as a printed circuit board (PCB) or other suitable substrate. The stacked dies can then be coupled to an interposer and / or the supporting substrate by bonding wires in a shingled stack of dies (e.g., dies stacked with an offset for each die) and / or by through-substrate vias (TSVs) between the dies and a supporting substrate (sometimes also referred to as a package substrate). Summary of the invention

[0003] One aspect of the present disclosure discloses a high bandwidth memory (HBM) device, comprising: a first die having an upper surface, a signal routing area, and a thermal zone; a plurality of second dies carried by the upper surface of the first die, the plurality of second dies including a topmost die; one or more active through substrate vias (TSVs) positioned within a footprint of the signal routing area and extending from a first metallization layer in the first die to a second metallization layer in the topmost die; and a cooling network configured to transport heat away from the first die, the cooling network comprising: a thermally conductive layer carried by the upper surface of the first die above the thermal zone; and one or more cooling TSVs in contact with the thermally conductive layer and extending from the thermally conductive layer to a height at or above a top surface of the topmost die.

[0004] Another aspect of the present disclosure discloses a system-in-package (SiP) device, comprising: an interposer substrate; a processing unit carried by the interposer substrate; and a high bandwidth memory (HBM) device carried by the interposer substrate, wherein the HBM device is coupled to the processing unit via an interposer bus, and wherein the HBM device comprises: an interface die carried by the interposer substrate; a plurality of memory dies carried by the interface die; a plurality of first through-substrate vias (TSVs) communicatively coupling each of the plurality of memory dies with the interface die; and a cooling network configured to transport heat away from the interface die, wherein the cooling network comprises: a thermally conductive layer thermally coupled to and carried by an upper surface of the interface die; and a plurality of second TSVs thermally coupled to the conductive layer and extending from the conductive layer to a height at or above a top surface of an uppermost memory die.

[0005] Another aspect of the present disclosure discloses a stacked semiconductor device comprising: an interface die having an active signal routing area and an active circuit area; a plurality of memory dies carried by an upper surface of the interface die, wherein each of the plurality of memory dies is communicatively coupled to the interface die through a plurality of signal through substrate vias (TSVs) extending from a first metallization layer in the active signal routing area of ​​the interface die to a second metallization layer in an uppermost memory die; a cooling layer carried by the upper surface of the interface die over at least a portion of the active circuit area; and a plurality of cooling TSVs, each having a proximal region thermally coupled to the cooling layer at a contact point and a distal region at a height parallel to a top surface of the uppermost memory die or above the top surface, wherein: the cooling layer is configured to transfer heat in a lateral direction toward the contact point, and the plurality of cooling TSVs are configured to transfer heat in an upward direction away from the cooling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram illustrating an environment incorporating a high bandwidth memory architecture.

[0007] Figure 2 is a partially schematic cross-sectional view of a system-in-package device configured in accordance with some embodiments of the present technology.

[0008] Figure 3 is a partially schematic cross-sectional diagram of a portion of a high bandwidth memory device configured in accordance with some embodiments of the present technology.

[0009] Figure 4 is a partially schematic cross-sectional view of a system-in-package device configured in accordance with further embodiments of the present technology.

[0010] Figure 5A and5B Partial schematic top views of an interface die and an uppermost memory die, respectively, from a high bandwidth memory device configured in accordance with some embodiments of the present technology.

[0011] Figure 6 is a partially schematic cross-sectional view of a system-in-package device configured in accordance with further embodiments of the present technology.

[0012] The drawings are not necessarily drawn to scale. In addition, it will be understood that some of the drawings have been drawn schematically and / or partially schematically. Similarly, for the purpose of discussing some embodiments of the present technology, some components and / or operations may be separated into different blocks or combined into a single block. In addition, although the present technology may have various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail below. However, it is not intended to limit the present technology to the specific embodiments described. DETAILED DESCRIPTION

[0013] High data reliability, high-speed memory access, low power consumption, and reduced chip size are features required of semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by vertically stacking memory dies and interconnecting the dies using through-silicon (or through-substrate) vias (TSVs). The benefits of 3D memory devices include shorter interconnects (which reduce circuit delays and power consumption), a large number of vertical pathways between layers (which allow wide bandwidth buses between functional blocks (such as memory dies) in different layers), and a relatively small footprint. Therefore, 3D memory devices contribute to higher memory access speeds, lower power consumption, and a reduction in chip size. Example 3D memory devices include hybrid memory cubes (HMCs) and high-bandwidth memories (HBMs). For example, HBM is a type of memory that includes a vertical stack of dynamic random access memory (DRAM) dies and interface dies (which, for example, provide an interface between the DRAM dies of the HBM device and a host device).

[0014] In a system-in-package (SiP) configuration, the HBM device can be integrated with a host device (e.g., a graphics processing unit (GPU) and / or a computer processing unit (CPU)) using a base substrate (e.g., a silicon interposer that provides interconnection between the GPU / CPU and the HBM device and / or provides mechanical support for components of the SiP device, an organic material substrate, an inorganic material substrate, and / or any other suitable material), through which the HBM device and the host communicate. Because the traffic between the HBM device and the host device resides within the SiP (e.g., using signals routed through the silicon interposer), a higher bandwidth can be achieved between the HBM device and the host device than in conventional systems. In other words, the TSVs that interconnect the DRAM dies within the HBM device and the silicon interposer that integrates the HBM device and the host device enable routing of a larger number of signals (e.g., a wider data bus) than is typically found between a packaged memory device and a host device (e.g., through a printed circuit board (PCB)). The high-bandwidth interface within the SiP enables large amounts of data to be quickly moved between the host device (e.g., GPU / CPU) and the HBM device during operation. For example, the high bandwidth channel may be on the order of 1000 gigabytes per second (GB / s, sometimes also referred to as gigabits (Gb)). It will be appreciated that such high bandwidth data transfer between the GPU / CPU and the memory of the HBM device may be advantageous in various high performance computing applications (e.g., video rendering, high resolution graphics applications, artificial intelligence and / or machine learning (AI / ML) computing systems, and other complex computing systems) and / or various other computing applications.

[0015] However, HBM devices may present certain challenges. One such challenge is that the vertically stacked arrangement of HBM devices may make it difficult to dissipate heat from components of the HBM device (e.g., DRAM dies and / or interface dies). For example, the interface die of an HBM device typically has the highest power density of the devices within the HBM device (due to its operating speed), but is typically arranged at the bottom of the HBM device and farthest from conventional cooling media. Therefore, there is a risk that the interface die may suffer from inadequate cooling. Therefore, described herein are systems and associated methods for improving heat dissipation within vertically stacked memory devices (e.g., HBM devices).

[0016] Figure 1 is a schematic diagram illustrating an environment 100 incorporating a high bandwidth memory architecture. Figure 1 As illustrated in FIG. 1 , environment 100 includes a SiP device 110 having one or more processing devices 120 ( 120 ) integrated with a silicon interposer 112 (or any other suitable base substrate). Figure 1 , sometimes referred to herein as one or more "hosts") and one or more HBM devices 130 ( Figure 11 ). The environment 100 additionally includes a storage device 140 coupled to the SiP device 110. The processing device(s) 120 may include one or more CPUs and / or one or more GPUs (referred to as processing units 122), each of which may include registers 124 and a level 1 cache 126. The level 1 cache 126 (also referred to herein as "L1 cache") is communicatively coupled to a level 2 cache 128 (also referred to herein as "L2 cache") via a first communication path 152. In the illustrated embodiment, the L2 cache 128 is incorporated into the processing device(s) 120. However, it will be understood that the L2 cache 128 may be integrated into the SiP device 110 separately from the processing device(s) 120. By way of example only, the processing device(s) 120 may be adjacent to the L2 cache 128 and carried by a base substrate (e.g., silicon interposer 112, a packaging substrate carrying silicon interposer 112, another suitable organic substrate, an inorganic substrate, and / or any other suitable material) via one or more signal lines (or other suitable signal routing lines) in the base substrate in communication with the L2 cache 128. The L2 cache 128 may be shared by one or more of the processing devices 120 (and the processing units 122 therein). During operation of the SiP device 110, the processing unit 122 may use the registers 124 and the L1 cache 126 to complete processing operations, and attempt to retrieve data from the larger L2 cache 128 whenever a cache miss occurs in the L1 cache 126. Thus, the multi-level cache may help speed up the average time it takes the processing device(s) 120 to access data, thereby speeding up the overall processing rate.

[0017] like Figure 1 As further described in the accompanying drawings, the L2 cache 128 is communicatively coupled to the (several) HBM devices 130 via a second communication channel 154. As described, the (several) processing devices 120 and the (several) HBM devices 130 are carried by the silicon interposer 112 and electrically coupled (e.g., integrated by the silicon interposer 112). The second communication channel 154 is provided by the silicon interposer 112 (e.g., the silicon interposer includes and routes interface signals to form a second communication channel, such as through one or more redistribution layers (RDLs)). Figure 11, the L2 cache 128 is also communicatively coupled to the memory device 140 via a third communication channel 156. As illustrated, the memory device 140 is outside of the SiP device 110 and utilizes signal routing components that are not included within the silicon interposer 112 (e.g., between the packaged SiP device 110 and the packaged memory device 140). For example, the third communication channel 156 may be a peripheral bus used to connect components on a motherboard or PCB, such as a peripheral component interconnect express (PCIe) bus. Thus, during operation of the SiP device 110, the processing device(s) 120 may read data from and / or write data to the HBM device(s) 130 and / or the memory device 140 via the L2 cache 128.

[0018] In the illustrated environment 100, the HBM device 130 includes an interface die 132 coupled to a second communication channel 154 and one or more stacked memory dies 134 (e.g., DRAM dies, Figure 1 110). As explained above, the (several) HBM devices 130 may be located on the silicon interposer 112, and the (several) processing devices 120 are also located on the silicon interposer 112. Thus, the second communication channel 154 may provide a high bandwidth (e.g., on the order of 1000 GB / s) channel through the silicon interposer 112. In addition, as explained above, each HBM device 130 may provide a high bandwidth channel (not shown) between the interface die 132 and / or the memory die 134 therein. Thus, data may be transferred at high speed between the (several) processing devices 120 and the (several) HBM devices 130 (and their components), which is advantageous for data-intensive processing operations. By way of example only, the interface die 132 may be a logic die that receives various read / write requests from the (several) processing devices 120, reads / writes the memory die 134 in response to the requests, performs any necessary processing, and responds to the (several) processing devices 120. During each read / write operation, the SiP device 110 uses a high-bandwidth communication channel, allowing the read / write request to be delivered and responded to in milliseconds (e.g., in real time). Although the (several) HBM devices 130 of the SiP device 110 provide relatively high-bandwidth communication as described above, integrating a large number of memory and / or processing devices on the silicon interposer 112 is associated with various disadvantages.

[0019] For example, increasing the number of memory dies 134 included in the HBM device(s) 130 may increase the memory capacity available on the SiP device 110 via the high-bandwidth communication path. However, as the number of memory dies 134 increases, the signal routing and / or processing functionality of the interface die 132 also increases, thereby increasing the heat generated within the HBM device 130. Furthermore, the increase in the number of memory dies 134 positions the interface die 132 further away from temperature control features external to the HBM device 130 and / or thermally isolates the interface die 132 within the HBM device 130. As a result, the temperature in the HBM device 130 may increase, thereby causing deleterious effects in the interface die 132 and / or the memory die 134.

[0020] Disclosed herein are HBM devices and associated systems and methods that address the shortcomings discussed above. For example, an HBM device may include a first die (e.g., an interface die), a plurality of second dies (e.g., memory dies) carried by an active signal routing area of ​​the first die, and one or more active through-substrate vias (TSVs) positioned within the footprint of the active signal routing area. The active TSVs extend from a first metallization layer in the first die to a second metallization layer in the uppermost memory die. The HBM device also includes a cooling network configured to transport heat from the first die. For example, the cooling network may include a thermally conductive layer carried by a hot zone of the first die and one or more cooling TSVs in contact with the thermally conductive layer of the first die. The thermally conductive TSVs extend from the thermally conductive layer of the first die to a height at or above the upper surface of the second die (e.g., the uppermost memory die). The thermally conductive layer (also sometimes referred to herein as a "cooling layer") can transport heat longitudinally across the top surface of the first die toward a point of contact with the thermally conductive TSVs (also sometimes referred to herein as "cooling TSVs"), which then transport heat in an upward direction from the first die. Thus, the thermally conductive layer allows the cooling network to transport heat from a relatively large surface area of ​​the first die (e.g., compared to a cooling network that includes only thermal TSVs).

[0021] In some embodiments, the cooling network further includes a cooling element carried by the upper surface of the top memory die. For example, the cooling network may include a second thermally conductive layer formed on the upper surface of the top memory die and / or an additional die carried by the upper surface of the top memory die, with the second cooling layer formed on the upper surface of the top memory die. The second cooling layer may dissipate heat from the hot TSVs in a longitudinal direction above the top memory die and / or the additional die, and increase the surface area from which heat may be removed from the HBM device (e.g., by airflow, another cooling system, and / or the like). Thus, the second cooling layer may further increase the efficacy of the cooling network.

[0022] Additional details regarding systems and methods for heat dissipation in vertically stacked memory devices (e.g., HBM devices) are set forth below. For ease of reference, semiconductor systems (and their components) are sometimes described herein with reference to front and back, top and bottom, up and down, upward and downward, and / or horizontal planes, xy planes, vertical or z directions relative to the spatial orientation of the embodiments shown in the figures. However, it should be understood that semiconductor systems (and their components) can be moved to and used in different spatial orientations without changing the structure and / or functionality of the disclosed embodiments of the present technology.

[0023] Furthermore, although the semiconductor systems disclosed herein are primarily discussed in the context of heat dissipation in HBM devices, those skilled in the art will appreciate that the scope of the present technology is not limited thereto. For example, the systems and methods disclosed herein may also be deployed to dissipate heat in various other stacked semiconductor environments, such as various other components of a SiP, other semiconductor die stacks, and the like.

[0024] Figure 2 is a partially schematic cross-sectional view of a SiP device 200 configured in accordance with some embodiments of the present technology. Figure 2 , the SiP device 200 may include a base substrate 210 (e.g., a silicon interposer, another organic interposer, an inorganic interposer, and / or any other suitable base substrate), and a processing device 220 and an HBM device 230 each integrated with an upper surface 212 of the base substrate 210. In the illustrated embodiment, the processing device 220 and associated components (e.g., a processing unit (e.g., CPU / GPU), registers, L1 cache, and the like) are illustrated as a single package, and the HBM device 230 includes a semiconductor die stack. The semiconductor die stack in the HBM device 230 includes an interface die 232 and one or more memory dies 234 ( Figure 2 The processing device 220 is coupled to the HBM device 230 via a high bandwidth bus 240, which includes one or more routing lines 244 ( Figure 2). In various embodiments, the routing line 244 may include one or more metallization layers formed in one or more RDL layers of the base substrate 210 and / or one or more vias interconnecting the metallization layers. In addition, the high-bandwidth bus 240 may also include a plurality of active through-substrate vias 242 ("active TSVs 242") extending from a first base B1 at a metallization layer 246 in the interface die 232 to a first top T1 at a metallization layer 248 in an uppermost memory die 234a. The active TSVs 242 (also sometimes referred to herein as "signal TSVs," "HBM buses," and / or the like) allow each of the dies in the HBM device 230 to transfer data (e.g., between a memory die 234 (e.g., a DRAM die) and an interface die 232) at a relatively high rate (e.g., on the order of 1000 GB / s or more). In addition, as Figure 2 2, it will be appreciated that the processing device 220 and the HBM device 230 may each be coupled to the routing line 244 via solder structures (e.g., solder balls), metal-metal bonds, and / or any other suitable conductive bonds. Thus, the components of the HBM device 230 and the processing device 220 may communicate data at a relatively high rate.

[0025] During operation of the SiP device 200, the interface die 232 generates heat (e.g., when responding to read / write requests from the processing device 220 and / or when performing various suitable processing operations). In addition, because the interface die 232 is the lowermost die in the HBM device 230, the interface die 232 may be partially insulated by the memory die 234 so that the generated heat is not quickly dissipated through the HBM device 230. If not addressed, the heat may cause various deleterious effects in the interface die 232 and / or within the memory die 234, which may result in lost data, slower processing, missed reads, and / or complete failure of one or more signal routing lines in the bandwidth bus 240. To help reduce (or minimize) these deleterious effects, the HBM device 230 may include a cooling network 250 within the HBM device 230 and / or a cooling system 260 carried by the upper surface 222 of the processing device 220 and the upper surface 235 of the uppermost memory die 234a in the HBM device 230.

[0026] The cooling network 250 is configured to dissipate heat from the interface die 232 and / or the memory die 234 and toward the upper surface 235 of the uppermost memory die 234a. For example, in the illustrated embodiment, the cooling network 250 includes a cooling layer 252 thermally coupled to the top surface 231 of the interface die 232 and one or more cooling TSVs 254 ( Figure 2 six are described in the Figure 2, the cooling layer 252 (also sometimes referred to herein as a "thermal conductive layer," "conductive layer," "heat dissipation layer," and / or the like) is thermally coupled to a region of the top surface 231 of the interface die 232 that surrounds the active TSVs 242 (sometimes referred to herein as a "hot zone"). Thus, the cooling layer 252 is positioned to dissipate heat from the various circuit components in the interface die 232 in the longitudinal direction, thereby transporting the heat to the contact points with the cooling TSVs 254.

[0027] The cooling TSV 254 (also sometimes referred to herein as a "heat dissipation TSV", "passive TSV" and / or the like) extends from a second base B2 (also sometimes referred to herein as a proximal region) at the cooling layer 252 to a second top T2 (also sometimes referred to herein as a distal region) at (or above) the upper surface 235 of the uppermost memory die 234a. Thus, the cooling TSV 254 can dissipate heat from the cooling layer 252 in an upward direction away from the interface die 232 (and toward the upper surface 235 of the uppermost memory die 234a).

[0028] Furthermore, in the illustrated embodiment, the cooling TSVs 254 are thermally coupled to a cooling system 260 at (or above) the upper surface 235 of the uppermost memory die 234a. Thus, the cooling system 260 can absorb heat transported by the cooling TSVs 254, dissipate heat in a longitudinal direction, and / or radiate heat from the SiP device 200. In some embodiments, the cooling system 260 includes a metal plate that can be positioned in the flow path of one or more fans. Thus, the cooling system 260 can radiate heat into the air surrounding the SiP device 200, which is then carried away by the airflow from the fans.

[0029] Figure 3 is a partially schematic, cross-sectional illustration of a portion of an HBM device 300 configured in accordance with some embodiments of the present technology. Figure 3 The portion of the HBM device 300 described in Figure 2 Region A of the HBM device 230 described in Figure 3 The description will be apparent to those skilled in the art and may be included in Figure 2 Additional details of the HBM memory device 230 and / or any of the other HBM memory devices discussed herein.

[0030] For example, in Figure 3, the HBM device 300 includes an interface die 310 and a memory die 320 (e.g., a lowermost memory die in a stack of memory dies). The interface die 310 includes a die substrate 312 and an active signal routing area 311a and an active circuit area 311b. In the illustrated embodiment, the active signal routing area 311a (also sometimes referred to herein as a "signal area") is positioned in a central portion of the interface die 310, while the active circuit area 311b (also sometimes referred to herein as a "thermal signal routing area" and / or a "thermal area") surrounds the active signal routing area 311a at the periphery. A first dielectric layer 332 is formed over a top surface 313 of the die substrate 312, thereby electrically insulating the top surface 313 and / or various components of the interface die 310. Similarly, the memory die 320 includes a die substrate 322 having a lower surface 323 facing the top surface 313 and a second dielectric layer 334 formed over the lower surface 323 .

[0031] The HBM device 300 also includes a plurality of signal TSVs 340 ( Figure 3 340 ). Each of the signal TSVs includes a first segment 342a formed in the interface die 310 and a second segment 342b formed in the memory die 320. The first segment 342a is coupled to the first bonding pad 344a (and / or formed integrally therewith) and the second segment 342b is coupled to the second bonding pad 344b (and / or formed integrally therewith). In addition, the first bonding pad 344a is coupled to the second bonding pad 344b, thereby forming individual ones of the signal TSVs 340. In the illustrated embodiment, the first bonding pad 344a and the second bonding pad 344b are coupled by a solder structure 346 (e.g., a solder ball, a solder pillar, and / or the like) therebetween. The solder structure 346 may provide a reliable conductive bond and / or help self-align the interface and memory dies 310, 320 during the stacking process. However, it will be understood that various other bonding techniques may couple the first bonding pad 344a and the second bonding pad 344b together. For example, the first bonding pad 344a and the second bonding pad 344b may be coupled via another suitable conductive element, a metal-metal bond (sometimes also referred to as a "direct bond"), and / or the like. Furthermore, it will be understood that the signal TSVs 340 may each be at each die interface in the HBM device 300 (e.g., at each die interface). Figure 2 A similar configuration is included between each of the memory dies 234 of the HBM device 300, thereby establishing a signal communication path through each die in the HBM device 300.

[0032] like Figure 3As further illustrated in FIG. 1 , the interface die 310 may also include one or more circuits 314 (e.g., CMOS circuits, buffer circuitry, test circuitry, and / or the like), each formed in an active circuit region 311 b, various other active components 316 (illustrated schematically), and one or more metallization layers 318. The circuits 314 and / or other active components 316 may implement the functionality of the interface die 310, while the metallization layers 318 form signal routing lines within the interface die 310. For example, the metallization layers 318 may interconnect various suitable ones of the circuits 314 and / or other active components 316. Additionally or alternatively, the metallization layers 318 may connect the circuits 314 and / or other active components 316 to the signal TSVs 340 to assist in routing signals in the HBM device 300.

[0033] During operation of the HBM device 300, the circuits 314 and other active components 316 generate heat. To help avoid harmful effects from overheating, the HBM device 300 may also include a cooling network 350 configured to transport heat from the interface die 310. For example, in the illustrated embodiment, the cooling network 350 includes a cooling layer 352 and a plurality of cooling TSVs 354 ( 356 ) thermally coupled to the cooling layer 352 at contact points 356. Figure 3 31). A cooling layer 352 is formed on the first dielectric layer 332 above the active circuit area 311b (e.g., at least partially vertically aligned with the circuit 314, other active components 316, and / or metallization layer 318). The first dielectric layer 332 electrically insulates the cooling layer from the circuit 314, other active components 316, and metallization layer 318 while allowing the cooling layer 352 to absorb heat from the interface die 310. Thus, the cooling layer 352 can help dissipate heat in a lateral direction toward the contact point 356. The cooling TSVs 354 are formed on the memory die 320 (and any number of additional memory dies, such as Figure 2 Because the cooling TSVs 354 are thermally coupled to the cooling layer 352 at the contact points 356, the cooling TSVs 354 can absorb heat from the cooling layer 352 and dissipate heat vertically from the interface die 310.

[0034] exist Figure 3In the embodiment illustrated in , the cooling TSV 354 is thermally coupled to the cooling layer 352 by direct contact with the cooling layer 352 without the need for bonding material and / or metal-to-metal bonding. Direct contact may be sufficient because the cooling TSV 354 is not used to transmit signals in the HBM device 300 and is not bonded to a specific structure. However, it will be understood that the cooling TSV can be thermally coupled to the cooling layer 352 through various solder structures, other conductive materials (e.g., thermal paste), metal-to-metal bonding, and / or any other suitable bonding. In some embodiments, for example, the process of forming the metal-to-metal bonding for the signal TSV 340 also forms a metal-to-metal bonding between the cooling TSV 354 and the cooling layer 352.

[0035] As discussed above, the combination of cooling layer 352 and cooling TSV 354 can improve heat dissipation away from interface die 310 by transporting heat from a relatively large surface area in active circuit region 311b toward a direct thermal pathway through HBM device 300 (e.g., compared to HBM devices that rely on radiation dissipation through memory dies and / or active signal TSVs). In turn, the improved heat dissipation can offset the increased distance between interface die 310 and ambient air and / or the additional temperature generation associated with including additional memory dies and / or a denser circuit array in interface die 310. Thus, the improved heat dissipation can help allow larger and / or denser HBM devices to be built while reducing (or eliminating) the deleterious effects of heat.

[0036] Figure 3 Additional details regarding various features of the cooling network 350 are also described. For example, in the illustrated embodiment, the HBM device 300 also includes a third dielectric layer 336 formed over the cooling layer 352 to help protect the cooling layer 352. The third dielectric layer 336 can help protect the cooling layer 352 to extend the life of the cooling layer 352 (and therefore extend the life of the HBM device 300). However, the third dielectric layer 336 can include a plurality of openings 337 to allow the cooling TSVs 354 to directly contact the cooling layer 352.

[0037] In another example, if Figure 3344a and the second bonding pad 344b. Thus, for example, the first bonding pad 344a may extend to a first height H1 above the top surface 313 of the interface die 310, and the cooling layer 352 may extend to a second height H2 different from the first height H1. In the illustrated embodiment, the cooling layer 352 is thicker than any of the first bonding pads 344a. Therefore, the second height H2 is greater than the first height H1. The additional thickness may increase the amount of heat that the cooling layer 352 may transfer in the lateral direction. However, in some embodiments, the cooling layer 352 is thinner than any of the first bonding pads 344a, which may reduce the material cost of forming the cooling network 350.

[0038] In yet another example, because the cooling layer 352 and the cooling TSVs 354 do not form signal routing lines, there is no signaling-related problem of shorting the cooling TSVs 354 to each other. Figure 3 As further described in , the cooling TSVs 354 may have a smaller pitch than the signal TSVs 340. For example, the signal TSVs 340 are each separated by at least a first distance D1, and the cooling TSVs 354 are separated by at least a second distance D2 that is less than the first distance D1. The first distance D1 is large enough to avoid (or reduce the number of) electrical shorts between the signal TSVs 340 (e.g., by performing solder extrusion, surface diffusion, and / or the like while forming and / or bonding the first bonding pad 344a and the second bonding pad 344b). In contrast, the second distance D2 may be small enough that if the signal TSVs 340 are formed at that pitch, then it will be possible (or possible) to form shorts between the signal TSVs 340. The smaller pitch of the cooling TSVs 354 may allow a relatively large number of cooling TSVs 354 to be formed in the available space. In turn, the smaller pitch may increase (or maximize) the conductive metal available to conduct heat from the interface die 310, thereby increasing (or maximizing) the heat dissipation capacity of the cooling network 350.

[0039] Figure 4 is a partially schematic cross-sectional view of a SiP device 400 configured in accordance with a further embodiment of the present technology. Figure 4 As described in the above reference, the SiP device 400 Figure 2 The SiP device 200 discussed is generally similar. For example, Figure 4 The SiP device 400 includes a base substrate 410, and a processing device 420 and an HBM device 430 each integrated with an upper surface 412 of the base substrate 410. The HBM device 430 includes an interface die 432, one or more memory dies 434 ( Figure 4), a plurality of active TSVs 442 extending from the interface die 432 to the uppermost memory die 434a, and a cooling network 450 configured to transport heat from the interface die 432.

[0040] In the illustrated embodiment, the Figure 2 Similar to the cooling network 250 discussed above, the cooling network 450 includes a first cooling layer 452 carried by the top surface 431 of the interface die 432 and one or more cooling TSVs 454 ( Figure 4 434a). In addition, in the illustrated embodiment, the cooling network 450 includes a second cooling layer 458 carried by the upper surface 435 of the uppermost memory die 434a. As discussed above, the first cooling layer 452 can transport heat from the interface die 432 in the longitudinal direction, thereby helping to transport heat from the interface die 432 toward the cooling TSV 454. The cooling TSV 454 extends from the first cooling layer 452, through each of the memory dies 434, to a second height T2 that is coplanar with (or above) the upper surface 435 of the uppermost memory die 434a. Therefore, the cooling TSV 454 can transport heat in the first cooling layer 452 in an upward direction through the HBM device 430, and then transfer the heat to the second cooling layer 458. Similar to the first cooling layer 452, the second cooling layer 458 can then dissipate heat from the cooling TSV 454 in the longitudinal direction above the upper surface 435. Thus, the second cooling layer 458 can increase the surface area of ​​the cooling system 460 that is carried by the upper surface 422 of the processing device 420 and the uppermost surface 457 of the second cooling layer 458. In turn, the increase in surface area can increase the amount of heat transferred into the cooling system 460, thereby increasing (or maximizing) the amount of heat dissipated from the interface die 432 by the cooling network 450.

[0041] Figure 5A FIG. 5 is a partially schematic top view of an interface die 510 of a high bandwidth memory device configured in accordance with some embodiments of the present technology. In the illustrated embodiment, the interface die 510 is similar to the interface die 510 of the high bandwidth memory device described above with reference to FIG. Figure 2 and 4 The interface dies 232, 432 discussed are generally similar. For example, the interface die 510 includes a die substrate 512 having a signal routing area 514 and a thermal area 516 positioned on opposite sides of the signal routing area 514. A plurality of signal TSVs 520 are formed within the footprint of the signal routing area 514 and can couple the interface die 510 to other dies in the HBM device. And a plurality of circuits and other active elements (e.g., Figure 3314 and other active components 316 of the die substrate 512 are formed in the thermal region 516. As discussed above, during operation of the HBM device, the plurality of circuits and other active elements generate heat in the thermal region 516. The heat may then be dissipated by the first cooling layer 530, which is carried by and thermally coupled to the thermal region 516 of the die substrate 512.

[0042] like Figure 5A As further described in FIG. 5 , the first cooling layer 530 may be formed of a grid pattern 532 including a plurality of openings 534. The grid pattern 532 may help to direct heat toward the contact points 521 (eg, Figure 3 The contact points 356 of the interface die 510 direct heat from the interface die 510. For example, Figure 5A 532, the cooling contact point 521 is aligned with the solid portion of the first cooling layer 530 (e.g., not above the opening of the grid pattern 532). Therefore, the solid portion of the grid pattern 532 can direct heat toward the contact point 521, where the cooling TSV contacts and thermally couples to the first cooling layer 530. In addition, the plurality of openings 534 can provide space for air to flow through the first cooling layer 530 and over the interface die 510, which can help cool the interface die 510 without dissipating heat through the cooling network. Therefore, the load on the cooling network can be reduced. Additionally or alternatively, the grid pattern 532 can reduce the amount of metal used in the first cooling layer 530, thereby reducing the manufacturing costs associated with forming the first cooling layer 530.

[0043] and Figure 5A similar, Figure 5B 5 is a partially schematic top view of an uppermost memory die 540 of a high bandwidth memory device configured in accordance with some embodiments of the present technology. In the illustrated embodiment, the uppermost memory die 540 includes a die substrate 542 having a signal routing area 544 and a memory cell area 546. A plurality of signal TSVs 520 are positioned within the footprint of the signal routing area 544 and can couple the uppermost memory die 540 to other dies in the HBM device (e.g., to Figure 5A In turn, the signal TSVs 520 are coupled to memory cells (e.g., DRAM cells, NAND flash memory cells, and / or any other suitable memory cells) in the memory cell region 546. In addition, the uppermost memory die 540 includes a plurality of cooling TSVs 522 positioned within the footprint of the memory cell region 546. The cooling TSVs 522 extend through the HBM device to (e.g., at Figure 5A The contact point 521) will Figure 5AThe first cooling layer 530 is thermally coupled to the second cooling layer 560 carried by the uppermost memory die 540 .

[0044] Similar to the first cooling layer 530 discussed above, the second cooling layer 560 can be formed of a grid pattern 562 including a plurality of openings 564. The grid pattern 562 can increase the surface area of ​​the second cooling layer 560, thereby increasing the heat that can be dissipated from the HBM device by the second cooling layer 560. Additionally, the plurality of openings 534 can provide space for air to flow through the second cooling layer 560, which can help carry heat away from the HBM device.

[0045] It will be understood that although the first cooling layer 530 and the second cooling layer 560 have been discussed and illustrated herein as having a particular grid pattern, the first cooling layer 530 and the second cooling layer 560 may be formed in various other patterns. Non-limiting examples of other suitable shapes include various other grid patterns (e.g., with larger openings, smaller openings, more openings, different grids, non-rectangular openings, and / or the like), solid layers, independent columns, independent rows, plated fins, and / or the like.

[0046] Figure 6 is a partially schematic cross-sectional view of a SiP device 600 configured in accordance with a further embodiment of the present technology. Figure 6 As described in the above reference, the SiP device 400 Figure 2 and 4 The SiP devices 200, 400 discussed are generally similar. For example, Figure 6 The SiP device 600 includes a base substrate 610, and a processing device 620 and an HBM device 630 each integrated with an upper surface 612 of the base substrate 610. The HBM device 630 includes an interface die 632, one or more memory dies 634 ( Figure 6 ), a plurality of active TSVs 642 extending from the interface die 632 to the uppermost memory die 634a, and a cooling network 650 configured to transport heat from the interface die 632.

[0047] However, in the illustrated embodiment, the HBM device 630 further includes an additional die 636 carried by the uppermost memory die 634a. In addition, the cooling network 650 may include a first cooling layer 652 carried by the top surface 631 of the interface die 632, one or more cooling TSVs 654 ( Figure 6 ), a second cooling layer 658 carried by the additional die 636, and one or more third cooling layers 655, each carried by one memory die 634.

[0048] The first cooling layer 652 can transport heat from the interface die 632 in the longitudinal direction toward the cooling TSVs 654. Similarly, the third cooling layer 655 can transport heat from the memory die 634 carrying the third cooling layer 655 in the longitudinal direction toward the cooling TSVs 654. The cooling TSVs 654 in turn extend from the first cooling layer 652, through each of the memory dies 634, to the additional die 636, thereby allowing the cooling TSVs 654 to transport heat from the first cooling layer 652 and the third cooling layer 655 in the upward direction through the HBM device 630. Thus, Figure 6 The cooling network 650 may also help transport heat from the electronics (e.g., memory cells) in the memory die 634, thereby reducing the operating temperature of the memory die 634. In turn, the reduction in operating temperature may improve the operation of the HBM device 630 (e.g., by requiring a lower refresh rate in the memory die 634).

[0049] The second cooling layer 658 is at least partially wrapped around the additional die 636. Thus, similar to the above discussion, the second cooling layer 658 can dissipate heat from the cooling TSV 654 around the additional die 636 and in the longitudinal direction, and then transfer the heat into the cooling system 660. The additional die 636 can be a non-electrically functional die that provides a large amount of surface area to receive and dissipate heat. Therefore, the additional die 636 can provide a low-cost addition to the HBM device 630, which improves the functionality of the cooling network 650. Additionally or alternatively, the additional die can be used to match the overall height of the HBM device 630 to the overall height of the processing device 620.

[0050] It will be appreciated that although the cooling network 650 is Figure 6 634, the techniques disclosed herein are not limited in this regard. Rather, the cooling network 650 may include the third cooling layer 655 on any suitable subset of the memory dies 634. In various non-limiting examples, the cooling network 650 may include the third cooling layer 655 only on the bottom-most memory die 634b, the two bottom-most memory dies, the bottom half of the memory dies, the top-most memory die 634a, the top half of the memory dies, every other memory die, and / or any other suitable subset of the memory dies. Furthermore, it will be appreciated that although the third cooling layer 655 has been described in detail above, the third cooling layer 655 may be included on the bottom-most memory die 634b, the two bottom-most memory dies, the bottom half of the memory dies, the top-most memory die 634a, the top half of the memory dies, every other memory die, and / or any other suitable subset of the memory dies. Figure 6 The third cooling layer 655 is discussed in the context of the embodiment of the cooling network 650 illustrated in FIG. 1 , but the third cooling layer(s) 655 may be included in any of the other embodiments discussed herein. For example, Figure 2 The cooling network 250 may additionally include one or more third cooling layers to help dissipate heat from the memory die 234. Still further, it will be understood that in some embodiments, Figure 6A cooling network 650 of the type illustrated in FIG. 6A may omit the third cooling layer 655 entirely while including an additional die 636 and a second cooling layer 658 .

[0051] It will be understood from the foregoing that, for the purpose of illustration, the specific embodiments of the present technology have been described herein, but the well-known structures and functions are not shown or described in detail to avoid unnecessary ambiguity in the description of the embodiments of the present technology. To the extent that any material incorporated herein by reference conflicts with the present disclosure, the present disclosure shall prevail. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, unless the word "or" is explicitly limited to only represent a single item that is mutually exclusive with other items in a list involving two or more items, the use of "or" in this list should be interpreted as including any single item in (a) the list, (b) all items in the list, or (c) any combination of items in the list. In addition, as used herein, the phrase "and / or" in "A and / or B" refers to only A, only B, and both A and B. In addition, the terms "include", "include", "have" and "with" are used throughout to indicate that at least (several) stated features are included so that any larger number of identical features and / or additional types of other features are not excluded. Additionally, the terms "substantially," "approximately," and "about" are used herein to mean within at least 10% of a given value or limit. By way of example only, an approximate ratio means within ten percent of a given ratio.

[0052] Several implementations of the disclosed technology are described above with reference to the figures. Computing devices on which the described technology may be implemented may include one or more central processing units, memory, input devices (e.g., keyboards and pointing devices), output devices (e.g., display devices), storage devices (e.g., disk drives), and network devices (e.g., network interfaces). Memory and storage devices are computer-readable storage media that can store instructions for implementing at least part of the described technology. In addition, data structures and message structures can be stored or transmitted via data transmission media (e.g., signals on a communication link). Therefore, computer-readable media may include computer-readable storage media (e.g., "non-transitory" media) and computer-readable transmission media.

[0053] It will also be appreciated that various modifications may be made without departing from the present disclosure or technology. For example, the dies in the HBM device may be arranged in any other suitable order (e.g., with the interface die positioned above one or more of the memory dies). Furthermore, one of ordinary skill in the art will appreciate that the various components of the present technology may be further divided into subcomponents, or the various components and functions of the present technology may be combined and integrated. Additionally, certain aspects of the present technology described in the context of a particular embodiment may also be combined or eliminated in other embodiments. For example, a cooling network may be incorporated into the above referenced Figure 6In another example, the cooling network may include one or more cooling layers on any subset of the memory dies (e.g., only on the bottommost memory die, the bottom two memory dies, every other memory die, and the like) without including a cooling layer formed above the topmost memory die.

[0054] In addition, although the advantages associated with certain embodiments of the present technology are described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the present technology. Therefore, the present disclosure and associated technology may encompass other embodiments not explicitly shown or described herein.

Claims

1. A high bandwidth memory HBM device, comprising: A first die having a top surface, a signal routing area, and a thermal area; a plurality of second dies carried by the upper surface of the first die, the plurality of second dies including an uppermost die; one or more active through substrate vias (TSVs) positioned within a footprint of the signal routing region and extending from a first metallization layer in the first die to a second metallization layer in the topmost die; and a cooling network configured to transport heat from the first die, the cooling network comprising: a thermally conductive layer carried by the upper surface of the first die on the thermal zone; and One or more cooling TSVs contact the thermally conductive layer and extend from the thermally conductive layer to a height at or above the top surface of the uppermost die.

2. The HBM device of claim 1 , wherein the thermally conductive layer is a first thermally conductive layer, wherein the cooling network further comprises a second thermally conductive layer carried by the top surface of the uppermost die, and wherein the second thermally conductive layer contacts each of the one or more cooling TSVs. 3 . The HBM device of claim 1 , wherein the height is a first height, and wherein the one or more active TSVs extend to a second height below the first height. 4 . The HBM device of claim 1 , wherein the cooling network further comprises a third die carried by the uppermost die, and wherein the height is at or above an uppermost surface of the third die. 5 . The HBM device of claim 4 , wherein the thermally conductive layer is a first thermally conductive layer, wherein the third die is at least partially wrapped in a second thermally conductive layer, and wherein the second thermally conductive layer is in contact with each of the one or more cooling TSVs. 6 . The HBM device of claim 1 , wherein the first die includes a dielectric layer that electrically insulates the hot region of the upper surface, and wherein the thermally conductive layer is in contact with the dielectric layer.

7. The HBM device of claim 1 , further comprising a dielectric layer formed over at least a portion of the thermally conductive layer, wherein the dielectric layer includes one or more openings corresponding to each of the one or more cooling TSVs to allow the one or more cooling TSVs to contact the thermally conductive layer through the dielectric layer.

8. A system-in-package SiP device, comprising: Interposer substrate; a processing unit carried by the interposer substrate; as well as a high bandwidth memory HBM device carried by the interposer substrate, wherein the HBM device is coupled to the processing unit through an interposer bus, and wherein the HBM device comprises: an interface die carried by the interposer substrate; a plurality of memory dies carried by the interface die; a first plurality of through substrate vias (TSVs) communicatively coupling each of the plurality of memory dies with the interface die; and a cooling network configured to transport heat from the interface die, wherein the cooling network comprises: a thermally conductive layer thermally coupled to and carried by an upper surface of the interface die; and A second plurality of TSVs are thermally coupled to the conductive layer and extend from the conductive layer to a height at or above a top surface of an uppermost memory die.

9. The SiP device of claim 8, wherein the conductive layer is a first conductive layer, and wherein the cooling network further comprises a second conductive layer carried by the top surface of the uppermost memory die and thermally coupled to the plurality of second TSVs.

10. The SiP device of claim 8, wherein the cooling network further comprises a heat dissipation die carried by the uppermost memory die, and wherein the second plurality of TSVs extend through the heat dissipation die.

11. The SiP device of claim 8, wherein a top surface of the processing unit is flush with a top surface of the HBM device, wherein the SiP device further comprises a cooling medium carried by the top surface of the processing unit and the top surface of the HBM device, and wherein the cooling medium is thermally coupled to the cooling network in the HBM device.

12. The SiP device of claim 8, wherein the conductive layer is vertically aligned with one or more active circuits in the interface die. 13 . The SiP device of claim 8 , wherein the plurality of first TSVs have a first pitch, and wherein the plurality of second TSVs have a second pitch smaller than the first pitch.

14. The SiP device of claim 8, wherein each of the plurality of first TSVs comprises a first TSV segment formed in the interface die and a second TSV segment formed in a lowermost memory die, wherein the first TSV segment is electrically coupled to the second TSV segment via a solder structure. 15 . The SiP device of claim 14 , wherein a top surface of the first TSV segment is at a different height than a top surface of the conductive layer.

16. The SiP device of claim 8, wherein the conductive layer is formed in a grid pattern over the upper surface of the interface die.

17. A stacked semiconductor device comprising: an interface die having an active signal routing area and an active circuit area; a plurality of memory dies carried by an upper surface of the interface die, wherein each of the plurality of memory dies is communicatively coupled to the interface die through a plurality of through-substrate vias (TSVs) extending from a first metallization layer in the active signal routing area of ​​the interface die to a second metallization layer in an uppermost memory die; a cooling layer carried by the upper surface of the interface die over at least a portion of the active circuit area; and a plurality of cooling TSVs each having a proximal region thermally coupled to the cooling layer at a contact point and a distal region at a height parallel to or above a top surface of the uppermost memory die, wherein: The cooling layer is configured to transfer heat in a lateral direction toward the contact point, and The plurality of cooling TSVs are configured to transfer heat from the cooling layer in an upward direction. 18 . The stacked semiconductor device of claim 17 , wherein the proximal region of each of the plurality of cooling TSVs is in direct contact with the cooling layer at the contact point.

19. The stacked semiconductor device of claim 17, wherein the cooling layer is a first cooling layer, and wherein the stacked semiconductor device further comprises a second cooling layer carried by an upper surface of a lowermost memory die, wherein the cooling TSV extends through and is thermally coupled to the second cooling layer. 20 . The stacked semiconductor device of claim 17 , wherein the cooling layer is a first cooling layer, and wherein the stacked semiconductor device further comprises a second cooling layer thermally coupled to the distal region of each of the plurality of cooling TSVs.

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