Port boneless low bias signal distribution with backside metallization and buried rail

Abstract

An integrated circuit structure with buried rails and backside metal is disclosed for routing input signals to and / or output signals from one or more cells of the integrated circuit structure. A port-unjoined connection with the input port and / or from the output port is enabled. Therefore, the flexibility of signal routing is enhanced.

Description

Technical Field

[0001] The present disclosure relates generally to high performance devices and more particularly, but not exclusively, to devices with port-free bonded low-skew signal distribution (eg, clock signals) with backside metallization and buried rails. Background Art

[0002] Integrated circuit technology has made great strides in increasing computing power through the miniaturization of components. Unfortunately, with miniaturization, the resistance of interconnects and vias has increased. Clock distribution is becoming a challenge as the resistance of interconnects and vias increases. The increased resistance can lead to more timing variations and, therefore, significant clock skew variations.

[0003] Therefore, there is a need for systems, apparatuses and methods that overcome the deficiencies of conventional devices, including the methods, systems and apparatuses provided herein. Summary of the invention

[0004] A simplified overview of one or more aspects and / or examples associated with the apparatus and methods disclosed herein is presented below. Therefore, the following overview should not be considered an extensive overview of all contemplated aspects and / or examples, nor should the following overview be considered to identify key or critical elements associated with all contemplated aspects and / or examples or to delineate scopes associated with any particular aspect and / or example. Therefore, the sole purpose of the following overview is to present certain concepts related to one or more aspects and / or examples associated with the apparatus and methods disclosed herein in a simplified form prior to the detailed description presented below.

[0005] An exemplary integrated circuit structure is disclosed. The integrated circuit structure may include an oxide layer located on an upper surface of a substrate. The integrated circuit structure may also include one or more cells located on the upper surface of the oxide layer. Each cell may include one or more transistors configured to provide a logic function, a storage function, or both. The integrated circuit structure may also include one or more buried rails formed partially within the oxide layer and partially formed above the oxide layer. The integrated circuit structure may also include one or more back metals on the lower surface of the substrate. The one or more buried rails and the one or more back metals may be configured so that an input signal to the cell is routed to an input port of the cell through the one or more buried rails and the one or more back metals. The cell may be one of the one or more cells. The input signal may be an input to a logic function and / or a storage function provided by the cell. Alternatively or in addition, the one or more buried rails and the one or more back metals may be configured so that a signal from the cell is routed from an output port of the cell through the one or more buried rails and the one or more back metals. The output signal may be an output of a logic function and / or a storage function provided by the cell.

[0006] A method for manufacturing an integrated circuit structure is disclosed. The method may include forming an oxide layer on an upper surface of a substrate. The method may also include forming one or more cells on the upper surface of the oxide layer. Each cell may include one or more transistors configured to provide a logic function, a memory function, or both. The method may also include forming one or more buried rails partially within the oxide layer and partially above the oxide layer. The method may also include forming one or more back metals on the lower surface of the substrate. The one or more buried rails and the one or more back metals may be configured such that an input signal to the cell is routed to an input port of the cell through the one or more buried rails and the one or more back metals. The cell may be one of the one or more cells. The input signal may be an input to a logic function and / or a memory function provided by the cell. Alternatively or in addition, the one or more buried rails and the one or more back metals may be configured such that a signal from the cell is routed from an output port of the cell through the one or more buried rails and the one or more back metals. The output signal may be an output of the logic function and / or the memory function provided by the cell.

[0007] Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete understanding of the various aspects of the present disclosure and its many attendant advantages will be readily obtained when considered in conjunction with the accompanying drawings, which are presented for purposes of illustration only and not limitation of the present disclosure, as they may be better understood by reference to the following detailed description.

[0009] Figure 1 An example of a conventional integrated circuit structure is shown.

[0010] Figure 2A , Figure 2B and Figure 2C An example of an integrated circuit structure according to one or more aspects of the present disclosure is shown.

[0011] Figure 3 An example of a clock distribution network in accordance with one or more aspects of the present disclosure is shown.

[0012] Figure 4 An example of an integrated circuit structure configured to route a clock signal according to one or more aspects of the present disclosure is shown.

[0013] Figures 5A-10B An example of stages in fabricating an integrated circuit structure according to one or more aspects of the present disclosure is shown.

[0014] Figure 11-Figure 14 A flowchart is shown of an example method of fabricating an integrated circuit structure according to one or more aspects of the present disclosure.

[0015] Fig.15 Various electronic devices are shown that may utilize one or more aspects of the present disclosure.

[0016] Based on the drawings and detailed description, other purposes and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. According to convention, the features depicted in the drawings may not be drawn to scale. Therefore, for the sake of clarity, the size of the features depicted may be arbitrarily enlarged or reduced. According to convention, for the sake of clarity, some drawings are simplified. Therefore, the drawings may not depict all components of a particular device or method. In addition, throughout the specification and drawings, the same reference numerals represent the same features.

[0017] Specific implementation method

[0018] The various aspects of the present disclosure are shown in the following description and the relevant drawings for specific embodiments. Without departing from the scope of this paper's teachings, alternative aspects or embodiments may be designed. Additionally, the well-known elements of this paper's exemplary embodiments may not be described in detail or may be omitted to avoid blurring the relevant details of the teachings in the present disclosure.

[0019] In some of the described exemplary implementations, examples are identified where various component structures and operating portions may be taken from known conventional techniques and then arranged according to one or more exemplary embodiments. In such cases, internal details of known conventional component structures and / or portions of operations may be omitted to help avoid potential confusion of concepts described in the illustrative embodiments of the present disclosure.

[0020] The terms used herein are used only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0021] As mentioned above, clock distribution is becoming a challenge as interconnect and via resistance increases. As critical dimensions (CD) of manufacturing technologies decrease to 12nm and below, interconnect resistance increases exponentially with dimension scaling. This means that a small change in interconnect width can cause a large change in resistance due to exponential regimes, which is caused by the fixed barriers and liners around the metal, as well as surface and particle scattering effects. Vias have similar issues. This means that there can be more variation in timing, which in turn causes significant clock skew variations.

[0022] It is well known that buried rails provide a low resistance solution for power delivery in standard cells. Buried rails with backside connections from backside metal can free up routing resources on the frontside by making power and ground connections from the backside. It is expected that buried rails will become a benchmark technology for integrated circuit structures or devices by 2025.

[0023] In an integrated circuit structure, there may be many units, each of which may be considered to include one or more circuits, for example, transistors configured or otherwise arranged to provide a logic function or a storage function or both. Examples of logic functions may be simple "AND", "NAND", "NOT" (e.g., inverter), "OR", "NOR", "XOR", etc. Units providing logic functions may also include adders (integer and floating point), multipliers (integer and floating point), shifters, multiplexers, demultiplexers, etc. Units providing storage functions may include units providing data storage and / or data forwarding capabilities, for example, triggers, storage cells, latches, buffers, etc.

[0024] Typically, for power pinouts of standard cells, metal plates (e.g., bonding pads) are introduced to enable bonding on key structures. Unfortunately, such bonding pads take up a large amount of area. In other words, there is a significant area penalty. This limits the use of buried rails and backside metal in clock distribution networks.

[0025] To solve one or more problems associated with conventional techniques, it is proposed to use buried rails (BR) and backside metal (BM) for signal distribution networks in integrated circuit structures. An example of a signal distribution network is a clock distribution network.

[0026] Here, signal allocation is different from power allocation. For each logic function or storage function, there may be one or more inputs and one or more outputs of the function. Therefore, in one aspect, the input signal of a unit can be regarded as the input to the logic function and / or storage function provided by the unit. Conversely, the output signal of a unit can be regarded as the output of the logic function and / or storage function provided by the unit.

[0027] Figure 1An example of a conventional integrated circuit (IC) structure 100 is shown. Figure 1 , wherein a cross-section of the IC structure 100 is highlighted. As seen, the IC structure 100 includes a substrate 110 and an oxide layer 120 above the silicon (Si) substrate 110. On the back side (e.g., lower surface) of the substrate 110, a back metal (BM) 145 and a back via 155 are configured to deliver power to one or more cells 130. As seen, there may be multiple levels of back metal 145. For example, the back metal 145 above and below the back via 155 may be BM0 and BM1, respectively. A through substrate via (TSV) 175 within the substrate 110 couples the back metal 145 with a buried rail 165 as a power rail. Power is delivered to the cell through a power via 177 and a bonding pad 179. In a conventional IC structure 100, the buried rail 165 and the back metal 145 only deliver power to the cell 130. All signals—input and / or output—are routed to pass through the front metal 180.

[0028] However, in one aspect, it is proposed to utilize back metal and buried rails for signal distribution. Figure 2A , Figure 2B and Figure 2C , an integrated circuit structure 200 is shown according to one or more aspects. Figure 2A Shown along Figure 2C The section of line AA, Figure 2B Shown along Figure 2C The section of line BB and Figure 2C A top view is shown.

[0029] The integrated circuit structure 200 may include a substrate 210 and an oxide layer 220 on an upper surface of the substrate 210. One or more cells 230 may be formed within the oxide layer 220 and / or on an upper surface of the oxide layer 220. In one aspect, each cell 230 may be viewed as including one or more circuits, for example, transistors configured or otherwise arranged to provide a logic function or a storage function or both. Examples of logic functions may be simple, such as "AND", "NAND", "NOT", "OR", "NOR", "XOR", etc. Cells providing logic functions may also include adders (integer and floating point), multipliers (integer and floating point), shifters, multiplexers, demultiplexers, etc. Cells providing storage functions may include cells providing data storage and / or data forwarding capabilities, for example, flip-flops, memory cells, latches, buffers, etc.

[0030] The integrated circuit structure 200 may also include one or more buried rails 260 and one or more back metals 240. As seen, the buried rails 260 may be formed partially within the oxide layer 220 and partially above the oxide layer 220. In general, it can be said that the one or more buried rails 260 and the one or more back metals 240 are configured or otherwise arranged to route signals to and / or from the cells 230 of the integrated circuit structure 200. For example, an input signal to the cell 230 may be routed to an input port of the cell 230 through the one or more buried rails 260 and the one or more back metals 240. The input signal may be one of one or more inputs to a logic function and / or a memory function provided by the cell 230. Alternatively or in addition, an output signal from the cell 230 may be routed from an output port of the cell 230 through the one or more buried rails 260 and the one or more back metals 240. The output signal may be one of one or more outputs of a logic function and / or a memory function provided by the cell 230.

[0031] Figure 2A Shown along Figure 2C 23. A cross-sectional view of the integrated circuit structure 300 along line AA of FIG. In one aspect, the gate 235 of the transistor (not shown) of the cell 230 can be considered as the input port of the cell 230. In one aspect, the transistor can be a finFET transistor, and therefore can include one or more fins 232, or a nanosheet transistor including one or more vertically stacked sheets. In one aspect, the gate 235 can be in direct contact with the first portion of the first buried rail 260-1 (the portion indicated by the dashed rounded square). More generally, the input port of the cell 230 can be in direct contact with the first portion of the first buried rail 260-1. With the direct connection between the input port and the first buried rail 260-1, other interconnect units such as vias and bonding pads are not necessary. This means that there is no area loss associated with vias and bonding pads.

[0032] Note that the gate 235 is not electrically coupled to the second buried rail 260-2. As seen, an insulating liner 290 may be located between the gate 235 and the second buried rail 260-2.

[0033] The shape of the gate 235 may conform to the shape of the first buried rail 260-1 at the first portion. That is, the gate 235 may be in direct contact with the upper surface and side surfaces of the first buried rail 260-1 at the first portion. In one aspect, the gate 235 may include a doped semiconductor. For example, the gate 235 may be formed of a polysilicon material.

[0034] Figure 2B is along Figure 2CBB is a cross-sectional view of the integrated circuit structure 300. Here, the trench contact 237 can be electrically coupled to the second portion (the portion indicated by the dashed circle) of the second buried rail 260-2. Specifically, the output port of the unit 230 can be in direct contact with the second portion of the second buried rail 260-2. By the direct connection between the output port and the second buried rail 260-2, other interconnection units such as through-holes and bonding pads are not necessary, that is, no area loss associated with through-holes and bonding pads is generated.

[0035] Note that the trench contact 237 is not electrically coupled to the first buried rail 260 - 1 . As seen, an insulating liner 290 may be located between the trench contact 237 and the first buried rail 260 - 1 .

[0036] The shape of the trench contact 237 may conform to the shape of the second buried rail 260-2 at the second portion. That is, the trench contact 237 may directly contact the upper surface and the side surface of the second buried rail 260-2 at the second portion. In one aspect, the trench contact 37 may include a metal. For example, the trench contact 37 may be formed of any one or more of tungsten (W), copper (Cu), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), ruthenium (Ru), etc.

[0037] Figure 2C is a top view of the integrated circuit structure 300. Figure 2C , first and second front side metals 280-1, 280-2, first and second buried rails 260-1, 260-2, gate 235 (e.g., of a transistor of cell 230), and trench contact 237 are shown. It should be noted that there may be one or more front side metals 280 (including first and second front side metals 280-1, 280-2), one or more buried rails 260 (including first and second buried rails 260-1, 260-2), and one or more trench contacts (including trench contact 237). There may also be one or more gates (including gate 235) - that is, there may be one or more input ports.

[0038] Figure 2C 2. Back metal 240, substrate 210, and oxide layer 220 are omitted in order to more clearly illustrate the layout of front metal 280, gate 235, trench contact 237, and buried rail 260. Dashed rounded squares indicate locations where gate 235 can be electrically coupled to one or more buried rails 260 (e.g., with first buried rail 260-1), and dashed circles indicate locations where trench contact 237 can be electrically coupled to one or more buried rails 260 (e.g., with second buried rail 260-2).

[0039] like Figure 2A and Figure 2B As shown, the integrated circuit structure 200 may also include one or more through-substrate / through-silicon vias (TSVs) 270 formed in the substrate 210 and the oxide layer 220. The TSVs 270 may be configured to couple the one or more buried rails 260 with the one or more backside metals 240. For example, Figure 2A TSVs 270 are shown coupling buried rails 260 (eg, first buried rail 2601 - 1 ) with corresponding backside metal 240 . Figure 2B Another TSV 270 is shown coupling a buried rail 260 (eg, second buried rail 260 - 2 ) with its corresponding backside metal 240 .

[0040] The specific TSV 270 may be a nano-TSV (ηTSV), which is a TSV having a width narrower than the width of the corresponding buried rail 260. Alternatively, the specific TSV 270 may be a micro-TSV (μTSV), which is a TSV having a width the same as or wider than the width of the corresponding buried rail 260. Figure 2A and Figure 2B , TSV 270 is shown as a nano-TSV.

[0041] like Figure 2A and Figure 2B As can be seen in FIG. 1 , there may be multiple levels of back metal 240, and different levels of back metal 240 may be coupled with back vias 250. For example, the back metal 240 above the back via 250 may extend in one direction (e.g., the X direction), and the back metal 240 below the back via 250 may extend in a different direction (e.g., the Y direction). The two directions may be orthogonal in one aspect. The back metal 240 may be formed of a metal material including any one or more of W, Cu, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.

[0042] In one aspect, in addition to the buried rails 260, signals may also be routed through one or more front metals 280. Figure 2A As shown in FIG. 2 , the first front metal 280 - 1 can be coupled to the gate 235 through the gate via 236. Figure 2B2, the second front side metal 280-2 can be coupled to the trench contact 237 through the trench contact via 238. That is, in general, the one or more front side metals 280, the one or more buried rails 260, and the one or more back side metals 240 can be configured or otherwise arranged to route input signals to the input port of the cell 230. Alternatively or in addition, the one or more front side metals 280, the one or more buried rails 260, and the one or more back side metals 240 can be configured or otherwise arranged to route output signals from the output port of the cell 230.

[0043] An example of a signal distribution network is Figure 3 The clock distribution network 300 shown in FIG. The clock distribution network 300 may include multiple buffers and a certain number of flip-flops (sixteen in this example). The clock signal is input at the center and is distributed to the flip-flops. Ideally, all flip-flops output the clock at the same time. Unfortunately, in conventional clock distribution networks, due to the high resistance (e.g., about 400Ω / μm) of the 10-11nm M0 width, routing using front-end metal at different levels (e.g., M0, M1...Mx) can produce a large amount of timing uncertainty, which is typical for 2nm and above nodes. As indicated, small changes in resistance at these dimensions change exponentially. This increases the uncertainty of clock timing, especially at the end of the clock network chain-between the last leaf unit and the flip-flop. To solve this problem, conventional clock distribution networks are over-designed to ensure timing convergence. Over-design can bring high area and timing losses, the latter of which is caused by large capacitance associated with wider lines and / or high-drive clock buffers. For example, even with 28nm technology, when the clock uncertainty is 0.35ns, the area loss can be as high as 36% due to hold time compensation.

[0044] However, by implementing routing via backside metal and buried rails, clock timing uncertainty and the attendant area and timing penalties can be significantly reduced. Figure 4 An example of an integrated circuit structure 400 for routing clock signals is shown in FIG. In this figure, the routing near the end leaf cell of the clock distribution network is shown. As can be seen, there can be multiple gates 235 (which are the input ports of the cell), multiple buried rails 260, multiple back metals 240, and one trench contact 237. It should be noted that this is merely an example. That is, the integrated circuit structure can include any number of gates 235, buried rails 260, back metals 240, and trench contacts 237.

[0045] Note that there may also be a buried rail 460 and a back metal 440 to deliver power (e.g., Vdd, Vss). For purposes of distinction, buried rail 260 may be referred to as a signal distribution buried rail, and buried rail 460 may be referred to as a power distribution buried rail. Also, back metal 240 may be referred to as a signal distribution back metal, and back metal 440 may be referred to as a power distribution back metal. Thus, in Figure 4 In the embodiment, both power and signal (eg, clock signal) routing may be handled by the buried rails 460 , 260 and the backside metal 440 , 240 .

[0046] In one aspect, the front metal 280 can also be used for signal distribution. By using the signal distribution buried rail 260 and the back metal 240, routing congestion at the front side is significantly reduced. In fact, routing congestion at the clock port can be completely eliminated due to the straight gate connection at the back side.

[0047] exist Figure 4 , the dashed rounded square indicates the connection (i.e., electrical coupling) between the gate 235 and the signal distribution buried rail 260, the dashed circle indicates the connection between the trench contact 237 and the signal distribution buried rail 260, the horizontal dashed ellipse indicates the connection between the front metal 280 and the signal distribution buried rail 260, and the small vertical dashed ellipse indicates the connection between the signal distribution buried rail 260 and the signal distribution back metal 240. In this case, the connection between the trench contact 237 and one of the signal distribution buried rails 260 can be an output port, where the output of the last leaf unit is provided. Note that in some locations, both the dashed rounded square and the small dashed vertical ellipse are present. This indicates that the gate 235, the buried rail 260, and the back metal 240 are connected. Similarly, when the location includes both the dashed rounded square and the dashed horizontal ellipse, this indicates that the front metal 280, the gate 235, and the buried rail 260 are connected.

[0048] Regarding power, the large vertical dashed ellipse indicates the connection between the power distribution buried rail 460 and the power distribution back metal 440. Note that the Vdd rails are coupled to each other through one of the power distribution back metals 440, and the Vss rails are coupled to each other through the other power distribution back metal 440. The power distribution back metal 440 and / or the power distribution buried rail 460 can be formed of a metal material including any one or more of W, Cu, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.

[0049] In one aspect, the power distribution buried rail 460 and the signal distribution buried rail 260 can be parallel. Moreover, the buried rails 460, 260 can be staggered across the routing channel. That is, at least one signal distribution buried rail 260 can be located between adjacent power distribution buried rails 460. Similarly, at least one power distribution buried rail 460 can be located between adjacent signal distribution buried rails 260.

[0050] Figures 5A-10B Different stages of fabricating an integrated circuit structure, such as integrated circuit structures 200, 400 are shown. To reduce clutter, backside metal 240, backside via 250, frontside metal 280, gate via 236, and trench contact via 238 are not shown in these figures.

[0051] Figure 5A and Figure 5B A stage is shown where trenches 525A and 525B are formed in the substrate 210 and the initial oxide layer 510 . Figure 5A is along Figure 2C A cross-sectional view of line AA, and Figure 5B is along Figure 2C A cross-sectional view along line BB.

[0052] Fig. 6A and Figure 6B The stage of filling trenches 525A and 525B with a metal material to form buried rails 260 and TSVs 270 is shown. Fig. 6A is along Figure 2C A cross-sectional view of line AA, and Figure 6B is along Figure 2C A cross-sectional view along line BB.

[0053] Fig. 7A and Figure 7B A stage is shown where a portion of the initial oxide layer 520 is removed and the oxide layer 220 remains. In doing so, a portion of the buried track 260 is exposed. Fig. 7A is along Figure 2C A cross-sectional view of line AA, and Figure 7B is along Figure 2C A cross-sectional view along line BB.

[0054] Fig. 8A and Figure 8B A stage is shown where a liner 290 is formed on the exposed portion of the buried rail 260 . Fig. 8A is along Figure 2C A cross-sectional view of line AA, and Figure 8B is along Figure 2C A cross-sectional view along line BB.

[0055] Fig. 9A and Fig. 9BThe stage of removing the liner 290 from the buried rail at the selected location using a mask is shown. For example, a first portion of the first buried rail 260-1 can be removed by using a first mask (e.g., a VBG mask). In addition, a second portion of the second buried rail 260-2 can be removed, for example, by using a second mask (e.g., a VBD mask). Fig. 9A is along Figure 2C A cross-sectional view of line AA, and Fig. 9B is along Figure 2C A cross-sectional view along line BB.

[0056] Fig. 10A and Fig. 10B A stage in forming gate 235 and trench contact 237 is shown. Fig. 10A is along Figure 2C A cross-sectional view of line AA, and Fig. 10B is along Figure 2C A cross-sectional view along line BB.

[0057] Fig.11 A flow chart is shown of an example method 1100 of fabricating an integrated circuit structure, such as integrated circuit structures 200 , 400 , in accordance with one or more aspects of the present disclosure. In block 1110 , an oxide layer 220 may be formed on an upper surface of a substrate 210 .

[0058] In block 1120, one or more cells 230 may be formed on the upper surface of the oxide layer 220. Each cell 230 may include one or more transistors configured to provide logic functions, memory functions, or both.

[0059] In block 1130 , one or more buried rails 260 may be formed partially within the oxide layer 220 and partially over the oxide layer 220 .

[0060] In block 1140, one or more back metals 240 may be formed on the lower surface of the substrate 210. The one or more buried rails 260 and the one or more back metals 240 may be configured such that an input signal to the cell 230 is routed to an input port through the one or more buried rails 260 and the one or more back metals 240. The input signal may be an input to a logic function and / or a memory function provided by the cell 230. Alternatively or additionally, the one or more buried rails 260 and the one or more back metals 240 may be configured such that an output signal from the cell 230 is routed from its output port through the one or more buried rails and the one or more back metals.

[0061] Fig.12 A flow chart of an example method 1200 of fabricating an integrated circuit structure, such as integrated circuit structures 200 , 400 , according to one or more aspects of the present disclosure is shown. Fig.12can be considered as Fig.11 Therefore, blocks 1210 to 1240 may be similar to blocks 1110 to 1140. Therefore, for the sake of brevity, a detailed description of blocks 1210 to 1240 will be omitted.

[0062] In block 1250, one or more TSVs 270 may be formed within the substrate 210 and the oxide layer 220. Recall that the one or more TSVs 270 may be configured to couple the one or more buried rails 260 with the one or more backside metals 240. Each of the TSVs 270 may be a nano-TSV or a micro-TSV.

[0063] Fig.13 A flow chart of an example process for implementing blocks 1230 (forming one or more buried rails 260) and 1250 (forming one or more TSVs 270) is shown. In block 1310, one or more trenches 525A, 525B may be formed in the initial oxide layer 520 and the substrate 210. The one or more trenches 525A, 525B may be aligned with the one or more backside metals 240. Block 1310 may correspond to Figure 5A and Figure 5B The stages shown in .

[0064] In block 1320, a metal material may be deposited in one or more trenches 525A, 525B to form one or more TSVs 270 and one or more buried rails 260. The metal material may include any one or more of tungsten (W), copper (Cu), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), ruthenium (Ru), etc. Block 1320 may correspond to Fig. 6A and Figure 6B The stages shown in .

[0065] In block 1330, a top portion of the initial oxide layer 520 may be removed to form oxide layer 220. That is, oxide layer 220 may be an oxide layer that remains after partially removing the initial oxide layer. One or more buried rails 260 may be partially located within oxide layer 220 and partially exposed above oxide layer 220. Block 1320 may correspond to Fig. 7A and Figure 7B The stages shown in .

[0066] Return to reference Fig.12 In block 1260, a gate 235 of a transistor of cell 230 may be formed. In one aspect, gate 235 may be in direct contact with a first portion of first buried rail 260-1, which may be one of one or more buried rails 260. Gate 235 may be an input port of cell 230.

[0067] In block 1270, one or more trench contacts 237 may be formed on oxide layer 220. Portions of trench contacts 237 may be in direct contact with a second portion of a second buried rail 260-2, which may also be one of the one or more buried rails 260. The portion of trench contacts 237 in direct contact with the second portion of second buried rail 260-2 may be an output port of cell 230.

[0068] Fig.14 A flow chart of an example process for implementing blocks 1260 (forming gate 235) and 1270 (forming trench contact 237) is shown. In block 1410, a liner 290 may be formed on portions of one or more buried rails 260 including first and second buried rails 260 that are not covered by oxide layer 220. Recall that liner 290 may be insulating. Block 1410 may correspond to Fig. 8A and 8B The stages shown in .

[0069] In block 1420, the liner 290 may be selectively removed to expose a first portion of the first buried rail 260-1 and a second portion of the second buried rail 260-2. Block 1420 may correspond to Fig. 9A and Fig. 9B The stages shown in .

[0070] In block 1430, gate 235 may be formed in direct contact with the exposed first portion of first buried rail 260-1. Block 1430 may correspond to Fig. 10A The stages shown in .

[0071] In block 1440, trench contact 237 may be formed in direct contact with the exposed second portion of second buried rail 260-2. Block 1440 may correspond to Fig. 10B The stages shown in .

[0072] Return to reference Fig.12 In block 1280, one or more front metals 280 may be formed over one or more cells 230. One or more front metals 280 may also participate in routing signals. For example, one or more buried rails 260, one or more back metals 240, and one or more front metals 280 may be configured to route input signals to an input port (e.g., gate 235) of cell 230. Alternatively or in addition, one or more buried rails 260, one or more back metals 240, and one or more front metals 280 may be configured to route output signals from cell 230 from output port 238 (e.g., trench contact via).

[0073] In block 1290, one or more power distribution buried rails 460 may be formed. And in block 1295, one or more power distribution back metals 440 may be formed. The one or more power distribution buried rails 460 and the one or more power distribution back metals 440 may be configured to route power (e.g., Vdd, Vss voltages) to one or more cells 230.

[0074] It should be understood that the aforementioned manufacturing process and related discussions are provided only as a general description of some aspects of the present disclosure and are not intended to limit the present disclosure or the appended claims. In addition, many details in the manufacturing process known to those skilled in the art may have been omitted or combined in the summary process section to facilitate understanding of the various aspects disclosed without presenting each detail and / or all possible process variations in detail. In addition, it should be understood that the configurations and descriptions shown are provided only to help explain the various aspects disclosed herein. For example, the number and position of insulating layers, the metallization structure can have more or less conductive and insulating layers, the cavity direction, size, whether it is formed by multiple cavities, whether it is closed or open, and other aspects can have variations driven by specific application design features, such as the number of CPU cores, the height of standard cells, the frequency range, power, etc. Therefore, the aforementioned illustrative examples and related drawings should not be interpreted as limiting the various aspects disclosed and claimed herein.

[0075] Fig.15 Various electronic devices 1500 are shown that can be integrated with any of the aforementioned devices according to various aspects of the present disclosure. For example, mobile phone device 1502, laptop device 1504, and fixed location terminal device 1506 can all be generally considered user equipment (UE) and can include one or more integrated circuit structures (e.g., 200, 400), as described herein. Fig.15 The devices 1502, 1504, 1506 shown in the figure are exemplary only. Other electronic devices may also include RF filters, including but not limited to a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices supporting global positioning systems (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (e.g., meter reading devices, communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions or any combination thereof.

[0076] The aforementioned disclosed devices and functions may be designed and configured as computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer readable medium. Some or all of such files may be provided to a manufacturing processor who manufactures the device based on such files. The final product may include a semiconductor wafer, which is then cut into semiconductor dies and packaged into an antenna on a glass device. The antenna on a glass device may then be employed in the devices described herein.

[0077] The following numbered clauses describe examples of implementations:

[0078] Item 1: An integrated circuit structure comprising: an oxide layer on an upper surface of a substrate; one or more cells on the upper surface of the oxide layer, each cell comprising one or more transistors configured to provide a logic function, a memory function, or both; one or more buried rails formed partially within the oxide layer and partially above the oxide layer; and one or more back side metals on the lower surface of the substrate, wherein the one or more buried rails and the one or more back side metals are configured such that an input signal to a cell is routed through the one or more buried rails and the one or more back side metals to an input port of the cell, the cell being one of the one or more cells, the input signal being an input to a logic function and / or a memory function provided by the cell, or an output signal from the cell is routed from an output port of the cell through the one or more buried rails and the one or more back side metals, the output signal being an output of a logic function and / or a memory function provided by the cell, or both.

[0079] Clause 2: The integrated circuit structure of clause 1, wherein the cell is a cell of a clock distribution network.

[0080] Clause 3: The integrated circuit structure of clause 2, wherein the cell is a buffer or a flip-flop.

[0081] Clause 4: The integrated circuit structure of any of clauses 1-3, wherein the input port is in direct contact with a first portion of a first buried rail of the one or more buried rails.

[0082] Clause 5: The integrated circuit structure of clause 4, wherein the input port is a gate of a transistor of the cell.

[0083] Item 6: The integrated circuit structure of Item 5, wherein the gate is in direct contact with an upper surface and a side surface of the first buried rail at the first portion.

[0084] Clause 7: The integrated circuit structure of any of clauses 5-6, wherein the gate comprises a doped semiconductor.

[0085] Clause 8: The integrated circuit structure of any of clauses 1-7, further comprising: a trench contact on the oxide layer, the trench contact electrically coupled to a second buried rail of the one or more buried rails.

[0086] Clause 9: The integrated circuit structure of clause 8, wherein the output port is a portion of the trench in direct contact with the second portion of the second buried rail.

[0087] Item 10: The integrated circuit structure of Item 9, wherein the portion of the trench contact is in direct contact with the upper surface and the side surface of the second buried rail at the second portion.

[0088] Clause 11: The integrated circuit structure of any of clauses 8-10, wherein the trench contact comprises metal.

[0089] Item 12: An integrated circuit structure according to Item 11, wherein the trench contact is formed of one or more of tungsten (W), copper (Cu), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo) and ruthenium (Ru).

[0090] Item 13: An integrated circuit structure according to any of Items 1-12, further comprising: one or more front side metals above one or more cells, wherein the one or more buried rails, the one or more back side metals and the one or more front side metals are configured such that an input signal of the cell is routed to an input port through the one or more buried rails, the one or more back side metals and the one or more front side metals; or an output signal from the cell is routed from an output port through the one or more buried rails, the one or more back side metals and the one or more front side metals; or both.

[0091] Clause 14: The integrated circuit structure of any of clauses 1-13, further comprising: one or more through substrate vias (TSVs) formed in the substrate and the oxide layer, the one or more TSVs configured to couple the one or more buried rails with one or more backside metals.

[0092] Clause 15: The integrated circuit structure of clause 14, wherein at least one TSV is a nano-TSV (ηTSV), wherein the ηTSV is a TSV having a width narrower than a width of a corresponding buried rail; or wherein at least one TSV is a micro-TSV (μTSV), wherein the μTSV is a TSV having a width as wide as or wider than a width of a corresponding buried rail; or both.

[0093] Clause 16: The integrated circuit structure of any of clauses 1-15, wherein the one or more buried rails are one or more signal distribution buried rails, and wherein the integrated circuit structure further comprises one or more power distribution buried rails configured to route power to the one or more cells.

[0094] Clause 17: The integrated circuit structure of clause 16, wherein the one or more signal distribution buried rails are parallel to the one or more power distribution buried rails, and wherein at least one signal distribution buried rail is located between two adjacent power distribution buried rails.

[0095] Clause 18: An integrated circuit structure according to any of clauses 16-17, wherein the one or more back side metals are one or more signal distribution back side metals, and wherein the integrated circuit structure further comprises one or more power distribution back side metals configured to route power to one or more cells in conjunction with one or more power distribution buried rails.

[0096] Clause 19: An integrated circuit structure according to any of clauses 1-18, wherein one or more buried rails are formed of one or more of tungsten (W), copper (Cu), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo) and ruthenium (Ru), and wherein one or more back metals are formed of one or more of W, Cu, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo and Ru.

[0097] Clause 20: An integrated circuit structure as described in any of clauses 1-19, wherein the integrated circuit structure is integrated into a device selected from the following group of devices: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automobile.

[0098] Item 21: A method of manufacturing an integrated circuit structure, the method comprising: forming an oxide layer on an upper surface of a substrate; and forming one or more cells on the upper surface of the oxide layer, each cell comprising one or more transistors configured to provide a logic function, a memory function, or both; forming one or more buried rails, which are partially located within the oxide layer and partially located above the oxide layer; forming one or more back metals on the lower surface of the substrate, wherein the one or more buried rails and the one or more back metals are configured such that an input signal to a cell is routed to an input port of the cell through the one or more buried rails and the one or more back metals, the cell being one of the one or more cells, the input signal being an input to a logic function and / or a memory function provided by the cell, or an output signal from the cell is routed from an output port of the cell through the one or more buried rails and the one or more back metals, the output signal being an output of a logic function and / or a memory function provided by the cell; or both.

[0099] Clause 22: The method of clause 21, further comprising: forming one or more through substrate vias (TSVs) within the substrate and the oxide layer, the one or more TSVs configured to couple the one or more buried rails with the one or more backside metals.

[0100] Clause 23: The method of clause 22, wherein at least one TSV is a nano-TSV (ηTSV), which is a TSV having a width narrower than a width of a corresponding buried rail, or wherein at least one TSV is a micro-TSV (μTSV), which is a TSV having a width as wide as or wider than a width of a corresponding buried rail, or both.

[0101] Clause 24: A method according to any one of clauses 22-23, wherein forming one or more buried rails and forming one or more TSVs comprises: forming one or more trenches in an initial oxide layer and a substrate, wherein the one or more trenches are aligned with one or more back metals; depositing metal material in the one or more trenches to form one or more TSVs and one or more buried rails; removing a top portion of the initial oxide layer to form an oxide layer, such that the one or more buried rails are partially located within the oxide layer and partially exposed above the oxide layer.

[0102] Item 25: The method according to Item 24 further includes: forming a gate of a transistor of a cell in direct contact with a first portion of a first buried rail among the one or more buried rails, the gate being an input port; and forming a trench contact on the oxide layer, a portion of the trench contact being in direct contact with a second portion of a second buried rail among the one or more buried rails, the portion of the trench contact being in direct contact with the second portion of the second buried rail being an output port.

[0103] Item 26: A method according to Item 25, wherein forming a gate and forming a trench contact include: forming a liner on portions of one or more buried rails including first and second buried rails not covered by a residual oxide layer, the liner being insulating; removing the liner to expose a first portion of the first buried rail and a second portion of the second buried rail; forming a gate in direct contact with the exposed first portion of the first buried rail; and forming a trench contact in direct contact with the exposed second portion of the second buried rail.

[0104] Clause 27: A method according to any of clauses 25-26, wherein the gate is in direct contact with the upper surface and side surfaces of the first buried rail at the first portion, or wherein the trench contact is in direct contact with the upper surface and side surfaces of the second buried rail at the second portion, or both.

[0105] Clause 28: The method of any of clauses 21-27, wherein the unit is a unit of a clock distribution network.

[0106] Clause 29: The method according to any one of clauses 21-28 further includes: forming one or more front side metals above the one or more units, wherein the one or more buried rails, the one or more back side metals, and the one or more front side metals are configured such that an input signal to the unit is routed to an input port through the one or more buried rails, the one or more back side metals, and the one or more front side metals; or an output signal from the unit is routed from an output port through the one or more buried rails, the one or more back side metals, and the one or more front side metals; or both.

[0107] Clause 30: A method according to any one of clauses 21-29, wherein the one or more buried rails are one or more signal distribution buried rails and the one or more back metals are one or more signal distribution back metals, and wherein the method further comprises: forming one or more power distribution buried rails; and forming one or more power distribution back metals, the one or more power distribution buried rails and the one or more power distribution back metals being configured to route power to the one or more cells.

[0108] As used herein, the terms "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal" and variations thereof may interchangeably refer to any suitable mobile or fixed device that can receive wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smart phones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in motor vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device that is capable of receiving wireless communications and / or navigation signals (e.g., via short-range wireless, infrared, wired connections, or other connections), whether satellite signal reception, assistance data reception, and / or location-related processing occurs at the device or other device. In addition, these terms are intended to include all devices capable of communicating with the core network through a radio access network (RAN), including wireless and wired communication devices, and through the core network UE can connect to external networks, such as the Internet and other UEs. Of course, other mechanisms for the UE to connect to the core network and / or the Internet are also possible, for example, through a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.), etc. The UE can be embodied by any of a variety of types of devices, including but not limited to a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smartphone, a tablet computer, a tracking device, an asset tag, etc. The communication link through which the UE can send a signal to the RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). The communication link through which the RAN can send a signal to the UE is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term traffic channel (TCH) can refer to an uplink / reverse or downlink / forward traffic channel.

[0109] Wireless communication between electronic devices can be based on different technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi) and IEEE802.15.4 (Zigbee / Thread) or other protocols that can be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group to significantly reduce power consumption and cost while maintaining a similar communication range. BLE was merged into the main Bluetooth standard in 2010 with the adoption of Bluetooth Core Specification Version 4.0 and updated in Bluetooth 5.

[0110] As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as preferred over other examples. Likewise, the term "example" does not mean that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0111] It should be noted that the terms "connected", "coupled" or any variations thereof represent any connection or coupling between elements, whether direct or indirect, and may include the presence of intermediate elements between the two "connected" elements, "through intermediate elements" or "coupled" together, unless the connection is explicitly disclosed as a direct connection.

[0112] Any reference to an element using names such as "first", "second" etc. herein does not limit the quantity and / or order of these elements. On the contrary, these names are used as a convenient method to distinguish two or more elements and / or element instances. In addition, unless otherwise stated, a group of elements may include one or more elements.

[0113] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0114] Nothing stated or described in this application is intended to confer upon the public any element, act, feature, benefit, advantage, or equivalent, regardless of whether the element, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0115] It can be seen in the above detailed description that different features are grouped together in the examples. This disclosure should not be interpreted as an intention that the claimed examples have more features than those explicitly mentioned in the corresponding claims. On the contrary, the present disclosure may include less than all the features of the disclosed individual examples. Therefore, the attached claims should be deemed to be incorporated into the specification, where each claim itself can serve as a separate example. Although each claim can serve as a separate example by itself, it should be noted that although the dependent claims may refer to a specific combination with one or more claims in the claims, other examples may also cover or include the combination of the claims. The subject matter or any feature of a dependent claim with any other dependent claim and the combination of the independent claim. Unless it is explicitly stated that a specific combination is not intended, such a combination is proposed herein. In addition, it is also intended that the features of a claim may be included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0116] It should also be noted that the methods, systems and apparatuses disclosed in the specification or claims may be implemented by devices including units for performing the corresponding actions and / or functions of the disclosed methods.

[0117] In addition, in some examples, a single action can be subdivided into one or more sub-actions or include one or more sub-actions. Such sub-actions can be included in the disclosure of the separate action and as part of the disclosure of the separate action.

[0118] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or actions of the method claims according to the disclosed examples described herein do not need to be performed in any particular order. In addition, well-known elements will not be described in detail or may be omitted to avoid blurring the relevant details of the aspects and examples disclosed herein. In addition, although the elements of the present disclosure may be described or claimed in the singular, plural forms may be envisioned unless explicitly stated to be limited to the singular.

Claims

1. An integrated circuit structure, comprising: an oxide layer on the upper surface of the substrate; one or more cells on the upper surface of the oxide layer, each cell comprising one or more transistors configured to provide a logic function, a memory function, or both; one or more buried rails formed partially within the oxide layer and partially above the oxide layer; as well as one or more backside metals on the lower surface of the substrate, wherein the one or more buried rails and the one or more back metals are configured such that: an input signal to a cell being one of the one or more cells, the input signal being an input to the logic function and / or the memory function provided by the cell being routed to an input port of the cell through the one or more buried rails and the one or more back metals, or an output signal from the cell is routed from an output port of the cell through the one or more buried rails and the one or more back metals, the output signal being an output of the logic function and / or the memory function provided by the cell, or Both.

2. The integrated circuit structure according to claim 1, wherein: The units are units of a clock distribution network.

3. The integrated circuit structure according to claim 2, wherein: The unit is a buffer or a flip-flop.

4. The integrated circuit structure according to claim 1, wherein: The input port is in direct contact with a first portion of a first buried rail of the one or more buried rails.

5. The integrated circuit structure according to claim 4, wherein: The input port is the gate of the transistor of the cell.

6. The integrated circuit structure according to claim 5, wherein: The gate directly contacts an upper surface and a side surface of the first buried rail at the first portion.

7. The integrated circuit structure according to claim 5, wherein: The gate includes a doped semiconductor.

8. The integrated circuit structure of claim 1 , further comprising: A trench contact is provided on the oxide layer, the trench contact being electrically coupled to a second buried rail of the one or more buried rails.

9. The integrated circuit structure according to claim 8, wherein: The output port is a portion in contact with the trench that is in direct contact with the second portion of the second buried rail.

10. The integrated circuit structure according to claim 9, wherein: The portion of the trench contact is in direct contact with an upper surface and a side surface of the second buried rail at the second portion.

11. The integrated circuit structure according to claim 8, wherein: The trench contact includes metal.

12. The integrated circuit structure according to claim 11, wherein: The trench contact is formed of one or more of tungsten (W), copper (Cu), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo) and ruthenium (Ru).

13. The integrated circuit structure of claim 1 , further comprising: one or more front metals above the one or more cells, The one or more buried rails, the one or more back metals and the one or more front metals are configured such that The input signal to the cell is routed to the input port through the one or more buried rails, the one or more back metals, and the one or more front metals, or the output signal from the cell is routed from the output port through the one or more buried rails, the one or more back metals, and the one or more front metals, or Both.

14. The integrated circuit structure of claim 1, further comprising: One or more through substrate vias (TSVs) are formed in the substrate and the oxide layer, the one or more TSVs configured to couple the one or more buried rails with the one or more backside metals.

15. The integrated circuit structure according to claim 14, in, At least one TSV is a nano-TSV (ηTSV), which is a TSV having a width narrower than a width of a corresponding buried rail, or wherein at least one TSV is a micrometer TSV (μTSV), which is a TSV having a width as wide as or wider than a corresponding buried rail, or Both.

16. The integrated circuit structure according to claim 1, in, The one or more buried rails are one or more signal distribution buried rails, and The integrated circuit structure further includes one or more power distribution buried rails, and the one or more power distribution buried rails are configured to route power to the one or more units.

17. The integrated circuit structure according to claim 16, in, The one or more signal distribution buried rails are parallel to the one or more power distribution buried rails, and Wherein, at least one signal distribution buried rail is located between two adjacent power distribution buried rails.

18. The integrated circuit structure according to claim 16, in, The one or more back metals are one or more signal distribution back metals, and The integrated circuit structure further comprises one or more power distribution backside metals, wherein the one or more power distribution backside metals are configured to route the power to the one or more cells in conjunction with the one or more power distribution buried rails.

19. The integrated circuit structure according to claim 1, in, The one or more buried rails are formed of one or more of tungsten (W), copper (Cu), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), and ruthenium (Ru), and Wherein, the one or more back metals are formed by one or more of W, Cu, Pd, Ni, Au, Ta, TaN, Ti, TiN, Bi, Sb, Mo and Ru.

20. The integrated circuit structure of claim 1, wherein: The integrated circuit structure is integrated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automobile.

21. A method of manufacturing an integrated circuit structure, the method comprising: forming an oxide layer on the upper surface of the substrate; forming one or more cells on an upper surface of the oxide layer, each cell comprising one or more transistors configured to provide a logic function, a memory function, or both; forming one or more buried rails, the one or more buried rails being partially within the oxide layer and partially above the oxide layer; as well as forming one or more backside metals on the lower surface of the substrate, wherein the one or more buried rails and the one or more back metals are configured such that an input signal to a cell being one of the one or more cells, the input signal being an input to the logic function and / or the memory function provided by the cell being routed to an input port of the cell through the one or more buried rails and the one or more back metals, or an output signal from the cell is routed from an output port of the cell through the one or more buried rails and the one or more back metals, the output signal being an output of the logic function and / or the memory function provided by the cell, or Both.

22. The method according to claim 21, further comprising: One or more through substrate vias (TSVs) are formed in the substrate and the oxide layer, the one or more TSVs being configured to couple the one or more buried rails with the one or more backside metals.

23. The method according to claim 22, in, At least one TSV is a nano-TSV (ηTSV), which is a TSV having a width narrower than a width of a corresponding buried rail, or wherein at least one TSV is a micrometer TSV (μTSV), which is a TSV having a width as wide as or wider than a corresponding buried rail, or Both.

24. The method according to claim 22, wherein: Forming the one or more buried rails and forming the one or more TSVs includes: forming one or more trenches in the initial oxide layer and the substrate, the one or more trenches being aligned with the one or more backside metals; depositing a metal material in the one or more trenches to form the one or more TSVs and the one or more buried rails; and A top portion of the initial oxide layer is removed to form the oxide layer such that the one or more buried rails are partially within the oxide layer and partially exposed above the oxide layer.

25. The method according to claim 24, further comprising: forming a gate of a transistor of the cell in direct contact with a first portion of a first buried rail of the one or more buried rails, the gate being the input port; as well as A trench contact is formed on the oxide layer, a portion of the trench contact directly contacts a second portion of a second buried rail among the one or more buried rails, and the portion of the trench contact directly contacting the second portion of the second buried rail is the output port.

26. The method according to claim 25, wherein: Forming the gate and forming the trench contact include: forming a liner on portions of the one or more buried rails including the first buried rail and the second buried rail not covered by the oxide layer, the liner being insulating; removing the liner to expose the first portion of the first buried rail and the second portion of the second buried rail; forming the gate in direct contact with the exposed first portion of the first buried rail; and The trench contact is formed in direct contact with the exposed second portion of the second buried rail.

27. The method according to claim 25, in, The gate is in direct contact with an upper surface and a side surface of the first buried rail at the first portion, or wherein the trench contact is in direct contact with an upper surface and a side surface of the second buried rail at the second portion, or both.

28. The method of claim 21, wherein: The units are units of a clock distribution network.

29. The method of claim 21, further comprising: forming one or more front side metals over the one or more cells, The one or more buried rails, the one or more back metals and the one or more front metals are configured such that The input signal to the cell is routed to the input port through the one or more buried rails, the one or more back metals, and the one or more front metals, or the output signal from the cell is routed from the output port through the one or more buried rails, the one or more back metals, and the one or more front metals, or Both.

30. The method according to claim 21, in, The one or more buried rails are one or more signal distribution buried rails and the one or more back metals are one or more signal distribution back metals, and Wherein, the method further comprises: forming one or more buried power distribution rails; and One or more power distribution back metals are formed, the one or more power distribution buried rails and the one or more power distribution back metals being configured to route power to the one or more cells.

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