Single-cycle control method for suppressing harmonic waves of traction inverter

Abstract

The invention belongs to the field of electric traction systems, and particularly relates to a single-cycle control method for suppressing harmonic waves of a traction inverter, which comprises the following steps of: adding a notch filter into an outer voltage loop to filter out a beat frequency component in a direct-current voltage, and reducing the harmonic wave content in a given current # imgabs0 #; a quasi-PR controller is adopted in an inner current loop and used for current tracking and suppression of grid-side low-order current harmonics. Under the condition of no LC resonant circuit, the harmonic and beat frequency phenomena are effectively inhibited, and the stability and efficiency of the system are improved.

Description

Technical Field

[0001] The present invention belongs to the field of electric traction systems, and in particular relates to a single-cycle control method for suppressing harmonics of a traction inverter. Background Art

[0002] In traditional electric traction systems, LC resonant circuits are usually used to suppress harmonics and beat frequency phenomena. However, this method has problems such as large equipment size, heavy mass, and resonant frequency shift caused by aging of components, which does not meet the requirements of lightweight and high efficiency of modern traction systems. In order to overcome these shortcomings, the present invention proposes a digital single-cycle control algorithm that can effectively suppress the harmonics and beat frequency phenomena of the traction inverter without an LC resonant circuit. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a digital single-cycle control method for suppressing harmonics of a traction inverter, which can effectively suppress harmonics and beat frequency phenomena and improve the stability and efficiency of the system without an LC resonant circuit.

[0004] The present invention is achieved in this way.

[0005] A single-cycle control method for suppressing harmonics in a traction inverter, the method comprising: in a control circuit, adding a notch filter to an outer voltage loop to filter out the beat frequency component in the DC voltage, thereby reducing a given current The harmonic content in

[0006] A quasi-PR controller is used in the inner current loop for current tracking and suppression of low-order current harmonics on the grid side.

[0007] Furthermore, the transfer function of the quasi-PR controller is:

[0008] H' PR (s) represents the transfer function, ω0 is the angular frequency of the signal to be tracked, ω c is the cut-off frequency, K i is the integral gain, s is the complex frequency variable in the continuous domain Laplace transform, K p is the proportional gain, K Ih In the multiplexed quasi-PR controller, the resonant phase of the hth harmonic, h represents the hth harmonic, and hω0 represents the Hth harmonic frequency.

[0009] Furthermore, the input end of the notch filter inputs the DC voltage U actually measured by the system dc , used to filter out the DC voltage U dc The beat frequency component in the given voltage The PI controller adjusts its proportional and integral parameters to make the output voltage reach the desired value. The output of the PI controller is provided to the current loop controller together with the power feedforward signal. The power feedforward signal comes from the total power of the motor. The high-frequency noise is removed by the low-pass filter. The current loop controller outputs the current that needs to be tracked. Enter the inner current loop.

[0010] A single-cycle control method for suppressing harmonics of a traction inverter adopts a DSP controller to transmit sampled data to an FPGA controller. After receiving the data, the FPGA controller performs multi-mode modulation to generate a control signal for driving the inverter to control a three-phase asynchronous motor. The DSP controller samples the output voltage and current of the inverter in real time. The real-time sampled signal is filtered out of the beat frequency component in the DC voltage through a notch filter. The sampled signal is subjected to Clark and Park transformation, the current error is calculated, and the compensation voltage is calculated through a PI controller. A quasi-PR controller is set at the output end of the PI controller to process the current errors of the d-axis and the q-axis.

[0011] Furthermore, the transfer function of the quasi-PR controller is:

[0012] H' PR (s) represents the transfer function, ω0 is the angular frequency of the signal to be tracked, ω c is the cut-off frequency, K i is the integral gain, s is the complex frequency variable in the continuous domain Laplace transform, K p is the proportional gain, K Ih In the multiplexed quasi-PR controller, the resonant phase of the hth harmonic, h represents the hth harmonic, and hω0 represents the Hth harmonic frequency.

[0013] Furthermore, the DSP controller interpolates and fits the DC voltage according to the actual DC voltage sampling and transmits it to the FPGA controller, including:

[0014] The DSP controller obtains the data of K points of DC bus voltage in the Nth cycle and stores them in an array. Each data point is represented by u dc(N) (k), where k = 1, 2, ..., K, K = T net / 2T s-DSP , T net Represents a total time period, used to calculate the number of points K, T sampled in this time period s-DSP Indicates the sampling period of the DSP controller;

[0015] The sampled data point u dc(N) (k) is stored in an array, where each data point in the array represents the net A sampling point within

[0016] In the Kth sampling interval within the N+1 period, the interpolation step size is Get, where T s-FPGA is the control cycle of the FPGA controller; u dc(N) (k+1) represents the data point corresponding to k+1 sampling points;

[0017] I points are inserted in each sampling interval, where the value of I is obtained by the following formula,

[0018] I=T s-DSP / T s-FPGA

[0019] The DC bus voltage obtained by fitting is shown as follows:

[0020] u i dc(N+1) (k) = u dc(N+1) (k)+i*u step

[0021] The array is updated using the DC voltage data acquired in the N+1 cycle.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] Through digital control means, under the condition of no LC resonant circuit, harmonics and beat frequency phenomena can be effectively suppressed, thereby improving the stability and efficiency of the system.

[0024] By introducing a notch filter and a quasi-proportional resonant (PR) controller, the beat frequency component in the DC voltage is eliminated and the harmonic content in the current is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of the control structure in the method provided in Example 1;

[0026] Figure 2 This is a schematic diagram of the control structure in the method provided in Example 2. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0028] Example 1

[0029] See also Figure 1A single-cycle control method for suppressing harmonics in a traction inverter is shown, characterized in that the method comprises: in a control circuit, a notch filter is added to the outer voltage loop to filter out the beat frequency component in the DC voltage, thereby reducing the given current The harmonic content in

[0030] A quasi-PR controller is used in the inner current loop for current tracking and suppression of low-order current harmonics on the grid side.

[0031] The transfer function of the quasi-PR controller is:

[0032] H' PR (s) represents the transfer function, ω0 is the angular frequency of the signal to be tracked, ω c is the cut-off frequency, K i is the integral gain, s is the complex frequency variable in the continuous domain Laplace transform, K p is the proportional gain, K Ih In the multiplexed quasi-PR controller, the resonant phase of the hth harmonic, h represents the hth harmonic, and hω0 represents the Hth harmonic frequency.

[0033] The input of the notch filter is the DC voltage U actually measured by the input system. dc , used to filter out the DC voltage U dc The beat frequency component in the given voltage The PI controller adjusts its proportional and integral parameters to make the output voltage reach the desired value. The output of the PI controller is provided to the current loop controller together with the power feedforward signal. The power feedforward signal comes from the total power of the motor. The high-frequency noise is removed by the low-pass filter. The current loop controller outputs the current that needs to be tracked. Enter the inner current loop.

[0034] Usually * s represents the given current, which is the current value that the system expects to track. In the control system, it is the controller that tries to make the actual current i s Approximation target value. s :It represents the actual measured current, that is, the current value of the system. The controller adjusts the output of the system to make i s Gradually approaching i * s .

[0035] u * ab : It represents the ideal output voltage calculated by the control system, which is used to drive power electronic equipment or motors. This is the target voltage signal output by the controller. abIndicates the actual output voltage, which is the voltage value measured in the actual system. Usually, the system will adjust u ab Approximation u * ab .

[0036] In this embodiment, the current inner loop adopts a quasi-PR controller to improve the current tracking capability and suppress the low-order current harmonics on the grid side. The quasi-PR controller can achieve steady-state error-free tracking of the fundamental current and effectively suppress harmonics. The calculated current command is converted into a drive signal through space vector pulse width modulation (SPWM) technology, which is used to control power electronic devices and achieve precise control of the motor.

[0037] Example 2

[0038] See also Figure 2 As shown, a single-cycle control method for suppressing harmonics of a traction inverter is disclosed. A DSP controller is used to transmit sampled data to an FPGA controller. After receiving the data, the FPGA controller performs multi-mode modulation to generate a control signal for driving the inverter to control the three-phase asynchronous motor. The DSP controller samples the output voltage and current of the inverter in real time. The real-time sampled signal is filtered out of the beat frequency component in the DC voltage through a notch filter. The sampled signal is subjected to Clark and Park transformation, the current error is calculated, and the compensation voltage is calculated through a PI controller. A quasi-PR controller is set at the output end of the PI controller to process the current errors of the d-axis and q-axis.

[0039] The DSP controller interpolates and fits the DC voltage based on the actual DC voltage sampling and transmits it to the FPGA controller, including:

[0040] The DSP controller obtains the data of K points of DC bus voltage in the Nth cycle and stores them in an array. Each data point is represented by u dc(N) (k), where k = 1, 2, ..., K, K = T net / 2T s-DSP , T net Represents a total time period, used to calculate the number of points K, T sampled in this time period s-DSP Indicates the sampling period of the DSP controller;

[0041] The sampled data point u dc(N) (k) is stored in an array, where each data point in the array represents the net A sampling point within

[0042] In the Kth sampling interval within the N+1 period, the interpolation step size is Get, where T s-FPGA is the control cycle of the FPGA controller; u dc(N)(k+1) represents the data point corresponding to k+1 sampling points;

[0043] I points are inserted in each sampling interval, where the value of I is obtained by the following formula,

[0044] I=T s-DSP / T s-FPGA

[0045] The DC bus voltage obtained by fitting is shown as follows:

[0046] u i dc(N+1) (k) = u dc(N+1) (k)+i*u step

[0047] The array is updated using the DC voltage data acquired in the N+1 cycle.

[0048] This embodiment is based on the principle of traditional analog single-cycle control and utilizes the high control frequency of FPGA (field programmable gate array) to achieve precise control of the inverter output voltage and suppress harmonics and beat frequency phenomena.

[0049] In order to solve the problem that the traditional modulation compensation algorithm cannot be applied to square wave conditions and to improve the beat frequency-free control effect, a digital single-cycle control algorithm is proposed to solve the zero-order hold error problem and the modulation algorithm switching problem. It is then applied to the traction inverter motor control system with vector control plus multi-mode modulation to effectively solve the beat frequency problem in the square wave area.

[0050] Based on the principle of traditional analog single-cycle control algorithm, a digital single-cycle control implementation method is given. Secondly, the higher control frequency of FPGA is used to solve the DC bus voltage sampling error problem, and the volt-second balance is accurately achieved through voltage compensation to solve the beat frequency suppression problem in the square wave area. Finally, the initial phase of the pulse is reasonably controlled to achieve smooth switching between modes, and a smooth transition between the square wave digital single-cycle control and the segmented synchronous area modulation algorithm is achieved.

[0051] The voltage sampling error can be attributed to the zero-order hold. In order to use a more realistic DC voltage in the integration process, the higher control frequency of the FPGA controller is used to linearly refine the discrete DC side voltage sent by the DSP controller.

[0052] At time k, the FPGA controller receives the voltage data u sent by the DSP controller. dc (k), the specific process is as follows:

[0053] 1. Data sampling:

[0054] At time k, the DSP controller samples the voltage data of the system, which includes the voltage udc (k) and other important signals.

[0055] 2. Data transmission:

[0056] The sampled data is transmitted to the FPGA controller via the high-speed serial interface SPI. After receiving the data, the FPGA controller needs to perform further processing and control.

[0057] 3.FPGA controller processing:

[0058] After receiving the voltage data, FPGA performs calculation and processing according to the pre-set control algorithm. The processing process includes filtering, PI control, PR control and other modules.

[0059] 4. Generate control signals:

[0060] Finally, the FPGA controller generates control signals based on the processing results to drive power electronic devices and achieve precise control of the system.

[0061] At time k, the FPGA controller receives the voltage data sent by the DSP controller. Linear interpolation step length u step It can be obtained by the following formula:

[0062] T s-DSP It represents the time period of data sampling in the DSP controller. That is to say, every T s-DSP At this time, the DSP controller will sample and process the signals in the system (such as voltage and current).

[0063] T s-DSP The sampling time determines how often the DSP updates the system state. A shorter TsDSP can provide a higher sampling frequency, making the system respond faster to changes, but it also increases the computational and processing burden.

[0064] T s-FPGA - represents the time period for data sampling and processing in the FPGA controller system. s-FPGA At this time, the FPGA controller will process the received data, such as filtering, control algorithm calculation, etc.

[0065] Data transmission and synchronization: Data transmission between the DSP controller and the FPGA controller needs to be synchronized to ensure that the DSP controller data received by the FPGA controller is the latest and can be processed accurately. This means that at time k, the data sampled by the DSP controller can be transmitted to the FPGA controller in time for processing.

[0066] For the railway system, since it is a large inertia system, the motor output power will not change significantly in a short period of time. Therefore, it can be considered that the beat frequency voltage amplitude remains unchanged in two adjacent beat frequency voltage cycles. At the same time, considering that the AC component in the DC bus voltage almost all comes from the beat frequency component, the sampled voltage value of the previous cycle can be used as the voltage prediction value of this cycle. The above formula can be rewritten as:

[0067]

[0068] Among them, u dc(N) (k+1) is the Nth beat frequency voltage cycle (hereinafter referred to as cycle), and the DC side voltage sampling value at time k+1. The above formula gives the calculation formula of the interpolation step size at time k in the N+1th beat frequency voltage cycle. Compared with the traditional repeated prediction method, this voltage prediction method makes full use of the periodic pulsation of the DC side voltage and the fast computing speed of the FPGA controller, greatly reducing the complexity of the algorithm, and the prediction error can be controlled within an acceptable range, which can meet the beat frequency suppression requirements.

[0069] The steps to simulate the real DC bus voltage by interpolation fitting are as follows:

[0070] Step 1: The DSP controller obtains the data of K points of DC bus voltage in the Nth cycle and stores them in an array. Each data point can be represented as u dc(N) (k), where k = 1, 2, ..., K, K = T net / 2T s-DSP . T net Represents a total time period, used to calculate the number of points K sampled during this time period. Specific formula T net / 2T s-DSP Indicates that T net / 2T s-DSP Used to calculate the number of sampling points K required within this time period.

[0071] Step 2: In the kth sampling interval within the N+1 period, the interpolation step size can be calculated by get.

[0072] Step 3: Insert I points in each sampling interval, where the value of I can be obtained by the following formula,

[0073] I=T s-DSP / T s-FPGA

[0074] The fitted DC bus voltage is shown in the following formula.

[0075] u i dc(N+1) (k) = u dc(N+1) (k)+i*ustep

[0076] Step 4: Update the array using the DC voltage data obtained in the N+1 cycle.

[0077] 3. Fitting and processing:

[0078] After data collection is completed, the system may filter the data to obtain a more accurate voltage value.

[0079] exist Figure 2 In the example, the PI controller modules are labeled `usd-PI` and `usq-PI` and are used to control the current. Each PI controller contains an integrator part, which has the following functions:

[0080] -usd-PI: processes the d-axis current error, accumulates the error through an integrator, and generates a d-axis voltage reference value.

[0081] -usq-PI: processes the q-axis current error, accumulates the error through an integrator, and generates a q-axis voltage reference value.

[0082] These integrators play the role of accumulating errors and eliminating steady-state errors in the PI controller, thereby improving the control accuracy of the system.

[0083] Integrators are mainly contained in the `usd-PI` and `usq-PI` modules in the DSP controller section. These PI controller modules process the error signal through the integrator and generate appropriate control outputs for adjusting the voltage and current of the system.

[0084] The basic principle of the traction inverter motor control system using digital single-cycle control is to implement the asynchronous motor vector control strategy in the DSP controller, sample the DC bus voltage value at the same time, calculate the interpolation voltage step size according to the linear interpolation algorithm and send it to the FPGA controller.

[0085] Figure 2 In the Anti-Park transformation, the voltage or current component in the rotating coordinate system is converted back to the stationary coordinate system.

[0086] Clark transformation is used to convert the three-phase stationary coordinate system (abc coordinate system) into the two-phase stationary coordinate system (α-β coordinate system). The formula is as follows:

[0087]

[0088] Through Clark transformation, the three-phase current can be converted into two-phase current for analysis and control in a stationary coordinate system.

[0089] BRT (Beat Frequency Technology): BRT, or beat frequency technology, uses the periodicity of the beat frequency signal to perform interpolation calculations by predicting the DC bus voltage at the next moment to reduce sampling errors. The specific process is as follows:

[0090] Predict the change of DC bus voltage and perform interpolation calculation through the beat frequency voltage formula.

[0091] In the FPGA controller, the DC voltage data sent from the DSP is linearly interpolated to reduce sampling errors and improve control accuracy.

[0092] The DSP controller inputs the FPGA controller mainly through the DC bus voltage u dc (k) Motor output total power P motor These quantities are involved in the following calculations: interpolation step calculation and fitting DC bus voltage:

[0093] The DSP controller obtains multiple sampling points of the DC bus voltage in one cycle and stores them in an array. In the next cycle, the interpolation step is used to perform linear interpolation calculations and insert more voltage points to fit the actual DC bus voltage.

[0094] When performing multi-mode modulation algorithm in FPGA controller, the voltage is refined according to the interpolation voltage calculated by DSP. Refined processing mainly refers to:

[0095] 1. Linear interpolation processing: Use high-frequency FPGA to perform linear interpolation on the discrete DC voltage sent from DSP to reduce the sampling error caused by zero-order hold.

[0096] 2. Interpolation fitting: Through the interpolation fitting technology, the real DC bus voltage is simulated, making the fitted voltage closer to the real value, thereby reducing the integral error and improving the control accuracy.

[0097] In summary, the three-phase current is converted into two-phase current through Clark transformation, the beat frequency voltage is predicted and interpolated using BRT technology, and the multi-mode modulation algorithm is refined through FPGA, which can improve the control accuracy of DC voltage and the stability of the system.

[0098] A high-precision voltage integration is achieved to ensure the accuracy of single-cycle control. At the same time, a reasonable switching algorithm is adopted to ensure smooth switching between various modulation modes.

[0099] Harmonic analysis and compensation: Through real-time monitoring of the inverter output voltage and current, the harmonic components are analyzed, and dynamic adjustments are made using frequency compensation algorithms to ensure the purity and stability of the output waveform.

[0100] The present invention provides a digital single-cycle control method for harmonic suppression of traction inverters in electric traction systems, which overcomes many defects of traditional LC resonant circuits and achieves effective harmonic suppression and beat frequency suppression without LC resonant circuits. The method has the advantages of small equipment size, light weight, high control accuracy, etc., and is suitable for the application requirements of modern electric traction systems.

[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A single-cycle control method for suppressing harmonics in a traction inverter, characterized in that: The method comprises: in a control circuit, a notch filter is added to the outer ring voltage loop to filter out the beat frequency component in the DC voltage, thereby reducing the given current The harmonic content in A quasi-PR controller is used in the inner current loop for current tracking and suppression of low-order current harmonics on the grid side.

2. A single-cycle control method for suppressing harmonics of a traction inverter according to claim 1, characterized in that: The transfer function of the quasi-PR controller is: H' PR (s) represents the transfer function, ω0 is the angular frequency of the signal to be tracked, ω c is the cut-off frequency, K i is the integral gain, s is the complex frequency variable in the continuous domain Laplace transform, K p is the proportional gain, K Ih In the multiplexed quasi-PR controller, the resonant phase of the hth harmonic, h represents the hth harmonic, and hω0 represents the Hth harmonic frequency.

3. A single-cycle control method for suppressing harmonics of a traction inverter according to claim 1, characterized in that: The input end of the notch filter inputs the DC voltage U actually measured by the system dc , used to filter out the DC voltage U dc The beat frequency component in the given voltage The PI controller adjusts its proportional and integral parameters to make the output voltage reach the desired value. The output of the PI controller is provided to the current loop controller together with the power feedforward signal. The power feedforward signal comes from the total power of the motor. The high-frequency noise is removed by the low-pass filter. The current loop controller outputs the current that needs to be tracked. Enter the inner current loop.

4. A single-cycle control method for suppressing harmonics in a traction inverter, characterized in that: The DSP controller is used to transmit the sampled data to the FPGA controller. After receiving the data, the FPGA controller performs multi-mode modulation to generate a control signal for driving the inverter to control the three-phase asynchronous motor. The DSP controller samples the inverter output voltage and current in real time. The real-time sampled signal is filtered out with a notch filter to remove the beat frequency component in the DC voltage; the sampled signal is subjected to Clark and Park transformation, the current error is calculated, and the compensation voltage is calculated through a PI controller. A quasi-PR controller is set at the output end of the PI controller to process the current errors of the d-axis and q-axis.

5. A single-cycle control method for suppressing harmonics of a traction inverter according to claim 4, characterized in that: The transfer function of the quasi-PR controller is: H' PR (s) represents the transfer function, ω0 is the angular frequency of the signal to be tracked, ω c is the cut-off frequency, K i is the integral gain, s is the complex frequency variable in the continuous domain Laplace transform, K p is the proportional gain, K Ih In the multiplexed quasi-PR controller, the resonant phase of the hth harmonic, h represents the hth harmonic, and hω0 represents the Hth harmonic frequency.

6. A single-cycle control method for suppressing harmonics of a traction inverter according to claim 4, characterized in that: The DSP controller performs interpolation fitting of the DC voltage according to the actual DC voltage sampling and transmits it to the FPGA controller, including: The DSP controller obtains the data of K points of DC bus voltage in the Nth cycle and stores them in an array. Each data point is represented by u dc(N) (k), where k = 1, 2, ..., K, K = T net / 2T s-DSP , T net Represents a total time period, used to calculate the number of points K, T sampled in this time period s-DSP Indicates the sampling period of the DSP controller; The sampled data point u dc(N) (k) is stored in an array, where each data point in the array represents the net A sampling point within In the Kth sampling interval within the N+1 period, the interpolation step size is Get, where T s-FPGA is the control cycle of the FPGA controller; u dc(N) (k+1) represents the data point corresponding to k+1 sampling points; Insert I points in each sampling interval, where the value of I is obtained by the following formula: I = T s-DSP / T s-FPGA The DC bus voltage obtained by fitting is shown as follows: in i dc(N+1) (k)=u dc(N+1) (k)+i*u step The array is updated using the DC voltage data acquired in the N+1 cycle.

Images