High-speed LVDS driver

Abstract

The invention is suitable for an integrated circuit technology, and provides a high-speed LVDS driver. The structure comprises four switch MOS (Metal Oxide Semiconductor) tubes M1, M2, M3 and M4, two 10 kilohm resistors, a common-mode feedback circuit consisting of operational amplifiers I0 and M5, and two pre-emphasis current sources Ipre. The circuit provided by the invention solves two key problems of output waveform offset caused by dynamic change of an output common-mode level, attenuation of a high-frequency component of a signal in a transmission process, higher harmonic loss of the output waveform and intersymbol interference, and realizes high-speed transmission of a data signal.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-speed LVDS driver. Background Art

[0002] LVDS (Low Voltage Differential Signaling) is a technical standard for high-speed data transmission. Its technical background and key features give it a crucial position in modern electronic communications. LVDS stands for Low-Voltage Differential Signaling. Traditional single-ended signal transmission methods often require higher voltages and are susceptible to electromagnetic interference. LVDS, on the other hand, uses differential signaling to achieve efficient and stable signal transmission at low voltages. Specifically, the operating voltage of LVDS is typically around 350 millivolts (mV), significantly reducing power consumption.

[0003] Another key technical feature of LVDS is its differential signaling. Differential signaling involves transmitting signals via two parallel wires, one carrying a positive signal and the other carrying an inverted signal. At the receiving end, the signal value is determined by comparing the voltage difference between the two wires. Compared to traditional single-ended signaling, differential signaling offers enhanced immunity to electromagnetic interference (EMI). The electromagnetic fields generated by electronic devices during operation may interfere with signal transmission, especially in high-speed data transmission scenarios. Because LVDS uses differential signaling, any external electromagnetic interference will act on both wires simultaneously. The receiving end is only concerned with the voltage difference between the two wires, effectively canceling out most external interference and improving signal integrity and reliability.

[0004] High data transfer rates are another key advantage of LVDS. LVDS is capable of data transfer rates ranging from hundreds of megabits per second (Mbps) to several gigabits per second (Gbps), making it ideal for applications requiring fast data transfer, such as high-definition video transmission and high-speed communications. In modern electronic devices, high-definition displays and cameras are experiencing increasing data transfer demands, and LVDS is able to meet these demands, ensuring that image and video data can be transmitted quickly and accurately.

[0005] like Figure 1The figure shows a traditional LVDS driver. When the input data signal level flips, the drive current flowing through the output matching impedance Rload reverses. The system's DC operating point is susceptible to variations due to process voltage and temperature (PVT). The output common-mode level is sensitive to device mismatches. During normal operation, the common-mode level can be affected by internal and external noise. For these reasons, maintaining a relatively precise output common-mode level is difficult. A shift in the output common-mode level can cause a shift in the output LVDS signal waveform, reducing the quality of the LVDS signal and limiting its transmission speed.

[0006] LVDS also faces a significant problem during transmission, which can also reduce signal quality and thus hinder transmission speed: the problem of "high-frequency component attenuation" during transmission. In actual operation, the two sets of switching MOSFETs in the main driver cannot switch their operating states immediately when the input data signal level flips. The switching MOSFETs require time to turn on and off, and the current flowing through the switching MOSFETs also has a process of decreasing and increasing. As a result, the output LVDS signal cannot flip the level as quickly as a rectangular wave, but has a certain rise / fall time. When the rise / fall time is too long, the LVDS signal will be distorted and inter-symbol interference will occur. This manifests as the loss of high-order harmonics in the frequency domain, that is, the high-frequency components are attenuated during signal transmission. Moreover, the output LVDS signal propagates on a pair of differential transmission lines. Transmission lines have low-pass characteristics. When high-frequency transmission occurs, distributed inductance and distributed capacitance will exist (transmission line theory). This further exacerbates the attenuation of the high-frequency components of the LVDS signal, reducing the quality of the LVDS signal, and thus hindering the improvement of LVDS signal transmission speed. Summary of the Invention

[0007] The main purpose of the present invention is to propose a high-speed LVDS driver to solve two key problems: the dynamic change of the output common-mode level causes the output waveform to shift; the attenuation of the high-frequency component of the signal during transmission causes the output waveform to lose higher harmonics and the inter-symbol interference phenomenon, thereby achieving high-speed transmission of data signals.

[0008] To achieve the above object, the present invention proposes a high-speed LVDS driver, the main structure of which is as follows: Figure 2 As shown, it includes four switch MOS tubes M1, M2, M3, and M4, two 10KΩ resistors, a common-mode feedback circuit composed of operational amplifiers I0 and M5, and two pre-emphasis current sources Ipre.

[0009] like Figure 1As shown in the figure, the main working principle of the high-speed LVDS driver proposed by the present invention is as follows: INN and INP are differential data signals. At time T0, the signal changes, INN is low and INP is high. The current of the top current source Im and the common-mode feedback current source Icm (Im+Icm=3.5mA) passes through M1, Output+, 100Ω load, Output-, M4, and reaches GND from the bottom 3.5mA current source. Through the changes in INN and INP, a 350mV differential output signal is generated on the load. The two 10KΩ resistors extract the common-mode level of Output+ and Output-.

[0010]

[0011] The output common-mode level changes dynamically, causing the output waveform to shift. A deviation amplifier is used to compare the common-mode level with the reference value Vcmref, and the result of the deviation amplifier is fed back to the LVDS driver to achieve the output common-mode level V OUT_CM The specific feedback process is: if the detection result of the common mode detection circuit is the output voltage V Output+ and V Output- The average common mode level V OUT_CM Increases, that is, the voltage at the positive input of the deviation amplifier increases, and the negative input Vcmref remains unchanged, then the output voltage V dev As the gate voltage of the feedback current source PMOS tube M5 increases, the gate-source voltage VGS of M5 decreases, resulting in a decrease in the drain common-mode feedback current Icm, while the current Im of the main drive current source remains unchanged. Therefore, the total drive current I (I = Icm + Im) flowing through the LVDS switch tube decreases, and V OUT_CM decline.

[0012] The high-frequency components of the signal are attenuated during transmission, resulting in the loss of higher harmonics in the output waveform. The two current sources Ipre controlled by the pre-emphasis logic are only turned on within a short time Tn after the T0 moment, increasing the current at the switching moment. When the high-speed data signal DATA flips in level, the pre-emphasis current is superimposed on the main drive current to speed up the state switching of the two pairs of MOS switch tube groups in the LVDS main driver, thereby reducing the rise / fall time when the output LVDS signal level flips. When the data signal DATA level is in a steady state, the pre-emphasis current stops supplying power.

[0013] Figure 3 This is a high-speed LVDS driver circuit of the present invention. It uses a five-tube OTA as an amplifier. The five-tube OTA and M5, Cc, and Rz form a two-stage operational amplifier with Miller compensation. The circuit contains two poles and one zero.

[0014] P1=(gm5 R L C c R out1 ) -1 #(2)

[0015]

[0016] where R L is the load resistance of the secondary op amp, C L is the load capacitance of the secondary op amp, g m5 is the transconductance of PMOS tube M5, R out1 is the output resistance of the five-tube OTA.

[0017] Figure 4 This is the circuit implementation diagram of the pre-emphasis logic. The data signal is buffered by two inverters and enters the XOR gate. The other signal passes through an odd number of inverters to generate a delay of Tn and then enters the XOR gate. After the XOR gate logic, the result XOR_OUT is generated. Figure 5 As shown, the XOR gate output, after increasing the drive capability through an odd and even number of inverters, generates the control signal for Ipre. When the high-speed data signal DATA transitions, the XOR gate output, XOR_OUT, changes from a high level "1" to a low level "0" for the duration of the Tn window.

[0018] In summary, the high-speed LVDS driver of the present invention has the following advantages: 1. The output common-mode level of the high-speed LVDS driver of the present invention is stable, and dynamic changes in the output common-mode level will not cause output waveform deviation. 2. The high-speed LVDS driver of the present invention compensates for the high-frequency components of the signal through pre-emphasis, reducing the attenuation of high-frequency harmonics in the output waveform and improving the quality of the LVDS signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below with reference to the accompanying drawings and examples.

[0020] Figure 1 It is a common LVDS driver structure;

[0021] Figure 2 The high-speed LVDS driver structure of the present invention;

[0022] Figure 3 A structural diagram of a two-stage operational amplifier for stabilizing the output common-mode level used in the present invention;

[0023] Figure 4 A gate circuit diagram for generating pre-emphasis logic used in the present invention;

[0024] Figure 5 This is a waveform diagram of the pre-emphasis logic output in the present invention;

[0025] Figure 6 The loop gain and phase change of the common-mode feedback amplifier of the present invention;

[0026] Figure 7 The transient simulation result of the output common mode level of the present invention;

[0027] Figure 8 This is a time domain analysis diagram of the transient waveform of the pre-emphasized LVDS signal of the present invention; DETAILED DESCRIPTION

[0028] [Example 1]

[0029] The circuit diagram of the embodiment is as follows Figure 3 As shown, the pre-emphasis logic is as follows Figure 4 As shown in Figure 1, the power supply voltage is 3.3V and the input signal frequency is 800MHz. The loop gain and phase changes of the output common-mode feedback amplifier are shown in Figure 1. Figure 6 As shown, the bandwidth is about 34MHz, the low-frequency gain is 97dB, the phase margin is 63 degrees, and the loop stability is good, which can meet the LVDS requirement of keeping the common mode level relatively constant during high-speed transmission. Figure 7 As shown in Figure 1, the LVDS driver can maintain a stable common mode voltage of about 1.25V when transmitting data signals at high speed. Figure 8 As shown, Figure 8 The figure above shows the transient waveform of a common LVDS driver output without pre-emphasis. Figure 8 The figure below shows the transient waveform of the high-speed LVDS driver output under the pre-emphasis of the present invention. It can be seen that the pre-emphasis of the present invention reduces the rise / fall time of the output LVDS signal.

Claims

1. A high-speed LVDS driving circuit, which includes two PMOS inputs M1 and M2, two NMOS inputs M3 and M4, two 10KΩ common-mode level extraction resistors, a common-mode voltage is output stably through an operational amplifier I0 and a PMOS tube M5, and a pre-emphasis function is realized through two current sources Ipre controlled by logic gates. The operational amplifier of the high-speed LVDS driver adopts a five-tube OTA, the output is connected to the gate of M5, the negative end of the operational amplifier is connected to the standard voltage 1.25V, and the positive end is connected to the output of two 10KΩ common-mode extraction circuits. The pre-emphasis circuit of the high-speed LVDS driver is implemented by a logic circuit composed of an inverter and an XOR gate.

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