RGMII interface

Abstract

The invention provides an RGMII interface comprising a frequency division module used for performing frequency division on an input clock to obtain a clock frequency division signal; the signal transmission module comprises a data signal channel and a clock signal channel, and the data signal channel comprises a data delay unit; the clock signal path comprises a clock delay unit and is connected with a clock frequency division signal; and the clock selection module is used for selecting one of the clock frequency division signal and the delay signal thereof under the action of a control signal and outputting the clock frequency division signal and the delay signal to the data delay unit. The method has the beneficial effects that after frequency division is carried out on an input clock, one path is directly input to a clock signal path, and the other path selects one of a clock frequency division signal and a delay signal to be input to a data signal path, so that two sending modes of signal clock edge synchronization or clock edge interval of 2ns between data and the clock are realized; and the delay of 2ns is not realized by a delay unit in a path.

Description

Technical Field

[0001] The present invention relates to the technical field of RGMII interface, and in particular to an RGMII interface. Background Art

[0002] Reduced Gigabit Media Independent Interface (RGMII) is a standard interface for Ethernet communication, commonly used to connect Ethernet controllers and PHY chips. RGMII interfaces use a 4-bit data interface, a 125MHz operating clock, and transmit data on both the rising and falling edges, so the transmission rate can reach 1000Mbps.

[0003] In the RGMII interface, there are two transmission modes:

[0004] First transmission mode: the clock edge interval between RXD and RXC is 2ns;

[0005] Second transmission mode: the clock edges of RXD and RXC are synchronized.

[0006] A digital delay line (DLL) is a circuit element used to adjust signal delay. In the RGMII interface, the delay time of the digital delay line is usually adjusted to make a 2ns delay difference between the clock signal of the clock signal channel and the clock signal of the data signal channel.

[0007] In this solution, the 2ns delay difference is completely dependent on the digital delay line, which means that the performance and reliability of the RGMII interface are highly dependent on the stability and accuracy of the digital delay line. If the digital delay line fails or is unstable, the delay difference may not be accurately achieved, thus affecting the overall performance. Summary of the invention

[0008] In order to solve the above technical problems, the present invention provides a RGMII interface.

[0009] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0010] An RGMII interface, comprising:

[0011] A frequency division module, used for receiving an input clock, performing frequency division processing on the input clock, and obtaining a clock frequency division signal;

[0012] The signal transmission module is used to receive the data signal and the clock signal from the digital circuit and transmit them to the signal output end. The signal transmission module includes:

[0013] a data signal path, the data signal path comprising a data delay unit;

[0014] A clock signal path, the clock signal path comprising a clock delay unit, the clock delay unit being connected to the clock frequency division signal;

[0015] The clock selection module selects one of the clock division signal and the delayed signal of the clock division signal under the action of a control signal, and outputs it to the data delay unit to maintain relative delay or synchronization between the data signal path and the clock signal path.

[0016] Preferably, the frequency division module includes:

[0017] A first trigger, wherein a clock input terminal of the first trigger is connected to the input clock, and an input terminal of the first trigger is connected to an output terminal of the first trigger via a first inverter.

[0018] Preferably, the clock selection module includes:

[0019] A first selector, wherein the control end of the first selector is connected to the control signal, the first input end of the first selector is connected to the clock division signal, the second input end of the first selector is connected to the clock division signal via a second inverter, and the output end of the first selector is connected to the data delay unit.

[0020] Preferably, the data signal path and the clock signal path respectively further include:

[0021] A first synchronization unit, which synchronously receives the data signal and the clock signal output by the digital circuit under the action of the clock frequency division signal;

[0022] A second synchronization unit, wherein the input end of the second synchronization unit is connected to the output end of the first synchronization unit, and the clock input end of the second synchronization unit is connected to the output end of the clock selection module through the corresponding data delay unit or the clock delay unit.

[0023] Preferably, the first synchronization unit comprises:

[0024] a second trigger, wherein a clock input terminal of the second trigger is connected to the clock frequency division signal, and an input terminal of the second trigger is connected to the digital circuit;

[0025] The second synchronization unit comprises:

[0026] A third trigger, wherein the input end of the third trigger is connected to the output end of the second trigger, and the clock input end of the third trigger is connected to the output end of the corresponding data delay unit or the clock delay unit.

[0027] Preferably, the data delay unit comprises: a first data delay unit for transmitting received data, a second data delay unit for transmitting a valid signal of received data;

[0028] The first data delay unit and the second data delay unit respectively include:

[0029] A first fixed delay subunit, connected to the output end of the clock selection module;

[0030] The first adjustable delay subunit is connected to the output end of the first fixed delay subunit and adjusts the delay value under the effect of the delay control signal output by the digital circuit.

[0031] Preferably, the clock delay unit comprises:

[0032] A second fixed delay subunit, connected to the clock frequency division signal;

[0033] The second adjustable delay subunit is connected to the output end of the second fixed delay subunit and adjusts the delay value under the effect of the delay control signal output by the digital circuit.

[0034] Preferably, it also includes:

[0035] The bypass unit, under the action of a bypass signal, selects to output one of the data signal and the clock signal received from the digital circuit, or the data signal and the clock signal processed by the signal transmission module.

[0036] Preferably, it also includes:

[0037] A level conversion unit, used for performing level conversion processing on the signals processed by the data signal path and the clock signal path respectively;

[0038] The driving unit is connected to the level conversion unit and is used to output the signal after level conversion to the signal output terminal.

[0039] Preferably, the digital circuit is further used to output the data signal and the clock signal under the action of the clock frequency division signal.

[0040] The advantages or beneficial effects of the technical solution of the present invention are:

[0041] The present invention divides the input clock of the RGMII interface by setting a frequency division module, wherein one path inputs the divided clock frequency division signal into the clock signal path, and the other path selects one of the clock frequency division signal and the delayed signal of the clock frequency division signal and inputs it into the data signal path, so that the signal clock edge synchronization or the clock edge interval 2ns between the data signal path and the clock signal path are two transmission modes, and the 2ns delay does not rely on the delay unit in the path to be realized, thereby reducing the impact on other modules in the path and improving the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A structural block diagram of the RGMII interface in a preferred embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of the structure of the specific implementation of the RGMII interface in a preferred embodiment of the present invention;

[0044] Figure 3 In a preferred embodiment of the present invention, Figure 2 A schematic diagram of the structure of the specific implementation of the frequency division module and the clock selection module;

[0045] Figure 4 In a preferred embodiment of the present invention, Figure 2 A schematic diagram of the structure of the specific implementation of the signal transmission module;

[0046] Figure 5 In a preferred embodiment of the present invention, Figure 2 A schematic diagram of the structure of the bypass unit, the level conversion unit and the driving unit;

[0047] Figure 6 In a preferred embodiment of the present invention, a waveform diagram of the received data and the received data valid signal at the signal output terminal when the control signal is 0;

[0048] Figure 7 In a preferred embodiment of the present invention, a waveform diagram of the received data and the received data valid signal at the signal output terminal when the control signal is 1;

[0049] Figure 8 It is a structural diagram of a specific implementation of a digital circuit in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0052] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0053] See also Figure 1 In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a RGMII interface is provided, including:

[0054] The frequency division module 1 is used to receive an input clock, perform frequency division processing on the input clock, and obtain a clock frequency division signal CK1, CK1 is used as the synchronization clock of the digital-analog interface;

[0055] The signal transmission module 2 is used to receive the data signal and the clock signal from the digital circuit 4 and transmit them to the signal output end. The signal transmission module 2 includes:

[0056] A data signal path 21, the data signal path 21 includes a data delay unit 211;

[0057] The clock signal path 22 includes a clock delay unit 221.

[0058] The clock delay unit 221 is connected to the clock frequency division signal CK1;

[0059] The clock selection module 3 selects one of the clock division signal CK1 and the delayed signal CK2 of the clock division signal under the action of a control signal edge_sel, and outputs it to the data delay unit 211 to maintain relative delay or synchronization between the data signal path 21 and the clock signal path 22.

[0060] Specifically, in the present embodiment, by setting a frequency division module 1, the input clock of the RGMII interface is divided, wherein one path inputs the divided clock frequency division signal CK1 to the clock signal path 22, and the other path selects one of the clock frequency division signal CK1 and the delayed signal CK2 of the clock frequency division signal and inputs it to the data signal path 21, so that the signal between the data signal path 21 and the clock signal path 22 has two transmission modes: clock edge synchronization or clock edge interval of 2ns, and the 2ns delay does not rely on the delay unit in the path to be realized, thereby reducing the impact on other modules in the path and improving the stability and reliability of the system.

[0061] As a preferred embodiment, wherein Figure 2 and Figure 3 As shown, the frequency division module 1 includes:

[0062] The first trigger DFF1, the clock input end of the first trigger DFF1 is connected to the input clock, the input clock is 500MHz, the input end of the first trigger DFF1 is connected to the output end of the first trigger DFF1 through a first inverter inv1, and the output end of the first trigger DFF1 is connected to the clock selection module 3 through a second inverter inv2.

[0063] Specifically, in this embodiment, the two-division processing is implemented by the first trigger DFF1 and the first inverter. The output terminal (Q) of the trigger is updated according to the value of its input terminal (D) at the rising edge or falling edge of the clock, and the value of the input terminal (D) is inverted by an inverter and output to the output terminal (Q) of the trigger, and superimposed with the updated value of the output terminal (Q) of the trigger, so as to divide the 500MHz clock signal into 250MHz, that is, the clock division signal CK1 is 250MHz. In some embodiments, the first trigger DFF1 is preferably implemented by a D trigger.

[0064] As a preferred embodiment, wherein Figure 2 and Figure 3 As shown, the clock selection module 3 includes:

[0065] The first selector mux1, the control end of the first selector mux1 is connected to the control signal edge_sel, the first input end of the first selector mux1 is connected to the clock division signal CK1, the second input end of the first selector mux1 is connected to the clock division signal CK1 through a second inverter inv2, and the output end of the first selector mux1 is connected to the data delay unit 211.

[0066] Specifically, the RGMII interface includes two transmission modes:

[0067] First transmission mode: the clock edge interval between RXD and RXC is 2ns;

[0068] Second transmission mode: the clock edges of RXD and RXC are synchronized.

[0069] If the control signal edge_sel=0, it indicates the first transmission mode, and the CK3 output by the first selector mux1 is the delayed signal CK2 of the clock frequency division signal. The waveforms of the clock signal RXC and the received data valid signal RXDV at the corresponding signal output end are as follows: Figure 6 As shown, the second-level synchronization unit corresponding to RXD / RXDV uses a clock with an opposite edge to the first-level synchronization unit to beat data, so that RXC needs to be output one cycle later than RXD / RXDV.

[0070] If the control signal edge_sel=1, it indicates the second transmission mode, and the CK3 output by the first selector mux1 is the clock frequency division signal CK1, and the waveforms of the receiving clock signal RXC and the receiving data valid signal RXDV at the corresponding signal output end are as follows: Figure 7 As shown, the second-level synchronization unit corresponding to RXD / RXDV uses the clock beat data with the same edge as the first-level synchronization unit, so that RXC and RXD / RXDV are output after being aligned in the same cycle.

[0071] Specifically, in this embodiment, a selector is used to select one of the outputs of the clock division signal CK1 and the delay signal CK2 of the clock division signal, thereby controlling the two transmission modes of the RGMII interface, so that the 2ns delay does not depend on the digital delay line (DLL) of the delay unit in the data signal path 21, thereby improving the stability and reliability of the system.

[0072] As a preferred embodiment, the data signal path 21 and the clock signal path 22 respectively further include:

[0073] The first synchronization unit (not shown) synchronously receives the data signal and the clock signal output by the digital circuit 4 under the action of the clock frequency division signal CK1;

[0074] A second synchronization unit (not shown in the figure), the input end of the second synchronization unit is connected to the output end of the first synchronization unit, and the clock input end of the second synchronization unit is connected to the output end of the clock selection module 3 through the corresponding data delay unit 211 or clock delay unit 221.

[0075] In some embodiments, the signal transmission module 2 includes a total of six signal paths, of which the data signal path 21 includes five paths, namely, reserve_rxd[3:0] and reserve_rxdv corresponding to the output of the transmission digital circuit 4; the clock signal path 22 includes one path, namely, reserve_rxc corresponding to the output of the transmission digital circuit 4. The analog circuits of the six signal paths use all consistent IO circuits to output the signal output by the digital circuit 4 to the signal output terminal PAD, and the signal output terminal PAD includes RXD[3:0], RXDV, and RXC.

[0076] Furthermore, each signal path is provided with two-stage synchronization units. For each signal path, the first synchronization unit is used to synchronize the data of the digital circuit 4; the second synchronization unit is used to synchronize the delay control of the output of the digital circuit 4, and the clock of the second synchronization unit determines the phase of the output data on the signal output terminal PAD, thereby realizing the control of the two transmission modes.

[0077] As a preferred implementation, the first synchronization unit includes:

[0078] A second trigger, wherein a clock input terminal of the second trigger is connected to the clock frequency division signal CK1, and an input terminal of the second trigger is connected to the digital circuit 4;

[0079] The second synchronization unit comprises:

[0080] A third trigger, wherein an input end of the third trigger is connected to an output end of the second trigger, and a clock input end of the third trigger is connected to an output end of a corresponding data delay unit 211 or a clock delay unit 221 .

[0081] Specifically, in this embodiment, the first synchronization unit and the second synchronization unit are both implemented by a trigger. In some implementations, the trigger is preferably a D trigger.

[0082] In the data signal path 21 for transmitting reserve_rxd[3:0], the second trigger is the second-first trigger DFF21, and the third trigger is the third-first trigger DFF31. The clock input end of the second-first trigger DFF21 is connected to the clock frequency division signal CK1, the input end of the second-first trigger DFF21 is connected to the reserve_rxd[3:0] output by the digital circuit 4, the output end of the second-first trigger DFF21 is connected to the input end of the third-first trigger DFF31, the clock input end of the third-first trigger DFF31 is connected to the output of the data delay unit 211, and the output end of the third-first trigger DFF31 is level-converted and driven to output to RXD[3:0] of the signal output end PAD.

[0083] Similarly, in the data signal path 21 for transmitting reserve_rxdv, the second trigger is the second flip-flop DFF22, and the third trigger is the third flip-flop DFF32. The clock input end of the second flip-flop DFF22 is connected to the clock frequency division signal CK1, the input end of the second flip-flop DFF22 is connected to the reserve_rxdv output by the digital circuit 4, the output end of the second flip-flop DFF22 is connected to the input end of the third flip-flop DFF32, the clock input end of the third flip-flop DFF32 is connected to the output of the data delay unit 211, and the output end of the third flip-flop DFF32 is level-converted and driven to output to RXDV of the signal output end PAD.

[0084] In the clock signal path 22 for transmitting reserve_rxc, the second trigger is the second three-trigger DFF23, and the third trigger is the third three-trigger DFF33. Among them, the clock input end of the second three-trigger DFF23 is connected to the clock frequency division signal CK1, the input end of the second three-trigger DFF23 is connected to the reserve_rxdv output by the digital circuit 4, the output end of the second three-trigger DFF23 is connected to the input end of the third three-trigger DFF33, the clock input end of the third three-trigger DFF33 is connected to the output of the clock delay unit 221, and the output end of the third three-trigger DFF33 is level-converted and driven to output to RXC of the signal output end PAD.

[0085] The data delay unit 211 is used to delay the clock output by the clock selection module 3, ie, the clock frequency division signal CK1 or the delayed signal CK2 of the clock frequency division signal; the clock delay unit 221 is used to delay the clock frequency division signal CK1.

[0086] Further, if the clock output by the clock selection module 3 is the clock frequency division signal CK1, the data delay unit 211 and the clock delay unit 221 both delay the clock frequency division signal CK1;

[0087] If the clock output by the clock selection module 3 is the delayed signal CK2 of the clock frequency division signal, the data delay unit 211 and the clock delay unit 221 differ by a delay signal, ie, an interval of 2 ns.

[0088] In some implementations, the data delay unit 211 and the clock delay unit 221 implement delay control according to the digital circuit 4 .

[0089] As a preferred embodiment, wherein Figure 4 As shown, the data delay unit 211 includes: a first data delay unit 211A for transmitting received data, and a second data delay unit 211B for transmitting a valid signal of received data;

[0090] The first data delay unit 211A and the second data delay unit 211B respectively include:

[0091] A first fixed delay subunit, connected to the output end of the clock selection module 3;

[0092] The first adjustable delay subunit is connected to the output end of the first fixed delay subunit, and adjusts the delay value under the effect of the delay control signal output by the digital circuit 4 .

[0093] Specifically, the first data delay unit 211A includes:

[0094] A first fixed delay subunit 2111A is connected to the output end of the clock selection module 3;

[0095] The first adjustable delay subunit 2112A is connected to the output end of the first fixed delay subunit 2111A, and adjusts the delay value under the effect of the delay control signal output by the digital circuit 4 .

[0096] The second data delay unit 211B includes:

[0097] The first second fixed delay subunit 2111B is connected to the output end of the clock selection module 3;

[0098] The first second adjustable delay sub-unit 2112B is connected to the output end of the first second fixed delay sub-unit 2111B, and adjusts the delay value under the effect of the delay control signal output by the digital circuit 4 .

[0099] As a preferred embodiment, the clock delay unit 221 includes:

[0100] The second fixed delay subunit 2211 is connected to the clock frequency division signal CK1;

[0101] The second adjustable delay subunit 2212 is connected to the output end of the second fixed delay subunit 2211 , and adjusts the delay value under the effect of the delay control signal output by the digital circuit 4 .

[0102] Specifically, in this embodiment, there are two delay subunits in series between the first-level synchronization unit and the second-level synchronization unit. The first delay subunit is a fixed delay, and the second delay subunit is a delay line with adjustable delay. The fixed delay subunit is used to protect the sampling of the second-level synchronization unit, ensure that the second synchronization unit has enough preparation time for sampling, avoid interference and errors in the sampling process, and improve the accuracy and reliability of the synchronization unit. The adjustable delay unit is used to provide more possibilities for the delay of RXD / RXC in addition to the two transmission mode selections of "RXD / RXC same edge" and "RXD / RXC staggered 2ns" specified by the protocol, meet the transmission mode selection specified by different protocols, and can also be flexibly adjusted according to specific needs. In principle, RXD / RXC can be adjusted from staggered 0ns to staggered 4ns throughout the process, meet the delay requirements in different application scenarios, provide greater flexibility and adjustability, and thus improve the adaptability and compatibility of the system.

[0103] As a preferred embodiment, wherein Figure 2 and Figure 5 As shown, it also includes:

[0104] The bypass unit 5 , under the action of a bypass signal (bypass), selects to output one of the data signal and the clock signal received from the digital circuit 4 , or the data signal and the clock signal processed by the signal transmission module 2 .

[0105] Specifically, in this embodiment, the data signal and clock signal output by the digital circuit 4, namely, reserve_rxd[3:0], reserve_rxdv, and reserve_rxc, are directly output to the bypass unit 5, and the other is processed by the signal transmission module 2 and output to the bypass unit 5. The bypass unit 5 directly selects one of the two inputs to output to the signal output terminal PAD.

[0106] Furthermore, if bypass=0, the bypass unit 5 selects the data signal and clock signal output by the digital circuit 4 and outputs the signal after being processed by the signal transmission module 2 to the signal output terminal PAD; if bypass=1, the bypass unit 5 directly outputs the data signal and clock signal output by the digital circuit 4 to the signal output terminal PAD, bypassing all the 500M and 250M clock logics. This facilitates the multiplexing of PAD and directly outputs the test signal inside the chip to the pin of the signal output terminal.

[0107] Furthermore, in some embodiments, the bypass unit 5 can be implemented by a selector, that is, a selector is provided for each path. Specifically, it includes:

[0108] The second selector mux51, under the action of the bypass signal, selects one of the two outputs, reserve_rxd[3:0] output by the digital circuit 4 and mid_rxd[3:0] output by the third flip-flop DFF31, for output;

[0109] The third selector mux52 selects and outputs one of the reserve_rxdv output by the digital circuit 4 and the mid_rxdv output by the third flip-flop DFF32 under the action of the bypass signal;

[0110] The fourth selector mux53 selects and outputs one of the reserve_rxc output by the digital circuit 4 and the Mid_rxc output by the third flip-flop DFF33 under the action of the bypass signal.

[0111] As a preferred embodiment, wherein Figure 2 and Figure 5 As shown, it also includes:

[0112] The level conversion unit 6 is used to perform level conversion processing on the signals processed by the data signal path 21 and the clock signal path 22 respectively;

[0113] The driving unit 7 is connected to the level conversion unit 6 and is used to output the signal after the level conversion process to the signal output terminal.

[0114] Specifically, in this embodiment, the level conversion unit 6 includes a first level conversion unit 61, a second level conversion unit 62, and a third level conversion unit 63, which respectively perform level conversion processing on the three selector output terminal signals in the bypass unit 5;

[0115] The driving unit 7 includes a first driving unit 71 , a second driving unit 72 , and a third driving unit 73 , which respectively drive the signals output by the three level conversion units to the signal output terminals corresponding to RXD[3:0], RXDV, and RXC.

[0116] As a preferred implementation, the digital circuit 4 is further configured to output a data signal and a clock signal under the action of the clock frequency division signal CK1, wherein the data signal includes reserve_rxd[3:0] and reserve_rxdv, and the clock signal includes reserve_rxc.

[0117] In the above preferred embodiment, the input clock of the RGMII interface is 500 MHz, which is transmitted from the physical layer (PHY) interface IP or the serializer / deserializer (Serdes) interface IP to the clock input of the RGMII interface via a special network special net.

[0118] Further, such as Figure 8 As shown, the digital circuit 4 also includes:

[0119] After the 25M clock is processed by the phase-locked loop 81 (PLL), one path is input to the receiving phase interpolation module 82 (RX PI) for processing, and the other path is input to the serial clock phase interpolation module 83 (SSC PI). The serial clock phase interpolation module 83 performs interpolation processing under the action of ssc piclk and ssc pi code; after being processed by the receiving phase interpolation module 82 and the serial clock phase interpolation module 83 respectively, it is output to the fifth selector 84, the fifth selector 84 selects one of the two under the action of rgmii_clk_sel, and outputs it to the clock gating module 85 (gate), the clock gating module 85 performs threshold control under the enable control of rgmii_clk_en, and then outputs the above-mentioned 500M input clock after being divided by the first data clock divider 86.

[0120] Furthermore, it also includes: a clock spread spectrum control module 87, which is used to output the above-mentioned ssc pi clk and ssc pi code signals under the action of the 500M input clock and rx pi code, and input them into the serial clock phase interpolation module 83.

[0121] Furthermore, it also includes: a second data clock divider 88, a serial synchronizer first-in first-out queue (SerialSynchronous Controller FIFO, SSC FIFO) 89, a sixth selector 810, a seventh selector 811, and a FIFO&CLK control module 812;

[0122] The second data clock divider 88 divides the 500M input clock output by the first data clock divider 86 after the division again; after the division, it is output to the SSC FIFO, and the SSC FIFO processes the data transmitted by GMII under the action of rx_clk, and outputs it to the seventh selector 811; the seventh selector 811 selects one of the outputs between the data output by the SSC FIFO and the data transmitted by GMII under the action of ssc_en, and outputs it to the FIFO&CLK control module 812; the sixth selector 810 selects one of the outputs between rx_clk and the signal output by the second data clock divider 88 under the action of ssc_en, and outputs it to the FIFO&CLK control module 812; the FIFO&CLK control module 812 obtains reserve_rxd[3:0], reserve_rxdv, and reserve_rxc according to the data output by the seventh selector 811 under the action of the clock division signal CK1 and the output clock of the sixth selector 810.

[0123] In some implementations, the clock output from the RGMII interface is always transmitted using an analog power supply to avoid clock uncertainty caused by digital power supply noise.

[0124] In some embodiments, the above-mentioned phase-locked loop 81, receiving phase interpolation module 82, serial clock phase interpolation module 83, fifth selector 84, clock gating module 85, first data clock divider 86, as well as the division module 1, clock selection module 3, signal transmission module 2, and bypass unit 5 all use a local analog low-voltage power supply, which can provide a lower operating voltage, thereby reducing the power consumption of the entire interface; at the same time, the use of a local analog low-voltage power supply can reduce noise and interference in the signal transmission process, improve the integrity and reliability of the signal, and improve the system's anti-interference (EMI) capability.

[0125] The advantages or beneficial effects of adopting the above technical solution are: the present invention divides the input clock of the RGMII interface by setting a frequency division module, wherein one path inputs the divided clock frequency division signal into the clock signal path, and the other path selects one of the clock frequency division signal and the delayed signal of the clock frequency division signal and inputs it into the data signal path, so that the signal clock between the data signal path and the clock signal path can be transmitted in two modes: synchronous clock edge or clock edge interval of 2ns, and the 2ns delay will not rely on the delay unit in the path to be realized, thereby reducing the impact on other modules in the path and improving the stability and reliability of the system.

[0126] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. An RGMII interface, characterized in that: include: A frequency division module, used for receiving an input clock, performing frequency division processing on the input clock, and obtaining a clock frequency division signal; The signal transmission module is used to receive the data signal and the clock signal from the digital circuit and transmit them to the signal output end. The signal transmission module includes: a data signal path, the data signal path comprising a data delay unit; A clock signal path, the clock signal path comprising a clock delay unit, the clock delay unit being connected to the clock frequency division signal; The clock selection module selects one of the clock division signal and the delayed signal of the clock division signal under the action of a control signal, and outputs it to the data delay unit to maintain relative delay or synchronization between the data signal path and the clock signal path.

2. The RGMII interface according to claim 1, characterized in that: The frequency division module comprises: A first trigger, wherein a clock input terminal of the first trigger is connected to the input clock, and an input terminal of the first trigger is connected to an output terminal of the first trigger via a first inverter.

3. The RGMII interface according to claim 1, characterized in that: The clock selection module comprises: A first selector, wherein the control end of the first selector is connected to the control signal, the first input end of the first selector is connected to the clock division signal, the second input end of the first selector is connected to the clock division signal via a second inverter, and the output end of the first selector is connected to the data delay unit.

4. The RGMII interface according to claim 1, characterized in that: The data signal path and the clock signal path respectively further include: A first synchronization unit, which synchronously receives the data signal and the clock signal output by the digital circuit under the action of the clock frequency division signal; A second synchronization unit, wherein the input end of the second synchronization unit is connected to the output end of the first synchronization unit, and the clock input end of the second synchronization unit is connected to the output end of the clock selection module through the corresponding data delay unit or the clock delay unit.

5. The RGMII interface according to claim 1, characterized in that: The first synchronization unit comprises: a second trigger, wherein a clock input terminal of the second trigger is connected to the clock frequency division signal, and an input terminal of the second trigger is connected to the digital circuit; The second synchronization unit comprises: A third trigger, wherein the input end of the third trigger is connected to the output end of the second trigger, and the clock input end of the third trigger is connected to the output end of the corresponding data delay unit or the clock delay unit.

6. The RGMII interface according to claim 1, characterized in that: The data delay unit comprises: a first data delay unit for transmitting received data, and a second data delay unit for transmitting a valid signal of received data; The first data delay unit and the second data delay unit respectively include: A first fixed delay subunit, connected to the output end of the clock selection module; The first adjustable delay subunit is connected to the output end of the first fixed delay subunit and adjusts the delay value under the effect of the delay control signal output by the digital circuit.

7. The RGMII interface according to claim 1, characterized in that: The clock delay unit comprises: A second fixed delay subunit, connected to the clock frequency division signal; The second adjustable delay subunit is connected to the output end of the second fixed delay subunit and adjusts the delay value under the effect of the delay control signal output by the digital circuit.

8. The RGMII interface according to claim 1, characterized in that: Also includes: The bypass unit, under the action of a bypass signal, selects to output one of the data signal and the clock signal received from the digital circuit, or the data signal and the clock signal processed by the signal transmission module.

9. The RGMII interface according to claim 1, characterized in that: Also includes: A level conversion unit, used for performing level conversion processing on the signals processed by the data signal path and the clock signal path respectively; The driving unit is connected to the level conversion unit and is used to output the signal after level conversion to the signal output terminal.

10. The RGMII interface according to claim 1, characterized in that: The digital circuit is also used to output the data signal and the clock signal under the action of the clock frequency division signal.

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