DMX and return-to-zero code synchronous output method and device

Abstract

The invention discloses a DMX and return-to-zero code synchronous output method and device, and the method comprises the steps: reading a plurality of paths of DMX data in one combined frame every time a new frame sequence generation pulse signal is received according to the frame sequence of a plurality of combined frames from the receiving of a first frame sequence generation pulse signal; and reading a plurality of paths of return-to-zero code data in one combined frame every time a new frame sequence generation pulse signal is received according to the frame sequences of the plurality of combined frames from the time when the second frame sequence generation pulse signal is received. According to the invention, the pulse signal is generated according to the frame sequence sent periodically to process the combined frame, and synchronous output of the DMX signal and the return-to-zero code signal is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of audio control, and in particular to a DMX and return-to-zero code synchronous output method and device. Background Art

[0002] In the existing technology, when it is necessary to output DMX signals and return-to-zero code signals at the same time, due to the different characteristics of the two signals, the signal output may be out of sync, resulting in the control equipment (such as lighting, sound system) unable to respond correctly. In addition, if the received data frames do not arrive in the correct order, the output signal will be wrong or chaotic. In the final waveform output process, DMX signals and return-to-zero code signals have different encoding rules and transmission formats. If appropriate conversion is not performed, the two signals of DMX and return-to-zero code cannot be correctly and synchronously expressed. Summary of the invention

[0003] The embodiment of the present invention provides a method and device for synchronously outputting DMX and return-to-zero code, which generates a pulse signal according to a periodically sent frame sequence to process a combined frame, thereby ensuring synchronous output of the DMX and return-to-zero code signals.

[0004] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application provides a DMX and return-to-zero code synchronous output method, comprising:

[0005] Continuously acquiring a plurality of combined frames sent according to a preset period; the combined frames include a frame sequence, a plurality of DMX data channels, and a plurality of return-to-zero code data channels;

[0006] Starting from receiving the first frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, each time a new frame sequence generating pulse signal is received, a plurality of channels of DMX data in the combined frame are read; the plurality of channels of DMX data in the plurality of combined frames are read in sequence to continuously generate a DMX output waveform;

[0007] Starting from receiving the second frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, each time a new frame sequence generating pulse signal is received, a plurality of return-to-zero code data in the combined frame are read; the plurality of return-to-zero code data of the plurality of combined frames are read in sequence, and the return-to-zero code output waveform is continuously generated;

[0008] Starting from the generation time of the DMX output waveform, the DMX output waveform is output at the corresponding port; starting from the generation time of the return-to-zero code output waveform, the return-to-zero code output waveform is output at the corresponding port.

[0009] In a possible implementation manner of the first aspect, starting from receiving the second frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, reading a plurality of return-to-zero code data in one of the combined frames each time a new frame sequence generating pulse signal is received, specifically includes:

[0010] Starting from receiving the second frame sequence generating pulse signal, the plurality of combined frames are sorted in ascending order of the frame sequence;

[0011] According to the sorting result and the preset return-to-zero code parameter duration, a plurality of return-to-zero code data in the combined frame are read each time a new frame sequence generating pulse signal is received.

[0012] In a possible implementation manner of the first aspect, reading a plurality of return-to-zero code data in a combined frame each time a new frame sequence generating pulse signal is received specifically includes:

[0013] According to the T0H parameter duration, the T0L parameter duration, the T1H parameter duration and the T1L parameter duration, a plurality of return-to-zero code data in one of the combined frames are converted into return-to-zero code output sub-waveforms.

[0014] In a possible implementation manner of the first aspect, converting the plurality of return-to-zero code data in one combined frame into a return-to-zero code output sub-waveform according to a T0H parameter duration, a T0L parameter duration, a T1H parameter duration, and a T1L parameter duration specifically includes:

[0015] Setting a first timer, a second timer and a third timer with consistent interruption periods and staggered triggering time points;

[0016] The difference between the triggering time point of the second timer and the triggering time point of the first timer is set to the T0H parameter duration;

[0017] The difference between the triggering time point of the third timer and the triggering time point of the first timer is set to the T1H parameter duration;

[0018] At a triggering time point of the first timer, a triggering time point of the second timer, and a triggering time point of the third timer, reading level values ​​of a plurality of channels of return-to-zero code data in one of the combined frames;

[0019] A return-to-zero code output sub-waveform is obtained according to all level values.

[0020] In a possible implementation manner of the first aspect, obtaining a return-to-zero code output sub-waveform according to all level values ​​specifically includes:

[0021] If three consecutive level values ​​are 110, convert them to 1;

[0022] If three consecutive level values ​​are 100, convert them to 0.

[0023] In a possible implementation of the first aspect, starting from receiving the first frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, reading a plurality of channels of DMX data in a combined frame each time a new frame sequence generating pulse signal is received, specifically includes:

[0024] Starting from receiving the first frame sequence generating pulse signal, the plurality of combined frames are sorted in ascending order of the frame sequence;

[0025] According to the sorting result and the preset DMX parameters, each time a new frame sequence is received to generate a pulse signal, several channels of DMX data in the combined frame are read.

[0026] In a possible implementation of the first aspect, reading a plurality of channels of DMX data in a combined frame each time a pulse signal is generated by receiving a new frame sequence according to the sorting result and the preset DMX parameters specifically includes:

[0027] According to the baud rate, the start bit and the stop bit, a plurality of channels of DMX data in one combined frame are converted into DMX output sub-waveforms.

[0028] In a possible implementation manner of the first aspect, converting the plurality of channels of DMX data in a combined frame into a DMX output sub-waveform according to the baud rate, the start bit, and the stop bit specifically includes:

[0029] Set the interrupt period to the fourth timer of the baud rate countdown;

[0030] Converting a plurality of channels of DMX data in one of the combined frames into a binary bit stream;

[0031] Inserting a start bit in front of the binary bit stream and inserting a stop bit after the binary bit stream;

[0032] Each time the fourth timer is interrupted, the binary bit stream is pushed bit by bit to obtain a DMX output sub-waveform.

[0033] In a possible implementation manner of the first aspect, inserting a start bit in front of the binary bit stream and inserting a stop bit after the binary bit stream specifically includes:

[0034] A start bit 0 is inserted in front of the binary bit stream, and a stop bit 11 is inserted after the binary bit stream.

[0035] A second aspect of an embodiment of the present application provides a DMX and return-to-zero code synchronous output device, comprising:

[0036] A frame rate control module, used to periodically output a frame sequence to generate a pulse signal;

[0037] A receiving module, used for continuously acquiring a plurality of combined frames sent according to a preset period; the combined frames include a frame sequence, a plurality of DMX data and a plurality of return-to-zero code data;

[0038] The DMX module is used to start from receiving the first frame sequence generating pulse signal, and read a plurality of channels of DMX data in a said combined frame each time a new frame sequence generating pulse signal is received according to the frame sequence of the said plurality of combined frames; sequentially read the plurality of channels of DMX data of the said plurality of combined frames, and continuously generate a DMX output waveform;

[0039] The return-to-zero code module is used to read a plurality of return-to-zero code data in one of the combined frames each time a new frame sequence generating pulse signal is received, starting from receiving the second frame sequence generating pulse signal; sequentially read a plurality of return-to-zero code data of the plurality of combined frames, and continuously generate a return-to-zero code output waveform;

[0040] The output module is used to output the DMX output waveform at the corresponding port starting from the generation time of the DMX output waveform; and to output the return-to-zero code output waveform at the corresponding port starting from the generation time of the return-to-zero code output waveform.

[0041] Compared with the prior art, the embodiment of the present invention provides a method and device for synchronous output of DMX and return-to-zero code. The DMX output waveform is generated from the first frame sequence pulse signal, while the return-to-zero code output waveform is generated from the second frame sequence pulse. This can effectively adjust the relative time relationship of the two signals and reduce the impact of delay. The unified frame sequence controls the processing order of the combined frames, and the reading of DMX data and return-to-zero code data, ensuring the synchronous output of the two signals; the arrangement of the processing time according to the frame sequence pulse signal also ensures the synchronous output of the DMX signal and the return-to-zero code signal, improving the consistency and accuracy of the signal output, reducing the risk of signal interference, and improving the overall efficiency of the system. This is very important for applications that require precise control of lighting, sound, and other stage equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a flowchart of a method for synchronously outputting DMX and return-to-zero code according to an embodiment of the present invention;

[0043] Figure 2 is a schematic diagram of a process of generating a frame sequence provided by an embodiment of the present invention;

[0044] Figure 3A schematic diagram of a process of converting return-to-zero code data in a combined frame into a return-to-zero code waveform is provided in one embodiment of the present invention;

[0045] Figure 4 The present invention provides a schematic diagram of a process of converting DMX data in a combined frame into a DMX waveform according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] To solve the above problems, see Figure 1 An embodiment of the present invention provides a method for synchronously outputting DMX and return-to-zero code, comprising:

[0048] S10, continuously acquiring a plurality of combined frames sent according to a preset period; the combined frames include a frame sequence, a plurality of DMX data and a plurality of return-to-zero code data. The frame sequence generation process can be referred to Figure 2 .

[0049] S11, starting from receiving the first frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, reading a plurality of channels of DMX data in the combined frame each time a new frame sequence generating pulse signal is received; sequentially reading a plurality of channels of DMX data in the plurality of combined frames, and continuously generating a DMX output waveform.

[0050] S12. Starting from receiving the second frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, reading a plurality of return-to-zero code data in one of the combined frames each time receiving a new frame sequence generating pulse signal; reading the plurality of return-to-zero code data of the plurality of combined frames in sequence, and continuously generating a return-to-zero code output waveform.

[0051] S13, starting from the generation time of the DMX output waveform, the DMX output waveform is output at the corresponding port; starting from the generation time of the return-to-zero code output waveform, the return-to-zero code output waveform is output at the corresponding port.

[0052] The above process can be used to achieve the synchronous output of DMX (Digital Multiplex) signal and return-to-zero (RZ) signal:

[0053] S10 continuously receives data streams from the outside, which contain a certain number of combined frames. Each combined frame contains necessary information, such as frame sequence, DMX data and return-to-zero code data. This step is to ensure that the input data stream of the system is continuous and sent at predetermined time intervals, which is very important for real-time control.

[0054] It should be noted that in Figure 2 In the combined frame shown, channels 1-6 are dmx data outputs, channels 7-8 are return-to-zero code data outputs. The combined frame can be pre-made by software and output in bin file format.

[0055] S11 starts to generate pulse signals from the first frame sequence received, and then begins to parse the DMX data in each combined frame and convert it into a DMX output waveform. DMX data is usually used to control stage lighting, special effects equipment, etc. By generating a DMX output waveform, it can ensure that these devices work in the intended way.

[0056] S12 starts with the second frame sequence pulse signal received, and the system begins to parse the return-to-zero code data in each combined frame and convert it into a return-to-zero code output waveform. Return-to-zero code is a special encoding method that returns to zero level at the end of each signal bit. This encoding method helps to reduce the cumulative error in signal transmission. The return-to-zero code output waveform can be used to control certain devices that require return-to-zero code signals.

[0057] After S13 generates the DMX and return-to-zero code output waveforms, the system will output these two signals on the corresponding ports. Outputting these two signals enables external devices to receive them and perform corresponding actions according to the received signals.

[0058] The above solution can ensure that DMX signals and return-to-zero signals can be correctly parsed and output synchronously. This is very important in many occasions, such as in stage lighting control systems, where accurate time synchronization can ensure perfect coordination of lighting effects and other special effects equipment. In addition, the use of return-to-zero codes helps reduce interference and errors in signal transmission, thereby improving the reliability and stability of the overall system.

[0059] Exemplarily, starting from receiving the second frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, reading a plurality of return-to-zero code data in one of the combined frames each time a new frame sequence generating pulse signal is received, specifically includes:

[0060] Starting from receiving the second frame sequence generating pulse signal, the plurality of combined frames are sorted in ascending order of the frame sequence.

[0061] According to the sorting result and the preset return-to-zero code parameter duration, a plurality of return-to-zero code data in the combined frame are read each time a new frame sequence generating pulse signal is received.

[0062] The processing of return-to-zero code data starts from the second frame sequence (i.e. the second set of data) received. The first frame sequence is usually used to address the delay problem of synchronous output, and the actual processing of return-to-zero code data starts from the second frame sequence. By setting the data to be processed from the second frame sequence, the system can be ensured to run stably, avoiding the impact caused by the instability in the initialization phase, and ensuring synchronous output with other misaligned DMX data.

[0063] All received combined frames are sorted in ascending order according to their frame sequence. This ensures that the system processes the data in the correct order. This is to ensure that the output of the return-to-zero code data is in time order, which is crucial to maintaining data accuracy and consistency.

[0064] Each time a new frame sequence is received to generate a pulse signal, the return-to-zero code data in the next combined frame is read according to the already sorted combined frame sequence and the preset return-to-zero code parameter duration. This ensures that the return-to-zero code data is read and processed in the correct timing, thereby ensuring the accuracy of the output.

[0065] In this way, the system can process the return-to-zero code data efficiently and accurately, ensuring that the output waveform meets expectations, thereby achieving good control effects.

[0066] Exemplarily, the step of reading a plurality of return-to-zero code data in a combined frame each time a new frame sequence generating pulse signal is received specifically includes:

[0067] According to the T0H parameter duration, the T0L parameter duration, the T1H parameter duration and the T1L parameter duration, a plurality of return-to-zero code data in one of the combined frames are converted into return-to-zero code output sub-waveforms.

[0068] See also Figure 3 Exemplarily, the converting of the return-to-zero code data of several channels in the combined frame into a return-to-zero code sub-waveform according to the T0H parameter duration, the T0L parameter duration, the T1H parameter duration and the T1L parameter duration specifically includes:

[0069] Set a first timer, a second timer and a third timer with consistent interruption periods and staggered triggering time points.

[0070] The difference between the triggering time point of the second timer and the triggering time point of the first timer is set to the T0H parameter duration.

[0071] The difference between the triggering time point of the third timer and the triggering time point of the first timer is set to the T1H parameter duration.

[0072] At the triggering time point of the first timer, the triggering time point of the second timer and the triggering time point of the third timer, the level values ​​of several channels of return-to-zero code data in one of the combined frames are read.

[0073] A return-to-zero code output sub-waveform is obtained according to all level values.

[0074] The following is a specific example to illustrate the conversion process:

[0075] A) Figure 3 As shown, three timers (a first timer, a second timer and a third timer) are defined, whose interrupt cycles are consistent, but whose triggering time points are staggered. The second timer timer2 lags behind the first timer timer1 by T0H, and the third timer timer3 lags behind timer1 by T1H.

[0076] B) Data conversion. For example, if you want to send the three-bit data 101, first convert it into 9-bit data such as 110100110, where 1 corresponds to 110 and 0 corresponds to 100.

[0077] C) At the interruption moment of timer1, the first bit of data "1" of 110 is pushed to the GPIO interface, and then at the interruption moment of timer2, the second bit of data "1" of 110 is pushed to the GPIO interface, and at the interruption moment of timer3, the third bit of data "0" of 110 is pushed to the GPIO interface.

[0078] D) Through the above process, 0 and 1 can be converted into a return-to-zero waveform and sent out. More data just repeats the above process because all data is composed of 0 and 1.

[0079] Exemplarily, obtaining a return-to-zero code output sub-waveform according to all level values ​​specifically includes:

[0080] If three consecutive level values ​​are 110, convert them to 1;

[0081] If three consecutive level values ​​are 100, convert them to 0.

[0082] Exemplarily, starting from receiving the first frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, reading a plurality of channels of DMX data in a said combined frame each time a new frame sequence generating pulse signal is received, specifically includes:

[0083] Starting from receiving the first frame sequence generating pulse signal, the plurality of combined frames are sorted in ascending order of the frame sequence;

[0084] According to the sorting result and the preset DMX parameters, each time a new frame sequence is received to generate a pulse signal, several channels of DMX data in the combined frame are read.

[0085] Starting from the receipt of the first frame sequence and generating a pulse signal, this means that the processing of DMX data starts from the receipt of the first frame sequence (i.e. the first set of data). This is the starting point of the entire processing flow. By setting the data processing to start from the first frame sequence, it can be ensured that the system can immediately start processing the received data, thereby achieving a fast response. More importantly, the sequential processing of DMX data according to the frame sequence and the start of processing of the DMX data by generating a pulse signal according to the frame sequence can maintain the same processing principle as the return-to-zero code data that is also processed sequentially according to the frame sequence and starts processing by generating a pulse signal according to the frame sequence, effectively controlling the synchronization of the output waveform. That is, by triggering the reading of new data by a pulse signal, precise synchronization with other system components can be achieved.

[0086] In this way, the system can process DMX data efficiently and accurately, ensuring that the output waveform meets expectations, thereby achieving good control effects.

[0087] Exemplarily, the step of reading a plurality of channels of DMX data in a combined frame each time a pulse signal is generated by receiving a new frame sequence according to the sorting result and the preset DMX parameters specifically includes:

[0088] According to the baud rate, the start bit and the stop bit, a plurality of channels of DMX data in one combined frame are converted into DMX output sub-waveforms.

[0089] Exemplarily, the converting of several channels of DMX data in one combined frame into DMX output sub-waveforms according to the baud rate, the start bit and the stop bit specifically includes:

[0090] Set the interrupt period to the fourth timer of the baud rate countdown;

[0091] Converting a plurality of channels of DMX data in one of the combined frames into a binary bit stream;

[0092] A start bit is inserted in front of the binary bit stream, and a stop bit is inserted in the back of the binary bit stream.

[0093] Each time the fourth timer is interrupted, the binary bit stream is pushed bit by bit to obtain a DMX output sub-waveform.

[0094] In DMX data, there are generally parameter configurations: break duration, mab duration, baud rate (usually 250000bps, 500000bps or other configurations based on chip parameters), start bit is 1 bit, stop bit is 2 bits, and data bit is 8 bits.

[0095] The following is a specific example to illustrate the conversion process:

[0096] A) First obtain the data to be output, by byte, for example, you need to send 0xA2 (hexadecimal).

[0097] B) Convert 0xA2 into a binary bit stream and get b'10100010.

[0098] C) Dmx data requires a start bit (0) and two stop bits (1), so inserting them into the original data gives b'01010001011.

[0099] D) Configure timer4 (the fourth timer) to fix the interrupt period to 1 / baud rate. Each time an interrupt occurs, the data obtained in step C is pushed to the GPIO interface bit by bit, so that a DMX waveform can be generated.

[0100] Exemplarily, inserting a start bit in front of the binary bit stream and inserting a stop bit after the binary bit stream specifically includes:

[0101] A start bit 0 is inserted in front of the binary bit stream, and a stop bit 11 is inserted after the binary bit stream.

[0102] Compared with the prior art, the embodiment of the present invention provides a method for synchronously outputting DMX and return-to-zero code, in which the DMX output waveform is generated from the first frame sequence pulse signal, and the return-to-zero code output waveform is generated from the second frame sequence pulse, so that the relative time relationship between the two signals can be effectively adjusted to reduce the impact of delay. The unified frame sequence controls the processing order of the combined frames, and the reading of DMX data and return-to-zero code data, thereby ensuring the synchronous output of the two signals; the arrangement of the processing time according to the frame sequence pulse signal also ensures the synchronous output of the DMX signal and the return-to-zero code signal, thereby improving the consistency and accuracy of the signal output, reducing the risk of signal interference, and improving the overall efficiency of the system. This is very important for applications that require precise control of lighting, sound, and other stage equipment.

[0103] An embodiment of the present application provides a DMX and return-to-zero code synchronous output device, comprising: a frame rate control module, a receiving module, a DMX module, a return-to-zero code module and an output module.

[0104] The frame rate control module is used to periodically output a frame sequence to generate a pulse signal.

[0105] The receiving module is used to continuously acquire a plurality of combined frames sent according to a preset period; the combined frames include a frame sequence, a plurality of DMX data and a plurality of return-to-zero code data.

[0106] The DMX module is used to start from receiving the first frame sequence to generate a pulse signal, and read a plurality of DMX data in a combined frame each time a new frame sequence to generate a pulse signal is received according to the frame sequence of the plurality of combined frames; read the plurality of DMX data of the plurality of combined frames in sequence, and continuously generate a DMX output waveform.

[0107] The return-to-zero code module is used to start from receiving the second frame sequence to generate a pulse signal, and read a plurality of return-to-zero code data in one of the combined frames each time a new frame sequence to generate a pulse signal is received according to the frame sequence of the plurality of combined frames; read the plurality of return-to-zero code data of the plurality of combined frames in sequence, and continuously generate a return-to-zero code output waveform.

[0108] The output module is used to output the DMX output waveform at the corresponding port starting from the generation time of the DMX output waveform; and to output the return-to-zero code output waveform at the corresponding port starting from the generation time of the return-to-zero code output waveform.

[0109] The DMX and return-to-zero code synchronous output device can be applied to the controller system. After the controller is powered on, the frame rate control module starts to work, and the internal timer of the system's single-chip microcomputer regularly outputs a frame sequence to generate a pulse signal according to the set frame rate.

[0110] The DMX module generates a pulse signal according to the frame sequence of the frame rate control unit, and the processed frame sequence starts to accumulate 1 and increase from frame sequence f1; the return-to-zero code module generates a pulse signal according to the frame sequence of the frame rate control unit, and when the pulse signal generated by the second frame sequence arrives, the processed frame sequence f1 starts to accumulate 1 and increase.

[0111] The DMX module and the return-to-zero code module read the content of frame sequence f1 when processing frame sequence f1, and read the content of fn when processing frame sequence fn, and organize them into DMX data and return-to-zero code data for sending out. The organized data format is described in the above embodiment.

[0112] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system described above can refer to the corresponding process in the aforementioned method embodiment and will not be described again here.

[0113] Compared with the prior art, the embodiment of the present invention provides a DMX and return-to-zero code synchronous output device, in which the DMX output waveform is generated from the first frame sequence pulse signal, and the return-to-zero code output waveform is generated from the second frame sequence pulse, which can effectively adjust the relative time relationship of the two signals and reduce the impact of delay. The unified frame sequence controls the processing order of the combined frames, and the reading of DMX data and return-to-zero code data, thereby ensuring the synchronous output of the two signals; the arrangement of the processing time according to the frame sequence pulse signal also ensures the synchronous output of the DMX signal and the return-to-zero code signal, thereby improving the consistency and accuracy of the signal output, reducing the risk of signal interference, and improving the overall efficiency of the system. This is very important for applications that require precise control of lighting, sound, and other stage equipment.

[0114] An embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute a DMX and return-to-zero code synchronous output method as described above.

[0115] The computer device may be a computing device such as a smart phone, a tablet computer, a desktop computer, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Those skilled in the art will appreciate that the figure is merely an example of a computer device and does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or a combination of certain components, or different components, such as input and output devices, network access devices, etc.

[0116] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0117] In some embodiments, the memory may be an internal storage unit of the computer device, such as a hard disk or memory of the computer device. In other embodiments, the memory may also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the computer device. Further, the memory may also include both an internal storage unit of the computer device and an external storage device. The memory is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program, etc. The memory may also be used to temporarily store data that has been output or is to be output.

[0118] An embodiment of the present application provides a computer program product. When the computer program product is run on a computer device, the computer device implements the steps in the above-mentioned method embodiments when executing the computer device.

[0119] In several embodiments provided in the present application, it is understood that each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved.

[0120] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0121] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A DMX and return-to-zero code synchronous output method, characterized in that: include: Continuously acquiring a plurality of combined frames sent according to a preset period; the combined frames include a frame sequence, a plurality of DMX data channels, and a plurality of return-to-zero code data channels; Starting from receiving the first frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, each time a new frame sequence generating pulse signal is received, a plurality of channels of DMX data in the combined frame are read; the plurality of channels of DMX data in the plurality of combined frames are read in sequence to continuously generate a DMX output waveform; Starting from receiving the second frame sequence generating pulse signal, according to the frame sequence of the plurality of combined frames, each time a new frame sequence generating pulse signal is received, a plurality of return-to-zero code data in the combined frame are read; sequentially reading a plurality of return-to-zero code data of the plurality of combined frames, and continuously generating return-to-zero code output waveforms; Starting from the generation time of the DMX output waveform, the DMX output waveform is output at the corresponding port; starting from the generation time of the return-to-zero code output waveform, the return-to-zero code output waveform is output at the corresponding port.

2. A DMX and return-to-zero code synchronous output method as claimed in claim 1, characterized in that: The method starts from receiving the second frame sequence generating pulse signal, and reads a plurality of return-to-zero code data in a combined frame each time a new frame sequence generating pulse signal is received according to the frame sequence of the plurality of combined frames, specifically comprising: Starting from receiving the second frame sequence generating pulse signal, the plurality of combined frames are sorted in ascending order of the frame sequence; According to the sorting result and the preset return-to-zero code parameter duration, a plurality of return-to-zero code data in the combined frame are read each time a new frame sequence generating pulse signal is received.

3. A DMX and return-to-zero code synchronous output method as claimed in claim 2, characterized in that: The step of reading a plurality of return-to-zero code data in a combined frame each time a new frame sequence generating pulse signal is received specifically includes: According to the T0H parameter duration, the T0L parameter duration, the T1H parameter duration and the T1L parameter duration, a plurality of return-to-zero code data in one of the combined frames are converted into return-to-zero code output sub-waveforms.

4. A DMX and return-to-zero code synchronous output method as claimed in claim 3, characterized in that: The converting of the plurality of return-to-zero code data in the combined frame into a return-to-zero code output sub-waveform according to the T0H parameter duration, the T0L parameter duration, the T1H parameter duration and the T1L parameter duration specifically includes: Setting a first timer, a second timer and a third timer with consistent interruption periods and staggered triggering time points; The difference between the triggering time point of the second timer and the triggering time point of the first timer is set to the T0H parameter duration; The difference between the triggering time point of the third timer and the triggering time point of the first timer is set to the T1H parameter duration; At a triggering time point of the first timer, a triggering time point of the second timer, and a triggering time point of the third timer, reading level values ​​of a plurality of channels of return-to-zero code data in one of the combined frames; A return-to-zero code output sub-waveform is obtained according to all level values.

5. A DMX and return-to-zero code synchronous output method as claimed in claim 4, characterized in that: The step of obtaining a return-to-zero code output sub-waveform according to all level values ​​specifically includes: If three consecutive level values ​​are 110, convert them to 1; If three consecutive level values ​​are 100, convert them to 0.

6. A DMX and return-to-zero code synchronous output method as claimed in claim 1, characterized in that: The method starts from receiving the first frame sequence generating pulse signal, and reads a plurality of channels of DMX data in a combined frame each time a new frame sequence generating pulse signal is received according to the frame sequence of the plurality of combined frames, specifically including: Starting from receiving the first frame sequence generating pulse signal, the plurality of combined frames are sorted in ascending order of the frame sequence; According to the sorting result and the preset DMX parameters, each time a new frame sequence is received to generate a pulse signal, several channels of DMX data in the combined frame are read.

7. A DMX and return-to-zero code synchronous output method as claimed in claim 6, characterized in that: The method of reading a plurality of channels of DMX data in a combined frame each time a pulse signal is generated by receiving a new frame sequence according to the sorting result and the preset DMX parameters specifically includes: According to the baud rate, the start bit and the stop bit, a plurality of channels of DMX data in one combined frame are converted into DMX output sub-waveforms.

8. A DMX and return-to-zero code synchronous output method as claimed in claim 7, characterized in that: The converting of the plurality of channels of DMX data in the combined frame into a DMX output sub-waveform according to the baud rate, the start bit and the stop bit specifically includes: Set the interrupt period to the fourth timer of the baud rate countdown; Converting a plurality of channels of DMX data in one of the combined frames into a binary bit stream; Inserting a start bit in front of the binary bit stream and inserting a stop bit after the binary bit stream; Each time the fourth timer is interrupted, the binary bit stream is pushed bit by bit to obtain a DMX output sub-waveform.

9. A DMX and return-to-zero code synchronous output method as claimed in claim 8, characterized in that: The inserting a start bit in front of the binary bit stream and inserting a stop bit after the binary bit stream specifically includes: A start bit 0 is inserted in front of the binary bit stream, and a stop bit 11 is inserted after the binary bit stream.

10. A DMX and return-to-zero code synchronous output device, characterized in that: include: A frame rate control module, used to periodically output a frame sequence to generate a pulse signal; A receiving module, used for continuously acquiring a plurality of combined frames sent according to a preset period; the combined frames include a frame sequence, a plurality of DMX data and a plurality of return-to-zero code data; The DMX module is used to start from receiving the first frame sequence generating pulse signal, and read a plurality of channels of DMX data in a said combined frame each time a new frame sequence generating pulse signal is received according to the frame sequence of the said plurality of combined frames; sequentially read the plurality of channels of DMX data of the said plurality of combined frames, and continuously generate a DMX output waveform; A return-to-zero code module is used to read a plurality of return-to-zero code data in a combined frame each time a new frame sequence generating pulse signal is received, starting from receiving the second frame sequence generating pulse signal according to the frame sequence of the plurality of combined frames; sequentially reading a plurality of return-to-zero code data of the plurality of combined frames, and continuously generating return-to-zero code output waveforms; The output module is used to output the DMX output waveform at the corresponding port starting from the generation time of the DMX output waveform; and to output the return-to-zero code output waveform at the corresponding port starting from the generation time of the return-to-zero code output waveform.

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