Electrical dual binary soft information receiver for NRZ modulated optical fiber transmission

Abstract

A receiver circuit configured to receive an optical signal is disclosed. The receiver circuit includes a receiving circuit configured to receive the optical signal and convert the optical signal from a binary signal format to a binary signal based on a plurality of decision thresholds. The receiver circuit further includes a clock data recovery circuit configured to: sample the binary signal for each data cycle at a first time and sample the binary signal for each data cycle at a second time offset from the first time based on a predetermined clock data recovery technique; and determining an intermediate sample according to the offset for decoding the transmitted bit sequence according to the sample-based soft information.

Description

[0001] This application is a divisional application of an application filed on April 9, 2020, with Chinese national application number 202080039703.9 and invention name “Electrically dual binary soft information receiver for NRZ modulated optical fiber transmission”.

[0002] Reference to related applications

[0003] This application claims the benefit of U.S. Provisional Application No. 62 / 833,108, filed on April 12, 2019, entitled “ELECTRICAL DUOBINARY SOFT INFORMATION RECEIVER FOR NRZ MODULATION FIBER TRANSMISSION,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0004] The present disclosure relates to receiver circuits and methods related to NRZ modulated transmission and other forms of data transmission over optical fiber media. Background Art

[0005] Passive Optical Network (PON), Ethernet PON (EPON), Gigabit EPON (GEPON), 10G-EPON (XEPON), Gigabit PON (GPON), Next Generation PON (NG-PON) and many other derivatives, collectively referred to herein as "PON" or "XGPON", is a telecommunications technology used to provide connectivity to end consumers via optical fiber. Data rates in Passive Optical Network (PON) are increasing, for example, 50 Gbit / s per wavelength. Low-density parity-check (LDPC) codes were introduced to improve error correction coding, and LDPC codes can handle soft inputs. Standard soft-decision receivers use analog-to-digital converters (ADCs) to obtain soft information from the signal amplitude. The disadvantages are increased power consumption due to the ADC and increased cost due to higher linearity requirements on the receiver, and the additional need for gain control in the receiver to operate the ADC in the useful range. Other existing technologies use digital receivers and do not provide soft information, which degrades decoder performance. ADCs can be a problem for PONs because low cost and low power consumption are important requirements for the application. Due to the high power consumption of the ADC itself, the power consumption approximately doubles for each additional bit of resolution. Furthermore, higher receiver linearity and more expensive optical and analog electronics are required to benefit from the ADC soft information. The higher the resolution, the higher the linearity requirement. Therefore, the cost of the receiver optical components needs to be reduced while keeping the power consumption and linearity requirements low. Summary of the invention

[0006] The above object can be achieved by the passive optical network (PON) receiver device of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example user equipment (UE) in a passive optical network (PON) having a transmitter and an electrical duobinary (EDB) receiver that may be used in conjunction with various embodiment aspects described herein;

[0008] Figure 2 is another block diagram illustrating an example UE in a PON having a transmitter and an EDB receiver that may be used in conjunction with aspects of the embodiments described herein;

[0009] Figure 3 is an example diagram of an EDB receiver for determining a probability density of a probability bit position based on one or more thresholds in conjunction with aspects of the embodiments described herein;

[0010] Figure 4 An example receiver signal and clock for soft information from a binary receiver in conjunction with aspects of the embodiments described herein;

[0011] Figure 5 is an example of mutual information of a two-bit or three-bit CDR of an EDB receiver incorporating aspects of the embodiments described herein;

[0012] Figure 6 An example configuration for CDR soft information adjustment in conjunction with aspects of the embodiments described herein;

[0013] Figure 7 An example of interactive information for a two-bit or three-bit CDR of an EDB receiver incorporating aspects of the embodiments described herein;

[0014] Figure 8 is an example of threshold optimization for an EDB receiver in conjunction with aspects of the embodiments described herein;

[0015] Fig. 9 is an example process flow for an EDB receiver incorporating aspects of the embodiments described herein;

[0016] Fig.10 An example network diagram illustrating one or more embodiments of the present disclosure;

[0017] Fig.11 Example apparatus according to aspects of the present disclosure are shown. DETAILED DESCRIPTION

[0018] The present disclosure will now be described with reference to the accompanying drawings, wherein the same reference numerals are used throughout to refer to the same elements, and the structures and devices shown therein are not necessarily drawn to scale. As used herein, the terms "component", "system", "interface", etc. are intended to refer to computer-related entities, hardware, software (e.g., in execution), and / or firmware. For example, a component can be a processor (e.g., a microprocessor, a controller, or other processing circuit or device), a process running on a processor, a controller, an object, an executable file, a program, a storage device, a computer, a tablet computer, and / or a user device with a processing device (e.g., a mobile phone, etc.). For example, an application and a server running on a server can also be a component. One or more components can reside in a process, and a component can be located on a computer and / or distributed between two or more computers. This article may describe a group of elements or a group of other components, wherein the term "group" can be interpreted as "one or more".

[0019] The use of the word example is intended to present concepts in a concrete way. The term "or" as used in this application is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive arrangement. That is, if X employs A; X employs B; or X employs A and B, then "X employs A or B" is satisfied in any of the above cases. In addition, unless otherwise specified or clearly pointed to the singular form from the context, the articles "a" and "an" used in this application and the appended claims should generally be interpreted as meaning "one or more". In addition, if the terms "including", "includes", "having", "has", "with" or their variations are used in the detailed description and claims, these terms are intended to include a manner similar to the term "comprising". In addition, where one or more numbered items are discussed (e.g., "first X", "second X", etc.), generally one or more numbered items can be different or they can be the same, although in some cases, the context may indicate that they are different or the same.

[0020] As used herein, the term "circuitry" may refer to, pertain to, or include: an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), or associated memory (shared, dedicated, or group); the memory may be operably coupled to a circuit that executes one or more software or firmware programs, a combinational logic circuit, or other suitable hardware components that provide the described functionality. In some embodiments, the circuit may be implemented in one or more software or firmware modules, or the functionality associated with the circuit may be implemented by one or more software or firmware modules. In some embodiments, the circuit may include logic that is at least partially operable in hardware.

[0021] Given the above-mentioned need for improved error correction coding and LDPC codes to handle soft inputs and reduce the cost of receiver optical components, low bandwidth components can be used with differential precoding at the transmitter to perform electrical dual binary modulation (EDB) at the EDB receiver. At the receiver, a demodulator using two thresholds (instead of one, for non-return to zero (NRZ) modulation) can be configured to decode the signal. Alternatively, or in addition, an analog-to-digital converter (ADC) is used in the receiver to provide amplitude information; the amplitude information is used to derive soft information for use by the LDPC decoder. LDPC codes for error correction allow soft (non-binary) inputs to improve decoder circuit performance. Soft information receivers derive soft information from signal amplitude, so ADCs are typically used. Therefore, when using an ADC in a passive optical network (PON), the resolution can be configured to remain low, such as 2-3 bits, to maintain low power consumption and linearity requirements.

[0022] As data rates increase in PON networks, limited receiver bandwidth may also be an issue that needs to be addressed.One embodiment includes configuring an electrical duobinary receiver to be able to decode signals with strong inter-symbol interference by using two receiver thresholds instead of one.

[0023] The present disclosure describes a method for deriving soft information from the digital output of an electrical dual binary receiver. With limited receiver bandwidth, the soft information derived from clock data recovery (CDR) can improve effectiveness and efficiency. Additionally, or alternatively, in embodiments herein, a low-resolution ADC can be configured for an electrical dual binary receiver. Additional aspects and details of the present disclosure are further described below with reference to the accompanying drawings.

[0024] Figure 1 An exemplary passive optical network (PON) 100 is shown including a transmitter circuit 101 and a receiver circuit 110 having optical fibers and passive splitters according to various embodiments herein.

[0025] The PON transmitter 101 includes a forward error checking encoder 102 (e.g., a low density parity check (LDPC) encoder) coupled to a differential precoder 103 for electrical duobinary modulation. The differential precoder 103 is configured to perform the operations: in is the precoded bit sequence at time instance t, and is an XOR operation. The precoded signal may be amplified by a laser driver 104 and a laser diode 105; the laser diode 105 converts the electrical signal into an optical signal for transmission over an optical fiber or optical medium.

[0026] Due to the high attenuation of the PON network 100, the electrical duobinary receiver 110 may have high sensitivity, as achieved by an avalanche photodiode (APD) receiver 120 and a transimpedance amplifier (TIA) 130 forming part of the receiver circuit 115. The APD 120 is configured to receive an optical signal and convert the optical signal into an electrical signal, which is sent to the TIA 130, where the electrical signal from the APD 120 is amplified.

[0027] The optical components of the receiver 110 used by the PON 100 may be non-linear to achieve the sensitivity required for receiving signals in a passive splitter network architecture. The receiver 110 may be implemented as a non-return-to-zero (NRZ) receiver, or a binary receiver for 50 Gbit / s transmission. The receiver circuit 115 may include a limiting amplifier, or two limiting amplifiers 140 and 145 as an electrical dual binary (EDB) receiver after the TIA 130. The limiting amplifiers 140 and 145 may be coupled to an exclusive OR operator 148 to perform an exclusive OR operation on the binary signal output generated from the limiting amplifiers 140 and 145, respectively.

[0028] APD 120, TIA 130 and limiting amplifiers 140 and 145 may form at least a portion of a Physical Medium Dependent (PMD) architecture. XOR device 148 and clock data recovery (CDR) 150 may form at least a portion of a Physical Medium Attachment (PMA) architecture. Log-likelihood ratio (LLR) calculation component or LLR circuit 170 and decoder circuit 190 may form at least a portion of a Physical Coding Sublayer (PBS) architecture.

[0029] As data rates increase in the PON network 100, limited receiver bandwidth can be addressed. One embodiment uses an electrical duobinary receiver in this case, which allows decoding of signals with strong inter-symbol interference by using two receiver thresholds instead of one receiver threshold. Limiting amplifiers 140 and 145 can convert the electrical signal output from TIA 130 based on the EDB format. Soft information can be further derived from the digital output of the receiver circuit 115 via the decoder circuit 155 of the electrical duobinary receiver. The soft information derived from CDR 150 can be effective with limited receiver bandwidth.

[0030] In response to the binary signals generated by the limiting amplifiers 140 and 145, they are combined by an XOR operation in an XOR operator 148. Based on the generated binary signals, the bit clock and the transmitted bit sequence can be recovered in the CDR component 150; the CDR component 150 derives the phase error between the local clock and the received bit sequence for updating the control loop of the phase locked loop (PLL) clock 180.

[0031] The LLR circuit 170 provides soft information for soft-decision forward error correction (FEC) based on one or more binary receivers or low-resolution analog-to-digital converters in combination with an electrical duobinary receiver that is configured to use lower bandwidth optical components than conventional NRZ receivers. For a binary receiver, the soft information can be derived from the clock data recovery circuit 150 using an oversampled binary signal. This is the point in time at which samples between bit positions can be acquired and selected to improve mutual information, thereby, for example, improving the performance of the soft-decision FEC decoder (e.g., LDPC decoder) circuit 190. The soft information can be derived based on log-likelihood ratios (LLRs) and is derived by the LLR circuit 170 from the equalized received signal amplitude. These outputs can then be further processed by the error correction circuit 190, for example, as an LDPC code to recover the transmitted bit sequence.

[0032] Figure 2 An example of another embodiment of an EDB receiver 200 is shown, in which the receiver circuitry may include an analog-to-digital converter (ADC). Figure 2 The receiver 200 shown includes Figure 1 For receivers based on analog-to-digital converters (ADCs), the electrical signal may be amplified by an automatic gain control (AGC) block 240 and converted to a digital signal by ADC 245. For example, ADC 245 may include 2 or 3 bits of resolution. By using a low resolution ADC 245 receiver, or using Figure 1The receiver configuration 100 can adjust the decision threshold to optimize the mutual information, thereby optimizing the performance of the soft decision of the decoder 190. This solution can improve the performance when a binary receiver is used with soft decision FEC and one or more electrical dual binary receivers. The proposed solution for ADC receiver can provide the same performance at a lower resolution, thereby saving cost and power through a simplified receiver design.

[0033] Figure 3 2 shows an example of an eye diagram of an EDB receiver according to various embodiments herein. Figure 3 The EDB received signal 300 shown has two eyes 302 and 304, and therefore, two limiting amplifiers (e.g., 140 and 145) are used, one for each eye. The binary signals of the limiting amplifiers (LA) 140 and 145 are combined by an XOR operation of an XOR operator 148. From the generated binary signals, the bit clock and the transmitted bit sequence can be recovered by the CDR block circuit 150; the CDR block circuit 150 derives the phase error between the local clock and the received bit sequence for updating the PLL clock control loop 180.

[0034] Based on the output of CDR 150, LLR calculation block provides soft information expressed as log-likelihood ratio (LLR). For received signal y, LLR 170 processes LLR as follows: y =log(p xy (x=0, y))-log(p xs (x=1, y)); (1)

[0035] Among them, p xs (x, y) is the conditional probability of receiving y when x is sent. Based on the soft information, the FEC decoder 190 (eg, an LDPC decoder) recovers the transmitted bit sequence.

[0036] In the case where the receiver 200 has an ADC 245, as Figure 2 As shown, there is an analog-to-digital converter after the TIA 130. The bit clock is recovered based on the AGC output signal of the AGC 240. The soft information is calculated in the LLR circuit 170 based on the ADC output.

[0037] When using Figure 1 In the receiver architecture shown, the binary signal can be used to derive non-binary soft information through the XOR operator 148, the CDR circuit 150 and the LLR circuit 170. The soft information output by the LLR circuit 170 can be obtained from multiple consecutive samples of the binary received signal. t These samples are available in a clock data recovery (CDR) circuit 150.

[0038] Figure 4 Soft information from a binary receiver according to various embodiments is shown. The CDR is configured to collect samples at bit position t, e.g., y t-1 ,y t , and, collecting intermediate samples 404 between bit positions (e.g., y t-1 / 2 ) to derive a phase error that is used for clock recovery by PLL 180. For soft information used by LDPC decoder 190, another / intermediate position 402 at time t-Δt may give more information about the received signal. Figure 4 Briefly discussed Figure 6 As shown in FIG. 1 , the example decoder circuit 155 is configured to derive soft information, a CDR state s is associated with T consecutive samples, which gives s∈0,...,2 T -1 possible value. For example, the value s = [y t-1 ,y t-Δt y t ]. Finding the optimal sampling point Δt can be a one-dimensional search, which can be performed in the receiver CDR.

[0039] Figure 5 The mutual information 500 of a 3-bit CDR of a 50G EDB (e.g., 50Gbit / s transmission by the EDB receiver 100 or 200) according to an embodiment is shown. The resulting curve 500 shows the possible values ​​of Δt between the two bit positions of 0 and 1, indicating that for approximately 10 -2 The sampling point of Δt=0.15 gives the highest theoretical capacity. For example, based on the binary output 502 deriving soft information with two bits of resolution, the CDR curve 504 reaches a maximum at t-Δt=0.85.

[0040] refer to Figure 6 , shows the CDR soft information adjustment with intermediate values ​​according to an embodiment of the present invention. In order to achieve optimized CDR soft information, in one embodiment, the sample points of the intermediate samples used to derive the soft information are adjusted. In LLR block 170, the input signal ll of the FEC decoder is created according to the CDR state s. The LLR value is defined as: llr s =log(p xs (x=0,s))-log(p xs (x=1, s)); (2) where when x=0 or x=1 is sent, the conditional probability of the receiving state p xs (x,s) is obtained by counting the probability of a known sequence in the transmitted signal. With probability p xs (x, s), the mutual information of the signal I(x, s) can be calculated as follows:

[0041]

[0042] And the sampling point Δt is moved to the position of maximum mutual information. Once identified, this additional sampling point timing is used to collect additional samples in the CDR circuit.

[0043] When analog-to-digital conversion is used in the receiver 200, such as Figure 2 As shown, the resolution of ADC245 (e.g., 2 to 3 bits) can be an important design parameter. As a rule of thumb, each additional bit of resolution doubles the power consumption, which is critical for the sampling rate required by PON. The decision thresholds of ADC245 are usually at equal distances, and the distance between them is selected to be small enough. However, for low-resolution ADC245, where soft information is derived directly from the ADC output, ADC245 can be configured with multiple decision thresholds that are not equally spaced, where having unequally spaced decision thresholds may be an advantage.

[0044] Figure 7 The mutual information 700 of a 3-bit CDR and ADC soft information receiver for a 50G EDB receiver (e.g., 50Gbit / s transmission by an EDB receiver) according to an embodiment is shown. Curve 700 indicates that for 50 Gbits samples, it may be difficult to utilize ADCs with a large number of bits (e.g., six, seven, eight bits) because they consume a lot of power and the equipment is very expensive. Therefore, the focus of the embodiments herein may be on only a few amplitude levels, such as only two or three bits, or at least more than one bit, because the resolution of ADC215 is the minimum number configured for sampling. As shown, a configuration may be implemented using only a two or three bit ADC, in which the intermediate region may be adjusted by a position threshold between four or eight levels. Curve 700 shows the transmission information, in which curve 702 of the binary signal (y) and curve 704 of the CDR soft information may be optimal and correspond to Figure 5 500. Curve 706 shows the curve for a two-bit ADC, while curve 708 shows the curve optimized using the middle sample. Similarly, curve 710 shows the curve for a three-bit ADC, while curve 712 shows the curve after the same optimization. Curve 714 shows the limit threshold.

[0045] In the ADC threshold optimization of the 3-bit ADC on the EDB signal, the result curve 700 of the threshold optimization of the EDB is as follows: Figure 8As shown. Curve 800 shows that the decision thresholds around the two transition regions between zero transmission probability density and one transmission probability density are much more efficient than uniformly distributed thresholds. Here, the intermediate threshold 806 can be displayed and optimized based on the incremental t variable as an offset of the intermediate sample position. The default threshold can be seen by the vertical dashed lines in the negative and positive regions. The curve for the one region is 802, while the curve for the zero region is 804. In general, using ADC245 can obtain more information from the transmitted bits, just as when using a two-bit ADC, where the distance between the amplitude positions can be equal to the threshold line and optimized using more samples; therefore, a threshold of 0.9 is optimal, and it can also be similar to a three-bit eight-level ADC.

[0046] Thus, curve 800 provides an example of what an optimal threshold is; in this example, the thresholds would otherwise be equally spaced as dashed lines rather than numbers, and this is what the ADC does when it has equally spaced levels (e.g., at levels related to minus three, minus one, and three plus one). If an optimization is performed to give the best possible levels, the result is Figure 3 There may be more thresholds in this transition region where the eyes 302, 304 are open; whereas in the region where the eyes are closed there are no thresholds and, for example, are more difficult to determine. Therefore, the optimal sampling points become closer together in the middle of the open eyes 302 and 304 region with the divided / divided thresholds. These are the relevant points where the steps between the ADC levels are located, except that they are equidistant, it will enter the two eyes, and by such an intermediate sample threshold adjustment increment t, for example, even with a two-bit or three-bit ADC, it is possible to obtain soft information of reasonably good quality without using more bits of ADC.

[0047] Other embodiments include how to obtain one or more adequate thresholds by adjusting using knowledge of the probability identity function; thus, for one and zero transmission, these are curves 802, 804; where 802 is for zero transmission and 804 is for one transmission. With this information, the gradient step that is finally done can give the optimal threshold position in the ADC.

[0048] In one embodiment, the optimal decision threshold can be approximated by two ADCs with half resolution and uniformly distributed thresholds, operating in two transition regions.

[0049] The information of the ADC sampled output signal can be given by the following formula:

[0050]

[0051] p xy (x, y) is the joint density of sending x and y, p x (x) is the probability of sending x, and p y (y) = p xy(0,y)+p xy (0, y), is the probability of receiving y. Understand the probability density function (PDF) F of sending bit x and receiving amplitude y xy (x,y) and the corresponding cumulative density function (CDF) F xy knowledge of (x, y), and F y (y) = F xy (0,y)+F xy (1, y), the optimal threshold can be found by the gradient method.

[0052] Therefore, the threshold value is y th，i , where, for a 3-bit ADC, there are 8 different levels, and therefore, 7 thresholds y th，1 , ..., y th，7 .

[0053] The update of the threshold can be expressed as follows: Here, the step size is a and the gradient is given by:

[0054]

[0055] Among them, when i=0, F xy (x,y th，i )=0; when i=2 adc bits Time F xy (x,y th，i )=1. For the PDF and CDF of the received signal amplitude, the f can be measured based on the known signal using an ADC with an initial setting of uniformly distributed thresholds during the training phase. xy (x, y) and F xy (x,y).

[0056] In an example of any of the embodiments herein, a binary receiver for an NRZ modulated signal with bandwidth limitation (electrical duobinary) uses two receiver decision thresholds, or a standard NRZ receiver uses one receiver decision threshold; wherein the soft information of the soft information FEC decoder is provided by a clock data recovery module, at bit position y t ,y t-1 ,y t -2 , ... and the position y between the bits t-Δt ,y t-1-Δt , ... using multiple consecutive samples. Controlling the sampling position of the intermediate samples t-Δt to improve soft information. An analog-to-digital conversion receiver for NRZ modulated signals with a receiver having bandwidth limitation (electrical duobinary), or a standard NRZ receiver, can be used; wherein the ADC decision threshold is adjusted to improve mutual information, thereby improving the efficiency of the subsequent FEC decoder.

[0057] refer to Fig. 9 is an example process flow for an EDB receiver according to aspects herein. Processing flow 900 may begin at 902 to cause an electrical dual binary receiver circuit to receive an optical signal via a photodiode. At 904, the processing flow includes: converting the optical signal via the photodiode to an electrical signal. At 906, the processing flow includes: converting the electrical signal to a binary signal based on a plurality of decision thresholds. At 908, the processing flow includes: determining, via a clock data recovery circuit, a plurality of samples based on a conditional probability that a received sample is a bit 1 or a bit 0, and determining at least one additional intermediate sample based on an offset. At 910, the processing flow includes: generating soft information based on the plurality of samples to decode a transmitted bit sequence.

[0058] In other embodiments, the processing flow 900 may include: outputting a first digital signal through a first limiting amplifier, the first digital signal having a high value when the electrical signal exceeds a first decision threshold among a plurality of decision thresholds, otherwise, the first digital signal having a digital low value; and outputting a second digital signal through a second limiting amplifier, the second digital signal having a digital high value when the electrical signal exceeds a second decision threshold among a plurality of decision thresholds, otherwise, the second digital signal having a digital low value. The first decision threshold and the second decision threshold may be different and unequally spaced from each other. Samples may be generated as continuous samples. An offset may be selected as an optimal sample offset to determine at least one intermediate sample. The probability of a bit position may be determined based on the continuous samples and the at least one intermediate sample, wherein the number of bit positions includes two or three. Multiple decision thresholds may be determined based on a gradient.

[0059] According to some embodiments, reference Fig.10 , shows a telecommunications network 1000 that provides broadband Internet access and / or other forms of packet-based communications network access to subscribers via a point-to-multipoint passive optical network (PON). In an example embodiment, network 1000 may be a Data Over Cable Service Interface Specification (DOCSIS) cable network that provides subscribers with access to the Internet 1009; and, if desired, provides access to other services such as a public switched telephone network 1008 via a 10Gb passive optical network (XGPON) 1012 using a cable modem termination system (CMTS) 1002 and subscriber DOCSIS cable modems 1015 (only 1 is shown for simplicity). Although in Fig.10 Only one endpoint is shown in the figure, but since XGPON is a passive optical network, XGPON will include: optical line terminal (OLT), optical distribution network (ODN) and multiple optical network units (ONUs).

[0060] In this example, a network provider HUB or headend 1010 including a DOCSIS cable modem termination system (CMTS) 1002 is communicatively coupled to an IP network 1009 and a PSTN 1008 via a router or switch 1006 at its network service interface (NSI), and is communicatively coupled to an XGPON 1012 at the CMTS upstream / downstream RF interface.

[0061] The headend 1010 may include related servers or port access to servers, providing an operations support system (OSS) interface 1004 that supports the CMTS 1002. The operations support system interface 1004 is a network element management layer interface between network elements and high-level OSS that supports basic business processes required for CMTS operation. For example, OSS DNS, DHCP, SMTP, system log, time server, and TFTP.

[0062] As shown in network 1000, compared with DPoE in the previous EPON, the embodiment of the present invention proposes a combination of the XGPON system and the DOCSIS system in the design to achieve the highest reuse of existing devices and software of both parties. In various embodiments of the present invention, the DOCSIS CMTS 1002 can effectively provide fast and high-bandwidth interconnection to subscribers of multiple cable modems (CMs) 1015 through the ODN of the XGPON 1012 by sending a signal to the XGPON to change its control to use DOCSIS as the management layer of the XGPON 1012; whether it is dedicated to the DOCSIS modem 1015 or coexists with other XGPON standards that manage different optical network units (ONUs) to support other end-user applications, the burden of the new PON can be reduced.

[0063] As an example embodiment, a DOCSIS-compliant wired network transceiver, such as a DOCSIS CMTS 1002 or possibly a CM 1015, sends a signal to a corresponding connected transceiver (e.g., one of an OLT or ONU) in the XGPON 1012 in the following manner: The DOCSIS wired network controls the optical network upper layer management process so that the XGPON is controlled by the PHY layer protocol. In some embodiments, except for the initialization process, the XGPON is limited to the first layer protocol, including the physical medium dependent sublayer (PMD) and the transmission convergence (TC) sublayer. DOCSIS controls the second and higher layer protocols, i.e., from the lower data link layer 2 to the media access control (MAC) sublayer and higher layers; DOCSIS will manage IP data flows through the optical network above the XGPON TC layer boundary. In this way, a simple division between the DOCSIS MAC layer and the XGPON PHY layer will manage the data flow through the XGPON, rather than trying to split the management tasks between the two standard protocols as in previous attempts to use DPoE DOCSIS / EPON management.

[0064] To further provide context for various aspects of the disclosed subject matter, Fig.11 A block diagram of an embodiment of a device 1100 (e.g., a cable modem or gateway, etc.) is shown; the device 1100 is associated with access to a network (e.g., a base station, a wireless access point, a femtocell access point, etc.), which can enable and / or utilize features or aspects of the disclosed aspects.

[0065] According to various aspects, the device 1100 can be used with one or more aspects of the passive optical network described herein (e.g., core components, PON components, or network components herein). For example, the EDB user device 1100 includes a digital baseband processor 1102, which can be coupled to a data storage or memory 1103 and a front end 1104 (e.g., an RF front end, an acoustic front end, or other similar front end). The device 1100 also includes one or more input / output ports 1107, which are configured to receive signals from one or more devices and send signals to one or more devices, such as access points, access terminals, wireless ports, routers, etc.; these devices can operate in a radio access network or other communication network through a network device (not shown).

[0066] Device 1100 may be a radio frequency (RF) device for transmitting RF signals, an acoustic device for transmitting sound signals, or any other signal communication device, such as a computer, a personal digital assistant, a mobile phone or smart phone, a tablet, a modem, a laptop, a router, a switch, a repeater, a personal computer, a network device, a base station, or a similar device that can communicate with a network or other devices according to one or more different communication protocols or standards.

[0067] The front end 1104 may include a communication platform including electronic components and associated circuitry that provides processing, manipulation, or shaping of signals received or transmitted via one or more receivers or transmitters (e.g., transceivers) 1108, multiplexer / demultiplexer components 1112, and modulation / demodulation components 1114. The front end 1104 is coupled to a digital baseband processor 1102 and an input / output port set 1107. The front end 1104 may be configured to perform the remodulation techniques described herein to extend the frequency range of the device 1100. In one aspect, the user equipment device 1100 may include a phase locked loop system 1110.

[0068] According to aspects of the present disclosure, the processor 1102 can, at least in part, impart functionality to substantially any electronic component within the mobile communication device 1100. As an example, the processor 1102 can be configured to: at least in part, execute executable instructions that cause the front end to remodulate the signal to a selected frequency. The processor 1102 is functionally and / or communicatively coupled (e.g., via a memory bus) to the memory 1103 to store or retrieve information necessary for operation and impart functionality; at least in part, to the communication platform or front end 1104, the phase-locked loop system 1110, and substantially any other operational aspects of the phase-locked loop system 1110. The phase-locked loop system 1110 includes at least one oscillator (e.g., VCO, DCO, etc.), which can be calibrated by a core voltage, a coarse adjustment value, a signal, a word, or a selection process.

[0069] The processor 1102 may be operable to enable the mobile communication device 1100 to process data (e.g., symbols, bits, or chips) for multiplexing / demultiplexing using a multiplexing / demultiplexing component 1112 or for modulation / demodulation via a modulation / demodulation component 1114, such as implementing direct and inverse fast Fourier transforms, selection of modulation rates, selection of data packet formats, inter-packet time, etc. The memory 1103 may store data structures (e.g., metadata), code structure(s) (e.g., modules, objects, classes, procedures, etc.) or instructions, network or device information, such as: policies and specifications, attachment protocols, code sequences for scrambling, spreading, and pilot (e.g., reference signal) transmission, frequency offsets, cell IDs, and other data for detecting and identifying various characteristics associated with RF input signals, power outputs, or other signal components during power generation.

[0070] As used in this specification, the term "processor" may refer to substantially any computing processing unit or device, including but not limited to: a single-core processor, a single processor with software multithreaded execution capability, a multi-core processor, a multi-core processor with software multithreaded execution capability, a multi-core processor using hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. In addition, a processor may refer to: an integrated circuit, an application-specific integrated circuit, a digital signal processor, a field programmable gate array, a programmable logic controller, a complex programmable logic device, discrete gate or transistor logic, a discrete hardware component, or any component designed to perform the functions and / or processes described herein. The processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates to optimize space usage or improve the performance of mobile devices. The processor may also be implemented as a combination of computing processing units.

[0071] Examples (embodiments) may include subject matter, such as methods, devices for performing actions or blocks of methods, and at least one machine-readable medium including instructions, which, when executed by a machine (e.g., a processor with memory, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.), causes the machine to perform the actions of a method or device or system for concurrent communication using multiple communication technologies according to the embodiments and examples described herein.

[0072] In the first set of examples:

[0073] Example 1 is a receiving circuit configured to receive an optical signal, comprising a front-end receiving circuit; the front-end receiving circuit is configured to: receive the optical signal and convert the optical signal from a dual binary signal format to a binary signal. The receiver circuit also includes a clock data recovery circuit, which is configured to: receive the binary signal, and based on a preset clock data recovery technology, sample the binary signal of each data cycle at a first moment; and sample the binary signal of each data cycle at a second moment deviating from the first moment.

[0074] In Example 2 dependent on Example 1, the receiver circuit further comprises a log-likelihood ratio circuit configured to: receive samples from the clock data recovery circuit and generate a soft information output signal represented by a log-likelihood ratio based on the samples.

[0075] In Example 3 dependent upon Example 2, the receiver circuit further comprises a decoder circuit; the decoder circuit being configured to: receive the soft information output signal, and generate a bit sequence in response to the signal.

[0076] In Example 4 dependent on Example 1, the front-end receiving circuit includes a photodiode; the photodiode is configured to: receive an optical signal and output an electrical signal in response to the optical signal.

[0077] In Example 5, which is dependent on Example 4, the electrical signal is in an analog signal format, and the front-end receiving circuit further includes a first limiting amplifier, which has a first threshold and is configured to: receive the electrical signal and output a first digital signal; when the electrical signal exceeds the first threshold, the first digital signal has a digital high value, otherwise, the first digital signal has a digital low value. The front-end receiver circuit further includes a second limiting amplifier, which has a second (different) threshold and is configured to: receive the electrical signal and output a second digital signal; and when the electrical signal exceeds the second threshold, the second digital signal has a digital high value, otherwise, the second digital signal has a digital low value.

[0078] In Example 6 that depends on Example 5, the front-end receiving circuit also includes a logic circuit configured to: receive a first digital signal and a second digital signal; and output a binary signal based on a logic operation performed on the first digital signal and the second digital signal.

[0079] In Example 7 which is dependent on Example 6, the logic circuit is configured to perform an exclusive-OR operation.

[0080] Example 8 is a receiving circuit configured to receive an optical signal, comprising a front-end receiving circuit; the front-end receiving circuit is configured to: receive the optical signal and convert the optical signal into an analog electrical signal. The receiver circuit also includes an analog-to-digital converter (ADC), which is configured to: receive the analog electrical signal and convert the analog electrical signal into a digital signal; wherein the ADC includes a plurality of decision thresholds, which are used to determine the digital level of the digital signal, and wherein the decision thresholds are unequally spaced from each other.

[0081] In Example 9, which is dependent on Example 8, the ADC comprises one or more thresholds at locations associated with a transmission region between where a probability density of zero transmissions reaches a maximum value and where a probability density of one transmission reaches a maximum value.

[0082] In Example 10 dependent on Example 8, the receiver circuit further comprises a log-likelihood ratio circuit configured to: receive samples from the clock data recovery circuit and generate a soft information output signal represented by a log-likelihood ratio based on the samples.

[0083] In Example 11 dependent upon Example 10, the receiver circuit further comprises a decoder circuit configured to receive the soft information output signal and generate a bit sequence in response to the signal.

[0084] In Example 12 dependent on Example 8, the front-end receiving circuit includes a photodiode; the photodiode is configured to: receive an optical signal and output an electrical signal in response to the optical signal.

[0085] In Example 13 dependent on Example 12, the receiver circuit further includes an adjustable gain amplifier configured to: receive the electrical signal and output the amplified electrical signal to the ADC.

[0086] In the second set of examples:

[0087] The first example is a device of a passive optical network (PON) receiver, which is configured to perform electrical duobinary demodulation in a PON network, including: an electrical duobinary receiver, the electrical duobinary receiver including a receiver circuit, the receiver circuit is configured to: receive an optical signal, and convert the electrical duobinary signal format into a binary signal based on multiple decision thresholds; and, a decoder circuit, the decoder circuit is configured to: receive the binary signal, and sample the binary signal for each data cycle based on an oversampled binary signal, and provide soft information derived from the output of a clock data recovery circuit.

[0088] A second example may include the first example, wherein the receiver circuit includes: a first limiting amplifier, the first limiting amplifier being configured to: generate a first binary signal based on an electrical duobinary signal in an electrical duobinary format; and a second limiting amplifier, the second limiting amplifier being configured to: generate a second binary signal based on the electrical duobinary signal in the electrical duobinary format.

[0089] A third example may include the first or second example, wherein the receiver circuit further includes an XOR operator configured to receive the first binary signal and the second binary signal and output a binary signal to the decoder circuit based on an XOR operation.

[0090] A fourth example may include any one or more of the first to third examples, wherein the receiver circuit is configured to generate a binary signal based on different amplitude thresholds as a plurality of decision thresholds of the first limiting amplifier and the second limiting amplifier.

[0091] The fifth example may include any one or more of the first to fourth examples, wherein the decoder circuit further includes a log-likelihood ratio circuit configured to: receive samples from a clock data recovery circuit and generate a soft information output signal represented by a log-likelihood ratio based on samples at bit positions and samples at one or more intermediate positions between offset-based bit positions.

[0092] A sixth example may include any one or more of the first to fifth examples, wherein the decoder circuit includes a forward error correction (FEC) decoder configured to receive a soft information output signal and generate a bit sequence based on the soft information.

[0093] A seventh example may include any one or more of the first to sixth examples, wherein the decoder circuit is further configured to: sample one or more intermediate positions by modifying an offset to optimize the soft information output signal; and wherein the decision thresholds are unequally spaced from each other.

[0094] An eighth example may include any one or more of the first to seventh examples, wherein the receiver circuit includes: a photodiode configured to convert an optical signal into an electrical signal; a downstream analog-to-digital converter including two to three bits of bit resolution to provide amplitude information at the output, wherein the decision thresholds are not equidistantly spaced from each other; and a decoder circuit configured to determine soft information based on the output of the analog-to-digital converter.

[0095] The ninth example may include any one or more of the first to eighth examples, wherein the oversampled binary signal is derived from intermediate samples selected between samples at different bit positions; and the decoder circuit includes a forward error correction (FEC) decoder to recover the transmitted bit sequence based on soft information based on the intermediate samples of the oversampled binary signal and the samples at different bit positions.

[0096] A tenth example may be an electrical duobinary receiver circuit configured to receive an optical signal, comprising: a receiving circuit configured to: perform electrical duobinary demodulation by processing the optical signal, and convert the optical signal into a binary signal based on a plurality of decision thresholds that are unequally spaced from each other; and a decoder circuit comprising a log-likelihood ratio circuit configured to: process samples from a clock data recovery circuit, and based on the samples, generate a soft information output signal expressed in a log-likelihood ratio; wherein the samples are based on different bit positions and one or more intermediate positions between the bit positions based on an offset.

[0097] The eleventh example may include the tenth example, further comprising an analog-to-digital converter (ADC) configured to: receive an analog electrical signal derived from the optical signal and convert the analog electrical signal into a binary signal; and wherein the sample is based on a plurality of determined thresholds located at a position associated with a transmission region between a probability density of zero transmission satisfying a first threshold and a probability density of one transmission satisfying a second threshold.

[0098] The twelfth example may include the eleventh example, wherein the receiver circuit includes: a photodiode, which is configured to convert an optical signal into an electrical signal; and, a plurality of limiting amplifiers, which are configured to convert the electrical signal into a binary signal to output an XOR operation; wherein a first limiting amplifier among the plurality of amplifiers includes a first decision threshold, and a second limiting amplifier among the plurality of amplifiers includes a second decision threshold among the plurality of decision thresholds that is different from the first decision threshold.

[0099] The thirteenth example may include any one or more of the eleventh to twelfth examples, wherein the log-likelihood ratio circuit is configured to: receive samples from a clock data recovery circuit and generate a soft information output signal represented by a log-likelihood ratio based on the conditional probability that the received sample is bit 1 or bit 0, and based on at least one additional intermediate value of the offset.

[0100] The fourteenth example may include any one or more of the eleventh to thirteenth examples, wherein the clock data recovery circuit is configured to: generate samples as continuous samples, and select an offset as an optimal sample offset to determine one or more intermediate samples at one or more intermediate positions between 0 and 1.

[0101] The fifteenth example may include any one or more of the eleventh to fourteenth examples, and further include an analog-to-digital converter comprising a bit resolution of 2 to 3 bits for multiple decision thresholds, wherein the multiple decision thresholds are based on gradients and are updated based on the step size and gradient in a training phase of the ADC.

[0102] The sixteenth example may be a method for an electrical dual binary receiver circuit, comprising: receiving an optical signal through a photodiode; converting the optical signal into an electrical signal through a photodiode; converting the electrical signal into a binary signal based on multiple decision thresholds; determining multiple samples based on the conditional probability that the received sample is bit 1 or bit 0 through a clock data recovery circuit, and determining at least one additional intermediate sample based on an offset; and generating soft information based on the multiple samples to decode a transmitted bit sequence.

[0103] The sixteenth example may include the sixteenth example, further comprising: outputting a first digital signal through a first limiting amplifier, wherein when the electrical signal exceeds a first decision threshold among multiple decision thresholds, the first data signal has a digital high value, otherwise, the first data signal has a digital low value; and outputting a second digital signal through a second limiting amplifier, wherein when the electrical signal exceeds a second decision threshold among multiple decision thresholds, the second digital signal has a digital high value, otherwise, the second digital signal has a digital low value; wherein the first decision threshold is different from the second decision threshold and are unequally spaced from each other.

[0104] An eighteenth example may include the sixteenth to seventeenth examples, further including: outputting a binary signal based on a logic operation performed on the first digital signal and the second digital signal.

[0105] The nineteenth example includes any one or more of the sixteenth to eighteenth examples, and further includes: generating samples as continuous samples; selecting an offset as an optimal sample offset to determine at least one intermediate sample; and determining the probability of a bit position based on the continuous samples and the at least one intermediate sample, wherein the number of bit positions includes two or three.

[0106] A twentieth example includes any one or more of the seventeenth to nineteenth examples, further comprising: determining a plurality of decision thresholds based on a gradient.

[0107] In addition, various aspects or features described herein may be implemented as methods, apparatus, or articles of manufacture using standard programming and / or engineering techniques. The term "article of manufacture" as used herein is intended to cover a computer program accessible from any computer-readable device, carrier, or medium. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips, etc.), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs), etc.), smart cards, and flash memory devices (e.g., EPROMs, cards, sticks, key drives, etc.). In addition, the various storage media described herein may represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to: wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data. In addition, a computer program product may include a computer-readable medium having one or more instructions or codes that are operable to cause a computer to perform the functions described herein.

[0108] Communication media includes computer readable instructions, data structures, program modules, or other structured or unstructured data in a data signal, such as a modulated data signal, such as a carrier wave or other transport mechanism, and includes any information communication or transmission medium. The term "modulated digital signal" or signal refers to a signal having one or more characteristics that are set or changed in a manner that encodes information in one or more signals. By way of example and not limitation, communication media includes: wired media, such as a wired network or direct wired connection; and, wireless media, such as acoustic, RF, infrared and other wireless media.

[0109] An exemplary storage medium may be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be a component of the processor. In addition, in some aspects, the processor and the storage medium may reside in an ASIC. In addition, the ASIC may reside in a user terminal. Alternatively, the processor and the storage medium may reside in a user terminal as discrete components. In addition, in some aspects, the process and / or action of the method or algorithm may be stored as one or any combination or a group of codes and / or instructions on a machine-readable medium and / or a computer-readable medium, which may be incorporated into a computer program product.

[0110] In this regard, while the disclosed subject matter has been described in conjunction with various embodiments and corresponding drawings, it should be understood that other similar embodiments may be used or modifications and additions may be made to the described embodiments to perform the same, similar, alternative, or alternative functions of the disclosed subject matter without departing from the disclosed subject matter. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims.

[0111] In particular, with respect to the various functions performed by the above-described components (components, devices, circuits, systems, etc.), unless otherwise noted, even if not structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments shown herein of the present disclosure, the terms used to describe these components (including references to "means") are intended to correspond to any component or structure that performs the specified functions of the described components (e.g., functionally equivalent). In addition, while a particular feature may be disclosed for only one of several embodiments, such feature may be combined with one or more other features of other embodiments, as may be desirable and advantageous for any given or particular application.

Claims

1. An apparatus of a passive optical network (PON) receiver, the apparatus being configured to perform electrical duobinary demodulation in a PON network, the apparatus comprising: An electrical duo-binary receiver includes: a receiver circuit configured to receive an optical signal and convert the electrical duo-binary signal format into a binary signal based on a plurality of decision thresholds; and a decoder circuit configured to receive the binary signal and sample the binary signal for each data cycle based on an oversampled binary signal and provide soft information derived from an output of a clock data recovery circuit.

2. The device according to claim 1, characterized in that The receiver circuit includes a first limiting amplifier configured to generate a first binary signal from an electrical duobinary signal in an electrical duobinary format, and a second limiting amplifier configured to generate a second binary signal based on the electrical duobinary signal in an electrical duobinary signal format.

3. The device according to claim 2, characterized in that The receiver circuit also includes an XOR operator configured to receive the first binary signal and the second binary signal and output the binary signal to the decoder circuit based on an XOR operation.

4. The device according to any one of claims 1 to 3, characterized in that The receiver circuit is configured to generate a binary signal based on different amplitude thresholds as a plurality of decision thresholds for a first limiting amplifier and a second limiting amplifier.

5. The device according to any one of claims 1 to 4, characterized in that The decoder circuit also includes a log-likelihood ratio circuit configured to receive samples from the clock data recovery circuit and generate a soft information output signal represented by a log-likelihood ratio based on samples at the bit position and samples at one or more intermediate positions between the offset-based bit positions.

6. The device according to claim 5, characterized in that The decoder circuit includes a forward error correction (FEC) decoder configured to receive a soft information output signal and generate a bit sequence based on the soft information.

7. The device according to claim 5, characterized in that The decoder circuit is further configured to: sample one or more intermediate positions by modifying the offset to optimize the soft information output signal; and wherein the decision thresholds are unequally spaced from each other.

8. The device according to any one of claims 1 to 7, characterized in that The receiver circuit includes: a photodiode, which is configured to convert an optical signal into an electrical signal; a downstream analog-to-digital converter, which includes a bit resolution of two to three bits to provide amplitude information at the output, wherein the decision thresholds are not equidistantly spaced from each other; and a decoder circuit, which is configured to determine soft information based on the output of the analog-to-digital converter.

9. The device according to any one of claims 1 to 8, characterized in that The oversampled binary signal is derived from intermediate samples selected between samples at different bit positions; and the decoder circuit includes a forward error correction (FEC) decoder to recover the transmitted bit sequence based on soft information based on the intermediate samples of the oversampled binary signal and the samples at different bit positions.

10. An electrical duobinary receiver circuit configured to receive an optical signal, the circuit comprising: a receiving circuit configured to: perform electrical duobinary demodulation by processing the optical signal and convert the optical signal into a binary signal based on a plurality of decision thresholds that are unequally spaced from each other; as well as, A decoder circuit includes a log-likelihood ratio circuit, which is configured to: process samples from a clock data recovery circuit and generate a soft information output signal represented by a log-likelihood ratio based on the samples; wherein the samples are based on different bit positions and one or more intermediate positions between the bit positions based on an offset.

11. The receiver circuit of claim 10, further comprising an analog-to-digital converter (ADC) configured to: receive an analog electrical signal derived from the optical signal and convert the analog electrical signal into a binary signal; and wherein, The samples are based on a plurality of decision thresholds located at locations associated with a transmission region between a probability density of zero transmissions satisfying a first threshold and a probability density of one transmission satisfying a second threshold.

12. The receiver circuit according to any one of claims 10 to 11, characterized in that The receiver circuit includes: a photodiode, which is configured to convert an optical signal into an electrical signal; and a plurality of limiting amplifiers, which are configured to convert the electrical signal into a binary signal to output an XOR operation; wherein a first limiting amplifier among the plurality of amplifiers includes a first decision threshold, and a second limiting amplifier among the plurality of amplifiers includes a second decision threshold among the plurality of decision thresholds that is different from the first decision threshold.

13. The device according to any one of claims 10 to 12, characterized in that The log-likelihood ratio circuit is configured to receive samples from the clock data recovery circuit and generate a soft information output signal represented by a log-likelihood ratio based on the conditional probability that the received sample is a bit 1 or a bit 0 and based on at least one additional intermediate value of the offset.

14. The device according to any one of claims 10 to 13, characterized in that The clock data recovery circuit is configured to generate samples as consecutive samples and select an offset as an optimal sample offset to determine one or more intermediate samples at one or more intermediate positions between 0 and 1.

15. The apparatus according to any one of claims 10 to 14 further comprises an analog-to-digital converter comprising a bit resolution of 2 to 3 bits for a plurality of decision thresholds; wherein the plurality of decision thresholds are based on gradients and are updated based on the step size and gradient in a training phase of the ADC.

16. A method for an electrical duobinary receiver circuit, comprising: receiving an optical signal through a photodiode; The optical signal is converted into an electrical signal through a photodiode; Based on multiple decision thresholds, convert the electrical signal into a binary signal; determining, by a clock data recovery circuit, a plurality of samples based on a conditional probability that a received sample is a bit 1 or a bit 0, and determining at least one additional intermediate sample based on an offset; and, Generate soft information based on multiple samples to decode the transmitted bit sequence.

17. The method according to claim 16, further comprising: Outputting a first digital signal through a first limiting amplifier, wherein when the electrical signal exceeds a first decision threshold among a plurality of decision thresholds, the first digital signal has a digital high value, otherwise, the first digital signal has a data low value; Outputting a second digital signal through a second limiting amplifier, wherein when the electrical signal exceeds a second decision threshold among a plurality of decision thresholds, the second digital signal has a digital high value, otherwise, the second digital signal has a data low value; The first determination threshold and the second determination threshold are different and are unequally spaced from each other.

18. The method according to claim 17, further comprising: Based on the logic operation performed on the first digital signal and the second digital signal, a binary signal is output.

19. The method according to any one of claims 16 to 18, further comprising: Generate samples as continuous samples; selecting an offset as an optimal sample offset to determine at least one intermediate sample; as well as, The probability of a bit position is determined based on consecutive samples and at least one intermediate sample; wherein the number of bit positions comprises two or three.

20. The method according to any one of claims 16 to 19, further comprising: A plurality of decision thresholds are determined based on the gradient.

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