A phase gate-free modular multiplication circuit usable for quantum key recovery attacks

Abstract

This invention relates to the fields of quantum computing and quantum cryptography, specifically to a modular multiplication circuit without phase gates that can be used for quantum key recovery attacks; it includes: an adder circuit for constructing +1; a +1 circuit; a semiclassical carry unit; a semiclassical constant arithmetic adder circuit; a semiclassical comparator; a semiclassical constant modular adder circuit based on bisection; a semiclassical out-of-place constant modular multiplication circuit; and a semiclassical in-place constant modular multiplication circuit. Since the circuit in this invention only contains X gates, √X gates, CX gates, and multiple CX gates, the quantum circuit in this invention can be easily simulated on a classical computer, and its correctness can be tested without a large amount of computational resources. At the same time, this circuit can also minimize the loss of computational accuracy caused by phase synthesis.

Description

Technical Field

[0001] This invention relates to the fields of quantum computing and quantum cryptography, and specifically to a phase-gate-free modular multiplication circuit that can be used for quantum key recovery attacks. Background Technology

[0002] Quantum cryptography and quantum computing are two important branches of quantum information science. They both utilize fundamental principles of quantum mechanics, such as superposition, entanglement, and the uncertainty principle, to achieve advantages in information processing and communication.

[0003] Quantum computing uses qubits as the basic unit of information and operates through quantum gates. Compared to classical computing, the main advantages of quantum computing are its parallelism and low energy consumption. Parallelism allows quantum computers to process large amounts of information simultaneously, while low energy consumption makes them more advantageous when processing large-scale data.

[0004] Quantum cryptography, especially quantum key recovery attacks, applies the fundamental principles of quantum mechanics, such as quantum entanglement and the Heisenberg uncertainty principle, and combines them with the advantages of quantum computing. It uses quantum algorithms to attack classical cryptosystems (such as RSA and ECC), providing a key recovery attack method based on quantum algorithms.

[0005] Most of the proposed quantum key recovery attack algorithms are based on phase gates, or on classical computing methods rather than quantum computing. Algorithms that do not use phase gates are still very rare. Summary of the Invention

[0006] To address the aforementioned problems, this invention provides a phase-gate-free modular multiplication circuit that can be used against quantum key recovery attacks. The circuit is characterized by the absence of phase gates and the use of semi-classical control. The circuit construction includes the following steps:

[0007] S1. Use Figure 2 PG gate construction in Figure 1 The PGAdder circuit is shown. The PGAdder circuit is used to calculate |b>|a>→|b+a>|a>, and does not accept carry from external inputs before the circuit is executed, nor does it output the carry of the highest bit after b+a;

[0008] S2. Using by Figure 1 The PGAdder circuit executes the generated PGSubtractor and X gate in reverse order to construct... Figure 3The +1 circuit shown. This circuit is used to calculate |x>|g> → |x + 1>|g>, which does not receive the carry input externally before the circuit execution and does not output the carry of the highest bit after +1, and g is a qubit in an unknown state;

[0009] S3. Use X, CX, CCX to construct a semi - classical carry adder as Figure 4 . If there is a carry in b + a, then c4 = 1, otherwise there is no carry, where a is classically known, b is stored in a qubit, c4 is the highest bit of b + a, and g is in an unknown state;

[0010] S4. Based on the semi - classical carry adder in Figure 4 , construct a semi - classical comparator. Let this circuit perform the subtraction operation b - a. If c4 = 1, then b ≥ a; if c4 = 0, then b < a. Before constructing this comparator, the two's complement of - a needs to be calculated first, and a is classically known, b is stored in a qubit, and g is in an unknown state;

[0011] S5. Based on the binary - splitting idea, use the semi - classical carry adder in Figure 4 , and the +1 circuit in Figure 3 to construct a semi - classical constant addition circuit that calculates b + a, where a is classically known, b is stored in a qubit, and g is in an unknown state. The specific construction process of the semi - classical constant addition circuit (as shown in Figure 5 ) based on the binary - splitting idea is as follows:

[0012] Suppose we use 7 qubits to store b. First, based on the binary - splitting idea, we construct the tree - like diagram shown in Figure 10 :

[0013] The small numbers in the nodes represent the lower - order bits of b in binary. The left child of the node represents the lower - order bit b l , and the right child of the node represents the higher - order bit b h . Then, in the order of level - order traversal, we perform the operations shown in Figure 11 on each node except the leaf nodes in this tree - like diagram, where carrier represents the semi - classical carry adder in Figure 4 :

[0014] Finally, for the leaf nodes, if the binary bit of a i corresponding to a qubit of b is 1, then we apply an X - gate to this qubit, otherwise do nothing;

[0015] S6. Use the semi - classical comparator in S4 and the semi - classical constant addition circuit in Figure 5 to construct a semi - classical constant modulo addition circuit as shown in Figure 6 ;

[0016] S7. Use Figure 6 To construct a semiclassical constant-modulus circuit, such as Figure 7 A semi-classical out-of-place version of the constant modular multiplication circuit, constructed according to the following formula:

[0017]

[0018] S8. Use Figure 7 A semi-classical out-of-place version of the constant modular multiplication circuit, utilizing classical modular inverse calculation and decomposition techniques to construct, for example... Figure 8 A semi-classical in-place version of the constant-modulus multiplication circuit;

[0019] The beneficial effects of this invention are:

[0020] This invention proposes a phase-gate-free modular multiplication circuit that can be used for quantum key recovery attacks. This circuit can be easily simulated on a classical computer and its correctness can be tested without a large amount of computing resources.

[0021] This invention can minimize the loss of computational accuracy caused by phase synthesis.

[0022] This invention has strong versatility and, in the case of quantum hardware, can theoretically perform any number of consecutive modular multiplications. Attached Figure Description

[0023] Figures 1 to 8 All the basic quantum circuit diagrams required for a phase-gate-free modular multiplication circuit that can be used for quantum key recovery attacks, as provided in this embodiment of the invention;

[0024] Figure 1 The circuit diagram of PGAdder provided for embodiments of the present invention;

[0025] Figure 2 A PG gate circuit diagram for a circuit provided in an embodiment of the present invention;

[0026] Figure 3 The +1 circuit diagram provided in the embodiment of the present invention, wherein PGSubtractor is composed of Figure 1 The circuit in the middle is executed in reverse order, and g is in an unknown state;

[0027] Figure 4 This is a semi-classical carry circuit diagram provided for an embodiment of the present invention. The classical known a... i When = 1, the part in the dashed box is inserted into the circuit. i The corresponding position is used; otherwise, no insertion is performed. c4 is the highest bit of b+a, and g is in an unknown state.

[0028] Figure 5 The circuit diagram for a semi-classical constant addition method provided in this embodiment of the invention is shown, where a is classically known and g is in an unknown state.

[0029] Figure 6 This is a semi-classical constant-modulus addition circuit diagram provided in an embodiment of the present invention. N and a are classically known, and cmp is... Figure 4 It was modified from the medium circuit, and the controlled circuit is Figure 5 A controlled version of the circuit;

[0030] Figure 7 The semi-classical out-of-place version of the constant modular multiplication circuit diagram provided in this embodiment of the invention, wherein the controlled circuit is composed of Figure 6 It was modified;

[0031] Figure 8 The semi-classical in-place version of the constant modular multiplication circuit diagram provided in this embodiment of the invention, wherein the modular multiplication circuit is composed of... Figure 7 The circuit configuration is shown in Figure 1. SWAPs represents a circuit diagram of n consecutively operating switching gates.

[0032] Figure 9 A quantum circuit for Shor's prime factorization algorithm provided in this embodiment of the invention;

[0033] Figure 10 A tree diagram provided for embodiments of the present invention;

[0034] Figure 11 This is a schematic diagram of node operations provided in an embodiment of the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] This invention provides a quantum circuit for Shor's prime factorization, such as... Figure 9 As shown, and L is the binary length of j, j k It is the kth bit of the binary representation of j.

[0037] In one embodiment, the present invention is based on Figures 1 to 8 The required modular multiplication circuit was constructed, and the construction process is as follows:

[0038] S1. Use Figure 2The PG gate structure in Figure 1 The PGAdder circuit shown. The PGAdder circuit is used to calculate |b>|a> → |b + a>|a>, does not receive the carry input externally before the circuit execution, and does not output the carry of the highest bit after b + a;

[0039] S2. Use the PGSubtractor generated by reversing the execution of the PGAdder circuit in Figure 1 and the X gate to construct the Figure 3 +1 circuit shown. This circuit is used to calculate |x>|g> → |x + 1>|g>, does not receive the carry input externally before the circuit execution, does not output the carry of the highest bit after +1, and g is a qubit in an unknown state;

[0040] S3. Use X, CX, CCX to construct the semi - classical carry adder as shown in Figure 4 . If there is a carry in b + a, then c4 = 1, otherwise there is no carry, where a is classically known, b is stored in a qubit, c4 is the highest bit of b + a, and g is in an unknown state;

[0041] S4. Based on the Figure 4 semi - classical carry adder in, construct a semi - classical comparator. Let the circuit perform subtraction, i.e., b - a. If c4 = 1, then b ≥ a; if c4 = 0, then b < a. Before constructing this comparator, the two's complement of - a needs to be calculated first, where a is classically known, b is stored in a qubit, and g is in an unknown state;

[0042] S5. Based on the binary - splitting idea, use the Figure 4 semi - classical carry adder in, and the Figure 3 +1 circuit in to construct a semi - classical constant addition circuit. This circuit calculates b + a, where a is classically known, b is stored in a qubit, and g is in an unknown state. The specific construction process of the semi - classical constant addition circuit (as shown in Figure 5 ) based on the binary - splitting idea is as follows:

[0043] Suppose we use 7 qubits to store b. First, based on the binary - splitting idea, we first construct the Figure 10 tree - like diagram shown:

[0044] The small numbers in the nodes represent the low - order bits of b in binary. The left child of the node represents the low - order bit b l , and the right child of the node represents the high - order bit b h . Then, in the order of level - order traversal, we perform the following Figure 11 operation on each node except the leaf nodes in this tree - like diagram, where carrier represents the Figure 4 semi - classical carry adder in:

[0045] Finally, for the leaf nodes, if a corresponds to a qubit of b... i If the binary bit is 1, then we apply an X gate to this qubit; otherwise, we do nothing.

[0046] S6. Uses the semi-classical comparator from S4 and Figure 5 To construct a semi-classical constant adder circuit, such as Figure 6 A semiclassical constant-modulus addition circuit;

[0047] S7. Use Figure 6 To construct a semiclassical constant-modulus circuit, such as Figure 7 A semi-classical out-of-place version of the constant modular multiplication circuit, constructed according to the following formula:

[0048]

[0049] S8. Use Figure 7 A semi-classical out-of-place version of the constant modular multiplication circuit, utilizing classical modular inverse calculation and decomposition techniques to construct, for example... Figure 8 A semi-classical in-place version of the constant-modulus multiplication circuit;

[0050] S9. Applications in cyclic phase estimation, such as Figure 8 The controlled version of the circuit is generated as follows Figure 9 A quantum circuit for Shor's prime factorization algorithm

[0051] The above-described embodiments illustrate the advantages of the present invention. The design of the present invention avoids the use of phase gates and minimizes the loss of computational accuracy caused by phase synthesis, while also providing strong noise immunity.

[0052] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A phase-gate-free modular multiplication circuit that can be used for quantum key recovery attacks, characterized in that, A modular multiplication circuit without phase gates that can be used for quantum key recovery attacks does not contain phase gates and adopts a semiclassical control method. The circuit construction includes the following steps: S1. Construct the PGAdder circuit using PG gates; the PGAdder circuit is used for calculation. ; The PG gate is based on the controlled NOT gate CX and the controlled square root of X Hermitian conjugate gate C-. Controlled square root X gate C- The implementation has three logical inputs arranged from top to bottom. , , , used to represent qubit The corresponding state, with 3 logical outputs arranged from top to bottom. , , , used to represent qubit The state corresponding to the action of the gate over time; in time order from left to right: The corresponding qubits are control bits, in and A controlled √X Hermitian conjugate gate C- is applied to the corresponding qubit. When the control bit is 1, the controlled √X Hermitian conjugate gate C- Work; with The corresponding qubits are control bits, in and A controlled √X Hermitian conjugate gate C- is applied to the corresponding qubit. When the control bit is 1, the controlled √X Hermitian conjugate gate C- Work; with The corresponding qubits are control bits, in and Applying CX to the corresponding qubit activates CX when the control bit is 1; The corresponding qubits are control bits, in and A controlled square root X gate C- is applied to the corresponding qubit. When the control bit is 1, the controlled square root X gate C- Work; The PGAdder circuit does not process carry-over from external inputs before the PGAdder circuit executes, nor does it generate carry-over from the highest bit of the summation result; the PGAdder circuit is implemented based on PG gates, controlled NOT gates CX, and Toffoli gates CCX, and has 8 logic inputs arranged sequentially from top to bottom. ~ , ~ , used to represent and The corresponding qubit state, 8 bits arranged from top to bottom as the logic output ~ , ~ , used to represent and The state of the corresponding qubit after passing through a gate over time; The construction of the PGAdder circuit, in chronological order from left to right, includes: S1.1, with ~ The corresponding qubits are control bits, in ~ and ~ A controlled NOT gate CX is applied sequentially to the corresponding qubit. The controlled NOT gate CX is active when the control bit is 1. S1.2, with ~ The corresponding qubits are control bits, in ~ and ~ A controlled NOT gate CX is applied sequentially to the corresponding qubit. The controlled NOT gate CX is active when the control bit is 1. S1.3, with ~ , ~ The corresponding qubits are control bits, in ~ , ~ and ~ CCX gates are applied sequentially to the corresponding qubits. When the control bit is 1, the Toffoli gate CCX is active. S1.4, in ~ , ~ and ~ PG gates are sequentially applied to the corresponding qubits, where 0, 1, and 2 represent the top-to-bottom arrangement of the input or output. Corresponding to the 0th input, Corresponding to the first input, Corresponding to the second input; S1.5, with ~ The corresponding qubits are control bits, in ~ and ~ A controlled NOT gate CX is applied sequentially to the corresponding qubit. The controlled NOT gate CX is active when the control bit is 1. S1.6, with ~ The corresponding qubits are control bits, in ~ and ~ A controlled NOT gate CX is applied sequentially to the corresponding qubit. The controlled NOT gate CX is active when the control bit is 1. S2. Construct a +1 circuit using the PGSubtractor generated by reversing the PGAdder circuit and the X gate; the +1 circuit is used to calculate... ; The +1 circuit does not process the carry from the external input before the +1 circuit is executed, nor does it generate the carry from the highest bit after the +1 circuit. Furthermore, in the +1 circuit... These are quantum bits in an unknown state; the +1 circuit has 8 logic inputs arranged from top to bottom. ~ , ~ , used to represent and The corresponding qubit state, 8 bits arranged from top to bottom as the logic output ~ , ~ , used to represent and The state of the corresponding qubit after passing through a gate over time; In chronological order from left to right, the +1 circuit includes: S2.1, in ~ and ~ PGSubtractor gates are applied sequentially to the corresponding qubits; S2.2, in ~ The corresponding qubits are sequentially subjected to NOT gate X; S2.3, in ~ and ~ PGSubtractor gates are applied sequentially to the corresponding qubits; S2.4, in ~ The corresponding qubits are sequentially subjected to NOT gate X; S3. Construct a semi-classical carry generator using X, CX, and CCX; if If there is a carry Conversely, there is no carry-over, among which express The highest position; Semi-classical carry Classic and known, Stored in qubits The state is unknown; the semi-classical carry unit has 4 logic inputs arranged from top to bottom. ~ , used to represent The corresponding state of a qubit, with 3 logical inputs arranged from top to bottom. ~ , used to represent The corresponding state of a qubit, 1 bit of logic input ; 4-bit logic output arranged from top to bottom ~ 3 logical outputs arranged from top to bottom ~ 1-bit logic output , used to represent ~ , ~ and The circuit calculates the state of the gate over time. Carry-over, That is, the carry flag; In chronological order from left to right, the construction of the semiclassical carry generator includes: S3.1, with The corresponding qubits are control bits, in and A controlled NOT gate CX is applied to the corresponding qubit. The controlled NOT gate CX is active when the control bit is 1. S3.2, with The corresponding classic binary bits are control bits, when When the corresponding classic binary bit is 1, in ~ and ~ A controlled NOT gate CX is sequentially applied to the corresponding qubit, and then... ~ Apply NOT gate X; ~ and ~ The corresponding qubits are control bits, in ~ , ~ and ~ Tooffoli gates and CCX gates are sequentially applied to the corresponding qubits. CCX is activated when the control bit is 1. S3.3, with and The corresponding qubits are control bits, in , and CCX gates are applied sequentially to the corresponding qubits. When the control bit is 1, the Toffoli gate CCX is active. S3.4, with ~ and ~ The corresponding qubits are control bits, in ~ , ~ and ~ CCX gates are applied sequentially to the corresponding qubits; the CCX gates are activated when the control bit is 1. S3.5, with The corresponding qubits are control bits, in and A controlled NOT gate CX is applied to the corresponding qubit. The controlled NOT gate CX is active when the control bit is 1. S3.6, Apply the gates in S3.4 in reverse order; S3.7, Apply the gates in S3.3 in reverse order; S3.8, Apply the gates in S3.2 in reverse order; S4. Construct a semi-classical comparator based on a semi-classical carry operator, and let the semi-classical comparator perform subtraction operations, i.e., execute... ,if but ,if but ; S5. Based on the binary search concept, a semiclassical carry circuit and a +1 circuit are used to construct a semiclassical constant adder circuit. The semiclassical constant adder circuit calculates... ; Semiclassical constant adder circuit Classic and known, Stored in qubits The state is unknown; the semiclassical constant adder circuit decomposes the semiclassical constant adder process into a finite number of carry and +1 operations, used to calculate the values ​​represented by qubits. and classic known The sum; the semiclassical constant adder circuit is equipped with Logical inputs arranged from top to bottom , used to represent The corresponding state of a qubit Logical inputs arranged from top to bottom , used to represent The state corresponding to a qubit; The logic outputs are arranged from top to bottom. , The logic outputs are arranged from top to bottom. , used to represent and The state of the corresponding qubit after passing through a gate over time; The specific construction process of the semiclassical constant adder circuit based on the bisection method includes: Stored using 7 qubits According to the dichotomy method A binary tree is obtained by partitioning the qubits. Each parent node in the binary tree has two child nodes: a left child and a right child, representing the low-order and high-order bits of the parent node's qubits, respectively. Each node is composed of binary qubits. The top-level parent node is labeled [0, 1, 2, 3, 4, 5, 6], which has 7 qubits. Dividing the number of qubits in the parent node by 2 and taking the upper bound, we obtain the number of qubits in the left child node. The lower four qubits, [0, 1, 2, 3], have corresponding right children. The three high-order qubits are [4, 5, 6]; this process is repeated until only one qubit in the left and right children forms a binary tree; according to the level-order traversal, low-order carry and high-order +1 are performed on each non-leaf node of the binary tree; the low-order carry and high-order +1 are implemented based on a controlled +1 gate, a controlled NOT gate (CX), and a semi-classical carry gate (carrier), where the controlled +1 gate is the controlled circuit of the +1 circuit, and the carrier is a semi-classical carry device; the circuit for implementing low-order carry and high-order +1 has logic inputs arranged sequentially from top to bottom. , , , respectively represent , , The states of the corresponding qubits; the logical outputs arranged from top to bottom. , , , respectively represent , , The state after the gate has been applied over time; The construction of the circuit for implementing carry-in from the low bit and +1 from the high bit, in left-to-right time order, includes: S5.1, with The corresponding qubit is the control bit, in and A controlled +1 gate is applied to the corresponding qubit; the controlled +1 gate operates when the control bit is 1. S5.2, with The corresponding qubit is the control bit, in and A controlled NOT gate is applied to the corresponding qubit; S5.3, in , and Apply a carrier gate to the corresponding qubit; S5.4, with The corresponding qubit is the control bit, in and A controlled +1 gate is applied to the corresponding qubit; the controlled +1 gate operates when the control bit is 1. S5.5, in , and Apply a carrier gate to the corresponding qubit; S5.6, with The corresponding qubit is the control bit, in and A controlled NOT gate is applied to the corresponding qubit; For leaf nodes, if they are... One qubit corresponds to If the binary bit is 1, an X gate is applied to this qubit; otherwise, nothing is done. S6. Construct a semiclassical constant modulus adder circuit using a semiclassical comparator and a semiclassical constant adder circuit; The semiclassical constant-modulus adder circuit is based on Door, under control Door, under control Door, Circuit and NOT gate implementation; The gate is obtained by executing a semiclassical comparator, which is controlled. The gate is a controlled circuit of a semiclassical constant adder circuit. It operates when the control bit is 0 and is controlled. The gate is a controlled circuit of a semiclassical constant adder circuit, and it operates when the control bit is 1; The logic inputs of a semiclassical constant-modulus adder circuit include: Logical inputs arranged from top to bottom , used to represent The corresponding state of a qubit Logical inputs arranged from top to bottom , used to represent The corresponding state of a qubit, 1 logic input , used to represent The state of the corresponding qubit; the logical output includes: The logic outputs are arranged from top to bottom. , The logic outputs are arranged from top to bottom. 1-bit logic output , used to represent , The state of a qubit corresponding to 0 after passing through a gate over time is... It is a positive integer not less than 2; the function of the semiclassical constant modulus adder circuit is to calculate... In chronological order from left to right: , and Apply to the corresponding qubit Door; with The corresponding quantum bit control bit, in and Apply controlled force to the corresponding qubit The gate is controlled when the control bit is 0. Door work; with The corresponding quantum bit control bit, in and Apply controlled force to the corresponding qubit The gate is controlled when the control bit is 1. Door work; in , and Apply to the corresponding qubit Door; at Apply an NOT gate to the corresponding qubit; S7. Use a semiclassical constant-modulus adder circuit to construct a semiclassical out-of-place constant-modulus multiplier circuit; S8. Use a semiclassical out-of-place constant modular multiplication circuit to construct a semiclassical in-place constant modular multiplication circuit.

2. The modular multiplication circuit without phase gates that can be used for quantum key recovery attacks according to claim 1, characterized in that, A semiclassical comparator requires calculation before construction. The complement, and Classic and known, Stored in qubits It is in an unknown state.

3. A modular multiplication circuit without phase gates that can be used for quantum key recovery attacks according to claim 1, characterized in that, Semi-classical out-of-place constant modular multiplication circuit, based on controlled The gate is implemented, the controlled The gate is a controlled circuit of a semiclassical constant-modulus addition circuit, and is equipped with... Logical inputs arranged from top to bottom ~ , used to represent The corresponding state of a qubit Logical inputs arranged from top to bottom The semi-classical out-of-place constant modular multiplication circuit has the following features: The logic outputs are arranged from top to bottom. ~ , The logic outputs are arranged from top to bottom. 1-bit logic output , respectively represent , Bit 0 and bit 10 correspond to the states of a quantum bit after being gated over time; An out-of-place version of the semiclassical constant modular multiplication circuit is used for calculation. The semiclassical out-of-place constant modular multiplication circuit is constructed according to the following formula: ； In chronological order from left to right, the construction of the semiclassical out-of-place constant modular multiplication circuit includes: The corresponding qubit is the control qubit, in , Bit 1 person Apply controlled force to the corresponding qubit The gate is controlled when the control bit is 1. Door work, .

4. A modular multiplication circuit without phase gates that can be used for quantum key recovery attacks according to claim 1, characterized in that, The semiclassical in-place constant modular multiplication circuit requires classical modular inverse calculation and decomposition techniques; it is implemented based on out-of-place semiclassical constant modular multiplication gates and swap gates. The out-of-place semiclassical constant modular multiplication gates are obtained by sequentially executing the semiclassical out-of-place constant modular multiplication circuit, and are equipped with... Logical inputs arranged from top to bottom , Logical inputs arranged from top to bottom The semi-classical in-place constant modular multiplication circuit is equipped with... The logic outputs are arranged from top to bottom. , The logic outputs are arranged from top to bottom. 1-bit logic output , respectively represent Bit , Bit 0 and bit 1 correspond to the states of a qubit after being gated over time; an in-place version of the semiclassical constant modular multiplication circuit is used to calculate... ; In chronological order from left to right, the construction of the semiclassical in-place constant modular multiplication circuit includes: Step 1, in Bit , Bit and 1 person Apply out-of-place semiclassical constant modular multiplication gates to the corresponding qubits ; Step 2, in Bit , Bit Swap gates are applied to the corresponding qubits; Step 3, in Bit , Bit and 1 person Apply out-of-place semiclassical constant modular multiplication gates to the corresponding qubits .

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