Data processing method based on Shenwei CPU instruction set

Abstract

The present application is about a data processing method based on the Shenwei CPU instruction set, and relates to the field of cryptographic processing technology. The method includes: obtaining data to be processed, the data to be processed is configured with a national secret algorithm type identifier; determining the operation optimization mode corresponding to the data to be processed based on the national secret algorithm type identifier; generating processing instructions corresponding to the operation optimization mode, the processing instructions include register processing instructions and data processing instructions, the register processing instructions are associated with the mode of writing the data to be processed into the register, and the data processing instructions are associated with the processing mode of the data to be processed. This method makes full use of the characteristics of the Shenwei CPU dedicated instruction set, works efficiently with the hardware, and improves the utilization rate of the CPU core by parallel processing and optimizing the instruction set. It not only ensures the security characteristics of the national secret algorithm, but also more obviously optimizes the overall algorithm performance when processing large amounts of data, so that the algorithm efficiency is greatly improved.

Description

Technical Field

[0001] The present application relates to the field of cryptographic processing technology, and in particular to a data processing method based on the Shenwei CPU instruction set. Background Art

[0002] Shenwei CPU has a unique architectural design. Based on the application of the unique architectural design, it has an independently supported efficient instruction set to achieve large-scale computing.

[0003] In the related technology, when using Shenwei CPU, its general instruction set is usually used to perform calculation functions.

[0004] However, when applying the general instruction set of Shenwei CPU, in the application scenario of modular operation, the general instruction set cannot give full play to the computing power of Shenwei CPU, resulting in low efficiency of data processing and algorithm execution. Summary of the invention

[0005] The present application relates to a data processing method based on the Shenwei CPU instruction set, which can improve the data processing efficiency of the Shenwei CPU. The method is applied to a computer device, and the method includes:

[0006] Get the data to be processed, which is configured with the national encryption algorithm type identifier;

[0007] Determine the operation optimization mode corresponding to the data to be processed based on the national secret algorithm type identifier;

[0008] Generate processing instructions corresponding to the operation optimization mode, the processing instructions include register processing instructions and data processing instructions, the register processing instructions are associated with the mode of writing the data to be processed into the register, and the data processing instructions are associated with the processing mode of the data to be processed.

[0009] In an optional embodiment, the national secret algorithm type identifier includes a national secret SM2 algorithm identifier, a national secret SM3 algorithm identifier, and a national secret SM4 algorithm identifier;

[0010] The operation optimization modes include the national secret SM2 operation optimization mode, the national secret SM3 block loop processing mode and the national secret SM4 vectorized processing mode.

[0011] In an optional embodiment, the national secret SM2 operation optimization mode includes an addition operation mode, a subtraction operation mode, a multiplication operation mode, and a modular operation mode;

[0012] In response to the optimization mode being the national secret SM2 operation optimization mode, generating a processing instruction corresponding to the operation optimization mode, including:

[0013] Determine a register data storage mode corresponding to the operation optimization mode;

[0014] Corresponding to the register data storage mode, the data to be processed is split;

[0015] Combined with the result of data splitting, the data to be processed is filled into the register;

[0016] Based on the operation optimization mode and the register data storage mode, a processing instruction corresponding to the operation optimization mode is generated.

[0017] In an optional embodiment, before determining the register data storage mode corresponding to the operation optimization mode, the method includes:

[0018] The number of data bits corresponding to the register data is determined based on the number of data bits of the data to be processed.

[0019] In an optional embodiment, the method further comprises:

[0020] Determine a mapping relationship corresponding to an operation optimization mode;

[0021] Based on the mapping relationship, a processing instruction corresponding to the operation optimization mode is generated.

[0022] In an optional embodiment, in response to the optimization mode being the national secret SM3 block loop processing mode, generating a processing instruction corresponding to the operation optimization mode includes:

[0023] Determine the block filling rules corresponding to the data to be processed;

[0024] Based on the block filling rule, determine the expansion rule and compression rule corresponding to the data to be processed;

[0025] Based on the expansion rule and the compression rule, a processing instruction corresponding to the calculation optimization mode is generated.

[0026] In an optional embodiment, based on the block filling rule, determining the expansion rule and the compression rule corresponding to the data to be processed includes:

[0027] Based on the block filling rule, determine the number of extensions corresponding to the extension instruction and the number of characters in the extension result;

[0028] Determine an expansion rule based on the number of expansions and the number of characters in the expansion result;

[0029] Based on the number of expansions and the number of characters in the expansion result, the number of compression groups and the concatenated elements are determined;

[0030] Based on the number of compression groups and the concatenated elements, expansion rules and compression rules corresponding to the data to be processed are determined.

[0031] In an optional embodiment, in response to the optimization mode being the national secret SM4 vectorized processing mode, generating a processing instruction corresponding to the operation optimization mode includes:

[0032] Acquire key expansion data, the key expansion data including key expansion times data and round key quantity data;

[0033] Acquire grouping mode data, where the grouping mode data is used to indicate a working mode of the data to be processed;

[0034] Based on the key expansion data and the grouping pattern data, a processing instruction corresponding to the operation optimization mode is generated.

[0035] In an optional embodiment, the working modes of the data to be processed include ECB mode, CBC mode, CFB mode and CTR mode.

[0036] In an optional embodiment, after the processing instruction corresponding to the operation optimization mode is generated, the method further includes:

[0037] The data to be processed is processed based on the processing instruction to obtain a data processing result.

[0038] The technical effects of each embodiment of the present application include at least:

[0039] This method makes full use of the characteristics of Shenwei CPU's dedicated instruction set, works efficiently with the hardware, and improves the utilization of CPU cores through parallel processing and optimized instruction sets. It not only ensures the security characteristics of the national secret algorithm, but also more obviously optimizes the overall algorithm performance when processing large amounts of data, greatly improving the algorithm efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 A flow chart of a data processing method based on the Shenwei CPU instruction set provided by an exemplary embodiment of the present application is shown.

[0042] Figure 2 A flowchart of a data processing method in an application scenario of the national encryption SM2 algorithm provided by an exemplary embodiment of the present application is shown.

[0043] Figure 3A flowchart of a data processing method in an application scenario of the national encryption SM3 algorithm provided by an exemplary embodiment of the present application is shown.

[0044] Figure 4 A flowchart of a data processing method in an application scenario of the national encryption SM4 algorithm provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0046] First, the various terms involved in the embodiments of the present application are introduced:

[0047] The Shenwei processor is a high-performance processor that uses system-on-chip technology to integrate 4 computing control cores and 256 computing cores in a single chip. It uses the independently designed 64-bit Shenwei RISC instruction system, supports 256-bit SIMD integer and floating-point vector accelerated operations, and the single-chip double-precision floating-point peak performance reaches 3.168TFLOPS. In one example, the processor corresponding to this application is the Shenwei 26010 processor. Optionally, the Shenwei 26010 processor is based on a 28nm process, with a chip area of ​​more than 500mm, and a stable operating frequency of 260 cores reaching 1.5GHz. From the structural level, microstructure level to the circuit level, a variety of low-power design technologies are comprehensively adopted, and the peak energy efficiency ratio reaches 10.559GFLOPS / W.

[0048] The corresponding Shenwei processor is equipped with a self-designed 64-bit Shenwei instruction set, which supports 256-bit SIMD integer and floating-point vector acceleration operations and is optimized for high-performance computing. The Shenwei processor is good at processing regular and easy-to-parallel computing-intensive tasks, with larger-scale multi-level parallel computing units and a unique on-chip storage structure. Therefore, it can adapt to the application scenarios of national secret computing.

[0049] Figure 1 A flow chart of a data processing method based on the Shenwei CPU instruction set provided by an exemplary embodiment of the present application is shown, and the method is described by taking the application of the method in a computer device as an example. The method includes:

[0050] Step 101, obtaining data to be processed.

[0051] In the embodiment of the present application, the data to be processed is configured with a national secret algorithm type identifier. That is, the data to be processed is processed under the application scenario of the national secret algorithm. Optionally, the data to be processed is data to be encrypted, or the data to be processed is data to be decrypted.

[0052] Step 102, determining the operation optimization mode corresponding to the data to be processed based on the national encryption algorithm type identifier.

[0053] In the embodiment of the present application, the national secret algorithm type identifier is used to indicate the algorithm processing type required for the data to be processed. Optionally, the national secret algorithm type identifier is marked by the computer device during the process of acquiring the data to be processed.

[0054] Step 103: Generate processing instructions corresponding to the operation optimization mode, where the processing instructions include register processing instructions and data processing instructions.

[0055] In the embodiment of the present application, the data processing instruction is associated with the processing mode of the data to be processed. That is, the computer device generates the register processing instruction and the data processing instruction according to the specific content of the national secret algorithm type identification. Optionally, the register processing instruction and the data processing instruction are associated with the processing requirements of the processed data.

[0056] It should be noted that, in the embodiment of the present application, the national secret algorithm type identifier includes the national secret SM2 algorithm identifier, the national secret SM3 algorithm identifier and the national secret SM4 algorithm identifier;

[0057] Corresponding to this situation, the operation optimization modes include the national secret SM2 operation optimization mode, the national secret SM3 block loop processing mode and the national secret SM4 vectorized processing mode.

[0058] In the embodiments of the present application, the operation optimization mode and the processing instructions are described corresponding to the data processing rules and data processing examples.

[0059] Optionally, after generating a processing instruction corresponding to the operation optimization mode, the computer device processes the data to be processed based on the processing instruction to obtain a data processing result.

[0060] Figure 2 A flow chart of a data processing method in an application scenario of the national secret SM2 algorithm provided by an exemplary embodiment of the present application is shown. The method is described by taking the application of the method in a computer device as an example. The method includes:

[0061] Step 201 : determining the number of data bits corresponding to register data based on the number of data bits of the data to be processed.

[0062] In the embodiment of the present application, since the SM2 algorithm involves large number operations and elliptic curve point operations, in view of its high computational complexity and slow computational speed, the optimization path includes:

[0063] (1) In large number operations, 256-bit parallel addition and subtraction instructions (such as vaddow and vsubow) are introduced to parallelize the addition and subtraction operations of large numbers, reducing the number of operation cycles.

[0064] (2) For the modular operation part, by optimizing the processing steps of modular addition and subtraction and modular multiplication, and using specific hardware acceleration instructions, multiple operation steps are combined into one instruction cycle, effectively improving the operation efficiency.

[0065] (3) In elliptic curve point operations, the Jacobian weighted projective coordinate system is used to represent point operations, which converts complex addition and subtraction in the affine coordinate system into simple projective coordinate system operations, and optimizes the operation speed of point multiplication and point addition through parallel computing.

[0066] In an embodiment of the present application, the computer device needs to determine the number of data bits corresponding to the data to be processed and the number of bits of registers that need to be allocated subsequently, so as to allocate virtual space in advance.

[0067] Step 202, determining a register data storage mode corresponding to the operation optimization mode.

[0068] Optionally, the data storage mode corresponds to the number of bits of the virtual register. In one example, the register is a 256-bit register.

[0069] Step 203, corresponding to the register data storage mode, splitting the data to be processed.

[0070] Optionally, the data to be processed is divided according to the number of bits of the register. In one example, the data to be processed is evenly divided based on the number of bits of the register, for example, the data to be processed is divided into 2 groups of 128 pieces of data.

[0071] Step 204, based on the result of data splitting, fill the data to be processed into the register.

[0072] Corresponding to the example shown in step 203, the first 128 bits and the last 128 bits of the 256-bit register are written respectively.

[0073] Step 205 : Based on the operation optimization mode and the register data storage mode, generate a processing instruction corresponding to the operation optimization mode.

[0074] In an embodiment of the present application, the operation optimization mode includes a specific operation optimization mode. Optionally, corresponding to the data to be processed of the national encryption SM2, the national encryption SM2 operation optimization mode includes an addition operation mode, a subtraction operation mode, a multiplication operation mode and a modular operation mode.

[0075] Next, in the form of examples, operation processing of addition, subtraction, multiplication and modular operation is exemplified.

[0076] (1) 256-bit addition operation:

[0077] Step 1: Parameter 1 is written into the 256-bit registers Va[0] and Va[1]. The first 128 bits are written into the first 128 bits of Va[0], and the last 128 bits are written into the first 128 bits of Va[1]. Parameter 2 is written into the 256-bit registers Vb[0] and Vb[1]. The first 128 bits are written into the first 128 bits of Vb[0], and the last 128 bits are written into the first 128 bits of Vb[1]. Reserve the 256-bit registers Vc[0] and Vc[1].

[0078] Step 2: Calculate Vc[0] = vaddow(Va[0], Vb[0]) of Va[0] and Vb[0], where vaddow is the octal word addition operator for 256-bit data;

[0079] Step 3: Determine whether the 128th bit of Vc[0] is 1. If it is 1, write 1 into the temporary variable t. At the same time, the 128th bit is ANDed with 0, and the other bits are ANDed with 1;

[0080] Step 4: Calculate Vc[1] = vaddow(Va[1] , Vb[1]) of Va[1] and Vb[1], then calculate Vc[1] = vaddow(Vc[1] , t);

[0081] Step 5: Output the calculation results: Vc[0] and Vc[1].

[0082] (2) 256-bit subtraction operation

[0083] Step 1: Parameter 1 is written into the 256-bit registers Va[0] and Va[1]. The first 128 bits are written into the first 128 bits of Va[0], and the last 128 bits are written into the first 128 bits of Va[1]. Parameter 2 is written into the 256-bit registers Vb[0] and Vb[1]. The first 128 bits are written into the first 128 bits of Vb[0], and the last 128 bits are written into the first 128 bits of Vb[1]. Reserve the 256-bit registers Vc[0] and Vc[1].

[0084] Step 2: Borrow from Va[0] in advance, Va[0] = vaddow(Va[0], 0x0ffff ffff ffff ffff ffffffff ffff+1), calculate Vc[0] = vsubow(Va[0], Vb[0]) of Va[0] and Vb[0], determine whether Vc[0] exceeds 128 bits, if the value of the 128th bit is 1, assign 1 to the temporary variable t, otherwise assign 0, Vc[0] = Vc[0] &0x0ffff ffff ffff ffff ffff ffff ffff;

[0085] Step 3: Calculate Va[1] = vaddow(Va[1], 0x0ffff ffff ffff ffff ffff ffff ffffff+t) and borrow one bit, calculate Vc[1] = vsubow(Va[1], Vb[1]) of Va[1] and Vb[1], and determine whether Vc[0] exceeds 128 bits. If the value of the 128th bit is 1, assign 1 to the temporary variable t, otherwise assign 0, remove the borrow bit, Vc[1] = Vc[1] & 0x0ffff ffff ffff ffff ffff ffff ffff;

[0086] Step 4, output data processing results;

[0087] (3) Modular addition and subtraction operations

[0088] In modular addition, a and b are added, and the return value r and the modulus m are determined. If r is greater than m, r is subtracted by n m until the result is less than m. The final value of r is the modulus result;

[0089] In the modular subtraction operation, if a is greater than b, calculate r = gm_i_bn_sub(a, b); otherwise, compare b and m. If b is less than m, calculate t = gm_i_bn_sub(m, b), r = gm_i_bn_add(t, a). If m is less than b, calculate n m added just greater than b, t = gm_i_bn_sub(n*m, b), r = gm_i_bn_add(t, a) (n*m) using addition. r is subtracted from k m until the result is less than m. The final value of r is the modulo result.

[0090] (4) Multiplication

[0091] Step 1: 256-bit a is split and written into the first 128 bits of Va[0] and Va[1], 256-bit b is split and written into the first 128 bits of Vb[0] and Vb[1], and five Vr[0], Vr[1], Vr[2], Vr[3], tmp spaces are reserved as return and cache spaces;

[0092] Step 2: Put Va[0]*Vb[0] into Vr[0], extract the last 128 bits of data of Vr[0] into Vr[1], Vr[0] = Vr[0]&0x0 ffff ffff ffff ffff ffff ffff ffff ffff, remove the carry. Put Va[0]*Vb[1] into tmp, Vr[1] = Vr[1] + tmp to get the first 128 bits and the carry, similarly extract the last 128 bits of data of Vr[1] into Vr[2], Vr[1] = Vr[1]&0x0 ffff ffff ffff ffff ffff ffff ffff;

[0093] Step 3: Put Va[1]*Vb[0] into tmp, Vr[1] = Vr[1] + tmp to get the first 128 bits and carry. Similarly, the data of the last 128 bits of Vr[1] is intercepted and added to Vr[2] and put into Vr[2]. Put Va[1]*Vb[1] into tmp, Vr[2] = Vr[2] + tmp to get the first 128 bits and carry. Similarly, the data of the last 128 bits of Vr[2] is intercepted and put into Vr[3], Vr[2] = Vr[2]&0x0ffff ffff ffff ffff ffff ffff ffff;

[0094] Step 4: The final Vr[0]~Vr[3] is the result, which is a 512-bit data.

[0095] (5) Multiplication to modular multiplication operation

[0096] Step 1: Set up temporary storage space Vtmp[0], Vtmp[1], Vtmp[2], Vtmp[3] Results Vr[0], Vr[1], Vr[2], Vr[3], set up temporary storage Vq[0], Vq[1];

[0097] Step 2: The result of multiplying data a and data b is placed in Vtmp, and Vtmp is assigned to the Vr register;

[0098] Step 3: Multiply the first two 128 bits of Vr or the last result by a fixed value t, and assign the result to split the first 128 bits to Vq[0] and the last 128 bits to Vq[1];

[0099] Step 4: Multiply Vq by the modulus and put the obtained data into Vtmp. Add Vr to Vtmp and put the result into Vr;

[0100] Step 5: If the Vr value is greater than the modulus, subtract the modulus until it is just less than the modulus. The result is the modular multiplication result.

[0101] (6) Modular exponentiation

[0102] Step 1: Set register space Va[0], Va[1], Vb[0], Vb[1], Vm, Vtmp[0], Vtmp[1], Vtmp[2], Vtmp[3];

[0103] Step 2: Set the Vtmp value to 0x1 and Vm to the value of the 256-bit data of Vb;

[0104] Step 3: Calculate the value of Vtmp*Vtmp modulo Vm. Determine whether Vm is an odd number. If it is an odd number, calculate the value of Vtmp*Va modulo Vm and write it into Vtmp;

[0105] Step 4: Vm 256 bits are shifted left by 1 (divided by 2). Return to step 3 until the value of Vm is 0. Vtmp is the result of data processing.

[0106] (7) Modular inverse operation

[0107] This process directly applies modular inverse equation thinking to find the inverse.

[0108] (8) Point operation

[0109] In the embodiment of the present application, the Jacobian weighted projective coordinate system is used to represent the points on the coordinate system. In the Jacobian weighted projective coordinate system, the coordinates of a projective point are represented as (x, y, z), where:

[0110] In Jacobian weighted projective coordinates, the point (x, y, z) corresponds to the point (x / z^2, y / z^3) in the coordinates; similarly, the point (x, y) in the coordinates corresponds to the point (x, y, 1) in Jacobian weighted projective coordinates. With such a correspondence, we let the elliptic curve equation y^2 = x^3 + a*x + b with x = x / z^2 and y = y / z^3, and we get the elliptic curve equation in Jacobian weighted projective coordinates:

[0111] Y^2=x^3+a*xz^4+bz^6,

[0112] We can also see that since the point (x, y, z) corresponds to the point (x / z2, y / z3) in the affine coordinates, when z is zero, there is a point (x, y, 0) in the projective coordinates. This point is also called the "point at infinity" in the affine coordinates, that is, the point where z=0 in the projective coordinates.

[0113] With the above mapping relationship from affine coordinates to Jacobian weighted projective coordinates, we can define the geometric addition operation under Jacobian weighted projective coordinates. Let P and Q be two unequal points, P (x1, y1, z1), Q (x2, y2, z2), let R (x3, y3, z3), and R = P + Q (geometric addition operation), the geometric addition operation process under Jacobian weighted projective coordinates is as follows:

[0114] λ1 = x1 * z2 ^ 2 ,

[0115] λ2 = x2 * z1 ^ 2 ,

[0116] λ3 = λ1 - λ2,

[0117] λ4 = y1 * z 2 ^ 3 ,

[0118] λ5 = y2 * z1 ^ 3 ,

[0119] λ6 = λ4 - λ5,

[0120] λ7 = λ1 + λ2,

[0121] λ8 = λ4 + λ5 ,

[0122] x3 = λ6 ^ 2 - λ7 * λ3 ^ 2 ,

[0123] λ9 = λ7 ^ λ3 ^ 2 - 2 * x3 ,

[0124] y3 = ( λ9 * λ6 - λ8 * λ3 ^ 3 ) / 2,

[0125] z3 = z1 * z2 * λ3,

[0126] The final x 3 , y 3 , z 3 are the Jacobian weighted projective coordinates of point R.

[0127] For scalar multiplication, we first need to calculate two equal points P+P, that is, calculate 2P. Let P (x 1, y 1, z 1), R (x 3, y 3, z 3), the Jacobian weighted projective coordinate operation process is as follows:

[0128] λ1 = 3 * x1 ^ 2 + a * z1 ^ 4 ,

[0129] λ2 = 4 * x1 * y1 ^ 2 ,

[0130] λ3 = 8 * y1 ^ 4 ,

[0131] x3 = λ1^2 – 2*λ2,

[0132] y3 = λ1 * ( λ2 - x3 ) - λ3 ,

[0133] z3 = 2 * y1 * z1 ,

[0134] The value of a is P -3, λ1 = 3 * x1 ^ 2 + a * z1 ^ 4, λ1 = 3 * x1 ^ 2 - 3 * z1 ^ 4, λ1 = 3 * ((x1 + z1 ^ 2) * (x1 - z1 ^ 2)). The final x 3 , y 3 , z 3 are the Jacobian weighted projective coordinates of point R.

[0135] Figure 3 A flow chart of a data processing method in an application scenario of the national secret SM3 algorithm provided by an exemplary embodiment of the present application is shown. The method is described by taking the application of the method in a computer device as an example. The method includes:

[0136] Step 301, determine the block filling rule corresponding to the data to be processed.

[0137] The national secret algorithm SM3 is a hash function designed based on SHA-256, which is mainly used to generate a fixed-length digest. In order to optimize the national secret algorithm SM3, the present invention optimizes its core process - message expansion and iteration. Therefore, the block filling rule is used to indicate the block method and filling method of the data to be processed into the register space.

[0138] Therefore, in the embodiment of the present application, a block filling rule corresponding to the data to be processed is determined.

[0139] Step 302: Determine the number of extensions corresponding to the extension instruction and the number of characters in the extension result based on the block filling rule.

[0140] In the embodiment of the present application, the data to be processed needs to be expanded or compressed when filling to adapt to the requirements of the register space.

[0141] Optionally, the number of expansion times and the number of characters in the expansion result are related to preset content of the computer device.

[0142] Step 303: determine an expansion rule based on the number of expansions and the number of characters in the expansion result.

[0143] Step 304, based on the number of expansions and the number of characters in the expansion result, determine the number of compression groups and the concatenation elements.

[0144] Step 305: Determine a compression rule corresponding to the data to be processed based on the number of compression groups and the concatenation elements.

[0145] In some embodiments of the present application, the number of compression groups corresponds to the number of arrays in the compression process. Optionally, in the compression process, in order to obtain the data processing result of the data to be processed, it is necessary to generate a hash value, so the expansion and compression process will be performed at least twice.

[0146] Next, the data processing process of the data to be processed is explained in the form of an example:

[0147] Step 1: The message data is divided into blocks and filled with data, denoted as M1…Mx…Mn.

[0148] Step 2: Each block of data is extended through a 256-bit instruction, M=vbinvw(Mx) is executed to convert the data endianness, and exp=vsm3msw(M) is executed 7 times to obtain the extended 68-word result.

[0149] Step 3: After the expansion, the 68 words of data are compressed through 8 groups, each group is comx=vsm3r(expx), 256 vconw(expx1,expx2) element splicing, and then execute comx=vsm3r(expx)

[0150] Step 4: The hash result of each block is the compression result of the last step, which is also the initial value IV of the next block.

[0151] Step 5: Loop and execute n times to finally get the hash result of the entire data.

[0152] Figure 4 A flow chart of a data processing method in an application scenario of the national secret SM4 algorithm provided by an exemplary embodiment of the present application is shown. The method is described by taking the application of the method in a computer device as an example. The method includes:

[0153] Step 401, obtaining key extension data.

[0154] In the embodiment of the present application, the key expansion data includes key expansion times data and round key quantity data.

[0155] Step 402, obtaining grouping mode data.

[0156] In the embodiment of the present application, the grouping mode data is used to indicate the working mode of the data to be processed.

[0157] Step 403, generating a processing instruction corresponding to the operation optimization mode based on the key expansion data and the grouping mode data.

[0158] Next, in the form of an example, the data processing process of the data to be processed is described in combination with the optimization mode being the national secret SM4 vectorized processing mode, and the working modes of the data to be processed include ECB mode (electronic codebook mode), CBC mode (cipher block chaining mode), CFB mode (cipher feedback mode) and CTR mode (counter mode):

[0159] First, for the data to be processed, the key expansion process will be performed first, during which:

[0160] Step 1: For key expansion, use the Shenwei sm4 key expansion instruction and loop 4 times to obtain 32 round keys;

[0161] Step 2: Encryption and decryption rounds, use the Shenwei sm4 round instruction, loop 4 times and finally get the encryption result after 32 rounds.

[0162] In the embodiment of the present application, the vsm4r instruction is applied to group the data based on the mode and quantity.

[0163] For ECB mode, the data processing process is as follows:

[0164] For step 1: determine whether the length is an integer multiple of 16, take two groups of data into the 256-bit register in sequence, and modify the big and small ends at the same time;

[0165] Step 2: Based on the reverse round instruction during sm4 decryption, the output is written into the input register four times to finally obtain the 256-bit out;

[0166] Step 3: The out register is converted to a 32-bit memory. Then the data in in is written to the in register to output a 256-bit result. If there are only 128 bits of data at the end, it can be padded with 0 and the first 128 bits can be returned (because ECB blocks do not affect each other).

[0167] For CBC mode, the data processing process is as follows:

[0168] Step 1: Write the rk-round key into four 256-bit registers in advance, get the IV initialization vector from the memory and write it into the 256-bit register, take two groups of ciphertext into the in 256-bit register, and prepare three empty 256-bit registers;

[0169] Step 2: Decrypt the two ciphertext groups as described above in the ECB process. Obtain the first group of decrypted data and XOR it word by word with the initial IV through the XOR instruction, and put the obtained data into the empty register prepared in advance. The decrypted data of the second group and subsequent cycles are XORed with the encrypted data of the previous group to obtain the plaintext;

[0170] Step 3: Get the following two sets of ciphertexts and repeat step 2. Decrypt them one by one to get the final data.

[0171] For CFB mode, the data processing process is as follows:

[0172] Step 1: Write the rk-round key into four 256-bit registers in advance, get the IV initialization vector from the memory and write it into the 256-bit register, take two groups of ciphertext into the in 256-bit register, and prepare three empty 256-bit registers;

[0173] Step 2: First, perform encryption operation on IV and the first ciphertext in ECB mode to obtain data, and then perform XOR with the first ciphertext and the second ciphertext to obtain two plaintexts;

[0174] Step 3: The second group of ciphertext is stored in the register as IV, and step 2 is repeated. All plaintexts are obtained in sequence.

[0175] For CTR mode, the data processing process is as follows:

[0176] Step 1: Write the rk round key into four 256-bit registers in advance, get the IV initialization vector from the memory and write it into the first 16 bits of the 256-bit register, take two groups of plaintext or ciphertext into the in 256-bit register, and prepare two empty 256-bit registers;

[0177] Step 2: First convert the IV value in the register to big and small endian, and set the last eight bits to zero. Then copy the IV value to the last 16 bits of this 256-bit register;

[0178] Step 3: Add 1 to the 256-bit IV register, and use this register as in to input into the SM4 encryption interface to obtain the output out_iv. Perform an octal XOR operation with the plaintext (encrypted) to obtain the encrypted ciphertext.

[0179] Step 4: Get the following two groups from the memory, and write the plaintext or ciphertext into in. Add 0x0000000000000000 00000000 00000001 00000000 00000000 00000000 00000000, and jump to step 3 until the data is read;

[0180] Step 5: Get the result data.

[0181] To sum up, the method provided in the embodiment of the present application fully utilizes the characteristics of Shenwei CPU's dedicated instruction set, works efficiently with the hardware, and improves the utilization rate of the CPU core through parallel processing and optimized instruction sets. It not only ensures the security characteristics of the national secret algorithm, but also more obviously optimizes the overall algorithm performance when processing large amounts of data, thereby greatly improving the algorithm efficiency.

[0182] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A data processing method based on Shenwei CPU instruction set, characterized in that: The method is applied in a computer device, and the method comprises: Obtaining data to be processed, wherein the data to be processed is configured with a national encryption algorithm type identifier; Determine the operation optimization mode corresponding to the data to be processed based on the national secret algorithm type identifier; Generate a processing instruction corresponding to the operation optimization mode, the processing instruction includes a register processing instruction and a data processing instruction, the register processing instruction is associated with a mode of writing the data to be processed into a register, and the data processing instruction is associated with a processing mode of the data to be processed; The national secret algorithm type identifier includes the national secret SM2 algorithm identifier, the national secret SM3 algorithm identifier and the national secret SM4 algorithm identifier; The operation optimization mode includes the national secret SM2 operation optimization mode, the national secret SM3 block loop processing mode and the national secret SM4 vectorized processing mode; wherein, the national secret SM2 operation optimization mode includes an addition operation mode, a subtraction operation mode, a multiplication operation mode and a modular operation mode; In response to the optimization mode being the national secret SM2 operation optimization mode, generating a processing instruction corresponding to the operation optimization mode includes: Determine a register data storage mode corresponding to the operation optimization mode; Corresponding to the register data storage mode, performing data splitting on the data to be processed; Based on the result of data splitting, the data to be processed is filled into the register; Based on the operation optimization mode and the register data storage mode, a processing instruction corresponding to the operation optimization mode is generated.

2. The method according to claim 1, characterized in that Before determining the register data storage mode corresponding to the operation optimization mode, the method includes: The number of data bits corresponding to the register data is determined based on the number of data bits of the data to be processed.

3. The method according to claim 1, characterized in that The method further comprises: Determining a mapping relationship corresponding to the operation optimization mode; Based on the mapping relationship, a processing instruction corresponding to the operation optimization mode is generated.

4. The method according to claim 1, characterized in that In response to the optimization mode being the national secret SM3 block loop processing mode, generating a processing instruction corresponding to the operation optimization mode includes: Determine a block filling rule corresponding to the data to be processed; Based on the block filling rule, determining an expansion rule and a compression rule corresponding to the data to be processed; Based on the expansion rule and the compression rule, a processing instruction corresponding to the operation optimization mode is generated.

5. The method according to claim 4, characterized in that The step of determining an expansion rule and a compression rule corresponding to the data to be processed based on the block filling rule includes: Based on the block filling rule, determine the number of extensions corresponding to the extension instruction and the number of characters in the extension result; Determine the expansion rule based on the number of expansions and the number of characters in the expansion result; Determine the number of compression groups and the concatenation elements based on the number of expansions and the number of characters in the expansion result; Based on the number of compression groups and the concatenated elements, the expansion rule and the compression rule corresponding to the data to be processed are determined.

6. The method according to claim 1, characterized in that In response to the optimization mode being the national secret SM4 vectorized processing mode, generating a processing instruction corresponding to the operation optimization mode includes: Acquire key expansion data, wherein the key expansion data includes key expansion times data and round key quantity data; Acquire grouping mode data, where the grouping mode data is used to indicate a working mode of the data to be processed; Based on the key expansion data and the grouping pattern data, a processing instruction corresponding to the operation optimization pattern is generated.

7. The method according to claim 6, characterized in that The working modes of the data to be processed include ECB mode, CBC mode, CFB mode and CTR mode.

8. The method according to claim 1, characterized in that After the processing instruction corresponding to the operation optimization mode is generated, the method further comprises: The data to be processed is processed based on the processing instruction to obtain a data processing result.

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