A security enhanced can controller based on cryptographic authentication and intrusion detection

Abstract

This invention discloses a security-enhanced CAN controller based on encryption authentication and intrusion detection, designed to address security threats such as remote unlocking and start-stop of vehicles via the Internet of Vehicles (IoV). This application constructs a security framework based on encryption authentication and intrusion detection, utilizing a pre-shared symmetric key combined with AES and HMAC-SHA256 algorithms to encrypt and authenticate CAN communication data, ensuring the confidentiality, integrity, and authenticity of data transmission. Simultaneously, it introduces intrusion detection technology based on information entropy to effectively defend against data frame injection attacks initiated by legitimate nodes. This application employs a strategy of parallel processing of data frame transmission and encryption computation, solving the problem of existing methods where the CAN controller and security module are implemented independently, introducing additional data handling overhead. This achieves efficient transmission of encrypted CAN data and has excellent development and application prospects.

Description

Technical Field

[0001] This invention relates to the field of intelligent connected vehicle security technology, specifically to a security-enhanced CAN controller based on encryption authentication and intrusion detection. Background Technology

[0002] The in-vehicle network (IVN) is the core hub for realizing the collaboration and control of vehicle functions, undertaking the critical tasks of data communication and interaction. The CAN bus, with its advantages of low cost, high integration, good real-time performance, and high flexibility, has become the vehicle's internal network for communication between ECUs. The CAN bus protocol is widely used in automotive powertrain systems and body control, connecting key functional components related to vehicle motion behavior. It is currently the most mature and widely used protocol, and is required as a standard in every mass-produced vehicle. However, the CAN bus protocol specification did not consider the possibility of the in-vehicle bus being exposed to external systems; therefore, the CAN bus protocol has almost no security measures. Once an attacker gains control of a legitimate node, they can control the vehicle's motion behavior, seriously threatening the lives of those involved.

[0003] Numerous researchers both domestically and internationally have proposed several solutions to address the security issues of automotive CAN communication networks. Based on different CAN bus security protection measures, current research can be divided into two categories: security strategies based on encryption and authentication, and security strategies based on intrusion detection. Encryption and authentication-based security strategies can guarantee the confidentiality, integrity, and authenticity of CAN data transmission, but they suffer from incompatibility with the CAN protocol. Compared to encryption and authentication-based security strategies, intrusion detection technology has advantages such as good compatibility, low resource and bandwidth consumption, and convenient deployment. It can effectively identify known attack types, but it suffers from complex algorithm design and cannot completely guarantee security.

[0004] Current research on CAN security strategies mainly focuses on the application layer. Most solutions assume that the ECU has powerful capabilities, but automotive chips are typically 8-bit or 16-bit MCUs, with limited computing power and storage space. Deploying complex and effective security strategies still faces certain challenges. Therefore, researching the hardware implementation of network security strategies for automotive CAN communication is of great significance. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a network security framework based on intrusion detection strategies and encryption authentication mechanisms to ensure the security of the vehicle-mounted CAN communication network. Simultaneously, it ensures the real-time performance of the vehicle-mounted CAN communication network by implementing security policies within the CAN controller.

[0006] The present invention adopts the following technical solution:

[0007] A security-enhanced CAN controller based on encryption authentication and intrusion detection includes the following components:

[0008] This invention designs a CAN controller based on the internal structure diagram of the SJA1000. It integrates intrusion detection, AES, and HMAC-SHA256 algorithm modules to construct a CAN controller with security functions. Its overall architecture is as follows: Figure 1 As shown, the intrusion detection module determines the presence of security threats within the vehicle's CAN communication network by receiving the information entropy of the data frame ID, enabling a rapid response. The encryption and authentication strategy is implemented internally by the bitstream controller, using AES and HMAC-SHA256 modules to perform encryption and authentication calculations, thereby ensuring the confidentiality, integrity, and authenticity of the data.

[0009] Specifically, it includes an intrusion detection module, a bit stream controller, an error logic management module, an HMAC-SHA256 module, an AES module, a register unit, and a bit timing unit. The intrusion detection module determines the presence of security threats within the vehicle's CAN communication network by receiving the entropy of the data frame ID, enabling a rapid response. The bit stream controller internally performs encryption and authentication calculations by calling the AES and HMAC-SHA256 modules, ensuring the confidentiality, integrity, and authenticity of data transmission. The error logic management module manages the error status of nodes in the CAN bus system by monitoring transmit and receive error counts, ensuring high availability of the data transmission system in the event of node failure. The HMAC-SHA256 module calculates MAC values ​​for authentication. The AES module performs encryption and decryption calculations for CAN data. The functions of some registers in the register unit are described in Appendix 1. The bit timing unit provides sampling and transmission points for the bit stream controller and is responsible for timing synchronization with other nodes in the vehicle's CAN communication network.

[0010] Table 1 Register Function Table

[0011]

[0012] As a further improvement of the present invention, the intrusion detection module uses information entropy analysis technology to monitor data frame anomalies in the CAN network, promptly detect and respond to potential network security threats. Its working state is controlled by the ENTR field of the CAN_CFG register. When the ENTR field is set to a high level, the intrusion detection module is activated.

[0013] As a further improvement of the present invention, the intrusion detection module includes a TIME_WINDOW counter, an information entropy calculation module, an anomaly management unit, and an anomaly ID buffer unit. The TIME_WINDOW counter is responsible for counting. When the count value reaches the preset time window length, it sends a calculation request to the information entropy calculation module. When the information entropy calculation module receives the calculation request, it calculates the information entropy based on the IDs recorded within the time window and their quantity. After the information entropy calculation is completed, the information entropy calculation module compares the information entropy value with the legal range. If the information entropy within the time window exceeds the legal range, it sends an anomaly flag to the anomaly management unit and the anomaly ID buffer. The anomaly ID buffer module is used to cache the IDs within the anomaly time window for subsequent in-depth analysis by other devices. The anomaly management unit is used to receive the anomaly flag signal from the information entropy calculation module and dynamically adjust the anomaly window count value. If the entropy value deviates from the normal range, the anomaly window count value is incremented by one. If the entropy value returns to the normal range, the anomaly window count value is decremented by one. When the anomaly count value exceeds the preset risk threshold, the intrusion detection module will trigger a risk interruption.

[0014] As a further improvement of the present invention, the time window is configured by the TIME_WINDOW field of the DFT_CFG register, and can be set to a maximum of 64 seconds.

[0015] As a further improvement of the present invention, the legal interval is the ENTROPY_BOTTOM and ENTROPY_TOP fields. If the anomaly count value further exceeds the danger threshold, when the node is configured as an ECU, an anomaly notification data frame is sent and a danger interruption is triggered; when the node is configured as a gateway, only a danger interruption is triggered; the specific status of the ECU is displayed through the ABN_STAT field of the STAT register; when the ABN_STAT value is 0, it indicates that the node is in a normal working state; when the value is 1, it indicates that the node is in a risk state; when the value is 2, it indicates that the node is in a dangerous state.

[0016] As a further improvement of the present invention, the bitstream controller includes a transmitting bitstream controller, a receiving bitstream controller, and a data path. When the transmission conditions are met, the data path reads the original data from the transmitting buffer and parses it to obtain the ID, DATA, and data frame type of the data frame to be transmitted. Then, the SEND_VLD signal is set to a high level, causing the transmitting bitstream controller to start data frame transmission. At the same time, the ID and DATA signals are assigned the ID and 0 values ​​of the data frame to be transmitted, respectively. After the encryption and authentication calculation is completed, the receiving bitstream controller assigns the ciphertext result to the DATA signal. If the encryption and authentication calculation is completed before the data frame is sent to the data field, the data transmission is guaranteed to be error-free.

[0017] As a further improvement of the present invention, the HMAC-SHA256 module is used to execute the HMAC-SHA256 algorithm, including the HMAC_FSM module and the SHA256_CORE module; the SHA256_CORE module implements the SHA256 algorithm and consists of a W calculation unit, a K calculation unit, a compression function, and a state machine, including the generation of W and K parameters, the iterative update of the compression function, and the calculation of the final hash value; the HMAC_FSM module is responsible for generating data blocks inner_block and outer_block to be processed according to specific padding rules based on the input data, pattern, and key, and sending these data blocks to the SHA256_CORE module in batches for processing.

[0018] As a further improvement of the present invention, the AES module is used to execute the AES algorithm. The bitstream controller first calls the HMAC-SHA256 module to complete the MAC calculation, and then concatenates {EX_DATA||DLC||TIME} with the 32-bit truncated MAC to form a 128-bit encrypted plaintext and performs AES encryption operation. In order to reduce the encryption and authentication operation time, when the MAC calculation starts, the bitstream controller sends the encryption key to the AES module and enables the AES module to start key expansion. When the MAC calculation is completed, the bitstream controller sends the 128-bit plaintext to the AES module and enables the AES module to start round function calculation.

[0019] As a further improvement of the present invention, the error logic management module is used to manage the error state of nodes in the CAN bus system by monitoring the transmit error count and receive error count. Based on the transmit error count register value and receive error count register value, the CAN node may be in: active error state, passive error state, and bus-off state. Active error state is the default state of the CAN node; when an error is detected, the node sends an active error data frame. When the transmit error register value or receive error register value is greater than 127, the node enters a passive error state; if an error is detected at this time, the node will send a passive error data frame. When the active register value or receive error register value is greater than 255, the node enters a bus-off state and does not participate in bus communication. Both the transmit error count register and the receive error count register are defined in the STAT register. The TEC field of the STAT register represents the transmit error count register, the REC field represents the receive error count register, and ERR_STAT represents the error state of the CAN node.

[0020] As a further improvement of the present invention, the CAN controller conforms to the ISO11898 protocol, and its operation process is as follows:

[0021] S1. When a node attempts to send a CAN data frame, the processor writes the raw data into the buffer of the CAN controller.

[0022] S2. When the transmission conditions are met, the CAN controller calls the HMAC-SHA256 and AES modules to complete the encryption and authentication operation, and then sends the data frame to the CAN bus according to the CAN bus protocol rules and encryption and authentication strategy.

[0023] S3. When the bus data frame ID meets the filtering conditions of the receiving node and the CRC check is correct, the receiving node sequentially performs decryption, MAC comparison and count value comparison to determine whether the message is valid.

[0024] S4. If the data is valid, the received data is written to the receive buffer and the ID of the successfully received data frame is sent to the intrusion detection module. If the count value or MAC of the received data frame is invalid, if the device is a gateway node, an interrupt request is sent to the processor to notify the processor that there is an invalid count value or MAC during the data frame reception process, which may indicate an abnormal attack. If the device is an ECU node, in addition to sending an interrupt request to the processor, an abnormal notification data frame is also sent to notify the gateway node that there may be an abnormal attack. When the intrusion detection module detects that the entropy value deviates from the normal situation, it also generates an interrupt request or sends an abnormal notification data frame.

[0025] The beneficial effects of this invention are as follows: by designing the security module inside the CAN controller and using a strategy of parallel processing of data frame transmission and encryption calculation, the problem of additional data handling overhead caused by the independent implementation of the CAN controller and security module in existing methods is solved, thus achieving efficient transmission of CAN encrypted data and having great potential for development and application. Attached Figure Description

[0026] Figure 1 This is a detailed structural diagram of the security-enhanced CAN controller of the present invention.

[0027] Figure 2 This is a structural diagram of the intrusion detection module.

[0028] Figure 3 This is a block diagram of the bitstream controller.

[0029] Figure 4 This is a diagram of the HMAC-SHA256 structure.

[0030] Figure 5 This is the state transition diagram for the AES algorithm. Detailed Implementation

[0031] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0032] Figure 1 The specific structure of the CAN controller is described, with the most important components including the intrusion detection module, bit stream controller module, HMAC-SHA256 module, and AES module.

[0033] Figure 2 This describes the specific structure of the intrusion detection module. The intrusion detection module consists of a TIME_WINDOW counter, anomaly management, information entropy calculation, and anomaly ID buffering modules. The intrusion detection module is a crucial component of the network security system; through the coordinated work of its meticulously designed components, it achieves real-time monitoring of network traffic and rapid identification of potential threats.

[0034] The TIME_WINDOW counter is responsible for the counting function. When the count value reaches the expected time window length, it sends a calculation request to the information entropy calculation module. The time window length is controlled by the detection configuration register (DFT_CFG). The TIME_WINDOW field indicates the time window length used for information entropy calculation, in system clock cycles, and its maximum supported time window length is 64 seconds.

[0035] Since the time window length is adjustable, the capacity of a FIFO structure to buffer received IDs cannot be estimated. Therefore, 56 registers are used (28 registers to store successfully received IDs, and 28 registers to describe the occurrence count of each ID) to store the reception status of data frames within the current time window. When an incoming ID is not within the recording range, the ID is recorded, and the corresponding count register value is incremented by one; when an incoming ID is within the recording range, the corresponding count register value is incremented by one.

[0036] When the information entropy calculation module receives a calculation request, it calculates the information entropy based on the IDs and their corresponding quantities buffered within the time window. The module first converts the fixed-point number (the current number of IDs and the sum of the IDs) into a floating-point number, calls the floating-point division module to obtain the probability p of the occurrence of the ID, then calculates ln2 and lnp, and uses the change-of-base formula to obtain the information content of the current ID. The above process is repeated until the calculation of all IDs is completed, and finally the information entropy is obtained.

[0037] After completing the information entropy calculation, the information entropy calculation module compares the information entropy value with the legal range. If the information entropy exceeds the reasonable range within the time window, the module sends an exception flag to the exception management unit and the exception ID buffer.

[0038] The anomaly ID buffer module caches IDs within an anomaly time window for further in-depth analysis by other devices. The anomaly management unit receives anomaly flag signals from the information entropy calculation module and dynamically adjusts the anomaly window count. If the entropy value deviates from the normal range, the anomaly window count is incremented; if the entropy value returns to the normal range, the anomaly window count is decremented. When the anomaly count exceeds a preset risk threshold, the intrusion detection module triggers a risk interrupt. If the anomaly count further exceeds a danger threshold, when the node is configured as an ECU, an anomaly notification data frame is sent, and a danger interrupt is triggered; when the node is configured as a gateway, only a danger interrupt is triggered. The specific status of the ECU is displayed through the ABN_STAT field of the STAT register. When ABN_STAT is 0, it indicates that the node is in normal working condition; when it is 1, it indicates that the node is in a risky state; and when it is 2, it indicates that the node is in a dangerous state.

[0039] Figure 3 This document describes the design block diagram of the bitstream controller. In the architecture of the security-enhanced CAN controller, the bitstream controller occupies a central position, responsible for performing several key tasks. It significantly improves code readability, maintainability, and overall system performance. The three main components—the transmitting bitstream controller, the receiving bitstream controller, and the data path—each perform their respective functions, working together to weave an efficient and secure data transmission network.

[0040] The transmit bitstream controller primarily performs the following three key functions:

[0041] (1) Generate a bit stream for CRC calculation and call the CRC check module to generate a CRC check code.

[0042] (2) Complete bit filling and fixed bit addition operations, and generate output level according to protocol specifications and data content sent in through the data path.

[0043] (3) Complete multi-host arbitration and automatic retransmission mechanism to ensure efficient and orderly network communication.

[0044] When the SEND_VLD signal is valid, the transmit bitstream controller begins data frame transmission.

[0045] The receive bitstream controller primarily performs the following three key functions:

[0046] (1) When the CAN controller is in the transmit state, it is responsible for listening to the bus level, comparing the controller's output level with the bus level, and generating an arbitration result.

[0047] (2) When the CAN controller is in the receiving state, it is responsible for determining whether to receive CAN data frames from the bus based on the contents of the filter register.

[0048] (3) Send the CAN data frame obtained from the bus into the data path.

[0049] When the start of a frame is detected on the bus, the receive bitstream controller receives the CAN data frame from the bus according to the data frame format state machine. If an error occurs during reception, the controller will suspend data reception and report the corresponding error flag to the error handling logic unit. If no error occurs, the controller checks whether the data frame ID matches the contents of the preset filter register group. If they do not match, the message is discarded; if they match, the CAN data message is further processed, the data frame ID, DATA, and frame type are extracted, and then sent to the data path.

[0050] The data pathway primarily undertakes the following six key functions:

[0051] (1) Parse the raw data obtained from the sending buffer to obtain the data frame type, ID field, DLC field and DATA field of the message to be sent.

[0052] (2) Combine the CAN message ID with the contents of the transmit enable register to perform illegal transmission detection.

[0053] (3) When the encrypted authentication mode is enabled, the session key and counter value are synchronized.

[0054] (4) When the encryption authentication mode is enabled, the HMAC-SHA256 and AES modules are called to complete the MAC calculation and data encryption.

[0055] (5) Transmit the actual data frame content to the transmitting bit stream sensor.

[0056] (6) Process data from the receive bitstream controller. When the encryption authentication mode is not enabled, the successfully received data is directly generated into a raw data frame; when the encryption authentication mode is enabled, the decryption, MAC verification and count value verification are performed, the successfully received data frame is generated into a raw data frame, and then written into the receive buffer and the corresponding register contents are refreshed.

[0057] Figure 4 The structure diagram of HMAC-SHA256 is described. As a key encryption and authentication method, the HMAC-SHA256 algorithm demonstrates its efficiency and flexibility. This invention, targeting application scenarios of HMAC-SHA256, details the encryption and authentication process before data frame transmission.

[0058] To achieve high-speed encryption authentication, this invention designs an efficient hardware architecture, whose core consists of two major modules: HMAC_FSM (HMAC Finite State Machine) and SHA256_CORE (SHA256 Core Processing Unit).

[0059] SHA256_CORE is responsible for performing the core operations of the SHA256 algorithm, including the generation of W and K parameters, iterative updates of the compression function, and the calculation of the final hash value. This module optimizes internal data flow and control logic to ensure that the compression function calculation is completed once per clock cycle, thus meeting the system's high-speed computing requirements.

[0060] HMAC_FSM plays the role of data preprocessing and scheduling. It is responsible for generating data blocks (inner_block and outer_block) to be processed according to specific padding rules based on the input data, pattern, and key, and then sending these data blocks in batches to SHA256_CORE for processing. By precisely controlling the flow of data and the processing order, HMAC_FSM ensures the smooth progress of the encryption and authentication process and ultimately outputs the correct MAC value.

[0061] With a system clock of 16MHz and a communication rate of 1Mbit / s, this invention can complete the encryption authentication calculation within 19μs, fully meeting the real-time requirements.

[0062] Figure 5 The state transition diagram of the AES algorithm is described. The state machine has eight states: A_IDLE, A_EXT, A_EXTD, A_ADD, A_SUB, A_SHIFT, A_MIX, and A_END. Solid arrows represent state transitions in the encryption process, and dashed arrows represent state transitions in the decryption process.

[0063] A_IDLE: The default state after power-on reset. When the key initialization flag (key_init) is valid, it jumps to A_EXT.

[0064] A_EXT: Generates the round key needed for this operation using the initial key from the input port. Once all extended key operations are complete, the state transitions to A_EXTD.

[0065] A_EXTD: Indicates that key expansion is complete and waiting for the computation request signal (invalid). When the invalid signal is high, the state transitions to A_ADD.

[0066] A_ADD: Performs an XOR operation on the round key and the state matrix. When the module is in the encrypted state and the round counter is less than 10, the state transitions to A_SUB after the operation is completed; when the module is in the encrypted state and the round counter is equal to 10, the state transitions to A_END after the operation is completed. When the module is in the decrypted state and the round counter is 0, the state transitions to A_SHIFT after the operation is completed; when the module is in the decrypted state and the round counter is less than 10, the state transitions to A_MIX after the operation is completed; when the module is in the decrypted state and the round counter is equal to 10, the state transitions to A_END after the operation is completed.

[0067] A_SUB: Performs byte substitution operation. When the module is in encrypted state, the state transitions to A_SHIFT after the operation is completed. When the module is in decrypted state, the state transitions to A_ADD after the operation is completed.

[0068] A_SHIFT: Performs row shift operation. When the module is in encrypted state and the round counter is less than 10, the state jumps to A_MIX after the operation is completed; when the module is in encrypted state and the round counter is equal to 10, the state jumps to A_END after the operation is completed; when the module is in decrypted state, the state jumps to A_SUB after the calculation is completed.

[0069] A_MIX: Completes column-mixed calculations. After the column-mixed operation is completed, the state transitions to A_ADD when the module is in encrypted state; and to A_SHIFT when the module is in decrypted state.

[0070] A_END: ​​The final state after the operation is completed. The AES module writes the final output to the bit stream controller, and then the state jumps to A_IDLE.

[0071] In the AES algorithm, byte substitution and column mixing are computationally intensive parts, while row shifting and round key addition are relatively simple and can be directly implemented using combinational logic to optimize resource usage. The state machine automatically transitions according to the encryption / decryption mode and round number to ensure correct algorithm execution. When the AES operation is complete, the encrypted data is sent back to the bitstream controller, ready for transmission, while the state machine resets to A_IDLE, waiting for the next operation.

[0072] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A security-enhanced CAN controller based on encryption authentication and intrusion detection, characterized in that, The system includes an intrusion detection module, a bit stream controller, an error logic management module, an HMAC-SHA256 module, an AES module, a register unit, and a bit timing unit. The intrusion detection module determines the presence of security threats within the vehicle's CAN communication network by receiving the entropy of the data frame ID, enabling a rapid response. The bit stream controller internally performs encryption and authentication calculations by calling the AES and HMAC-SHA256 modules, ensuring the confidentiality, integrity, and authenticity of data transmission. The error logic management module manages the error status of nodes in the CAN bus system by monitoring transmit and receive error counts, ensuring high availability of the data transmission system in the event of node failure. The HMAC-SHA256 module calculates MAC values ​​for authentication, the AES module performs encryption and decryption calculations for CAN data, and the bit timing unit provides sampling and transmission points for the bit stream controller and is responsible for timing synchronization with other nodes in the vehicle's CAN communication network. The bitstream controller includes a transmitting bitstream controller, a receiving bitstream controller, and a data path. When the transmission conditions are met, the data path reads the original data from the transmitting buffer and parses it to obtain the ID, DATA, and data frame type of the data frame to be transmitted. Then, it sets the SEND_VLD signal to a high level, causing the transmitting bitstream controller to start data frame transmission. At the same time, the ID and DATA signals are assigned the ID and 0 values ​​of the data frame to be transmitted, respectively. After the encryption and authentication calculation is completed, the receiving bitstream controller assigns the ciphertext result to the DATA signal. If the encryption and authentication calculation is completed before the data frame is sent to the data field, the data transmission is guaranteed to be error-free. The HMAC-SHA256 module is used to execute the HMAC-SHA256 algorithm, including the HMAC_FSM module and the SHA256_CORE module. The SHA256_CORE module implements the SHA256 algorithm and consists of a W calculation unit, a K calculation unit, a compression function, and a state machine, including the generation of W and K parameters, the iterative update of the compression function, and the calculation of the final hash value. The HMAC_FSM module is responsible for generating inner_block and outer_block of data to be processed according to specific padding rules based on the input data, pattern, and key, and sending these data blocks to the SHA256_CORE module in batches for processing. The AES module is used to execute the AES algorithm. The bitstream controller first calls the HMAC-SHA256 module to complete the MAC calculation, and then concatenates {EX_DATA||DLC||TIME} with the 32-bit truncated MAC to form a 128-bit encrypted plaintext and performs AES encryption. To reduce the encryption and authentication operation time, when the MAC calculation starts, the bitstream controller sends the encryption key to the AES module and enables the AES module to start key expansion. When the MAC calculation is completed, the bitstream controller sends the 128-bit encrypted plaintext to the AES module and enables the AES module to start round function calculation.

2. The security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 1, characterized in that, The intrusion detection module uses information entropy analysis technology to monitor data frame anomalies in the CAN network, promptly detects and responds to potential network security threats. Its working state is controlled by the ENTR field of the CAN_CFG register. When the ENTR field is set to a high level, the intrusion detection module is activated.

3. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 2, characterized in that, The intrusion detection module includes a TIME_WINDOW counter, an information entropy calculation module, an anomaly management unit, and an anomaly ID buffer unit. The TIME_WINDOW counter is responsible for counting; when the count reaches a preset time window length, it sends a calculation request to the information entropy calculation module. When the information entropy calculation module receives the request, it calculates the information entropy based on the IDs recorded within the time window and their quantities. After the information entropy calculation is completed, the information entropy calculation module compares the information entropy value with a valid range. If the information entropy within the time window exceeds the valid range, it sends an anomaly flag to the anomaly management unit and the anomaly ID buffer unit. The anomaly ID buffer unit is used to cache IDs within the anomaly time window for subsequent in-depth analysis by other devices. The anomaly management unit receives the anomaly flag signal from the information entropy calculation module and dynamically adjusts the anomaly window count. If the entropy value deviates from the normal range, the abnormal window count is incremented by one; if the entropy value returns to the normal range, the abnormal window count is decremented by one; when the abnormal count exceeds the preset risk threshold, the intrusion detection module will trigger a risk interruption.

4. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 3, characterized in that, The time window is configured by the TIME_WINDOW field of the DFT_CFG register, and can be set to a maximum of 64 seconds.

5. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 3, characterized in that, The legal range is defined by the ENTROPY_BOTTOM and ENTROPY_TOP fields. If the anomaly count exceeds the danger threshold, when the node is configured as an ECU, an anomaly notification data frame is sent, and a danger interruption is triggered. When the node is configured as a gateway, only a danger interruption is triggered. The specific status of the ECU is displayed through the ABN_STAT field of the STAT register. When the ABN_STAT value is 0, it indicates that the node is in normal working condition. When the value is 1, it indicates that the node is in a risky state. When the value is 2, it indicates that the node is in a dangerous state.

6. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 1, characterized in that, The error logic management module is used to manage the error state of nodes in the CAN bus system by monitoring the transmit error count and receive error count. Based on the transmit error count register value and receive error count register value, the CAN node may be in: active error state, passive error state, and bus off state. Active error state is the default state of the CAN node. When an error is detected, the node sends an active error data frame. When the transmit error register value or receive error register value is greater than 127, the node enters a passive error state. If an error is detected at this time, the node will send a passive error data frame. When the value of the active register or the value of the receive error register is greater than 255, the node enters the bus shutdown state and does not participate in bus communication. Both the transmit error count register and the receive error count register are defined in the STAT register. The TEC field of the STAT register represents the transmit error count register, the REC field represents the receive error count register, and ERR_STAT represents the error status of the CAN node.

7. A security-enhanced CAN controller based on encryption authentication and intrusion detection according to claim 1, characterized in that, The CAN controller conforms to the ISO11898 protocol, and its operation is as follows: S1. When a node attempts to send a CAN data frame, the processor writes the raw data into the buffer of the CAN controller. S2. When the transmission conditions are met, the CAN controller calls the HMAC-SHA256 and AES modules to complete the encryption and authentication operation, and then sends the data frame to the CAN bus according to the CAN bus protocol rules and encryption and authentication strategy. S3. When the bus data frame ID meets the filtering conditions of the receiving node and the CRC check is correct, the receiving node sequentially performs decryption, MAC comparison and count value comparison to determine whether the message is valid. S4. If the data is valid, the received data is written to the receive buffer and the ID of the successfully received data frame is sent to the intrusion detection module. If the count value or MAC of the received data frame is invalid, if the device is a gateway node, an interrupt request is sent to the processor to notify the processor that there is an invalid count value or MAC during the data frame reception process, which may indicate an abnormal attack. If the device is an ECU node, in addition to sending an interrupt request to the processor, an abnormal notification data frame is also sent to notify the gateway node that there may be an abnormal attack. When the intrusion detection module detects that the entropy value deviates from the normal situation, it also generates an interrupt request or sends an abnormal notification data frame.

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