Receiver device for two-wire bus

Abstract

The invention relates to a receiver device for a two-wire bus. An apparatus includes a first terminal and a second terminal configured to be connected to a first conductor and a second conductor of a differential two-wire bus, respectively. And the same first resistance voltage-dividing bridge and second resistance voltage-dividing bridge are respectively connected between the reference node and the first node and between the reference node and the second node. And the same third resistance voltage-dividing bridge and fourth resistance voltage-dividing bridge are respectively connected between the power supply node and the first node and between the power supply node and the second node. The read circuit is configured to determine a binary state of the bus from a current flowing through a transistor of the read circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Patent Application No. 2307671 filed on July 18, 2023, which is hereby incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic circuits, such as receiver devices or two-wire buses. Background Art

[0004] Many differential two-wire buses are known. In these known buses, the digital data or bits transmitted through the bus are represented by the differential voltage between the two conductors of the two-wire bus. An example of such a known differential two-wire bus is the CAN bus.

[0005] Data transmitting and / or receiving devices are connected to the two conductors of the differential two-wire bus.

[0006] In particular, when such a device is configured to read digital data from a bus, the device comprises a circuit or device configured to read from the bus connected to two bus conductors.

[0007] In such a differential two-wire bus, the common mode potential of the bus may vary, for example, between -40 V and +40 V, for example in the event of an electrostatic discharge (ESD).

[0008] These changes in the common mode potential of the bus may render inoperative known circuits for reading from the bus of data transmitting and / or receiving devices connected to the bus. Summary of the invention

[0009] The present disclosure relates generally to electronic circuits, for example integrated electronic circuits. A specific example relates to a receiving electronic circuit or device for a differential two-wire bus, for example of the CAN (Controller Area Network) type.

[0010] Embodiments provide a device for reading from a differential two-wire bus that overcomes all or part of the disadvantages of known devices for reading from a differential two-wire bus, for example of the CAN type.

[0011] For example, there is a need for a device for reading from a differential two-wire bus, for example of the CAN type, that is robust to variations in the common mode potential of the bus.

[0012] For example, there is a need for a device for reading from a differential two-wire bus, for example of the CAN type, that is robust to increases in the common mode potential of the bus.

[0013] Embodiments overcome all or part of the disadvantages of known devices for reading from a differential two-wire bus, for example of the CAN type.

[0014] An embodiment provides a device, the device comprising: a first terminal and a second terminal, the first terminal and the second terminal being configured to be connected to a first conductor and a second conductor of a differential two-wire bus, respectively. A first resistor divider bridge and a second resistor divider bridge are connected between a reference node and a corresponding first node and a second node, the first node and the second node being coupled to the first terminal and the second terminal, respectively. The same third resistor divider bridge and a fourth resistor divider bridge are connected between a power supply node and a corresponding first node and a second node. A read circuit comprises: a first NMOS transistor and a second NMOS transistor, whose gates are connected to each other and whose sources are connected to an intermediate node of the second bridge; a third NMOS transistor and a fourth NMOS transistor, whose gates are connected to each other and whose sources are connected to a corresponding intermediate node of the first bridge; a fifth PMOS transistor and a sixth PMOS transistor, whose gates are connected to each other and whose sources are connected to an intermediate node of the fourth bridge; and a seventh PMOS transistor and an eighth PMOS transistor, whose gates are connected to each other and whose sources are connected to a corresponding intermediate node of the third bridge. The second transistor and the third transistor have their drains connected to a first current source. The sixth transistor and the seventh transistor have their drains connected to a second current source. The read circuit is configured to determine a binary state of the bus based on currents flowing through the first transistor, the fourth transistor, the fifth transistor, and the eighth transistor.

[0015] According to an embodiment, the reference node is configured to receive a reference potential and the supply node is configured to receive a supply potential which is preferably positive with respect to the reference potential.

[0016] According to an embodiment, each of the first bridge and the second bridge includes a first resistance element connected between a reference node and an intermediate node of the bridge and a second resistance element connected between the intermediate node of the bridge and the corresponding first node and the second node. Each of the third bridge and the fourth bridge includes a third resistance element connected between a power supply node and the intermediate node of the bridge and a fourth resistance element connected between the intermediate node of the bridge and the corresponding first node and the second node.

[0017] According to an embodiment, a ratio of a resistance value of the first resistance element to a resistance value of the second resistance element is equal to a ratio of a resistance value of the third resistance element to a resistance value of the fourth resistance element.

[0018] According to an embodiment, in each of the first bridge and the second bridge, the first resistive element and the second resistive element are configured such that: the AC voltage at the intermediate node of the first bridge corresponds to the AC voltage at the first terminal divided by a factor A, and the AC voltage at the intermediate node of the second bridge corresponds to the AC voltage at the second terminal divided by the factor A. In each of the third bridge and the fourth bridge, the third resistive element and the fourth resistive element are configured such that: the AC voltage at the intermediate node of the third bridge corresponds to the AC voltage at the first terminal divided by the factor A, and the AC voltage at the intermediate node of the fourth bridge corresponds to the AC voltage at the second terminal divided by the factor A.

[0019] According to an embodiment, in each of the first bridge and the second bridge, the resistance value of the first resistance element is lower than the resistance value of the second resistance element, and in each of the third bridge and the fourth bridge, the resistance value of the third resistance element is lower than the resistance value of the fourth resistance element.

[0020] According to an embodiment, a fifth resistance element couples the first node with the first terminal, and a sixth resistance element identical to the fifth resistance element couples the second node with the second terminal.

[0021] According to an embodiment, the read circuit includes a first bias circuit configured to apply a first bias potential to the gates of the first transistor and the second transistor and to apply a second bias potential to the gates of the third transistor and the fourth transistor. The second potential is different from the first potential. The second bias circuit is configured to apply a third bias potential to the gates of the fifth transistor and the sixth transistor and to apply a fourth bias potential to the gates of the seventh transistor and the eighth transistor. The fourth potential is different from the third potential.

[0022] According to an embodiment, the first bias circuit includes a first current source, a seventh resistance element connected between the drain and the gate of the second transistor, an eighth resistance element having the same resistance value as the seventh resistance element connected between the drain and the gate of the third transistor, and a third current source connected to the gates of the third transistor and the fourth transistor. The second bias circuit includes a second current source, a ninth resistance element connected between the drain and the gate of the sixth transistor, a tenth resistance element having the same resistance value as the ninth resistance element connected between the drain and the gate of the seventh transistor, and a fourth current source connected to the gates of the seventh transistor and the eighth transistor.

[0023] According to an embodiment, the read circuit includes a first circuit for replicating current, configured to extract a mirror image of the current through the first transistor at a node for summing the current of the read circuit. A second circuit for replicating current, configured to deliver a mirror image of the current through the fourth transistor at the node for summing the current. A third circuit for replicating current, configured to deliver a mirror image of the current through the fifth transistor at the node for summing the current. A fourth circuit for replicating current, configured to extract a mirror image of the current through the eighth transistor at the node for summing the current.

[0024] According to an embodiment, a first circuit for replicating current includes a first current mirror with a PMOS transistor and a second current mirror with an NMOS transistor. The first current mirror couples the drain of the first transistor with the second current mirror, and the second current mirror couples the first current mirror with a node for summing. The second circuit for replicating current includes a third current mirror with a PMOS transistor, and the third current mirror couples the drain of the fourth transistor with the node for summing. The third circuit for replicating current includes a fourth current mirror with an NMOS transistor and a fifth current mirror with a PMOS transistor. The fourth current mirror couples the drain of the fifth transistor with the fifth current mirror, and the fifth current mirror couples the fourth current mirror with the node for summing. The fourth circuit for replicating current includes a sixth current mirror with an NMOS transistor, and the sixth current mirror couples the drain of the eighth transistor with the node for summing.

[0025] According to an embodiment, the read circuit includes a transimpedance amplifier configured to receive a current determined by currents flowing through the first transistor, the fourth transistor, the fifth transistor, and the eighth transistor, and to deliver a binary voltage representing a bus differential voltage in accordance with the received current.

[0026] According to an embodiment, the read circuit comprises a transimpedance amplifier having inputs preferably coupled to the node for summing and outputs configured to deliver a binary voltage representative of a differential voltage of the bus in dependence on a current received at its inputs.

[0027] According to an embodiment, a transimpedance amplifier includes an inverter and a resistance element connected between an input terminal of the inverter and an output terminal of the inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above features and advantages and others will be described in detail in the remainder of the disclosure of specific embodiments thereof, which are given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0029] Figure 1 An example of a device for reading from a differential two-wire bus is shown;

[0030] Figure 2 By Figure 1 A more detailed approach is shown in Figure 1 Examples of circuits of devices;

[0031] Figure 3 An example of an embodiment of a differential two-wire bus reading device is shown; and

[0032] Figure 4 By Figure 3 A more detailed approach is shown in Figure 3 An example of an embodiment of a circuit of a device. DETAILED DESCRIPTION

[0033] In the various drawings, similar features have been designated by similar reference symbols. In particular, common structural and / or functional features between the various embodiments may have the same reference symbols and may have the same structure, dimensions, and material properties.

[0034] For clarity, only the steps and elements useful for understanding the described embodiments have been illustrated and described in detail.

[0035] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate elements other than conductors, and when referring to two elements coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0036] In the following description, when reference is made to terms that quantify absolute positions such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative positions such as terms "above", "below", "upper", "lower", etc., or terms that quantify directions such as terms "horizontal", "vertical", etc., it refers to the orientation in the drawings unless otherwise specified.

[0037] Unless otherwise specified, the expressions "about," "approximately," "substantially," and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0038] In the following description, the expression "resistance element" designates an element having two terminals between which the resistance element behaves as a resistor and thus exhibits a resistance value. The resistance element corresponds to, for example, a single resistor whose terminals correspond to the terminals of the resistance element, or, for example, to a plurality of resistors connected in series between the terminals of the resistance element.

[0039] Figure 1 An example of a device 1 for reading from a two-wire bus 2 , for example of the CAN type, is shown.

[0040] Bus 2 includes two conductors or wires 2H and 2L. Digital data is transmitted over the bus by varying the differential voltage Vdiff of bus 2, which is equal to V(2H)-V(2L), where V(2H) is the potential on conductor 2H and V(2L) is the potential on conductor 2L.

[0041] The device 1 comprises a terminal 100H intended to be connected to a conductor 2H of a bus 2, the terminal 100H being Figure 1 The device 1 further comprises a terminal 100L intended to be connected to a conductor 2L of the bus 2, the terminal 100H being connected to a conductor 2H. Figure 1 is shown connected to conductor 2H.

[0042] The device 1 includes two identical resistive voltage divider bridges 102 and 104. Bridge 102 is connected between a reference node 106 and a node 108 coupled to terminal 100H. Bridge 104 is connected between node 106 and a node 110 coupled to terminal 100L.

[0043] The reference node 106 is configured to receive a reference potential GND, eg ground.

[0044] For example, node 108 is coupled to terminal 100H through a resistive element R4, and node 110 is coupled to terminal 100L through another resistive element R4, and the two elements R4 have the same resistance value. For example, one of the elements R4 has one terminal connected to node 108 and another terminal connected to terminal 100H, and the other of the elements R4 has one terminal connected to node 110 and another terminal connected to terminal 100L.

[0045] For example, the element R4 has a function of setting the impedances seen by the conductors 2H and 2L at the terminals 100H and 100L, respectively.

[0046] By way of example, when the bus 2 is of the CAN type, each of the elements R4 has a resistance value approximately equal to 12 kilo-ohms (kOhm).

[0047] exist Figure 1 In the example of FIG. 1 , the node 108 is coupled to the power supply node 112 through a resistance element R3, and the node 110 is coupled to the node 112 through another resistance element R3. The two elements R3 have the same resistance value.

[0048] The node 112 is configured to receive a power supply potential VCC. Preferably, the potential VCC is positive relative to the potential GND. For example, the potential VCC with reference to the potential GND has a value substantially equal to (preferably equal to) 5V.

[0049] Preferably, the resistance value of element R3 is equal to the resistance value of each of bridges 102 and 104 so that the potential at each of nodes 108 and 110 is equal to VCC / 2.

[0050] The bridges 102, 104 each include a resistive element R1 connected between the node 106 and an intermediate node 114, 116 of the bridges 102, 104, respectively. For example, in each of the bridges 102, 104, the resistive element R1 has a terminal connected to the node 106 and another terminal connected to the nodes 114, 116, respectively. The element R1 has the same resistance value.

[0051] In addition, the bridges 102, 104 each include a resistance element R2 connected between the node 114 and the node 118, and between the nodes 116 and 110, respectively. For example, in the bridge 102, the resistance element R2 has one terminal connected to the node 114 and another terminal connected to the node 108, and in the bridge 104, the resistance element R2 has one terminal connected to the node 116 and another terminal connected to the node 110. The elements R2 have the same resistance value.

[0052] In each of the bridges 102 and 104, the resistance values ​​of the elements R1 and R2 are configured so that the AC voltage across the nodes 114 and 116 of the bridge 102 and 104 respectively corresponds to the AC voltage across the terminals 100H and 100L respectively divided by a factor A. In other words, the voltage across the nodes 114 and 116 respectively has an AC (alternating current) component corresponding to the AC component of the voltage across the terminals 100H and 100L respectively divided by the factor A. Therefore, the amplitude of the AC component across the nodes 114 and 116 respectively is A times smaller than the amplitude of the AC component across the terminals 100H and 100L respectively.

[0053] As an example, the factor A is greater than or equal to 10, for example greater than or equal to 20, preferably substantially equal to 20.

[0054] Furthermore, in each of the bridges 102 and 104, the resistance value of the element R1 is smaller than the resistance value of the resistance element R2, for example, at least ten times smaller. As a result, the DC (direct current) voltage on each of the nodes 114 and 116 (i.e., the DC component of the voltage on each of the nodes 114 and 116) is closer to the voltage on the node 106 than the DC voltage on each of the nodes 108 and 110.

[0055] For example, the resistance values ​​of elements R1 and R2 are selected so that even when the common mode voltage of bus 2 varies within a range of, for example, approximately -40V to approximately +40V, the DC component of the voltage on each of nodes 114 and 116 falls within a range of voltage values ​​from approximately -1V to approximately +2V.

[0056] The device 1 further comprises a reading circuit LECT. The circuit LECT comprises a terminal 100LI connected to the node 116 of the bridge 104 and a terminal 100HI connected to the node 114 of the bridge 102.

[0057] Although this Figure 1 Not shown in the figure, and as will be Figure 2 As further described in detail in the example of implementation illustrated in , the circuit LECT may include two NMOS transistors 200 and 202 whose gates are connected together and whose sources are connected to the node 116 of the bridge 104, two other NMOS transistors 204 and 206 whose gates are connected together and whose sources are connected to the node 114 of the bridge 102, and a current source 208 connected to the drains of the transistors 202 and 204, and the drains of the transistors 202 and 204 are connected to each other.

[0058] In this circuit LECT, the binary state of bus 2 (i.e., the binary state corresponding to the current value of voltage Vdiff of bus 2) is determined based on the current flowing through each of transistors 200 and 206 (e.g., based on the difference between these two currents). For example, different bias voltages are applied to the gates of transistors 200 and 202 and to the gates of transistors 204 and 206 for this purpose.

[0059] Figure 2 By Figure 1 An example of a circuit LECT of the device 1 is shown in a more detailed manner in FIG.

[0060] As previously mentioned Figure 1 As indicated, the circuit LECT comprises NMOS transistors 200, 202, 204 and 206 and a current source 208, which are interconnected to each other and to the circuit as described with respect to FIG. Figure 1 The described circuit LECT has terminals 100LI and 100HI.

[0061] In other words, transistors 200 and 202 form a first differential pair in which transistors 200 and 202 are configured or installed with a common source, and transistors 204 and 206 form a second differential pair in which transistors 204 and 206 are configured or installed with a common source. The first differential pair and the second differential pair are of NMOS type and are, for example, floating.

[0062] For example, the current source 208 is connected between the drains of the transistors 202 and 204 and a power supply node 210. The node 210 is configured to receive a power supply potential VCC2 that is positive, for example, relative to the reference potential GND. For example, the potential VCC2 is lower than the potential VCC. For example, when the potential VCC is substantially equal to (preferably equal to) 5V, the potential VCC2 is substantially equal to (preferably equal to) 3.3V.

[0063] The potential VCC2 forms the supply potential of the circuit LECT.

[0064] The circuit LECT includes a bias circuit 212 configured to apply a first bias potential to the gates of the transistors 200 and 202 and to apply a second bias potential to the gates of the transistors.

[0065] The first bias potential is different from the second bias potential so that when the two terminals 100HI and 100LI are at the same potential (zero voltage Vdiff of bus 2), the current through transistor 202 is different from the current through transistor 204, and then the current through transistor 200 is different from the current through transistor 206.

[0066] Preferably, the first bias potential and the second bias potential are further determined so that when the potential on terminal 100HI is greater than the potential on terminal 100LI (the positive voltage Vdiff of the bus), the unequal relationship between the currents through transistors 202 and 204 is reversed relative to the case where the potentials of terminals 100HI and 100LI are equal.

[0067] As an example, the first bias potential and the second bias potential are configured so that when the potentials on the terminals 100HI and 100LI are equal, the current through the transistor 202 is greater than the current through the transistor 204, and conversely, when the potential on the terminal 100HI is greater than the potential on the terminal 100LI, the current through the transistor 202 is lower than the current through the transistor 204. In other words, when the potentials on the terminals 100HI and 100LI are equal, the current through the transistor 200 is then greater than the current through the transistor 206, and conversely, when the potential on the terminal 100HI is greater than the potential on the terminal 100LI, the current through the transistor 200 is lower than the current through the transistor 206.

[0068] As an alternative example, the first bias potential and the second bias potential are configured so that when the potentials on the terminals 100HI and 100LI are equal, the current through the transistor 202 is lower than the current through the transistor 204, and conversely, when the potential on the terminal 100HI is greater than the potential on the terminal 100LI, the current through the transistor 202 is greater than the current through the transistor 204. In other words, when the potentials on the terminals 100HI and 100LI are equal, the current through the transistor 200 is lower than the current through the transistor 206, and conversely, when the potential on the terminal 100HI is greater than the potential on the terminal 100LI, the current through the transistor 200 is greater than the current through the transistor 206.

[0069] Preferably, transistors 202 and 204 have the same size, and furthermore, the size ratio between transistors 202 and 200 is equal to the size ratio between transistors 204 and 206 .

[0070] exist Figure 2 In the example of , the circuit LECT is configured such that the first bias potential is higher than the second bias potential.

[0071] exist Figure 2 In the example of , the bias circuit 212 includes a current source 208, a resistance element R6 connected between the drain and the gate of the transistor 202, another resistance element R6 connected between the drain and the gate of the transistor 204, two elements R6 having the same resistance value, and a current source 214 connected to the gates of the transistors 204 and 206.

[0072] For example, one of the elements R6 has one terminal connected to the gates of transistors 200 and 202 and another terminal connected to the interconnected drains of transistors 202 and 204, and another of the elements R6 has one terminal connected to the gates of transistors 204 and 206 and another terminal connected to the interconnected drains of transistors 202 and 204.

[0073] As an example, current source 214 is connected between the gates of transistors 204 and 206 and node 210. For example, current source 214 has one terminal connected to node 210 and another terminal connected to the drains of transistors 202 and 204.

[0074] Preferably, current source 214 delivers a current I2 having a value lower than current I1 delivered by current source 208 , for example at least 10 times or even at least 20 times.

[0075] As an example, current source 208 delivers a current approximately equal to 20 μA, and current source 214 delivers a current approximately equal to 0.9 μA.

[0076] The current source 214 enables a difference to be generated between the potential at the gates of the transistors 200 and 202 and the potential at the gates of the transistors 204 and 206 due to the current I2 it delivers and flows through the resistor element connected between the drain and the gate of the transistor 204 .

[0077] exist Figure 2 In the example of , in order to determine the binary state of bus 2, circuit LECT includes a current replication circuit 216 and a current replication circuit 220, wherein the current replication circuit 216 is configured to extract an image I4 of the current I3 through transistor 200 from a current summing node 218 of circuit LECT, and the current replication circuit 220 is configured to deliver an image I6 of the current I5 through transistor 206 at node 218.

[0078] In this specification, a circuit configured to deliver a first current based on a second current is referred to as a "current mirror circuit", and the first current is then referred to as a "mirror" of the second current and equal to the second current within a multiplication factor. For example, current I4 is a mirror image of current I2 and is delivered by circuit 216.

[0079] Preferably, when transistors 202 and 204 have the same size and the size ratio between transistors 202 and 200 is equal to the size ratio between transistors 204 and 206, the ratio of the value of current I6 to the value of current I5 is equal to the ratio of the value of current I4 to the value of current I3.

[0080] like Figure 2 As shown in FIG. 2 , circuit 216 includes, for example, a current mirror 222 with a PMOS transistor and a second current mirror 228 with an NMOS transistor. Current mirror 222 couples the drain of transistor 200 to current mirror 228. Current mirror 228 couples current mirror 222 to node 218.

[0081] As an example, the current mirror 222 includes a PMOS transistor 224 whose drain is connected to its gate and the drain of the transistor 200 and whose source is connected to the node 210, and a PMOS transistor 226 whose gate is connected to the gate of the transistor 224, whose source is connected to the node 210 and whose drain corresponds to the output terminal of the current mirror 222.

[0082] Still as an example, the current mirror 228 includes an NMOS transistor 230 whose drain is connected to its gate and the drain of the transistor 226 and whose source is connected to the node 106, and an NMOS transistor 232 whose gate is connected to the gate of the transistor 230, whose source is connected to the node 106 and whose drain corresponds to the output terminal of the current mirror 228, and the drain of the transistor 232 then delivers the current I4 which is the mirror of the current I3.

[0083] like Figure 2 As shown in FIG. 2 , circuit 220 includes a current mirror 234, for example, with a PMOS transistor. Current mirror 234 couples the drain of transistor 206 to node 218.

[0084] As an example, the current mirror 234 includes a PMOS transistor 236 whose drain is connected to its gate and the drain of the transistor 206 and whose source is connected to the node 210, and a PMOS transistor 238 whose gate is connected to the gate of the transistor 236, whose source is connected to the node 210 and whose drain corresponds to the output terminal of the current mirror 234, and the drain of the transistor 238 then delivers the current I6 which is the mirror of the current I5.

[0085] Therefore, the current available at node 218 represents the difference between currents I3 and I4 and therefore the difference between the current through transistor 202 and the current through transistor 204 , and thus represents the voltage value Vdiff of bus2 .

[0086] As an example, the read circuit LECT comprises a transimpedance amplifier TIA. The amplifier TIA is configured to receive a current determined by the current through the transistors 202 and 204 and to deliver a binary voltage representative of the voltage Vdiff of the bus 2 based on the received current.

[0087] For example, amplifier TIA has an input connected to node 218 and an output delivering a binary voltage representative of voltage Vdiff.

[0088] For example, the amplifier TIA includes an inverter INV and a resistance element connected between an output terminal and an input terminal of the inverter.

[0089] Refer again Figure 1 , when the common mode of bus 2 decreases relative to its nominal value (e.g. equal to 2.5 V) and reaches a high negative value (e.g. a value of −40 V) relative to the potential VCC2 for the given example of determining the specifications of the resistor elements R1, R2 and R3, the DC component on nodes 114 and 116 (which is a mirror image of the common mode voltage of bus 2) then becomes approximately equal to −1 V. Then, via the DC component of the voltage at nodes 114 and 116, the MOS transistors of circuits 216 and 220 are correctly biased, so that circuit LECT is properly functional and robust to this decrease in the common mode voltage relative to its nominal value.

[0090] However, for this same given example of determining the specification, when the common-mode voltage of bus 2 increases relative to its nominal value and reaches a high positive value (e.g., a value of +40 V) relative to potential VCC2, the DC component on nodes 114 and 116 then becomes approximately equal to 2 V. The MOS transistors of circuits 216 and 220 are then no longer correctly biased via the DC component of the voltage at nodes 114 and 116, and circuit LECT is no longer properly functional and robust to this increase in the common-mode voltage relative to its nominal value.

[0091] A device 3 similar to the device 1 is provided here, comprising a reading circuit (LECT') similar to the reading circuit (LECT), which reading circuit (LECT') maintains normal operation not only for the common mode voltage of the bus 2 to be reduced, for example to a value of up to -40V, but also for the common mode voltage of the bus 2 to be increased, for example to a value of up to +40V.

[0092] Figure 3 An example of an embodiment of such a device 3 for reading from a differential two-wire bus 2 is shown.

[0093] Device 3 includes many elements in common with Device 1 and only the differences between Device 1 and Device 3 are highlighted here. Therefore, unless otherwise indicated, reference to Figure 1 Everything indicated or described in the device 1 applies to Figure 3 Device 3.

[0094] Compared with the device 1, in the device 3, each resistance element R3 is replaced by a voltage dividing bridge.

[0095] More specifically, the element R3 connected between nodes 108 and 112 in device 1 is replaced by a resistive voltage divider bridge 300 connected between nodes 108 and 112 in device 3, and the element R3 connected between nodes 110 and 112 in device 1 is replaced by a resistive voltage divider bridge 302 connected between nodes 110 and 112 in device 3. The two resistive bridges 300 and 302 are identical.

[0096] According to an embodiment, the resistance value of each of the bridges 300 and 302 is equal to the resistance value of the resistance element R3 of the device 1, or in other words, the resistance value of each of the bridges 300 and 302 is equal to the resistance value of each of the bridges 102 and 104. Therefore, the potential of each of the nodes 108 and 110 is equal to VCC / 2.

[0097] According to an embodiment, the bridges 300 and 302 include a resistance element R31 respectively connected between the node 112 and the intermediate nodes 304 and 306 of the bridges 300 and 302. For example, in each of the bridges 300 and 302, the resistance element R31 has one terminal connected to the node 112 and another terminal connected to the nodes 304 and 306 respectively. The element R31 has the same resistance value. In addition, the bridges 300 and 302 include a resistance element R32 respectively connected between the nodes 304 and 108 and the nodes 306 and 110. For example, in the bridge 300, the resistance element R32 has one terminal connected to the node 304 and another terminal connected to the node 108, and in the bridge 302, the resistance element R32 has one terminal connected to the node 306 and another terminal connected to the node 110. The element R32 has the same resistance value.

[0098] According to an embodiment, similar to the description for bridges 102 and 104, in each of bridges 300 and 302, the resistance values ​​of elements R31 and R32 are configured such that the AC voltage across each of nodes 304 and 306 of bridge 300 and bridge 302 corresponds to the AC voltage across each of terminals 100H and 100L divided by a factor A. In other words, the voltage across each of nodes 304 and 306 has an AC component corresponding to the AC component of the voltage across each of terminals 100H and 100L divided by the factor A. Therefore, the amplitude of the AC component across each of nodes 304 and 306 is A times smaller than the amplitude of the AC component across each of terminals 100H and 100L.

[0099] According to an embodiment, in each of the bridges 300 and 302, the resistance value of the element R31 is smaller than the resistance value of the resistance element R32, for example, at least ten times smaller. Therefore, the DC voltage on each of the nodes 304 and 306 (i.e., the DC component of the voltage on each of the nodes 304 and 306) is closer to the voltage on the node 112 than the DC voltage on each of the nodes 108 and 110.

[0100] For example, the resistance values ​​of elements R31 and R32 are selected so that even when the common mode voltage of bus 2 varies within a range of, for example, from about -40V to about +40V, the DC component of the voltage on each of nodes 304, 306 falls within a voltage value range of from about +4V to about +6V.

[0101] According to an embodiment, a ratio of a resistance value of each element R1 to a resistance value of each element R2 is equal to a ratio of a resistance value of each element R31 to a resistance value of each element R32 .

[0102] Therefore, according to an embodiment, the ratio R31val / (R31val+R32val) is equal to the ratio R1val / (R1val+R2val), where R31val is the resistance value of element R31, R32val is the resistance value of element R32, R1val is the resistance value of element R1, and R2val is the resistance value of element R2.

[0103] Compared to the device 1 , in the device 3 the circuit LECT is replaced by a circuit LECT′, as indicated above.

[0104] Similar to LECT, circuit LECT′ comprises terminal 100LI connected to node 116 of bridge 104 and terminal 100HI connected to node 114 of bridge 102. Furthermore, in contrast to circuit LECT, circuit LECT′ comprises terminal 100HS connected to node 304 of bridge 300 and terminal 100LS connected to node 306 of bridge 302.

[0105] Although this Figure 3 There is no diagram in the figure, and if you will use Figure 4 As further described in detail in the example of implementation shown in FIG. 1 , the circuit LECT′ comprises two NMOS transistors 200 and 202 whose gates are connected together and whose sources are connected to the node 116 of the bridge 104 and thus to the terminal 100LI of the circuit LECT′, two other NMOS transistors 204 and 206 whose gates are connected together and whose sources are connected to the node 114 of the bridge 102 and thus to the terminal 100HI of the circuit LECT′, a current source 208 connected to the drains of the transistors 202 and 204 (the transistors 204 and 206 are connected to the drains of the transistors 202 and 204). 206 whose drains are connected to each other), two PMOS transistors 308 and 310 whose gates are connected to each other and whose sources are connected to the intermediate node 306 of the bridge 302 and therefore to the terminal 100LS of the circuit LECT′, two PMOS transistors 312 and 314 whose gates are connected to each other and whose sources are connected to the corresponding intermediate node 304 of the bridge 300 and therefore to the terminal 100HS of the circuit LECT′, and a current source 316 connected to the drains of the transistors 310 and 312 (the drains of the transistors 310 and 312 are connected to each other).

[0106] In this circuit LECT′, the binary state of bus 2 is determined not only based on the current flowing through each of transistors 200 and 206 , but also based on the current flowing through each of transistors 310 and 312 .

[0107] For example, to this end, as in circuit LECT, the bias potential applied to the gates of transistors 200 and 202 is different from the bias potential applied to the gates of transistors 204 and 206, and in addition, the bias potential applied to the gates of transistors 308 and 310 is different from the bias potential applied to the gates of transistors 312 and 314.

[0108] Preferably, when the bias potential applied to the gates of transistors 200 and 202 is higher and lower than the bias potential applied to the gates of transistors 204 and 206, respectively, the bias potential applied to the gates of transistors 308 and 310 is higher and lower than the bias potential applied to the gates of transistors 312 and 314, respectively.

[0109] Thus, when the common-mode voltage of bus 2 decreases relative to its nominal value, for example to a value ranging down to -40 V, correct operation of the holding circuit LECT' is ensured via transistors 200, 202, 204 and 206, and when the common-mode voltage of bus 2 increases relative to its nominal value, for example to a value ranging up to +40 V, correct operation of the holding circuit LECT' is ensured via transistors 308, 310, 312 and 314.

[0110] In other words, when the common-mode voltage of bus 2 decreases relative to its nominal value, for example to a value ranging down to -40 V, the DC component of the voltage via nodes 114 and 116 ensures correct operation of the holding circuit LECT', and when the common-mode voltage of bus 2 increases relative to its nominal value, for example to a value ranging up to +40 V, the DC component of the voltage via nodes 304 and 306 ensures correct operation of the holding circuit LECT'.

[0111] Figure 4 By Figure 3 An example of a circuit LECT' of the device 3 is shown in a more detailed manner in FIG.

[0112] Figure 4 The circuit LECT' includes many Figure 2 The circuits LECT of FIG. 1 and FIG. 2 are common to the circuits LECT of FIG. 1 and 2, and only the differences between these circuits LECT and LECT' are highlighted here. Therefore, everything indicated or described for the circuit LECT applies to the circuit LECT' unless otherwise indicated.

[0113] As previously mentioned Figure 3 As indicated, the circuit LECT′ comprises NMOS transistors 200, 202, 204 and 206 and a current source 208 and PMOS transistors 308, 310, 312, 314 and a current source 316, which are interconnected together and to terminals 100LI, 100HI, 100LS and 100HS of the circuit LECT′, as described with reference to FIG. Figure 3 Descriptive.

[0114] In other words, transistors 200 and 202 form a first differential pair in which transistors 200 and 202 are configured or installed with a common source, transistors 204 and 206 form a second differential pair in which transistors 204 and 206 are configured or installed with a common source, and transistors 308 and 310 form a third differential pair in which transistors 310 and 308 are configured or installed with a common source, and transistors 312 and 314 form a fourth differential pair in which transistors 312 and 314 are configured or installed with a common source. The first differential pair and the second differential pair are NMOS type, and the third differential pair and the fourth differential pair are PMOS type. The four differential pairs are, for example, floating.

[0115] For example, current source 208 is connected between the drains of transistors 202 and 204 and a power supply node 210 configured to receive a power supply potential VCC2 .

[0116] For example, current source 316 is connected between the drains of transistors 310 and 312 and reference node 106 .

[0117] The potential VCC2 forms the supply potential of the circuit LECT'.

[0118] According to an embodiment, the circuit LECT′ includes a bias circuit 212 configured to apply different first and second bias potentials to the gates of the transistors 200 and 202 and to the gates of the transistors 204 and 206. In addition, the circuit LECT′ includes a bias circuit 318. The circuit 318 is configured to apply a third bias potential to the gates of the transistors 308 and 310, and to apply a fourth bias potential to the gates of the transistors 312 and 314.

[0119] The third bias potential is different from the fourth bias potential so that when the two terminals 100HS and 100LS are at the same potential (zero voltage Vdiff of bus 2), the current through transistor 310 is different from the current through transistor 312, and the current through transistor 308 is different from the current through transistor 314.

[0120] Preferably, the third bias potential and the fourth bias potential are further determined so that when the potential at terminal 100HS is greater than the potential at terminal 100LS (the positive voltage Vdiff of the bus), the unequal relationship between the currents through transistors 310 and 312 is opposite to the case where the potentials of terminals 100HS and 100LS are equal.

[0121] As an example, the third bias potential and the fourth bias potential are configured such that when the potentials of the terminals 100HS and 100LS are equal, the current through the transistor 310 is greater than the current through the transistor 312, and conversely, when the potential on the terminal 100HS is greater than the potential on the terminal 100LS, the current through the transistor 310 is lower than the current through the transistor 312. In other words, when the potentials of the terminals 100HS and 100LS are equal, the current through the transistor 308 is greater than the current through the transistor 314, and, conversely, when the potential on the terminal 100HS is greater than the potential on the terminal 100LS, the current through the transistor 308 is lower than the current through the transistor 314.

[0122] As an alternative example, the third bias potential and the fourth bias potential are configured so that when the potentials on the terminals 100HS and 100LS are equal, the current through the transistor 310 is lower than the current through the transistor 312, and conversely, when the potential on the terminal 100HS is greater than the potential on the terminal 100LS, the current through the transistor 310 is greater than the current through the transistor 312. In other words, when the potentials on the terminals 100HS and 100LS are equal, the current through the transistor 308 is lower than the current through the transistor 314, and conversely, when the potential on the terminal 100HS is greater than the potential on the terminal 100LS, the current through the transistor 308 is greater than the current through the transistor 314.

[0123] Preferably, transistors 308 and 310 have the same size, and furthermore, the size ratio between transistors 308 and 310 is equal to the size ratio between transistors 312 and 314 .

[0124] exist Figure 4 In the example of , circuit LECT′ is configured such that a first bias potential applied to the gates of transistors 200 and 202 is higher than a second bias potential applied to the gates of transistors 204 and 206, and further such that a third bias potential applied to the gates of transistors 308 and 310 is higher than a fourth potential applied to the gates of transistors 312 and 314.

[0125] According to an embodiment, the circuit 212 includes Figure 2 The described current source 208, two resistor elements R6 and current source 214 are connected together, and further, the circuit 318 includes a current source 316, a resistor element R7 connected between the drain and the gate of the transistor 310, another resistor element R7 connected between the drain and the gate of the transistor 312, two elements R7 having the same resistance value, and a current source 320 connected to the gates of the transistors 312 and 314.

[0126] For example, one of the elements R7 has one terminal connected to the gates of transistors 308 and 310 and another terminal connected to the interconnected drains of transistors 310 and 312, and the other of the elements R7 has one terminal connected to the gates of transistors 312 and 314 and another terminal connected to the interconnected drains of transistors 310 and 312.

[0127] As an example, current source 320 is connected between the gates of transistors 312 and 314 and node 106. For example, current source 320 has one terminal connected to node 106 and another terminal connected to the drains of transistors 312 and 314.

[0128] Preferably, current source 320 delivers a current I8 having a value lower than current I7 delivered by current source 316 , for example at least 10 times or even at least 20 times.

[0129] As an example, current source 316 delivers current I7 approximately equal to 20 μA, and current source 320 delivers current I8 approximately equal to 0.9 μA.

[0130] For example, source 316 delivers a current I7 that is equal to current I1 delivered by source 208 , and source 320 delivers a current I8 that is equal to current I2 delivered by current source 214 .

[0131] The current source 320 enables a difference to be generated between the potential at the gates of the transistors 308 and 310 and the potential at the gates of the transistors 312 and 314 by delivering the current I8 flowing through the resistor R7 connected between the drain and the gate of the transistor 312 .

[0132] According to an embodiment, in order to determine the binary state of bus 2, circuit LECT′ includes current replication circuit 216, current replication circuit 220, current replication circuit 322 and current replication circuit 324, current replication circuit 216, current replication circuit 220 and current replication circuit 322 are configured to provide a mirror image I10 of current I9 passing through transistor 308 to node 218, and current replication circuit 324 is configured to extract a mirror image I12 of current I11 passing through transistor 314 from node 218.

[0133] Preferably, when transistors 310 and 312 have the same size and the size ratio between transistors 308 and 310 is equal to the size ratio between transistors 312 and 314 , the ratio of the value of current I10 to the value of current I9 is ​​equal to the ratio of the value of current I12 to the value of current I11 .

[0134] According to an embodiment, circuit 216 includes current mirrors 222 and 328 , circuit 220 includes current mirror 234 , circuit 322 includes current mirror 326 with NMOS transistors and current mirror 328 with PMOS transistors, and circuit 324 includes current mirror 330 with NMOS transistors.

[0135] Current mirror 326 couples the drain of transistor 308 to current mirror 328, and current mirror 328 couples current mirror 326 to node 218. Additionally, current mirror 330 couples the drain of transistor 314 to node 218.

[0136] As an example, current mirror 326 includes an NMOS transistor 332 whose drain is connected to its gate and the drain of transistor 308 and whose source is connected to node 106, and an NMOS transistor 334 whose gate is connected to the gate of transistor 332, whose source is connected to node 106, and whose drain corresponds to the output of current mirror 326. Current mirror 328 includes a PMOS transistor 336 whose drain is connected to its gate and the drain of transistor 334 and whose source is connected to node 210, and a PMOS transistor 338 whose gate is connected to the gate of transistor 336, whose source is connected to node 210, and whose drain corresponds to the output of current mirror 322, the drain of transistor 338 then delivering current I10 as a mirror of current I9.

[0137] As an example, the current mirror 330 includes an NMOS transistor 340 whose drain is connected to its gate and the drain of the transistor 314 and whose source is connected to the node 106, and an NMOS transistor 342 whose gate is connected to the gate of the transistor 340, whose source is connected to the node 106 and whose drain corresponds to the output terminal of the current mirror 330, and the drain of the transistor 342 then delivers the current I12 which is the mirror of the current I11.

[0138] Therefore, the current available at node 218 represents not only the difference between currents I3 and I4, and thus the difference between the current through transistor 202 and the current through transistor 204, but also the difference between currents I9 and I11, and thus the difference between the current through transistor 310 and the current through transistor 312.

[0139] As a result, when the common-mode voltage of bus 2 increases to a value at which circuits 216 and 220, and in particular their respective current mirrors 222 and 234, no longer function properly, circuits 322 and 324 remain functional and the total current available at node 218 remains determined by the difference between currents I10 and I12, as represented by the value of voltage Vdiff of bus 2.

[0140] Conversely, when the common-mode voltage of bus 2 drops to a value at which circuits 320 and 322, and in particular their respective current mirrors 326 and 330, no longer operate normally, circuits 216 and 220 remain in normal operation and the total current available at node 218 remains determined by the difference between currents I4 and I6, which is represented by the value of the voltage Vdiff of bus 2.

[0141] According to an embodiment, the read circuit LECT′ comprises a transimpedance amplifier TIA. The amplifier TIA is configured to receive a current determined by the current through the transistors 202, 204, 310 and 312 and to deliver a binary voltage representative of the voltage Vdiff of the bus 2 based on the received current.

[0142] According to an embodiment, amplifier TIA has an input connected to node 218 and an output delivering a binary voltage representative of voltage Vdiff.

[0143] According to an embodiment, the amplifier TIA includes an inverter INV and a resistance element connected between an output terminal and an input terminal of the inverter.

[0144] Combination of the above Figure 3 and Figure 4 Examples of embodiments are described.

[0145] In particular, examples of size ratios between various transistors are given, but the application is not limited to these specific examples and a person skilled in the art will be able to modify these size ratios between transistors while maintaining the operation described for the device 3 .

[0146] In addition, specific examples of the values ​​of the potentials VCC and VCC2 are given in conjunction with specific examples of negative and positive values ​​of the common mode voltage of the bus 2 to illustrate the operation of the device 3 and the circuits forming it. Here, too, the present application is not limited to these specific examples, and those skilled in the art will be able to apply the present description to other examples of the value range of the potentials VCC and VCC2 and the variation of the common mode voltage of the bus 2.

[0147] Furthermore, one skilled in the art will be able to provide other implementations of the amplifier TIA and / or bias circuits 212 and 318 and / or various current replication circuits while maintaining the operation described above for the device 3. For example, the amplifier TIA may be implemented with an operational amplifier component having an inverting input coupled to the node 218 and a resistive element R connected between the inverting input and the output of the operational amplifier, with the non-inverting input receiving a voltage capable of biasing the node 218 to a potential VCC2 / 2 similar to the inverter INV of the amplifier TIA described previously.

[0148] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features and variations of these various embodiments may be combined, and those skilled in the art will recognize other variations.

[0149] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of those skilled in the art. In particular, those skilled in the art will be able to determine the specifications of the resistance values ​​of the resistor elements R1, R2, R31, R32 based on the functional descriptions given above, and will be able to determine the specifications of the resistance value of the resistor element R5 (if present) to obtain the above-described operation. When the bias circuits 212 and 318 are implemented with current sources 208, 214, 316 and 320, those skilled in the art will also be able to determine the specifications of these current sources to obtain the described operation.

Claims

1. A device comprising: a first terminal and a second terminal, the first terminal and the second terminal being configured to be connected to a first conductor and a second conductor of a differential two-wire bus, respectively; A first resistance voltage divider bridge and a second resistance voltage divider bridge, the first resistance voltage divider bridge and the second resistance voltage divider bridge are identical and are connected between a reference node and a first node, and between the reference node and the second node, respectively, wherein the first node and the second node are coupled to the first terminal and the second terminal, respectively; a third resistance voltage-dividing bridge and a fourth resistance voltage-dividing bridge, wherein the third resistance voltage-dividing bridge and the fourth resistance voltage-dividing bridge are identical and are connected between a power supply node and the first node, and between the power supply node and the second node, respectively; as well as A reading circuit, the reading circuit comprising: a first NMOS transistor and a second NMOS transistor, a gate of the first NMOS transistor and a gate of the second NMOS transistor being connected to each other and a source of the first NMOS transistor and a source of the second NMOS transistor being connected to an intermediate node of the second bridge; a third NMOS transistor and a fourth NMOS transistor, wherein the gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to each other and the source of the third NMOS transistor and the source of the fourth NMOS transistor are connected to the corresponding intermediate node of the first bridge; a fifth PMOS transistor and a sixth PMOS transistor, a gate of the fifth PMOS transistor and a gate of the sixth PMOS transistor being connected to each other and a source of the fifth PMOS transistor and a source of the sixth PMOS transistor being connected to an intermediate node of the fourth bridge; a seventh transistor and an eighth transistor, a gate of the seventh transistor and a gate of the eighth transistor being connected to each other and a source of the seventh transistor and a source of the eighth transistor being connected to corresponding intermediate nodes of the third bridge; wherein the second transistor and the third transistor have drains connected to a first current source; wherein the sixth transistor and the seventh transistor have drains connected to a second current source; and Wherein the read circuit is configured to determine a binary state of the bus from currents flowing through the first transistor, the fourth transistor, the fifth transistor, and the eighth transistor.

2. The apparatus according to claim 1, wherein: The reference node is configured to receive a reference potential; and The power supply node is configured to receive a power supply potential.

3. The apparatus of claim 2, wherein the power supply is preferably positive relative to the reference potential.

4. The apparatus according to claim 1, wherein: Each of the first bridge and the second bridge comprises: a first resistive element connected between the reference node and the intermediate node of the bridge; and a second resistance element connected between the middle node of the bridge and the first node, and between the middle node of the bridge and the second node, respectively; and Each of the third bridge and the fourth bridge comprises: a third resistance element connected between the power supply node and the intermediate node of the bridge; and A fourth resistance element is connected between the middle node of the bridge and the first node, and between the middle node of the bridge and the second node, respectively. 5 . The apparatus according to claim 4 , wherein a ratio of a resistance value of the first resistance element to a resistance value of the second resistance element is equal to a ratio of a resistance value of the third resistance element to a resistance value of the fourth resistance element.

6. The apparatus of claim 4, wherein: In each of the first bridge and the second bridge, the first resistive element and the second resistive element are configured such that: The AC voltage at the intermediate node of the first bridge corresponds to the AC voltage at the first terminal divided by a factor A, and The AC voltage at the intermediate node of the second bridge corresponds to the AC voltage at the second terminal divided by the factor A; In each of the third bridge and the fourth bridge, the third resistance element and the fourth resistance element are configured such that: The AC voltage at the intermediate node of the third bridge corresponds to the AC voltage at the first terminal divided by the factor A, and The AC voltage at the intermediate node of the fourth bridge corresponds to the AC voltage at the second terminal divided by the factor A.

7. The apparatus of claim 4, wherein: In each of the first bridge and the second bridge, a resistance value of the first resistance element is lower than a resistance value of the second resistance element; as well as In each of the third bridge and the fourth bridge, a resistance value of the third resistance element is lower than a resistance value of the fourth resistance element.

8. The apparatus of claim 1, wherein: a fifth resistive element coupling the first node with the first terminal; as well as A sixth resistance element couples the second node with the second terminal, the sixth resistance element being the same as the fifth resistance element.

9. The apparatus of claim 1 , wherein the read circuit comprises: A first bias circuit, wherein the first bias circuit is configured to: applying a first bias potential to a gate of the first transistor and a gate of the second transistor, and applying a second bias potential to a gate of the third transistor and a gate of the fourth transistor, wherein the second potential is different from the first potential; as well as A second bias circuit, wherein the second bias circuit is configured as: applying a third bias potential to the gate of the fifth transistor and the gate of the sixth transistor, and A fourth bias potential is applied to the gate of the seventh transistor and the gate of the eighth transistor, wherein the fourth potential is different from the third potential.

10. The apparatus of claim 9, wherein: The first bias circuit comprises: The first current source, a seventh resistance element connected between the drain and the gate of the second transistor, an eighth resistance element having the same resistance value as that of the seventh resistance element, the eighth resistance element being connected between the drain and the gate of the third transistor, and a third current source connected to a gate of the third transistor and a gate of the fourth transistor; and The second bias circuit comprises: The second current source, a ninth resistor element connected between the drain and the gate of the sixth transistor, a tenth resistance element having the same resistance value as that of the ninth resistance element, the tenth resistance element being connected between the drain and the gate of the seventh transistor, and A fourth current source is connected to the gate of the seventh transistor and the gate of the eighth transistor.

11. The apparatus of claim 1 , wherein the read circuit comprises: a first circuit for replicating current configured to extract a mirror image of the current through the first transistor at a node for summing the current of the read circuit; a second circuit for replicating current configured to deliver a mirror image of the current through the fourth transistor at the node for summing the currents; a third circuit for replicating current configured to deliver a mirror image of the current through the fifth transistor at the node for summing the currents; as well as A fourth circuit for replicating current is configured to extract a mirror image of the current through the eighth transistor at the node for summing the currents.

12. The apparatus of claim 11, wherein: The first circuit for replicating current comprises: a first current mirror with a PMOS transistor, and A second current mirror with NMOS transistors, wherein the first current mirror couples the drain of the first transistor to the second current mirror, and the second current mirror couples the first current mirror to the node for summing; The second circuit for replicating current includes a third current mirror with a PMOS transistor, the third current mirror coupling the drain of the fourth transistor with the node for summing; the third circuit for replicating current includes: a fourth current mirror with NMOS transistors, and The fifth current mirror with PMOS transistors, wherein the fourth current mirror couples the drain of the fifth transistor to the fifth current mirror, and the fifth current mirror couples the fourth current mirror to the node for summing; and The fourth circuit for replicating current includes a sixth current mirror with an NMOS transistor, the sixth current mirror coupling the drain of the eighth transistor with the node for summing.

13. The apparatus of claim 1 , wherein the read circuit comprises a transimpedance amplifier configured to: receiving a current determined by currents flowing through the first transistor, the fourth transistor, the fifth transistor, and the eighth transistor, and A binary voltage is delivered according to the received current, the binary voltage representing the differential voltage of the bus.

14. The apparatus of claim 12 , wherein the read circuit comprises a transimpedance amplifier having an input coupled to the node for summing and an output configured to deliver a binary voltage in accordance with a current received at the input of the transimpedance amplifier, the binary voltage representing a differential voltage of the bus.

15. The apparatus of claim 13, wherein the transimpedance amplifier comprises: Inverter, and A resistance element is connected between an input terminal of the inverter and an output terminal of the inverter.

16. A read circuit for a differential two-wire bus device, the read circuit comprising: a first differential pair of NMOS transistors, wherein sources of the first differential pair of NMOS transistors are connected to a first intermediate node of a first resistor divider bridge; a second differential pair of NMOS transistors, wherein sources of the second differential pair of NMOS transistors are connected to a second intermediate node of a second resistor divider bridge; a third differential pair of PMOS transistors, wherein sources of the third differential pair of PMOS transistors are connected to a third intermediate node of a third resistor divider bridge; a fourth differential pair of PMOS transistors, wherein sources of the fourth differential pair of PMOS transistors are connected to a fourth intermediate node of a fourth resistor divider bridge; a first current source connected to a drain of one transistor in the first differential pair and a drain of one transistor in the second differential pair; a second current source connected to a drain of one transistor in the third differential pair and a drain of one transistor in the fourth differential pair; a first bias circuit configured to apply different bias potentials to a gate of the first differential pair and a gate of the second differential pair; a second bias circuit configured to apply different bias potentials to the gate of the third differential pair and the gate of the fourth differential pair; as well as A current summing node is provided, wherein the read circuit is configured to determine a binary state of the bus based on a current flowing to the current summing node through one transistor in each of the four differential pairs.

17. The read circuit according to claim 16, further comprising: a first current replica circuit configured to extract a mirror image of a current through a first transistor of the first differential pair at the current summing node; a second current replica circuit configured to deliver a mirror image of a current through a second transistor of the second differential pair at the current summing node; a third current replica circuit configured to deliver a mirror image of a current through a first transistor of the third differential pair at the current summing node; as well as A fourth current replica circuit is configured to extract a mirror image of a current through a second transistor of the fourth differential pair at the current summing node.

18. The read circuit of claim 17 , further comprising a transimpedance amplifier having an input and an output, the input being coupled to the current summing node, the output being configured to deliver a binary voltage representing a differential voltage of the bus, wherein the transimpedance amplifier comprises an inverter and a resistive element connected between the input of the inverter and the output of the inverter.

19. A device for reading from a differential two-wire bus, comprising: a first terminal and a second terminal, the first terminal and the second terminal being configured to be connected to a first conductor and a second conductor of the differential two-wire bus, respectively; a first resistive voltage divider bridge connected between a reference node and a first node, wherein the first node is coupled to the first terminal; a second resistive voltage divider bridge connected between the reference node and a second node, wherein the second node is coupled to the second terminal; A third resistor voltage-dividing bridge, wherein the third resistor voltage-dividing bridge is connected between a power supply node and the first node; a fourth resistor voltage-dividing bridge connected between the power supply node and the second node; as well as A reading circuit, the reading circuit comprising: a first differential pair of NMOS transistors, wherein sources of the first differential pair of NMOS transistors are connected to a middle node of the second resistor divider bridge; a second differential pair of NMOS transistors, wherein sources of the second differential pair of NMOS transistors are connected to a middle node of the first resistor divider bridge; a third differential pair of PMOS transistors, wherein sources of the third differential pair of PMOS transistors are connected to a middle node of the fourth resistor divider bridge; a fourth differential pair of PMOS transistors, wherein sources of the fourth differential pair of PMOS transistors are connected to a middle node of the third resistor divider bridge; a first bias circuit configured to apply different bias potentials to a gate of the first differential pair and a gate of the second differential pair; and a second bias circuit configured to apply different bias potentials to the gate of the third differential pair and the gate of the fourth differential pair; Wherein the read circuit is configured to determine a binary state of the bus based on current flowing through the first differential pair, the second differential pair, the third differential pair, and the fourth differential pair.

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