Switching regulator

Abstract

Provided is a switching regulator that generates a comparison result signal relating to an input / output voltage difference even if there is no terminal for monitoring an output voltage. This switching regulator is provided with: a switching circuit for switching an input voltage and outputting a switching voltage on the basis of a predetermined gate control signal; a voltage difference detector that outputs a comparison result signal by comparing the switching voltage with a threshold value depending on the input voltage; and a control circuit that generates a gate control signal and outputs the gate control signal to the switching circuit based on an output voltage in which the switching voltage is smoothed and fed back and the comparison result signal. The voltage difference detector includes: an integrating circuit that generates and outputs a pseudo output voltage that is a voltage obtained by time-integrating a switching voltage and that is substantially equal to an output voltage; and a comparator circuit that compares the pseudo output voltage with a threshold value depending on the power supply voltage and outputs a comparison result signal.

Description

Technical Field

[0001] The present invention relates to a switching regulator used in, for example, a power conversion device or the like. Background Art

[0002] Conventionally, it is known that in a switching regulator, a specific sequence is used when the input-output voltage difference is small, such as in a battery through mode.

[0003] For example, Patent Document 1 discloses a conventional switching converter that provides a driving unit for each of a plurality of switches and controls each switch according to a load current, an input voltage, an output voltage, or an input / output voltage, thereby improving conversion efficiency during DC-DC conversion.

[0004] The switching converter of this conventional example is characterized in that when a plurality of first switches and a plurality of second switches are alternately set to an on state to perform synchronous rectification, the plurality of first switches are repeatedly driven to an on or off state according to required outputs, and the plurality of second switches are driven to an on or off state in synchronization with the first switches, and the driving of part of the plurality of first switches and the driving of part or all of the plurality of second switches are stopped according to load current, output voltage, input voltage or input-output voltage difference.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2006-296186 Summary of the invention

[0008] Problems to be solved by the invention

[0009] However, in an input / output voltage monitoring circuit using a conventional voltage detection circuit, it is necessary to take in the power supply voltage and the output voltage for comparison. In an external output voltage adjustment circuit in which the customer can arbitrarily set the feedback rate, there is a problem that the output voltage cannot be monitored.

[0010] In the above-mentioned conventional switching converter, a structure is disclosed for monitoring the power supply voltage and the output voltage for the purpose of switching control by the input-output voltage difference. However, the problem that it cannot cope with the problem that there is no terminal for monitoring the output voltage cannot be solved.

[0011] An object of the present invention is to solve the above-mentioned problems and to provide a switching regulator capable of generating a comparison result signal related to an input-output voltage difference even when a terminal for monitoring an output voltage does not exist in the switching regulator.

[0012] Means for solving problems

[0013] A switching regulator according to one aspect of the present invention includes:

[0014] A switching circuit switches an input voltage and outputs a switching voltage based on a given gate control signal;

[0015] a voltage difference detector for outputting a comparison result signal by comparing the switch voltage with a threshold value depending on the input voltage; and

[0016] a control circuit that generates the gate control signal and outputs it to the switch circuit based on the smoothed output voltage of the switch voltage and the comparison result signal;

[0017] The voltage difference detector comprises:

[0018] an integrating circuit, generating and outputting a voltage obtained by time-integrating the switching voltage, that is, a pseudo output voltage substantially equal to the output voltage; and

[0019] The comparator circuit compares the pseudo output voltage with a threshold value depending on the power supply voltage and outputs a comparison result signal.

[0020] Effects of the Invention

[0021] Therefore, according to the switching regulator involved in the present invention, a comparison result signal is generated by comparing the voltage after time integration of the switching voltage with a threshold value depending on the power supply voltage. Therefore, even if there is no terminal for monitoring the output voltage, a comparison result signal related to the input-output voltage difference can be generated. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 1 is a circuit diagram showing a configuration example of the switching regulator 1 according to the first embodiment.

[0023] Figure 2 It is shown Figure 1 A circuit diagram showing a configuration example of the operation of the voltage difference detector 20 of the switching regulator 1.

[0024] Figure 3 It is shown in Figure 1 1 is a timing diagram of each signal of the operation when the PWM method is used in the switching regulator 1.

[0025] Figure 4 It is shown in Figure 1 1 is a timing diagram of each signal of the operation when the PFM method is used in the switching regulator 1.

[0026] Figure 5 : is a circuit diagram showing a configuration example of a voltage difference detector 20A according to Modification 1.

[0027] Figure 6 : is a circuit diagram showing a configuration example of a voltage difference detector 20B according to Modification 2.

[0028] Figure 7 : is a circuit diagram showing a configuration example of a voltage difference detector 20C according to Modification 3.

[0029] Figure 8 : is a circuit diagram showing a configuration example of a voltage difference detector 20D according to a fourth modification.

[0030] Fig. 9 : is a circuit diagram showing a configuration example of a voltage difference detector 20E according to Modification 5.

[0031] Fig.10 1 is a circuit diagram showing a configuration example of a switching regulator 1A according to the second embodiment.

[0032] Fig.11 : is a circuit diagram showing a configuration example of a switching regulator 1D according to the third embodiment.

[0033] Fig.12 1 is a circuit diagram showing a configuration example of a switching regulator 1E according to a fourth embodiment.

[0034] Fig.13 1F is a circuit diagram showing a configuration example of a switching regulator 1F according to the fifth embodiment.

[0035] Fig.14 1 is a circuit diagram showing a configuration example of a switching regulator 1G according to a sixth embodiment.

[0036] Fig.15 1 is a circuit diagram showing a configuration example of a switching regulator 1H according to the seventh embodiment.

[0037] Fig.16 : is a circuit diagram showing a configuration example of a switching regulator 1I according to the eighth embodiment.

[0038] Fig.17 1 is a circuit diagram showing a configuration example of a switching regulator 1J according to the ninth embodiment.

[0039] Fig.18 : is a circuit diagram showing a configuration example of a switching regulator 1K according to the tenth embodiment.

[0040] Fig.19 1 is a circuit diagram showing a configuration example of a switching regulator 1L according to the eleventh embodiment.

[0041] Fig. 20 : is a circuit diagram showing the configuration of an input / output voltage monitoring circuit 101 according to Comparative Example 1.

[0042] Fig.21 : is a circuit diagram showing the configuration of the input / output voltage monitoring circuit 102 according to the second comparative example.

[0043] Fig. 22 : is a circuit diagram showing the structure of the switching regulator 103 according to the comparative example 3.

[0044] Fig.23 : is a circuit diagram showing the structure of the switching regulator 104 according to the fourth comparative example. DETAILED DESCRIPTION

[0045] Hereinafter, embodiments and modifications of the present invention will be described with reference to the accompanying drawings. In addition, the same or similar components are denoted by the same reference numerals.

[0046] (Opinion of the inventor)

[0047] (Comparative Example 1)

[0048] Fig. 20 is a circuit diagram showing the configuration of an input / output voltage monitoring circuit 101 according to Comparative Example 1. Fig. 20 In FIG. 1 , the input / output voltage monitoring circuit 101 is configured to include two differential amplifiers 111 and 112 and a selector 113 .

[0049] In the input / output voltage monitoring circuit 101 configured as described above, the power supply voltage input to the input terminal T1, that is, the input voltage VIN, is input to the non-inverting input terminal of the differential amplifier 111, and the differential amplifier 111 amplifies the difference voltage between the input voltage VIN and the first reference voltage Vre1 from the reference voltage source 121, and outputs it to the selector 113. On the other hand, the output voltage VOUT is input to the non-inverting input terminal of the differential amplifier 112, and the differential amplifier 112 amplifies the difference voltage between the output voltage VOUT and the second reference voltage Vre2 from the reference voltage source 122, and outputs it to the selector 113. The selector 113 selects one of the two input voltages in accordance with a given selection condition, and outputs the selected voltage as the comparison result voltage COMP.

[0050] (Comparative Example 2)

[0051] Fig.21is a circuit diagram showing the configuration of the input / output voltage monitoring circuit 102 according to Comparative Example 2. Fig.21 In FIG. 1 , the input / output voltage monitoring circuit 102 is configured to include four resistors R91 to R94 and a comparator 114 .

[0052] In the input / output voltage monitoring circuit 102 configured as described above, the power supply voltage input to the input terminal T1, that is, the input voltage VIN, is divided by the voltage-dividing resistors R91 and R92, and the divided voltage is input to the non-inverting input terminal of the comparator 114. On the other hand, the output voltage VOUT is divided by the voltage-dividing resistors R93 and R94, and the divided voltage is input to the inverting input terminal of the comparator 114. The comparator 114 generates and outputs a comparison result signal COMP of each divided voltage.

[0053] As described above, generally, when generating a comparison result signal related to the input-output voltage difference, a circuit such as a comparator 114 is required to take in the input voltage VIN and the output voltage VOUT and compare them, which increases the circuit area. Fig. 20 In this case, differential amplifiers 111 and 112 and a selector 113 are required. When a voltage detector is used, a voltage dividing circuit for taking in the input voltage VIN and the output voltage VOUT and a comparator 114 for comparing the two taken-in divided voltages are required.

[0054] (Comparative Example 3)

[0055] Fig. 22 is a circuit diagram showing the structure of the switching regulator 103 according to Comparative Example 3. Fig. 22 In the figure, the switching regulator 103 is constructed to include terminals T1~T4, voltage-dividing resistors R95 and R96, a differential amplifier 11, a comparator 12, a reference voltage source 21, a triangular wave oscillator 22, a control circuit 10 that generates gate control signals S1 and S2 with at least different levels at a given period, MOS transistors Q1 and Q2 as switching elements, and a voltage difference detector 20F.

[0056] The switching output voltage from the terminal T4 of the switching regulator 103 configured as above is smoothed by the output inductor Lout and the smoothing capacitor Cout to become the output voltage VOUT, and the output voltage VOUT is fed back to the feedback terminal T3. Here, the terminal T4 is the switching output voltage terminal (SW). In addition, the terminal T3 is the feedback terminal (FB).

[0057] The output voltage VOUT input to the terminal T3 is input to the voltage difference detector 20F and is divided by the voltage dividing resistors R95 and R96. The divided voltage is input to the differential amplifier 11, which uses the reference voltage from the reference voltage source 21 to amplify the difference voltage and outputs it to the comparator 12. The comparator 12 compares the amplified error voltage with the triangular wave voltage from the triangular wave oscillator 22, thereby generating a comparison result signal (synchronous control signal) for generating gate control signals S1 and S2, and outputs it to the control circuit 10. If the comparator 12 is a PWM comparator, based on the amplified error voltage, the lower the output voltage VOUT is than the reference voltage, the pulse signal with a narrower pulse width of the comparison result is generated. On the other hand, the voltage difference detector 20F detects the difference between the two input voltages and outputs the error signal of the voltage difference to the control circuit 10. The control circuit 10 generates gate control signals S1 and S2 based on the error signal of the voltage difference and the pulse signal of the comparison result as is well known, and applies them to the gates of the MOS transistors Q1 and Q2, respectively, thereby controlling the on / off of the MOS transistors Q1 and Q2.

[0058] (Comparative Example 4)

[0059] Fig.23 is a circuit diagram showing the structure of the switching regulator 104 according to Comparative Example 4. Fig.23 In the embodiment, the switching regulator 104 and Fig. 22 Compared with the switching regulator 103, the following points are different.

[0060] (1) The voltage-dividing resistors R95 and R96 are replaced with variable resistors VR1 and VR2 disposed outside the switching regulator 104 .

[0061] As in Comparative Example 3 Fig. 22 In this way, if the circuit feeds back the output voltage VOUT, the output voltage VOUT can be monitored. Fig.23 In this way, when the output voltage VOUT is externally adjusted using the variable resistors VR1 and VR2 , since there is no monitoring target, it is necessary to add the terminal T5 (VOUT) which is not originally necessary.

[0062] In an embodiment of the present invention, a switching regulator is provided that can generate a comparison result signal related to an input-output voltage difference even when a terminal for monitoring an output voltage does not exist in the switching regulator. Specifically, the switching regulator is characterized in that, when detecting an input-output voltage difference in a circuit that cannot take in an output voltage VOUT, a voltage obtained by time-integrating a switching voltage is detected using a threshold value that depends on a power supply voltage.

[0063] (Implementation method 1)

[0064] Figure 1 is a circuit diagram showing a configuration example of a switching regulator 1 according to Embodiment 1. Figure 2 It is shown Figure 1 A circuit diagram showing a configuration example of the operation of the voltage difference detector 20 of the switching regulator 1.

[0065] exist Figure 1 In the embodiment, the switching regulator 1 is configured to include terminals T1 to T4, variable resistors VR1 and VR2, a differential amplifier 11, a comparator 12, a reference voltage source 21, a triangular wave oscillator 22, a control circuit 10 that generates gate control signals S1 and S2 having at least mutually different levels at a given cycle, MOS transistors Q1 and Q2 that are switching elements and constitute a switching circuit, and a voltage difference detector 20. Figure 2 In the embodiment, the voltage difference detector 20 includes an integrating circuit 25 including a resistor R1 and a capacitor C1, a comparator circuit 27 including MOS transistors Q11 and Q12, and an inverter INV1. Here, the MOS transistor Q1 is a P-channel MOS transistor (PMOSFET), and the MOS transistor Q2 is an N-channel MOS transistor (NMOSFET).

[0066] The comparator circuit 27 is formed by connecting a P-channel MOS transistor (PMOS transistor) Q11 and an N-channel MOS transistor (NMOS transistor) Q12 in series between an input voltage VIN as a power supply voltage VDD and ground, and compares the output voltage of the integration circuit 25 using a threshold value depending on the power supply voltage VDD, thereby outputting a comparison result signal.

[0067] As for the output voltage, the output voltage VOUT is smoothed by the output inductor Lout and the smoothing capacitor Cout from the terminal T4 of the switching regulator 1 configured as above, and the output voltage VOUT is fed back to the feedback terminal T3 via the variable resistor VR1. The voltage obtained by dividing the output voltage VOUT by the resistor is input to the differential amplifier 11 via the terminal T3, and the differential amplifier 11 amplifies the difference voltage between the divided voltage and the reference voltage, and inputs it to the non-inverting input terminal of the comparator 12. The comparator 12 compares the amplified error voltage with the triangular wave voltage from the triangular wave oscillator 22, thereby generating a comparison result signal (synchronous control signal) for generating gate control signals S1 and S2, and outputs it to the control circuit 10. If the comparator 12 is a PWM comparator, based on the amplified error voltage, the lower the output voltage VOUT is than the reference voltage, the pulse signal with a narrower pulse width of the comparison result is generated. On the other hand, the power supply voltage VDD input to the terminal T1, that is, the input voltage VIN, and the output voltage of the terminal T4 are input to the voltage difference detector 20. The voltage difference detector 20 integrates the output voltage of the terminal T4 with time through the integration circuit 25, and then outputs the voltage to the control circuit 10 via the comparator circuit 27 and the inverter INV1 that perform the comparison operation, and the terminal T13. The control circuit 10 generates gate control signals S1 and S2 based on the comparison result signal from the voltage difference detector 20 and the pulse signal of the comparison result from the comparator 12, and applies them to the gates of the MOS transistors Q1 and Q2, respectively, as is well known, thereby controlling the on / off of the MOS transistors Q1 and Q2.

[0068] Here, the integration constant is set so that the output voltage VOUTa of the integration circuit 25 is substantially consistent with the output voltage VOUT, the comparator circuit 27 operates with the input voltage VIN as the power supply voltage, and the threshold duty ratio of the comparator circuit 27 is determined according to the ratio of the gate size of the PMOS transistor Q11 and the gate size of the NMOS transistor Q12. Here, the output voltage VOUTa of the integration circuit 25 is substantially consistent with the output voltage VOUT, so it can be called a "pseudo-output voltage".

[0069] As explained above, Figure 1 In the switching regulator 1 , when there is no terminal for monitoring the output voltage VOUT, the SW voltage of the terminal T4 is monitored without adding a terminal for the output voltage VOUT. Figure 2 The voltage difference detector 20 generates a pseudo output voltage (pseudo output voltage) VOUTa after time-integrating the SW voltage, and the comparator circuit 27 compares the pseudo output voltage VOUTa with a threshold value depending on the power supply voltage VDD, thereby generating and outputting a comparison result signal.

[0070] Figure 3 It is shown in Figure 1 The timing diagram of each signal of the operation when the PWM method is used in the switching regulator 1. Figure 3 , a voltage VOUTa generated according to a SW voltage different from an input voltage VIN and a voltage difference detection signal OUT are shown. Figure 3 The ripple voltage of the voltage VOUTa is about several mV to several tens of mV. Here, the configuration is such that when the PN ratio (gate size ratio of the PMOS transistor Q11 and the NMOS transistor Q12) is adjusted so that the threshold value of the comparator circuit 27 becomes 75%, the detection signal rises from the L level to the H level under the condition that the output voltage VOUT exceeds 75% of the power supply voltage VDD.

[0071] Figure 4 It is shown in Figure 1 The timing diagram of each signal when the switching regulator 1 uses the PFM method is shown in FIG. Figure 3 In addition to the continuous action PWM method, the skip action PFM method can also be detected. Figure 4 The ripple voltage of the voltage VOUT and VOUTa is about several mV to several tens of mV.

[0072] The integration multiplier (time constant) of the integration circuit 25 can be optimized to a multiplier corresponding to the oscillation frequency of the switching regulator 1. In addition, even in the case of having a terminal for outputting the voltage VOUT, it is effective to reduce the circuit area by changing the application of the SW voltage to the application of the output voltage VOUT.

[0073] As described above, according to the first embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0074] Next, a plurality of modified examples of the voltage difference detector 20 will be described below.

[0075] (Variant 1)

[0076] Figure 5 : is a circuit diagram showing a configuration example of a voltage difference detector 20A according to Modification 1. Figure 5 The voltage difference detector 20A and Figure 2 Compared with the voltage difference detector 20, the following points are different.

[0077] (1) Four MOS transistors Q21 to Q24 connected in series and MOS transistors Q25 and Q26 for generating hysteresis characteristics are provided instead of MOS transistors Q11 and Q12. Here, MOS transistors Q21, Q22, and Q25 are P-channel MOS transistors (PMOSFET), and MOS transistors Q23, Q24, and Q26 are N-channel MOS transistors (NMOSFET).

[0078] (Variant 2)

[0079] Figure 6 : is a circuit diagram showing a configuration example of a voltage difference detector 20B according to Modification 2. Figure 6 The voltage difference detector 20B and Figure 2 Compared with the voltage difference detector 20, the following points are different.

[0080] (1) The delay generating inverter INV2 and the capacitor C2 are provided instead of the MOS transistors Q11 and Q12.

[0081] (Variant 3)

[0082] Figure 7 : is a circuit diagram showing a configuration example of a voltage difference detector 20C according to Modification 3. Figure 7 The voltage difference detector 20C and Figure 2 Compared with the voltage difference detector 20, the following points are different.

[0083] (1) In place of the MOS transistors Q11 and Q12 and the inverter INV1, there are voltage-dividing resistors R11 and R12 and a comparator 13. Here, the voltage-dividing resistors R11 and R12 apply a voltage obtained by dividing the input voltage VIN to the inverting input terminal of the comparator 13. The output voltage of the integration circuit 25 is applied to the non-inverting input terminal of the comparator 13. The comparator 13 outputs a comparison result signal obtained by comparing the two voltages from a terminal T13.

[0084] (Variant 4)

[0085] Figure 8 : is a circuit diagram showing a configuration example of a voltage difference detector 20D according to a fourth modification. Figure 8 The voltage difference detector 20D and Figure 2 Compared with the voltage difference detector 20, the following points are different.

[0086] (1) The comparator 13 is provided with a level shifter for input conversion instead of the MOS transistors Q11 and Q12 and the inverter INV1 . Here, the input voltage VIN is applied to the inverting input terminal of the comparator 13 , and the output voltage of the integration circuit 25 is applied to the non-inverting input terminal of the comparator 13 .

[0087] (Variant 5)

[0088] Fig. 9 : is a circuit diagram showing a configuration example of a voltage difference detector 20E according to Modification 5. Fig. 9 The voltage difference detector 20E and Figure 2 Compared with the voltage difference detector 20, the present invention further includes the following structural elements.

[0089] (1) A constant current source CI1 connected between a terminal T11 of an input voltage VIN and the gates of MOS transistors Q11 and Q12;

[0090] (2) a constant current source CI2 connected between the source of the MOS transistor Q12 and ground; and

[0091] (3) MOS transistor Q13 is inserted between the integration circuit 25 and the comparator circuit 27 .

[0092] Here, the circuit between the integrating circuit 25 and the inverter INV1 constitutes a constant current inverter circuit.

[0093] (Implementation method 2)

[0094] Fig.10 1 is a circuit diagram showing a configuration example of a switching regulator 1A according to the second embodiment. Fig.10 The switching regulator 1A with Figure 1 Compared with the switching regulator 1, the following points are different.

[0095] (1) A NOR gate 14 is provided in place of the control circuit 10 .

[0096] Here, the output voltage of the voltage difference detector 20 is input to the first input terminal of the NOR gate 14, and the output voltage of the comparator 12 is input to the second input terminal of the NOR gate 14. The NOR gate 14 applies the output voltage to the gates of the MOS transistors Q11 and Q12 as the gate control signal S1. Thus, a voltage control type switching regulator 1A is formed.

[0097] As described above, according to the second embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0098] Alternatively, the differential amplifier 11 , the comparator 12 , the reference voltage source 21 , and the triangular wave oscillator 22 may be assembled and modularized as a switching modulation circuit. This also applies to the following embodiments.

[0099] (Implementation method 3)

[0100] Fig.11 : is a circuit diagram showing a configuration example of a switching regulator 1D according to Embodiment 3. Fig.11 For the switching regulator 1D, the circuit in the switching regulator has the following features except for the connection between the terminals T1 and T5. Fig.10 The switching regulator 1A is the same as that of the first embodiment, but is different in the following points.

[0101] (1) The input voltage VIN of the terminal T1 is input from the terminal T4 via the input inductor Lout and is input to the voltage difference detector 20 .

[0102] (2) The drain voltage of the MOS transistor Q1 is output to the voltage difference detector 20 and is output to the voltage dividing resistors VR1 and VR2 as the output voltage VOUT via the output capacitor Cout.

[0103] Thus, a switching regulator in boost mode is constructed.

[0104] As described above, according to the third embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0105] (Implementation method 4)

[0106] Fig.12 1 is a circuit diagram showing a configuration example of a switching regulator 1E according to a fourth embodiment. Fig.12 The switching regulator 1E with Fig.10 Compared with the switching regulator 1A, the following points are different.

[0107] (1) Instead of the comparator 12 having the triangular wave oscillator 22 , comparators 12A and 12B having triangular wave oscillators 22A and 22B, respectively, are provided.

[0108] (2) NOR gates 14A and 14B are provided instead of the NOR gate 14 .

[0109] (3) MOS transistors Q33 and Q34 are provided between the output inductor Lout and the output capacitor Cout.

[0110] (4) The terminal T5 is connected to the terminal T12 of the voltage difference detector 20 instead of the terminal T4 .

[0111] Here, the MOS transistors Q31 and Q34 are P-channel MOS transistors (PMOSFET), and the MOS transistors Q32 and Q33 are N-channel MOS transistors (NMOSFET).

[0112] exist Fig.12 In the embodiment, the output voltage from the differential amplifier 11 is input to the inverting input terminals of the comparators 12A and 12B. The comparison result signals of the comparators 12A and 12B are output to the gates of the MOS transistors Q31 and Q32 and the gates of the MOS transistors Q33 and Q34 via the NOR gates 14A and 14B, respectively. Here, the source of the MOS transistor Q31 is connected to the terminal T1 of the input voltage VIN and the voltage difference detector 20, and the connection point of the drains of the MOS transistors Q31 and Q32 is connected to the connection point of the drain of the MOS transistor Q33 and the source of Q34 via the terminal T6, the connection capacitor Lcn, and the terminal T7. The connection point of the sources of the MOS transistors Q32 and Q33 is grounded. The drain of the MOS transistor Q34 is connected to the terminal T5, and the output voltage VOUT from the terminal T5 is connected to the voltage dividing resistors VR1 and VR2 via the output capacitor Cout.

[0113] Here, the terminal T6 is a step-down side switching voltage terminal (BUSW), and the terminal T7 is a step-up side switching voltage terminal (BOSW).

[0114] The switching regulator 1E configured as described above operates in the buck-boost mode.

[0115] As described above, according to the fourth embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0116] (Implementation method 5)

[0117] Fig.13 1F is a circuit diagram showing a configuration example of a switching regulator 1F according to the fifth embodiment. Fig.13 The switching regulator 1F and Figure 1 Compared with the switching regulator 1, the following points are different.

[0118] (1) The device further includes a voltage regulator 30 , a diode D1 , a boost terminal T6 , and a boost capacitor Cbst.

[0119] exist Fig.13In the embodiment, the input voltage VIN is input to the voltage regulator 30 and the voltage difference detector 20. After the voltage regulator 30 adjusts the input voltage VIN to a given voltage, it outputs it to the control circuit 10 via the diode D1, and at the same time, it is outputted via the boost terminal T8, the boost capacitor Cbst, the output inductor Lout, and the output capacitor Cout to become the output voltage VOUT. Figure 1 Likewise, thereby, a so-called NN type (N channel-N channel type) bootstrap type switching regulator is configured.

[0120] As described above, according to the fifth embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0121] Next, the voltage difference detector 20 has a different use from the above, and can be applied to an electronic circuit that monitors the power supply voltage and the output voltage to control the switching regulator as described below.

[0122] (Implementation method 6)

[0123] Fig.14 1 is a circuit diagram showing a configuration example of a switching regulator 1G according to a sixth embodiment. Fig.14 In, with Fig.10 Compared with the switching regulator 1A, the following points are different.

[0124] (1) The differential amplifier 11 , the comparator 12 , the reference voltage source 21 , and the triangular wave oscillator 22 are replaced by the comparator 12 , the reference voltage source 21 , the pulse oscillator 26 , and the set-reset flip-flop 16 .

[0125] (2) The comparison result signal from the voltage difference detector 20 is input to the first input terminal of the NOR gate 14. The output signal from the set-reset flip-flop 16 is output to the gate of the MOS transistor Q1 as the gate control signal S1 via the inverter INV11.

[0126] (3) The output signal of the inverter INV11 is output to the second input terminal of the NOR gate 14 via the inverter INV12 .

[0127] (4) The output signal of the NOR gate 14 is applied to the gate of the MOS transistor Q2 as the gate control signal S2.

[0128] exist Fig.14In the embodiment, the comparator 12 compares the divided voltage of the output voltage VOUT with the reference voltage source from the reference voltage source 21, and outputs the comparison result signal to the set terminal of the set-reset type flip-flop 16 and the control terminal of the pulse oscillator 26. The pulse oscillator 26 generates a pulse signal in synchronization with the comparison result signal, and outputs it to the reset terminal of the set-reset type flip-flop 16. The switching regulator 1C configured as above operates in a so-called hysteresis control method.

[0129] In the switching regulator 1G configured as described above, by providing the voltage difference detector 20 and the NOR gate 14 , the peak value of the inductor current is reduced in a low input-output voltage state, and when there is a concern about a reverse current flow, the reverse current can be prevented.

[0130] As described above, according to the sixth embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0131] (Implementation method 7)

[0132] Fig.15 1 is a circuit diagram showing a configuration example of a switching regulator 1H according to a seventh embodiment. Fig.15 middle, Fig.15 The switching regulator 1H with Fig.14 Compared with the switching regulator 1G, the following points are different.

[0133] (1) A zero cross detector 40 is inserted between the voltage difference detector 20 and the input terminal of the NOR gate 14 .

[0134] (2) The current detector 2 is inserted between the terminal T4 and the output inductor Lout.

[0135] Here, the zero-crossing detector 40 outputs an H-level detection signal to the NOR gate 14 when the current value from the current detector 2 crosses zero or when the voltage difference from the voltage difference detector 20 is within a given voltage range.

[0136] In the switching regulator 1H configured as described above, by including the voltage difference detector 20, the zero crossing detector 40, and the NOR gate 14, the peak value of the inductor current becomes small in a low input-output voltage state, and when there is a concern about a reverse current, the reverse current can be prevented.

[0137] As described above, according to the ninth embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0138] (Implementation method 8)

[0139] Fig.16 : is a circuit diagram showing a configuration example of a switching regulator 1I according to the eighth embodiment. Fig.16 The switching regulator 1I with Fig.10 Compared with the switching regulator 1A, the following points are different.

[0140] (1) An inverter INV11 is provided in place of the NOR gate 14 .

[0141] (2) The comparison result signal from the voltage difference detector 20 is input to the pulse oscillator 26 .

[0142] In the switching regulator 1I configured as described above, the pulse oscillator 26 generates a pulse signal in synchronization with the comparison result signal or when the comparison result signal is within a predetermined voltage range, and outputs the pulse signal to the reset terminal of the set-reset flip-flop 16 .

[0143] In the switching regulator 1I configured as above, the comparison result signal from the voltage difference detector 20 is input to the pulse oscillator 26, so that the timer time can be varied within a given voltage range, thereby adjusting the control time involved in the gate control of the switching element.

[0144] (Implementation method 9)

[0145] Fig.17 1 is a circuit diagram showing a configuration example of a switching regulator 1J according to the ninth embodiment. Fig.17 The switching regulator 1J and Fig.10 Compared with the switching regulator 1A, the following points are different.

[0146] (1) The current detector 2 is inserted between the terminal T4 and the output inductor Lout. The current detector 2 detects the inductor current and outputs the detected current value to the peak current detector 50 .

[0147] (2) The comparison result signal from the voltage difference detector 20 is input to the peak current detector 50 .

[0148] (3) When the comparison result signal is within a given voltage range, the peak current detector 50 detects the peak current based on the inductor current detected by the current detector 2 , and outputs the detection signal to the reset terminal of the set-reset flip-flop 15 .

[0149] (4) The comparison result signal of the comparator 12 is output to the set terminal of the set-reset flip-flop 15 .

[0150] According to the switching regulator 1J configured as described above, when a predetermined peak current is reached, the current detection threshold can be adjusted by resetting the switching operation.

[0151] In the switching regulator 1J configured as above, the comparison result signal from the voltage difference detector 20 is input to the pulse oscillator 26, so that the comparison result signal generates a pulse signal within a given voltage range, which can reset the set-reset flip-flop 16. Thus, the switching action threshold involved in the gate control of the switching element can be adjusted.

[0152] As described above, according to the ninth embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0153] (Implementation 10)

[0154] Fig.18 : is a circuit diagram showing a configuration example of a switching regulator 1K according to the tenth embodiment. Fig.18 The switching regulator 1K with Fig.14 Compared with the switching regulator 1G, the following points are different.

[0155] (1) The comparison result signal from the voltage difference detector 20 is input to the soft start circuit 60 .

[0156] (2) The output signal of the soft start circuit 60 is input to the non-inverting input terminal of the comparator 12 .

[0157] In the switching regulator 1K configured as described above, the comparison result signal from the voltage difference detector 20 is input to the soft start circuit 60, so that the comparison result signal is soft-started with a given time delay using the reference voltage from the reference voltage source 21 within a given voltage range, and a given trigger signal is generated and input to the inverting input terminal of the comparator 12. Thus, the set-reset type flip-flop 16 can be set after being reset by the H-level set signal from the comparator 12 and the trigger signal to the pulse oscillator 26. Thus, the gate control signal involved in the gate control of the switching element can be soft-started.

[0158] As described above, according to the tenth embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0159] (Implementation 11)

[0160] Fig.19 1 is a circuit diagram showing a configuration example of a switching regulator 1L according to the eleventh embodiment. Fig.19 The switching regulator 1L with Fig.12 Compared with the switching regulator 1E, the following points are different.

[0161] (1) Inverters INV21 and INV22 are provided in place of the NOR gates 14A and 14B, respectively.

[0162] (2) Comparators 12C and 12D are provided in place of comparators 12A and 12B. The comparison result signal from the voltage difference detector 20 is input to the control terminal of the comparator 12C via the inverter INV31, and is also input to the control terminal of 12D. Here, when the comparison result signal is within a given first voltage range, the comparator 12C is operated, and when the comparison result signal is within a second voltage range different from the first voltage range, the comparator 12D is operated.

[0163] According to the switching regulator 1L configured as described above, the operations of the comparator 12C and the comparator 12D can be selectively switched according to the voltage difference from the voltage difference detector 20 .

[0164] As described above, according to the eleventh embodiment, in the switching regulator, even when there is no terminal for monitoring the output voltage, it is possible to generate a comparison result signal related to the input-output voltage difference.

[0165] (Other variations)

[0166] In the above embodiment and modification, the MOS transistors Q1 to Q31 as switching elements are provided in the circuit of the switching regulators 1 and 1A to 1L, but the present invention is not limited thereto and may be provided outside the circuit of the switching regulators 1 and 1A to 1L.

[0167] Industrial Application Possibility

[0168] As described in detail above, according to the switching regulator involved in the present invention, a comparison result signal is generated by comparing the voltage after time integration of the switching voltage with a threshold value depending on the power supply voltage. Therefore, even if there is no terminal for monitoring the output voltage, a comparison result signal related to the input-output voltage difference can be generated.

[0169] Description of Reference Numerals

[0170] 1. 1A~1L: Switching regulator, 10: Control circuit, 11: Differential amplifier, 12, 12A~12D: Comparator, 13: Comparator, 14, 14A, 14B: NOR gate, 16: Set-reset flip-flop, 20, 20A~20F: Voltage difference detector, 21: Reference voltage source, 22, 22A, 22B: Triangular wave oscillator, 23: Adder, 25: Integrator circuit, 26: Pulse oscillator, 27: Comparator circuit, 30: Voltage regulator, 50: Peak current detector, 60: Soft start circuit, 101, 102: Input and output voltage monitoring Circuit, 103~104: switching regulator, 111, 112: differential amplifier, 113: selector, 114: comparator, 121, 122: reference voltage source, CI1, CI2: constant current source, Cbst: boost capacitor, Ccn: connecting capacitor, Cout: output capacitor, D1: diode, INV1~INV31: inverter, Lcn: connecting inductor, Lout: output inductor, Q1~Q34: MOS transistor, R1~R96: resistor, C1: capacitor, VR1~VR2: variable resistor, T1~T13: terminal.

Claims

1. A switching regulator comprising: A switching circuit switches an input voltage and outputs a switching voltage based on a given gate control signal; a voltage difference detector for outputting a comparison result signal by comparing the switch voltage with a threshold value depending on the input voltage; as well as a control circuit that generates the gate control signal and outputs it to the switch circuit based on the smoothed output voltage of the switch voltage and the comparison result signal; The voltage difference detector comprises: an integrating circuit, generating and outputting a voltage obtained by time-integrating the switching voltage, that is, a pseudo output voltage substantially equal to the output voltage; as well as The comparator circuit compares the pseudo output voltage with a threshold value depending on the power supply voltage and outputs a comparison result signal.

2. The switching regulator according to claim 1, wherein: The comparator circuit includes two MOS transistors connected in series.

3. The switching regulator according to claim 1, wherein: The comparator circuit has a hysteresis characteristic and includes four MOS transistors connected in series.

4. The switching regulator according to claim 1, wherein: The comparator circuit includes an inverter and an output capacitor connected to a subsequent stage of the inverter.

5. The switching regulator according to claim 1, wherein: The comparator circuit includes a comparator that compares a voltage corresponding to the input voltage with the time-integrated voltage and outputs a comparison result signal.

6. The switching regulator as claimed in claim 5, wherein: The voltage corresponding to the input voltage is a voltage obtained by level-shifting the input voltage.

7. The switching regulator as claimed in claim 1, wherein: The comparator circuit includes a constant current inverter circuit.

8. The switching regulator of claim 1, wherein: The switching regulator is a voltage control mode, a current control mode, or a hysteresis control mode switching regulator.

9. The switching regulator of claim 1, wherein: The switching regulator is a step-up switching regulator or a buck-boost switching regulator.

10. The switching regulator of claim 1, wherein: The switching regulator monitors the input voltage and the output voltage to control the operation of the switching regulator.

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