Methods, processors, and computing devices that perform FFTs

Abstract

The embodiment disclosed by the application belongs to the technical field of computing, and particularly relates to a method for performing FFT, a processor and a computing device. The method comprises the following steps: in response to an execution request of a fast Fourier transform (FFT) calculation of an application program, a processor decomposes the FFT calculation into multiple calculations; the processor sequentially executes multiple calculation stages, wherein, when a target calculation stage is executed, a rotation factor calculation is executed based on a vector operation unit, and a DFT calculation is executed based on a matrix operation unit; after the execution of the multiple calculation stages is completed, an execution result of the FFT calculation is determined based on an execution result of the last calculation stage, and the execution result is returned to the application program. According to the application, the processor can jointly implement the FFT calculation based on the vector operation unit and the matrix operation unit, and the efficiency of the processor in executing the FFT calculation can be improved.

Description

[0001] This application is a divisional application of the original application with the application number 202311113216.4 and the original filing date of August 29, 2023, and the entire contents of the original application are incorporated herein by reference.

[0002] This application and the Chinese application with the application number 202311113216.4 both claim the priority of the Chinese patent application with the application number 202310667453.9 and the invention title of "An optimization method of application", which was filed on June 6, 2023, and the entire contents of the Chinese patent application are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of computers, and in particular to a method for performing FFT, a processor and a computing device. BACKGROUND

[0004] Discrete Fourier Transform (DFT) is a commonly used technology in the field of computers, which is used to convert discrete time domain data and discrete frequency domain data. Generally, when performing DFT, Fast Fourier Transform (FFT) technology is used to improve processing efficiency.

[0005] In related technologies, FFT can be implemented by a processor with a scalar operation unit and / or a vector operation unit, that is, FFT can be implemented by scalar operation and / or vector operation. However, the efficiency of implementing FFT by scalar operation and / or vector operation is still not high. SUMMARY

[0006] Embodiments of the present application provide a method for performing FFT, a processor and a computing device, which can improve the efficiency of performing FFT. The technical solution is as follows:

[0007] In a first aspect, a method for performing FFT is provided, which is performed by a processor including a vector operation unit and a matrix operation unit. The method for performing FFT by the processor includes:

[0008] The processor responds to an execution request of a fast Fourier transform (FFT) calculation of an application program. The FFT calculation is decomposed into a plurality of calculation stages, wherein at least one target calculation stage is included in the plurality of calculation stages, and the target calculation stage includes a twiddle factor calculation and a discrete Fourier transform (DFT) calculation after the FFT calculation is split. The plurality of calculation stages are executed in sequence, wherein when the target calculation stage is executed, the twiddle factor calculation is performed based on a vector operation unit, and the DFT calculation is performed based on a matrix operation unit. After the execution of the plurality of calculation stages is completed, an execution result of the FFT calculation is determined based on an execution result of the last calculation stage, and the execution result is returned to the application program.

[0009] In the scheme shown in the present application, during the execution of the FFT calculation, the processor can implement the complex number vector multiplication calculation of the twiddle factor corresponding to the input data through the vector operation unit, and implement the DFT calculation of the rotated input data and the DFT matrix through the matrix operation unit. In this way, the twiddle factor calculation and the DFT calculation are respectively implemented through the vector operation unit and the matrix operation unit, which can improve the calculation efficiency of the twiddle factor calculation and the DFT calculation, and further improve the efficiency of the processor executing the FFT calculation.

[0010] In an implementable manner, the twiddle factor calculation includes complex number vector multiplication calculation of input data of the target calculation stage and corresponding twiddle factors, and the twiddle factor calculation is performed based on the vector operation unit, including: performing complex number multiplication calculation of input data of the target calculation stage and corresponding twiddle factors based on the vector operation unit to obtain a calculation result, and the calculation result includes input data of each butterfly unit in the target calculation stage.

[0011] In the scheme shown in the present application, the vector operation unit can implement the complex number multiplication calculation of the input data and the plurality of twiddle factors by executing one complex number vector multiplication calculation, which can improve the efficiency of the processor executing the twiddle factor calculation.

[0012] In an implementable manner, the DFT calculation includes complex number matrix multiplication calculation of input data of each butterfly unit in the target calculation stage and the DFT matrix, and the DFT calculation is performed based on the matrix operation unit, including: obtaining real part data and imaginary part data in the input data of each butterfly unit. Obtaining real part data and imaginary part data of each column element in the DFT matrix. Based on the real part data and the imaginary part data corresponding to each butterfly unit, the real part data and the imaginary part data corresponding to the DFT matrix, and the matrix operation unit, the complex number matrix multiplication calculation is implemented.

[0013] In the scheme shown in the present application, when the DFT calculation is implemented based on the matrix operation unit, the real part data and the imaginary part data in the input data can be separated and respectively form the real part data matrix and the imaginary part data matrix for the DFT matrix calculation. In this way, the real part data and the imaginary part data are separated and calculated with the DFT matrix, which can avoid the non-continuous access of the real part data and the imaginary part data, and further improve the efficiency of the DFT calculation.

[0014] In an implementable manner, based on the real part data and the imaginary part data corresponding to each butterfly unit, the real part data and the imaginary part data corresponding to the DFT matrix, and the matrix operation unit, the complex matrix multiplication calculation is implemented, including: forming a first real part matrix by rows from the real part data in the input data of each butterfly unit. Forming a first imaginary part matrix by rows from the imaginary part data in the input data of each butterfly unit. Forming a second real part matrix by columns from the real part data included in each column element of the DFT matrix. Forming a second imaginary part matrix by columns from the imaginary part data included in each column element of the DFT matrix. Implementing the complex matrix multiplication calculation based on the first real part matrix, the first imaginary part matrix, the second real part matrix, the second imaginary part matrix, and the matrix operation unit.

[0015] In the scheme shown in the present application, the real part data and the imaginary part data of the input data for DFT calculation form a first real part matrix and a first imaginary part matrix, and the DFT matrix is divided into a second real part matrix and a second imaginary part matrix. In this way, the matrix operation unit respectively performs complex matrix multiplication calculation on the first real part matrix, the first imaginary part matrix, the second real part matrix, and the second imaginary part matrix, which can reduce the matrix size for matrix multiplication calculation, and further reduce the storage space of the matrix and improve the matrix calculation efficiency. In addition, it can avoid the non-continuous access of the real part data and the imaginary part data, and further improve the efficiency of the DFT calculation.

[0016] In an implementable manner, the number of columns in the DFT matrix is N, and based on the first real part matrix, the first imaginary part matrix, the second real part matrix, the second imaginary part matrix, and the matrix operation unit, the complex matrix multiplication calculation is implemented, including: adding the yth row of the first real part matrix to the xth row, and deleting the real part data of the yth row to obtain a third real part matrix, where y=N+2-x, x∈[2, N / 2] when N is even, and x∈[2, (N+1) / 2] when N is odd. Subtracting the yth row from the xth row of the first imaginary part matrix, and deleting the imaginary part data of the yth row to obtain a third imaginary part matrix. Forming a fourth real part matrix by the first M columns of the second real part matrix, where M=N / 2+1 when N is even, and M=(N+1) / 2 when N is odd. Forming a fourth imaginary part matrix by the first M columns of the second imaginary part matrix. Inputting the third real part matrix, the third imaginary part matrix, the fourth real part matrix, and the fourth imaginary part matrix into the matrix operation unit, and performing the complex matrix multiplication calculation by the matrix operation unit.

[0017] In the scheme shown in the present application, the symmetry of the DFT matrix is utilized to reduce the size of the first real matrix, the first imaginary matrix, the second real matrix, and the second imaginary matrix for DFT calculation, to obtain the corresponding third real matrix, the third imaginary matrix, the fourth real matrix, and the fourth imaginary matrix. Then the matrix operation unit can obtain the calculation result of the DFT calculation by performing complex matrix multiplication calculation on the third real matrix, the third imaginary matrix, the fourth real matrix, and the fourth imaginary matrix after size reduction. In this way, by reducing the size of the matrix, the efficiency of the processor in performing DFT calculation can be further improved.

[0018] In an implementable manner, the calculation result of each calculation stage in the FFT calculation is composed of the output data of the butterfly unit included in the calculation stage, and the method further comprises: for each calculation stage, reading the input data of the calculation stage in batches according to a specified reading step before performing the calculation, and storing the input data read each time separately into a specified number of vector registers, the specified number being the same as the value of the specified reading step, the specified reading step being equal to the ratio of the length of the input data of the FFT calculation to a specified number value, and the specified number value being equal to the product of the bases corresponding to the calculation stage and other calculated calculation stages respectively. For each calculation stage, the output data of each butterfly unit is sequentially obtained after the calculation is completed, the output data of the first butterfly unit obtained is stored in the memory according to a specified storage interval, and the output data of the other butterfly units obtained after the first butterfly unit is stored in the memory after the position where the output data of the butterfly unit is last stored, and the specified storage interval is equal to the ratio of the length of the input data of the FFT calculation to the base of the calculation stage.

[0019] In the scheme shown in the present application, the input data of each calculation stage in the FFT calculation is read according to a specified reading step, and the output data is stored according to an execution storage interval, so that a new butterfly network can be constructed. In the butterfly network, the input data corresponding to the same rotation factor in each calculation stage in the FFT calculation can be arranged continuously. In this way, the input data corresponding to each calculation stage can be read continuously, and then the input data of each butterfly unit in the calculation stage can be read by storing the input data corresponding to the same rotation factor into different vector registers. In this way, compared with the existing butterfly network, non-continuous reading of the input data of the calculation stage can be avoided when reading the input data of the butterfly unit. Therefore, the efficiency of the rotation factor calculation can be improved by using the butterfly network provided in the present application.

[0020] In an implementable manner, the rotation factor calculation includes complex vector multiplication calculation of the rotation factor corresponding to the input data of the target calculation stage and the DFT matrix, and the DFT calculation includes complex matrix multiplication calculation of the input data of the target calculation stage and the DFT matrix.

[0021] In the scheme shown in the present application, since in the target calculation stage, the input data of the plurality of butterfly units that can be stored in the plurality of butterfly units corresponding to the same rotation factor need to be respectively multiplied by the same rotation factor, and the calculation results of the plurality of butterfly units corresponding to the complex multiplication calculation need to be multiplied by the same DFT matrix. Therefore, in the present application, the rotation factor calculation can be set as the calculation of the rotation factor and the DFT matrix, and then the DFT calculation is set as the calculation of the input data of the target calculation stage and the calculated DFT matrix. In this way, the calculation of the rotation factor and the DFT matrix is performed once, which can avoid the multiple calculations of the input data and the rotation factor, so as to improve the efficiency of the processor in performing the FFT calculation.

[0022] In an implementable manner, the rotation factor calculation is performed based on the vector operation unit, including: forming the real part data in the input data of each butterfly unit into a fifth real part matrix by row, and forming the imaginary part data in the input data of each butterfly unit into a fifth imaginary part matrix by row. The real part data included in each column element of the DFT matrix is formed into a sixth real part matrix by column, and the imaginary part data included in each column element of the DFT matrix is formed into a sixth imaginary part matrix by column. Through the vector operation unit, the real part data of the rotation factor corresponding to the s-th row in the fifth real part matrix is multiplied to the s-th column of the sixth real part matrix to obtain a seventh real part matrix, and the imaginary part data of the rotation factor corresponding to the s-th row in the fifth imaginary part matrix is multiplied to the s-th column of the sixth imaginary part matrix to obtain a seventh imaginary part matrix, where s∈[1, N], and N is the number of columns in the DFT matrix.

[0023] The DFT calculation is performed based on the matrix operation unit, including: performing complex matrix multiplication calculation based on the fifth real part matrix, the fifth imaginary part matrix, the seventh real part matrix, the seventh imaginary part matrix, and the matrix operation unit.

[0024] In the scheme shown in the present application, the rotation factor calculation is set as the calculation of the rotation factor and the DFT matrix, and then the DFT calculation is set as the calculation of the input data of the target calculation stage and the calculated DFT matrix, and when performing the rotation factor calculation and the DFT calculation, the real part data and the imaginary part data can be calculated separately, so as to further improve the efficiency of the processor in performing the FFT calculation.

[0025] In an implementable manner, when N is even, s∈[2, N / 2], when N is odd, s∈[2, (N+1) / 2]; before the real part data in the input data of each butterfly unit is grouped into the fifth real part matrix, the input data in the rth row of the input data of each butterfly unit is subjected to complex multiplication calculation with a compensation rotation factor, to obtain updated input data in the rth row, the compensation rotation factor is calculated from the rotation factors corresponding to the input data in the rth row and the input data in the sth row of the input data of each butterfly unit, and r=N+2-s.

[0026] Based on the fifth real part matrix, the fifth imaginary part matrix, the seventh real part matrix, the seventh imaginary part matrix and the matrix operation unit, complex matrix multiplication calculation is implemented, including: adding the rth row of the fifth real part matrix to the sth row, and deleting the real part data in the rth row, to obtain an eighth real part matrix; subtracting the rth row of the fifth imaginary part matrix from the sth row, and deleting the imaginary part data in the rth row, to obtain an eighth imaginary part matrix; grouping the first M columns of the seventh real part matrix into a ninth real part matrix, and grouping the first M columns of the seventh imaginary part matrix into a ninth imaginary part matrix, where when N is even, M=N / 2+1, and when N is odd, M=(N+1) / 2; inputting the eighth real part matrix, the eighth imaginary part matrix, the ninth real part matrix and the ninth imaginary part matrix into the matrix operation unit, and performing complex matrix multiplication calculation by the matrix operation unit, to obtain a result matrix, where the first M columns of the result matrix are the output data of the M butterfly units in the target calculation stage.

[0027] In the scheme shown in the present application, when performing complex matrix multiplication calculation of the input data and the DFT matrix after the rotation factor calculation, the fifth real part matrix and the fifth imaginary part matrix corresponding to the input data, and the seventh real part matrix and the seventh imaginary part matrix corresponding to the DFT matrix can be further reduced in size in combination with the symmetry of the DFT matrix. In this way, the efficiency of the processor in performing DFT calculation can be further improved.

[0028] In a second aspect, a processor is provided, including a vector operation unit and a matrix operation unit, and the processor is configured to implement the method for performing FFT according to the first aspect and any one of the implementable manners of the first aspect, where the vector operation unit included in the processor is configured to perform vector operation included in the FFT calculation, and the matrix operation unit is configured to perform matrix operation included in the FFT calculation.

[0029] In a third aspect, a computing device is provided, including a memory and a processor according to the second aspect, and the memory stores at least one instruction, and the processor is configured to execute the at least one instruction to implement the method for performing FFT according to the first aspect and any one of the implementable manners of the first aspect.

[0030] In a fourth aspect, a computer readable storage medium is provided, which stores computer program codes. When the computer program codes are executed by a computer device, the computer device is caused to perform the method for performing FFT according to the first aspect and any possible implementation of the first aspect.

[0031] In a fifth aspect, a computer program product containing instructions is provided, which, when executed on a computer device, causes the computer device to perform the method for performing FFT according to the first aspect and any possible implementation of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a flowchart of performing 18-point FFT calculation according to an embodiment of the present application;

[0033] Figure 2 is a structural diagram of a butterfly unit according to an embodiment of the present application;

[0034] Figure 3 is a structural diagram of a computer device according to an embodiment of the present application;

[0035] Figure 4 is a structural diagram of a processor according to an embodiment of the present application;

[0036] Figure 5 is a flowchart of a method for performing FFT according to an embodiment of the present application;

[0037] Figure 6 is a structural diagram of a butterfly network according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0039] Discrete Fourier Transform (DFT) is a form of Fourier Transform that presents discrete in time domain data and frequency domain data, which is used to transform discrete time domain sampling data into discrete frequency domain sampling data. In terms of data form, the input data (discrete time domain sampling data) and output data (discrete frequency domain data) of DFT are complex number sequences of finite length, and the lengths of the two complex number sequences are equal.

[0040] Fast Fourier Transform (FFT) is a method for fast calculating DFT or inverse DFT, which has lower computational complexity than DFT.

[0041] The Cooley-Tukey algorithm is a commonly used FFT algorithm, which is based on the divide-and-conquer strategy, and can decompose the DFT of a complex sequence with length N into DFTs with lengths N1 and N2 and complex multiplications with rotation factors, where N=N1*N2.

[0042] Figure 1 is a flowchart for implementing an 18-point FFT calculation by Cooley-Tukey, which can be referred to as a butterfly network. As shown in Figure 1 The calculation process of the FFT calculation can be divided into multiple calculation stages. The number of calculation stages is equal to the number of bases into which the length of the input data is divided. The input data is a complex sequence, and the length of the input data is the length of the complex sequence. For an FFT calculation with an input data length of N, it can be referred to as an N-point FFT calculation. For example, for an N-point FFT calculation, N can be decomposed into N1, N2, …, Ni (N=N1*N2*…*Ni), and the calculation process of the N-point FFT can include i calculation stages. N1, N2, …, Ni can be referred to as a base. N1 is the base corresponding to the first calculation stage, N2 is the base corresponding to the second calculation stage, and Ni is the base corresponding to the i-th calculation stage.

[0043] In the FFT calculation, the input data of the first calculation stage is the input data corresponding to the execution of the FFT calculation. For other calculation stages after the first calculation stage, the input data of each calculation stage is the output data of the previous calculation stage, and the length of the input data of each calculation stage is the same. A calculation stage can be divided into at least one block, and a block can be divided into at least one butterfly unit. By performing butterfly calculation on each butterfly unit in the calculation stage, the output data of the calculation stage can be obtained. As shown in Figure 1 The 18-point FFT calculation can be divided into three calculation stages, the base corresponding to the first calculation stage is 3, including 6 butterfly units; the base corresponding to the second calculation stage is 3, including 6 butterfly units; and the base corresponding to the third calculation stage is 2, including 9 butterfly units. In addition, Figure 1The in_stride of the middle is an input stride of a target calculation stage, indicating a storage interval of input data of each butterfly unit in input data of a corresponding calculation stage. The out_stride is an output stride of the target calculation stage, indicating a storage interval of output data of each butterfly unit in output data of the corresponding calculation stage. The section_num is a quantity of sections included in the calculation stage.

[0044] The twiddle calculation of the butterfly unit can be divided into a twiddle factor calculation and a DFT calculation. In an example, the twiddle factor calculation can be a complex number multiplication calculation of input data of the butterfly unit and a twiddle factor, and the DFT calculation can be a complex matrix multiplication calculation of the rotated input data (the input data after the complex number multiplication calculation of the twiddle factor) and a DFT matrix corresponding to the butterfly unit. The DFT matrix corresponding to the butterfly unit is related to the structure of the butterfly unit, and the DFT matrix corresponding to each butterfly unit in each calculation stage is the same.

[0045] As shown in FIG. 1, Figure 2 Figure 2 The structures of a base-2 butterfly unit and a base-3 butterfly unit are respectively shown. The DFT matrix corresponding to the butterfly unit is a complex number matrix. In an example, the DFT calculation corresponding to the base-N butterfly unit can be represented as:

[0046]

[0047] wherein, is the rotated input data corresponding to the base-N butterfly unit, is the DFT matrix corresponding to the base-N butterfly unit, is the output data corresponding to the base-N butterfly unit. is the twiddle factor.

[0048] In the related art, the FFT calculation is generally implemented by a scalar operation unit and / or a vector operation unit, that is, the twiddle factor calculation and the DFT matrix calculation included in the FFT calculation are performed by the scalar operation unit and / or the vector operation unit, and the execution efficiency is low.

[0049] Embodiments of the present application provide a method for performing FFT calculation, which can implement the FFT calculation by combining the vector operation unit and the matrix operation unit, and improve the execution efficiency of the FFT calculation. Figure 3 is a structural schematic diagram of a computing device provided by an embodiment of the present application. As shown in FIG. 2, Figure 3 ​As shown, the computing device 300 can include a bus 302, a processor 304, a memory 306, and optionally a communication interface 308. The processor 304, the memory 306, and the communication interface 308 communicate via the bus 302. The computing device 300 can be a server or a terminal device. It should be understood that the number of processors and memories in the computing device 300 is not limited. The computing device 300 can be a device running a model, which can be a terminal or a server. When the computing device 300 is a terminal, the computing device 300 includes, but is not limited to, a desktop computer, a mobile phone, a notebook computer, a tablet computer, and the like. When the computing device 300 is a server, the computing device 300 can be a single server or a server cluster composed of multiple servers, and can be a physical machine or a virtual machine, a container, and the like virtualized by a virtual technology.

[0050] The bus 302 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 Although only one line is used to represent the bus in the figure, it does not mean that there is only one bus or only one type of bus. The bus 302 can include a path for transmitting information between various components (e.g., the memory 306, the processor 304, the communication interface 308) of the computing device 300.

[0051] The processor 304 can include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP), etc. The processor 304 can further include a vector operation unit and a matrix operation unit, etc. The vector operation unit can be a Scalable Vector Extension (SVE) and can be used to perform a rotation factor calculation included in the FFT calculation. The matrix operation unit can be a Scalable Matrix Unit (SME) and can be used to perform a DFT calculation included in the FFT calculation.

[0052] The memory 306 can include volatile memory, such as random access memory (RAM) including a cache area for the temporary storage of data. The memory 306 also can include non-volatile memory, such as read only memory (ROM), floppy, mechanical, solid state, or electrical medium for the non-transitory storage of data. Any of the foregoing memory can be considered a global memory.

[0053] The communication interface 308 enables communication among the computing device 300, other devices, or communication networks using, for example, but not limited to, a transceiver, a network interface card, a modem, or other types of interface modules.

[0054] Figure 4 is a schematic diagram of a processor structure provided by an embodiment of the present application. The processor can be the processor 304 in the computing device described above, as shown in Figure 3 The processor includes a vector operation unit and a matrix operation unit. The processor can execute the operation method provided by an embodiment of the present application. Figure 4 Figure 5 is a flowchart of a method for performing FFT provided by an embodiment of the present application. Referring to Figure 5 The method for performing FFT by the processor includes:

[0055] Step 501, the processor responds to an execution request of a Fast Fourier Transform (FFT) calculation of an application program.

[0056] The application program can be any application program involving FFT calculation, for example, a High Performance Computing (HPC) application, an Artificial Intelligence (AI) application, etc. The application program can send an execution request of FFT to the processor when FFT calculation is needed in the process of running. For example, the application program can be VASP (Vienna Ab-initio Simulation Package), when a wave function needs to be solved in VASP, a wave function solving request can be sent to the processor, the wave function solving request is the execution request of FFT. The wave function is a common function in the field of quantum mechanics, and the solution of the wave function can be obtained by performing FFT calculation on the input data of the wave function.

[0057] ​In an example, for the method of performing FFT provided in the present application, a skilled person can write a corresponding processing program as an FFT processing function and add it to a mathematical library, where the mathematical library can be stored in a computing device performing an application program and includes a large number of processing functions that can be used to implement various mathematical calculations involved in the application program. When FFT calculation is required in the application program, the processor can be sent an execution request for FFT, and then the processor can implement the following steps by calling the FFT processing function.

[0058] Step 502, decompose the FFT calculation into a plurality of calculation stages, wherein the plurality of calculation stages include at least one target calculation stage, and the target calculation stage includes a twiddle factor calculation and a discrete Fourier transform (DFT) calculation after the FFT calculation is split.

[0059] In an example, after receiving the execution request for the FFT calculation, the processor can obtain the length of the input data to be subjected to the FFT calculation, and decompose the FFT calculation into a plurality of calculation stages. For example, the processor can decompose the length of the input data according to the Cooley-Tukey algorithm to obtain each calculation stage for performing the FFT calculation on the input data and the base corresponding to each calculation stage. For example, if the number of data elements in the input data is 8, 8 can be decomposed into 2*2*2, and the process of performing FFT on the input data includes three calculation stages, and the base corresponding to each calculation stage is 2. For example, if the number of data elements in the input data is 27, 27 can be decomposed into 3*3*3, and the process of performing FFT on the input data includes three calculation stages, and the base corresponding to each calculation stage is 3.

[0060] In the plurality of calculation stages corresponding to the FFT calculation, each calculation stage includes a twiddle factor calculation and a DFT calculation, but since the twiddle factor in the first calculation stage is generally 1, the twiddle factor calculation of the first calculation stage can not be performed in practice. In the embodiments of the present application, the target calculation stage can refer to the other calculation stages after the first calculation stage. The DFT calculation of the target calculation stage refers to the DFT calculation in each butterfly unit in each section after the input data of the target calculation stage is split according to the base.

[0061] Step 503, sequentially perform the plurality of calculation stages, wherein when the target calculation stage is reached, the twiddle factor calculation is performed based on the vector operation unit, and the DFT calculation is performed based on the matrix operation unit.

[0062] After determining the plurality of calculation stages corresponding to the FFT calculation, the processor can sequentially execute the plurality of calculation stages. Wherein, when executing the first calculation stage, the matrix multiplication calculation of the input data of the FFT and the DFT matrix can be implemented based on the matrix operation unit. When executing the target calculation stage after the first calculation stage, the rotation factor calculation can be executed based on the vector operation unit, and the DFT calculation can be executed based on the matrix operation unit.

[0063] In an example, the rotation factor calculation includes the complex vector multiplication calculation of the input data of the target calculation stage and the corresponding rotation factor, and the DFT calculation includes the complex matrix multiplication calculation of the rotated input data of each butterfly unit in the target calculation stage and the DFT matrix.

[0064] For the rotation factor calculation executed based on the vector operation unit in step 503:

[0065] When executing the rotation factor calculation, the input data of the specified number of butterfly units can be respectively stored in the vector register, the rotation factor corresponding to the specified number of butterfly units can be stored in the vector register, and then based on the vector multiplication instruction, the complex vector multiplication calculation of the input data of the specified number of butterfly units and the corresponding rotation factor can be implemented in the vector operation unit.

[0066] The following is an example of a method for executing a rotation factor calculation by a vector operation unit provided by the present application:

[0067] Step A1, for the target calculation node, if the base of the target calculation stage is R, the input data of t butterfly units can be read in one section of the target calculation stage. The real part data in the input data of one butterfly unit read each time can be stored in R vector registers The imaginary part data in the input data can be stored in R vector registers Wherein, t = min(vscale, n_butterfly), vscale is the length of the input data that can be stored in the vector register, and n_butterfly is the number of butterfly units under each section in the layer.

[0068] Step A2, the rotation factor corresponding to the t butterfly units in step A1 is read respectively, wherein the real part data in the rotation factor corresponding to each butterfly unit can be respectively stored in R vector registers The imaginary part data in the rotation factor corresponding to each butterfly unit can be respectively stored in R vector registers

[0069] Step A3, the SVE multiplication instruction is used to calculate and the product result is stored to and the product result is stored to the result of the multiplication of is subtracted and the result is stored in the vector register the result of the multiplication of is added and the result is stored in the vector register . In the above steps, the data stored in the vector register is the real part data included in the result data of the calculation of the rotation factor corresponding to the t butterfly units, is the imaginary part data included in the result data of the calculation of the rotation factor corresponding to the t butterfly units, i∈[0, R-1].

[0070] The above steps A1-A3 can obtain the calculation of the rotation factor corresponding to the t butterfly units. Based on the same steps, the calculation of the rotation factor corresponding to other butterfly units in the target calculation stage can also be completed, which will not be described in detail in the embodiments of the present application.

[0071] In the process of performing the rotation factor calculation included in the target calculation stage, the obtained result data can be used as the input data of the DFT calculation in the target calculation stage, and the subsequent calculation is performed. Thus, the rotation factor calculation and the DFT calculation in the target calculation stage are performed in parallel, which can improve the efficiency of performing the FFT calculation.

[0072] In the embodiments of the present application, the complex multiplication calculation of the butterfly unit input data and the rotation factor can be converted into complex vector multiplication calculation and implemented through the vector operation unit. Thus, one complex vector multiplication calculation can implement the complex multiplication calculation of the input data and multiple rotation factors, which can improve the efficiency of the rotation factor calculation in the FFT calculation.

[0073] For the DFT calculation based on the matrix operation unit in step 503:

[0074] In the process of performing the DFT calculation, the real part data and the imaginary part data in the input data of each butterfly unit can be obtained, the real part data and the imaginary part data of each column element in the DFT matrix can be obtained, and the complex matrix multiplication calculation can be implemented based on the real part data and the imaginary part data corresponding to each butterfly unit, the real part data and the imaginary part data corresponding to the DFT matrix, and the matrix operation unit.

[0075] In the DFT calculation, the input data of each butterfly unit refers to the rotated input data. In the embodiment of the present application, the real part data and the imaginary part data of the rotated input data are stored in the vector registers respectively. Therefore, the real part data and the imaginary part data of the input data are calculated separately with the DFT matrix. In this way, the continuous reading of the real part data and the imaginary part data can be realized, and the calculation efficiency of the DFT is improved.

[0076] In an example, the complex matrix multiplication calculation of the input data of each butterfly unit and the DFT matrix can include: forming the real part data in the input data of each butterfly unit into a first real part matrix by rows, and forming the imaginary part data in the input data of each butterfly unit into a first imaginary part matrix by rows. Forming the real part data included in each column element of the DFT matrix into a second real part matrix by columns, and forming the imaginary part data included in each column element of the DFT matrix into a second imaginary part matrix by columns. Based on the first real part matrix, the first imaginary part matrix, the second real part matrix, the second imaginary part matrix and the matrix operation unit, the complex matrix multiplication calculation is realized. In the first real part matrix, each row element can be the real part data in the rotated input data corresponding to one butterfly unit. In the first imaginary part matrix, each row element can be the imaginary part data in the rotated input data corresponding to one butterfly unit.

[0077] The following provides an example of a complex matrix multiplication calculation method performed by the matrix operation unit of the present application:

[0078] Step B1, initialize two matrix registers ZA r , ZA i .

[0079] Step B2, load the real part data of each column in the DFT matrix into r vector registers load the imaginary part data of each column into r vector registers wherein, store each column element of the second real part matrix respectively, wherein, store each column element of the second imaginary part matrix respectively.

[0080] Step B3, load the real part data included in the input data of the n butterfly units in the target calculation stage into n vector registers by rows load the imaginary part data included in the input data of the n butterfly units into n vector registers by rows wherein, store each row element of the first real part matrix respectively, wherein, store each row element of the first imaginary part matrix respectively.

[0081] Step B4, use the outer product accumulation instruction to realize with and accumulate the outer product result in ZA r , implement with and accumulate the outer product result in ZA i , where k∈[0, r-1].

[0082] Step B5, implement Z r minus with and accumulate the outer product result in ZA r , implement with and accumulate the outer product result in ZA i .

[0083] After executing the above steps B4-B5, the calculation result of the complex matrix multiplication calculation performed by the matrix operation unit can be obtained, wherein the calculation result is composed of a real part matrix and an imaginary part matrix, the real part matrix is stored in ZA r , and the imaginary part matrix is stored in ZA i . In this way, by using the outer product accumulation / addition / subtraction instructions and the two matrix registers, the real part data and the imaginary part data are calculated respectively, which can reduce the additional SVE instruction overhead and improve the calculation efficiency.

[0084] In the DFT calculation based on the matrix operation unit in the embodiments of the present application, the DFT matrix can be decomposed into two matrices composed of real part data and imaginary part data, and then the complex matrix multiplication calculation is performed with the two matrices composed of the real part data and the imaginary part data in the corresponding input data. In this way, the real part data and the imaginary part data are calculated respectively to form matrices, which can avoid non-continuous access to the real part data and the imaginary part data, improve the efficiency of constructing the matrix, reduce the size of the matrix, reduce the storage space occupied by the matrix, and improve the calculation efficiency of the matrix.

[0085] Step 504, after completing the execution of the plurality of calculation stages, determining the execution result of the FFT calculation based on the execution result of the last calculation stage, and returning the execution result to the application program.

[0086] After completing the execution of the plurality of calculation stages in the FFT calculation, the output data of the last calculation stage can be used as the execution result of the FFT calculation, and the execution result of the FFT is returned to the application program.

[0087] In the embodiments of the present application, the complex multiplication of the rotation factor is implemented by the vector operation unit, and the complex matrix multiplication of the DFT matrix is implemented by the matrix operation unit, so that the efficiency of performing the FFT calculation can be improved.

[0088] The method for performing the FFT provided in the present application can be combined with Figure 1 The method for performing the FFT provided in the present application can be combined with the implementation of the butterfly network shown in the figure, or the implementation of other self-ordered or non-self-ordered butterfly network. When the method for performing the FFT provided in the present application is combined with the implementation of the self-ordered butterfly network, the process of ordering the input data of the FFT calculation can be avoided, and the efficiency of the processor performing the FFT calculation can be further improved.

[0089] The embodiments of the present application provide a method for performing the DFT calculation based on the matrix operation unit, in which the symmetry of the DFT matrix can be combined to reduce the size of the matrix for performing the DFT calculation, so that the efficiency of the matrix operation unit performing the DFT calculation can be further improved.

[0090] The symmetry of the DFT matrix includes: when the number N of columns in the DFT matrix is even, the xth column and the yth column in the DFT matrix are conjugate symmetric, x∈[2, N / 2], y=N+2-x. When the number N of columns in the DFT matrix is odd, the xth column and the yth column in the DFT matrix are conjugate symmetric, x∈[2, (N+1) / 2], y=N+2-x. For example, when the size of the DFT matrix W is 8x8, the 2nd column element and the 8th column element in the DFT matrix are conjugate symmetric, the 3rd column element and the 7th column element are conjugate symmetric, and the 4th column element and the 6th column element are conjugate symmetric. In this way, after the real part data in the DFT matrix is grouped into a second real part matrix and the imaginary part data in the DFT matrix is grouped into a second imaginary part matrix, the elements of the xth column and the yth column in the second real part matrix are equal, and the elements of the xth column and the yth column in the second imaginary part matrix are opposite.

[0091] When two matrices perform the matrix outer product, if one of the matrices has two columns with equal elements or two columns with opposite elements, the following optimization can be performed:

[0092]

[0093] As shown in the above formula, when the outer product of two matrices is calculated, if there are two columns with equal elements in one of the matrices, the two columns with equal elements can be combined into one column to obtain an updated matrix. For the other matrix, the elements of the corresponding two rows in the other matrix can be added and one row of elements can be deleted to obtain another updated matrix. The outer product result of the two updated matrices is the same as that of the two matrices before updating. Since the two updated matrices are reduced in size relative to the two matrices before updating, the efficiency of the outer product calculation can be improved by using the two updated matrices to perform the outer product calculation.

[0094]

[0095] As shown in the above formula, when the outer product of two matrices is calculated, if there are two columns with opposite elements in one of the matrices, the two columns with equal elements can be combined into one column to obtain an updated matrix. For the other matrix, the elements of the corresponding two rows in the other matrix can be subtracted and one row of elements can be deleted to obtain another updated matrix. The outer product result of the two updated matrices is the same as that of the two matrices before updating. Since the two updated matrices are reduced in size relative to the two matrices before updating, the efficiency of the outer product calculation can be improved by using the two updated matrices to perform the outer product calculation.

[0096] Correspondingly, in the embodiments of the present application, the first real part matrix, the first imaginary part matrix, the second real part matrix and the second imaginary part matrix for outer product calculation are optimized by using the symmetry of the DFT matrix and the optimization method shown in the above two formulas, so that the efficiency of the outer product calculation of the first real part matrix, the first imaginary part matrix, the second real part matrix and the second imaginary part matrix can be improved. The DFT calculation based on the matrix operation unit in step 503 can further include:

[0097] In step C1, the yth row of the first real part matrix is added to the xth row, and the real part data of the yth row is deleted to obtain a third real part matrix, where y=N+2-x, x∈[2, N / 2] when N is even, and x∈[2, (N+1) / 2] when N is odd.

[0098] In step C2, the xth row of the first imaginary part matrix is subtracted from the yth row, and the imaginary part data of the yth row is deleted to obtain a third imaginary part matrix.

[0099] In step C3, the first M columns of the second real part matrix are combined to form a fourth real part matrix, where M=N / 2+1 when N is even, and M=(N+1) / 2 when N is odd.

[0100] In step C4, the first M columns of the second imaginary part matrix are combined to form a fourth imaginary part matrix.

[0101] After obtaining the third real matrix and the third imaginary matrix corresponding to the input data of the DFT calculation, and the fourth real matrix and the fourth imaginary matrix corresponding to the DFT matrix, the complex matrix multiplication calculation of the third real matrix, the third imaginary matrix, the fourth real matrix and the fourth imaginary matrix can be implemented based on the matrix operation unit.

[0102] The following is an exemplary method of complex matrix multiplication calculation implemented by the matrix operation unit after combining the symmetry of the DFT matrix (the size of the DFT matrix is 8x8) provided by the embodiments of the present application:

[0103] Step D1, initialize two matrix registers ZA and ZB with all 0s r , ZA i .

[0104] Step D2, load the real part data of the first 5 columns in the DFT matrix to r vector registers Load the imaginary part data of the first 5 columns in the DFT matrix to r vector registers wherein, each column element in the fourth real matrix is stored in each column element in the fourth imaginary matrix is stored in

[0105] Step D3, load the real part data included in the input data of the 8 butterfly units of the DFT calculation to be performed to 8 vector registers by row Load the imaginary part data included in the input data of the 8 butterfly units to 8 vector registers by row wherein, each row element of the first real matrix is stored in each row element of the first imaginary matrix is stored in

[0106] Step D4, perform addition operation on and and and by SVE instruction, and store the result to and and and perform subtraction operation, and store the result to wherein, each row element of the third real matrix is stored in each row element of the third imaginary matrix is stored in ​

[0107] Step D5, using the outer product accumulation instruction, implements the outer product of and accumulates the outer product result in ZA r , implements the outer product of and accumulates the outer product result in ZA i .

[0108] Step D6, ZA r is refreshed again by subtracting the result of the outer product of and , and ZA r is refreshed again by adding the result of the outer product of and to ZA i . i

[0109] After the above steps D5-D6 are executed, the calculation result of the complex matrix multiplication calculation performed by the matrix operation unit can be obtained.

[0110] In the embodiments of the present application, the DFT calculation is optimized according to the symmetry of the DFT matrix. The above optimization method replaces the SME outer product accumulation / subtraction instruction with a lower latency SVE addition / subtraction instruction, reduces the execution overhead of the instruction, and at the same time, due to the symmetry, the DFT matrix only needs to store part of the elements, reducing the storage overhead and memory access overhead. Further, by interspersing SVE calculation instructions in SME calculation, the chip Pipeline can be better utilized, thereby improving the overall calculation efficiency.

[0111] Figure 6 is a structural diagram of a new type of butterfly network provided by the embodiments of the present application. In the FFT calculation, the input data at the same position in different sections in the target calculation stage correspond to the same rotation factor, and in the butterfly network shown in Figure 6 , the input data corresponding to the same rotation factor can be arranged to adjacent positions in the input data of the calculation stage.

[0112] The construction method of the butterfly network shown in Figure 6 may be as follows:

[0113] For each calculation stage, the input data of the calculation stage is read in batches according to the specified reading step before calculation, and the input data read each time is stored separately in a specified number of vector registers. The specified number and the value of the specified reading step are the same, the specified reading step is equal to the ratio of the length of the input data of the FFT calculation to the specified number, and the specified number is equal to the product of the bases corresponding to the calculation stage and the other calculated calculation stages, respectively. ​

[0114] The specified read step size for each calculation stage is... Figure 6 The butterfly network shown illustrates the in_stride for each computational stage. The in_stride1 of the first computational stage equals N / R0, where N is the length of the input data for the first computational stage, and R0 is the basis of the first computational stage. The in_stridei of the i-th computational stage after the first computational stage equals... R i Let be the basis corresponding to the i-th computation stage.

[0115] like Figure 6 As shown, in Figure 6 In the second computational stage of the butterfly network, with an in_stride of 2 (meaning a read step size of 2), two input data points can be read at a time, and then stored in two separate vector registers. For example, 0, 1; 2, 3; 4, 5 can be read consecutively; then 0, 2, 4 can be stored in vector register A, and 1, 3, 5 in vector register B. This ensures that the input data in vector registers A and B have the same rotation factor.

[0116] For each computation stage, after the computation is completed, the output data of each butterfly unit is acquired sequentially. The output data of the first butterfly unit is acquired and stored in memory according to the specified storage interval. The output data of other butterfly units acquired after the first butterfly unit are stored in memory after the position where the output data of the butterfly unit was last stored. The specified storage interval is equal to the ratio of the length of the input data of the FFT computation to the basis of the computation stage.

[0117] The specified storage interval corresponding to each computation stage is . Figure 6 The butterfly network shown represents the out_stride for each computation stage. The out_stride i for the i-th computation stage is equal to N / R. i , where R i Let be the basis corresponding to the i-th computation stage.

[0118] like Figure 6 As shown, in Figure 6The second calculation stage of the butterfly network, out_stride is 6, that is, the specified storage interval is 6, when reading the input data of the calculation stage, the input data is stored according to the specified storage interval. For example, for the output 0, 6, 12 of the first butterfly unit, 0 can be stored in the starting position of the output data in the memory of the second calculation stage, then 6 is stored after the position of 0 by offsetting 6 storage positions, and then 12 is stored after the position of 6 by offsetting 6 storage positions. For the output 1, 7, 13 of the second butterfly unit, 1 can be stored after the position of 0 by offsetting 1 storage position, 7 can be stored after the position of 6 by offsetting 1 storage position, and 13 can be stored after the position of 12 by offsetting 1 storage position.

[0119] From the first calculation stage of the FFT calculation, the input data of the calculation stage is read according to the specified reading step provided in the embodiments of the present application, and the output data of the calculation stage is stored according to the specified storage interval provided in the embodiments of the present application, so that the calculation process corresponding to the butterfly network as shown in Figure 6 Figure 6 In the butterfly network as shown in Figure 6 The butterfly network as shown in FIG. 18 is the corresponding butterfly network of the 18-point FFT calculation, and includes three calculation stages in total. The first calculation stage corresponds to a base of 3, an in_stride of 6, an out_stride of 6, a section number of 6, and each section includes one butterfly unit. The second calculation stage corresponds to a base of 3, an in_stride of 2, an out_stride of 6, a section number of 2, and each section includes three butterfly units. The third calculation stage corresponds to a base of 2, an in_stride of 1, an out_stride of 9, a section number of 1, and the section includes nine butterfly units.

[0120] In an example, the butterfly network as shown in Figure 6 In an example, the butterfly network as shown in

[0121] In this way, the input data stored in each vector register corresponds to the same rotation factor. Therefore, the rotation factor corresponding to the input data stored in the vector register can be loaded into the vector register, and then the rotation factor calculation can be performed on the rotation factor stored in the vector register and the input data stored in each vector register.​

[0122] Thus, the FFT computation is performed by the butterfly network shown in FIG. 4, the input data of the computation stage can be continuously read, and the non-continuous access of the input data by the butterfly units is avoided. On the other hand, the number of reading the twiddle factors is reduced, and the reading of the twiddle factors corresponding to each butterfly unit is avoided. As can be seen, the FFT computation performed by the butterfly network shown in FIG. 4 can further improve the efficiency of the computation of the twiddle factors. Figure 1 Figure 6 Thus, the FFT computation is performed by the butterfly network shown in FIG. 4, the input data of the computation stage can be continuously read, and the non-continuous access of the input data by the butterfly units is avoided. On the other hand, the number of reading the twiddle factors is reduced, and the reading of the twiddle factors corresponding to each butterfly unit is avoided. As can be seen, the FFT computation performed by the butterfly network shown in FIG. 4 can further improve the efficiency of the computation of the twiddle factors. Figure 6

[0123] In addition, the reading, storing and computation of the input data and the twiddle factors can be specifically divided into the reading, storing and computation of the real part data and the imaginary part data. The specific reading, storing and computation of the real part data and the imaginary part data are similar to the steps of the steps A1-A3, and will not be described in detail herein.

[0124] Based on the butterfly network shown in FIG. 4, the computation of the twiddle factors included in the target computation stage can be the complex vector multiplication computation of the twiddle factors corresponding to the input data of the target computation stage and the DFT matrix, and the DFT computation can be the complex matrix multiplication computation of the input data of the target computation stage and the DFT matrix. Figure 6 When the number of sections included in the target computation stage is large, the number of butterfly units corresponding to the same twiddle factor in the target computation stage is large. Thus, for the plurality of butterfly units corresponding to the same twiddle factor, the input data of the plurality of butterfly units need to be respectively multiplied by the same twiddle factor, and then multiplied by the same DFT matrix. Therefore, in the embodiments of the present application, for the target computation stage including a large number of sections (for example, when the number of sections is greater than the length MVL supported by the matrix operation unit SME, or is greater than the number threshold set by the skilled person), the twiddle factor can be multiplied by the DFT matrix first to complete the computation of the twiddle factor, and then the input data of the butterfly units can be multiplied by the DFT matrix after the computation of the twiddle factor. In this way, the multiplication operation of the twiddle factor and the DFT matrix once can replace the multiplication operation of the twiddle factor and the input data of the plurality of butterfly units, and thus the efficiency of the FFT computation can be improved. Based on the butterfly network shown in FIG. 4, the processing of the computation of the twiddle factors and the DFT computation can be as follows:

[0125] Figure 6

[0126] ​​​​Step E1, the real part data in the input data of each butterfly unit is grouped into a fifth real part matrix by row, and the imaginary part data in the input data of each butterfly unit is grouped into a fifth imaginary part matrix by row.

[0127] Step E2, the real part data included in each column element of the DFT matrix is grouped into a sixth real part matrix by column, and the imaginary part data included in each column element of the DFT matrix is grouped into a sixth imaginary part matrix by column.

[0128] For the processing of steps E1-E2, reference can be made to the processing of step B2 described above, which will not be described again here.

[0129] Step E3, the real part data of the rotation factor corresponding to the s-th row in the fifth real part matrix is multiplied to the s-th column of the sixth real part matrix to obtain a seventh real part matrix. Wherein, s∈[1, N], N is the number of columns in the DFT matrix.

[0130] Step E4, the imaginary part data of the rotation factor corresponding to the s-th row in the fifth imaginary part matrix is multiplied to the s-th column of the sixth imaginary part matrix to obtain a seventh imaginary part matrix.

[0131] Wherein, steps E3-E4 are rotation factor calculation, the specific calculation process can be realized by a vector operation unit, which will not be described in detail in this application. The seventh real part matrix and the seventh imaginary part matrix are the DFT matrix after the rotation factor calculation.

[0132] Due to the change of the structure of the butterfly network, the rotation factor corresponding to each input data in each calculation stage will change, wherein for each calculation stage, the updated rotation factor corresponding to the input data can be calculated by the following formula:

[0133]

[0134] Wherein, N is the length of the input data of the FFT calculation, N s _ i is the number of butterfly units included in each section in the calculation stage. i represents the order of the calculation stage in the FFT calculation. j represents the position of the input data in the corresponding section in the butterfly unit, and k represents the position of the input data in the corresponding butterfly unit.

[0135] In addition, for the updated rotation factor described above, it can be pre-calculated and stored in the memory of the computing device, and when the rotation factor calculation is needed, the processor can directly obtain the updated rotation factor from the memory, thereby improving the calculation efficiency of the rotation factor.

[0136] Step E5, based on the fifth real part matrix, the fifth imaginary part matrix, the seventh real part matrix, the seventh imaginary part matrix and the matrix operation unit, the complex matrix multiplication calculation is realized.

[0137] The processing procedure of step E5 is the implementation procedure of DFT calculation. The specific processing procedure of step E5 can refer to the step of implementing DFT calculation by the matrix operation unit shown in step 503, which will not be repeated here.

[0138] The embodiment of the present application also provides a method for performing DFT calculation based on a matrix operation unit. In the method, the above-mentioned Figure 6 The symmetry of DFT calculation and DFT matrix is combined, the size of the matrix for DFT calculation is reduced, so as to improve the efficiency of the matrix operation unit for performing DFT calculation. The processing of step E5 can include the following steps:

[0139] In step G1, the first M columns of the seventh real part matrix are grouped into a ninth real part matrix, and the first M columns of the seventh imaginary part matrix are grouped into a ninth imaginary part matrix. When N is even, M=N / 2+1; when N is odd, M=(N+1) / 2.

[0140] The seventh real part matrix is a matrix composed of real part data after the DFT matrix is multiplied by the rotation factor, and the seventh imaginary part matrix is a matrix composed of imaginary part data after the DFT matrix is multiplied by the rotation factor.

[0141] In step G2, the rth row of the fifth real part matrix is added to the sth row, and the real part data of the rth row is deleted to obtain an eighth real part matrix. The sth row of the fifth imaginary part matrix is subtracted from the rth row, and the imaginary part data of the rth row is deleted to obtain an eighth imaginary part matrix. Wherein, s∈[2, N / 2], and when N is odd, s∈[2, (N+1) / 2].

[0142] Since the first M columns of the seventh real part matrix or the seventh imaginary part matrix have been multiplied by the rotation factor corresponding to the input data of the first M rows, the input data of the first M rows includes the input data of the sth row. Thus, when the symmetry of the DFT matrix is used to perform DFT calculation, the input data of the rth row in the matrix composed of input data will combine the input data of the sth row to perform calculation with the rotation factor corresponding to the sth row. Therefore, before the fifth real part matrix and the fifth imaginary part matrix are composed, the input data of the rth row can be compensated by the rotation factor, so that after the compensated input data of the rth row is calculated with the rotation factor corresponding to the sth row, the effect of calculating the input data of the rth row with the rotation factor of the rth row can be achieved.

[0143] For example, the input data of the rth row can be multiplied by the compensation rotation factor to obtain updated input data of the rth row, wherein the compensation rotation factor is calculated from the rotation factors corresponding to the input data of the rth row and the input data of the sth row in the input data of each butterfly unit. The specific calculation can be as follows:

[0144] For example, the rotation factors corresponding to the input data of the s-th row are T' i,a = [W i,0,a W i,1,a …W i,t-1,a The rotation factors corresponding to the input data of the r-th row are T' i,b = [W i,0,b W i,1,b …W i,t-1,b Since T' i,a is the common rotation factor of the input data of the s-th row and the input data of the r-th row, the rotation factor compensation is needed for the input data of the r-th row to eliminate the influence of the rotation factor corresponding to the input data of the s-th row on the input data of the r-th row. Before the DFT calculation, the imaginary part of T' i,a is negated to obtain a negated result. Then, T' i,b is divided by the negated result to obtain a new rotation factor (i.e., the compensated rotation factor) T" i,b (When T" i,b is actually calculated, it can be directly implemented by multiplying T' i,b element by element with T' i,a ).

[0145] In step G3, the eighth real matrix, the eighth imaginary matrix, the ninth real matrix and the ninth imaginary matrix are input into the matrix operation unit, and the complex matrix multiplication is calculated by the matrix operation unit to obtain a result matrix, wherein the first M columns of the result matrix are the output data of the M butterfly units in the target calculation stage.

[0146] The specific implementation process of step G3 can refer to the steps of implementing the DFT calculation by the matrix operation unit shown in step 503, which will not be described here.

[0147] The embodiments of the present application further provide a computer program product containing instructions. The computer program product can be software or a program product containing instructions, which can run on a computing device or be stored in any available medium. When the computer program product runs on at least one computing device, the at least one computing device is caused to execute the method for performing FFT provided by the embodiments of the present application.

[0148] The embodiments of the present application further provide a computer readable storage medium. The computer readable storage medium can be any available medium or data storage device that can be accessed by a computing device and includes one or more available media or data storage devices. The available medium can be a magnetic medium, (e.g., a floppy diskette, a hard disk drive, a magnetic tape), an optical medium, (e.g., a DVD), or a semiconductor medium, (e.g., a solid state hard drive), etc. The computer readable storage medium includes instructions that instruct the computing device to perform the method of performing FFT by the embodiments of the present application.

[0149] The terms "first", "second", and the like in the present application are used to distinguish between similar or identical items or elements having substantially the same function, and it should be understood that there is no logical or chronological dependency between "first" and "second", and the number and execution order are not limited. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first real part matrix can be referred to as a second real part matrix, and similarly, a second real part matrix can be referred to as a first real part matrix. The first real part matrix and the second real part matrix can both be collectively referred to as a real part matrix, and in some cases, can be separate and distinct real part matrices.

[0150] The term "at least one" in the present application means one or more, and the term "a plurality" in the present application means two or more.

[0151] The above description is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any skilled person in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for performing an FFT, characterized in that, The method includes: The processor responds to an application's request to perform a Fast Fourier Transform (FFT) calculation, and the processor includes a vector operation unit and a matrix operation unit. The processor decomposes the FFT calculation into multiple calculation stages, wherein the multiple calculation stages include at least one target calculation stage, the target calculation stage includes twitch factor calculation and Discrete Fourier Transform (DFT) calculation, wherein the DFT calculation is obtained by splitting the FFT calculation; The processor sequentially executes the plurality of computation stages. When executing the target computation stage, the processor performs the rotation factor calculation based on the vector operation unit to obtain a computation result. The real and imaginary parts of the computation result are stored in different vector registers. The processor also performs the DFT calculation based on the matrix operation unit. In the case where the rotation factor calculation includes complex multiplication of the input data from the target computation stage with the corresponding rotation factor, the DFT calculation includes complex matrix multiplication of a first real matrix, a first imaginary matrix, a second real matrix, and a second imaginary matrix. The first real matrix includes the real part of the computation result, the first imaginary matrix includes the imaginary part of the computation result, the second real matrix includes the real part of the DFT matrix, and the second imaginary matrix includes the imaginary part of the DFT matrix. The second real matrix and the second imaginary matrix are stored in different vector registers. After completing the execution of the multiple calculation stages, the processor determines the execution result of the FFT calculation based on the execution result of the last calculation stage, and returns the execution result to the application.

2. The method according to claim 1, characterized in that, The calculation of the rotation factor based on the vector operation unit includes: The vector operation unit performs complex multiplication of the input data of the target calculation stage with the corresponding rotation factor to obtain the calculation result, which includes the input data of each butterfly unit in the target calculation stage.

3. The method according to claim 2, characterized in that, The DFT calculation includes complex matrix multiplication of the input data of each butterfly unit in the target calculation stage with the DFT matrix. The execution of the DFT calculation based on the matrix operation unit includes: Obtain the real and imaginary data from the input data of each butterfly unit; Obtain the real and imaginary parts of each column element in the DFT matrix; The complex matrix multiplication calculation is realized based on the real and imaginary data corresponding to each butterfly unit, the real and imaginary data corresponding to the DFT matrix, and the matrix operation unit.

4. The method according to claim 3, characterized in that, The complex matrix multiplication calculation is implemented based on the real and imaginary data corresponding to each butterfly unit, the real and imaginary data corresponding to the DFT matrix, and the matrix operation unit, including: The real part data in the input data of each butterfly unit are arranged row by row to form the first real part matrix; The imaginary data in the input data of each butterfly unit are arranged in rows to form a first imaginary matrix; The real part data included in each column of the DFT matrix are arranged column by column to form a second real part matrix; The imaginary data included in each column of the DFT matrix are arranged column by column to form a second imaginary matrix; The complex matrix multiplication calculation is implemented based on the first real part matrix, the first imaginary part matrix, the second real part matrix, the second imaginary part matrix, and the matrix operation unit.

5. The method according to claim 4, characterized in that, The DFT matrix has N columns. The complex matrix multiplication calculation based on the first real part matrix, the first imaginary part matrix, the second real part matrix, the second imaginary part matrix, and the matrix operation unit includes: Add the y-th row of the first real part matrix to the x-th row, and delete the real part data of the y-th row to obtain the third real part matrix, where y = N+2-x, x∈[2,N / 2] when N is even, and x∈[2,(N+1) / 2] when N is odd; Subtract the y-th row from the x-th row of the first imaginary matrix, and delete the imaginary data in the y-th row to obtain the third imaginary matrix; The first M columns of the second real part matrix are used to form the fourth real part matrix, where M = N / 2 + 1 when N is even and M = (N+1) / 2 when N is odd. The first M columns of the second imaginary matrix are used to form the fourth imaginary matrix; The third real part matrix, the third imaginary part matrix, the fourth real part matrix, and the fourth imaginary part matrix are input to the matrix operation unit, and the matrix operation unit performs the complex matrix multiplication calculation.

6. The method according to claim 1, characterized in that, The calculation result of each calculation stage in the FFT calculation consists of the output data of the butterfly unit included in the calculation stage, and the method further includes: For each computation stage, before computation, the input data of the computation stage is read in batches according to a specified read step size. The input data read each time is stored separately in a specified number of vector registers. The specified number is the same as the value of the specified read step size. The specified read step size is equal to the ratio of the length of the input data of the FFT computation to a specified value. The specified value is equal to the product of the basis corresponding to the computation stage and the basis of other computation stages that have been computed. For each computation stage, after the computation is completed, the output data of each butterfly unit is sequentially acquired. The output data of the first butterfly unit is acquired and stored in memory according to a specified storage interval. The output data of other butterfly units acquired after the first butterfly unit are stored in memory after the position where the output data of the butterfly unit was last stored. The specified storage interval is equal to the ratio of the length of the input data of the FFT computation to the basis of the computation stage.

7. The method according to claim 6, characterized in that, When the rotation factor calculation includes the calculation of complex vector multiplication of the rotation factor corresponding to the input data of the target calculation stage with the DFT matrix, the DFT calculation includes the calculation of complex matrix multiplication of the input data of the target calculation stage with the DFT matrix.

8. The method according to claim 7, characterized in that, The calculation of the rotation factor based on the vector operation unit includes: The real part data in the input data of each butterfly unit is arranged in rows to form a fifth real part matrix, and the imaginary part data in the input data of each butterfly unit is arranged in rows to form a fifth imaginary part matrix. The real part data included in each column of the DFT matrix are arranged into a sixth real part matrix, and the imaginary part data included in each column of the DFT matrix are arranged into a sixth imaginary part matrix. The vector operation unit multiplies the real part data of the rotation factor corresponding to the s-th row of the fifth real part matrix into the s-th column of the sixth real part matrix to obtain the seventh real part matrix. The imaginary part data of the rotation factor corresponding to the s-th row of the fifth imaginary part matrix is ​​multiplied into the s-th column of the sixth imaginary part matrix to obtain the seventh imaginary part matrix. Here, s∈[1,N], and N is the number of columns in the DFT matrix. The execution of the DFT calculation based on the matrix operation unit includes: The complex matrix multiplication calculation is implemented based on the fifth real part matrix, the fifth imaginary part matrix, the seventh real part matrix, the seventh imaginary part matrix, and the matrix operation unit.

9. The method according to claim 8, characterized in that, When N is even, s∈[2, N / 2], and when N is odd, s∈[2, (N+1) / 2]; Before arranging the real part data from the input data of each butterfly unit into a fifth real part matrix row by row, the following steps are included: The input data of the r-th row in the input data of each butterfly unit is multiplied by a complex number with the compensation rotation factor to obtain the updated input data of the r-th row. The compensation rotation factor is calculated from the rotation factors corresponding to the input data of the r-th row and the input data of the s-th row in the input data of each butterfly unit, respectively, where r = N + 2 - s. The complex matrix multiplication calculation based on the fifth real part matrix, the fifth imaginary part matrix, the seventh real part matrix, the seventh imaginary part matrix, and the matrix operation unit includes: Add the r-th row of the fifth real part matrix to the s-th row and delete the real part data of the r-th row to obtain the eighth real part matrix. Subtract the r-th row from the s-th row of the fifth imaginary part matrix and delete the imaginary part data of the r-th row to obtain the eighth imaginary part matrix. The first M columns of the seventh real part matrix are used to form the ninth real part matrix, and the first M columns of the seventh imaginary part matrix are used to form the ninth imaginary part matrix. When N is even, M = N / 2 + 1, and when N is odd, M = (N + 1) / 2. The eighth real part matrix, the eighth imaginary part matrix, the ninth real part matrix, and the ninth imaginary part matrix are input to the matrix operation unit, which performs the complex matrix multiplication calculation to obtain the result matrix. The first M columns of the result matrix are the output data of the M butterfly units in the target calculation stage.

10. A processor, characterized in that, The processor includes a vector operation unit and a matrix operation unit, and the processor is used to execute the method of performing FFT as described in any one of claims 1 to 9 above.

11. A computing device, characterized in that, The computing device includes a memory and a processor as described in claim 10, the memory storing at least one instruction, and the processor executing the at least one instruction to implement the method of performing an FFT as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program code that, when executed by a computer device, causes the computer device to perform the method for performing an FFT as described in any one of claims 1 to 9.

13. A computer program product containing instructions, characterized in that, When the computer program product is run on a computer device, the computer device performs the method of performing FFT as described in any one of claims 1 to 9.

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