Offset calibration method, OLDI interface testing method and device

Abstract

The present invention provides an offset calibration method, an OLDI interface testing method, and an apparatus. These methods relate to the technical field of data transmission. A specific implementation scheme is as follows: a first data stream is input into a first register and a second register of a control chip in sequence to obtain a target processing signal output by the first register or the second register; the first data stream is calibrated based on a target instruction in the target processing signal and then input into a corresponding data channel in the OLDI interface; wherein the target instruction is determined based on a display result including calibration information output by a display after the Lth round of data transmission is completed. The disclosed embodiment, by calibrating the offset between multiple data channels in the interface, can effectively eliminate data transmission errors caused by the offset, thereby helping to improve the accuracy of data transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to an offset calibration method, and an OLDI interface testing method and device. Background Art

[0002] In data transmission, the Open LVDS Display Interface (OLDI) is an interface used to connect controllers to liquid crystal displays (LCDs). With the growing demand for high-resolution displays, the transmission speed of the OLDI interface is also increasing. However, various anomalies can be encountered during testing, such as skew between several data channels within the interface. Therefore, calibrating the skew between multiple data channels within the interface is crucial. Summary of the Invention

[0003] The present disclosure provides an offset calibration method, and an OLDI interface testing method and device.

[0004] According to a first aspect of the present disclosure, there is provided an offset calibration method for calibrating offsets between multiple data channels in an OLDI interface, where the OLDI interface is used to connect a control chip and a display. The method comprises:

[0005] Inputting the first data stream into the first register and the second register of the control chip in sequence to obtain a target processing signal output by the first register or the second register;

[0006] The first data stream is calibrated based on the target instruction in the target processing signal and then input into the corresponding data channel in the OLDI interface; wherein the target instruction is determined based on the display result including the calibration information output by the display after the Lth round of data transmission is completed.

[0007] According to a second aspect of the present disclosure, a method for testing an OLDI interface is provided, the method comprising:

[0008] Obtaining data to be transmitted corresponding to the first data stream of the L+1th round; the first data stream is obtained according to the method of the first aspect;

[0009] The data to be transmitted is transmitted from the control chip to the display through the OLDI interface to test the functions of other OLDI interfaces except the OLDI interface offset.

[0010] According to a third aspect of the present disclosure, an offset calibration device is provided for calibrating offsets between multiple data channels in an OLDI interface, where the OLDI interface is used to connect a control chip and a display. The device includes:

[0011] A first acquisition module is used to input the first data stream into the first register and the second register of the control chip in sequence, and obtain a target processing signal output by the first register or the second register;

[0012] A calibration module is configured to calibrate the first data stream based on a target instruction in a target processing signal and then input the calibrated data stream into a corresponding data channel in the OLDI interface; wherein the target instruction is determined based on a display result including calibration information output by the display after the Lth round of data transmission is completed.

[0013] According to a fourth aspect of the present disclosure, there is provided an offset calibration device, the device comprising:

[0014] A third acquisition module acquires the data to be transmitted corresponding to the first data stream of the L+1th round; the first data stream is obtained according to the method described in the first aspect;

[0015] The test module transmits the data to be transmitted from the control chip to the display through the OLDI interface to test the functions of other OLDI interfaces except the OLDI interface offset.

[0016] According to a fifth aspect of the present disclosure, there is provided an electronic device, including:

[0017] at least one processor;

[0018] a memory communicatively coupled to the at least one processor;

[0019] The memory stores instructions that can be executed by at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the offset calibration method and / or the OLDI interface testing method provided in the first aspect.

[0020] According to a sixth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable a computer to execute the offset calibration method and / or the OLDI interface testing method provided in the first aspect.

[0021] According to a seventh aspect of the present disclosure, a computer program product is provided, including a computer program stored on a storage medium, which, when executed by a processor, implements the offset calibration method and / or the OLDI interface testing method provided in the first aspect.

[0022] According to the technical solution disclosed in the present invention, by calibrating the offset between multiple data channels in the interface, data transmission errors caused by the offset can be effectively eliminated, thereby helping to improve the accuracy of data transmission.

[0023] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a flow chart of an offset calibration method provided in an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of an OLDI interface application according to an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of a serial clock channel and a data channel in an OLDI interface provided in an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of a first register and a second register provided in an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of a data channel that is shifted one bit ahead according to an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of a data channel with a one-bit delay offset provided by an embodiment of the present invention;

[0030] Figure 7 A schematic diagram of offset calibration provided by an embodiment of the present invention;

[0031] Figure 8 A schematic diagram of a flow chart of a method for testing an OLDI interface provided in an embodiment of the present invention;

[0032] Figure 9 A schematic structural diagram of an offset calibration device provided in an embodiment of the present invention;

[0033] Figure 10 A schematic diagram of the structure of an OLDI interface testing device provided in an embodiment of the present invention;

[0034] Figure 11 3 is a schematic structural diagram of an electronic device used to implement the offset calibration method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] The present disclosure will be described in further detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0036] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, circuits, etc. well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present disclosure.

[0037] The term "and / or" herein indicates that there may be three relationships. For example, A and / or B may indicate the existence of A alone, the existence of A and B at the same time, and the existence of B alone. The term "at least one" herein indicates any combination of at least two of any one or more of a plurality of. For example, at least one of A, B, and C may indicate any one or more elements selected from the set consisting of A, B, and C. The terms "first" and "second" herein refer to and distinguish between multiple similar technical terms, and do not mean to limit the order or to limit the meaning to only two. For example, the first feature and the second feature refer to two types / two features. The first feature can be one or more, and the second feature can also be one or more.

[0038] In related technology, OLDI is an interface connecting controllers and LCD display panels, widely used in various display devices such as laptops and in-vehicle displays. With the growing demand for high-resolution displays, the transmission speed of OLDI interfaces is also increasing. However, various anomalies may be encountered during testing, such as skew between several data channels in the interface.

[0039] In the prior art, skew balancing between multiple data channels in OLDI typically relies on the layout and configuration of routing, including both internal and external routing within the chip. However, if significant skew occurs between data channels during testing, it can affect data transmission accuracy. In this case, there's no effective way to eliminate skew between multiple data channels, potentially impacting other test items.

[0040] To at least partially address one or more of the aforementioned and other potential issues, the present disclosure proposes a calibration scheme for OLDI. The scheme includes: sequentially inputting a first data stream into a first register and a second register of a control chip to obtain a target processing signal output by the first register or the second register; calibrating the first data stream based on the target instruction in the target processing signal and then inputting it into the corresponding data channel of the OLDI interface. In this way, in a test scenario, by calibrating the offset between multiple data channels in the interface, data transmission errors caused by offset can be effectively eliminated, thereby helping to improve data transmission accuracy and reducing the impact on other test items.

[0041] Figure 1 FIG. 1 is a flow chart of offset calibration according to an embodiment of the present disclosure. Figure 1 As shown, the method comprises at least the following steps:

[0042] S101: Inputting a first data stream into a first register and a second register of a control chip in sequence to obtain a target processing signal output by the first register or the second register;

[0043] S102: Calibrate the first data stream based on the target instruction in the target processing signal and input the result to the corresponding data channel in the OLDI interface; wherein the target instruction is determined according to the display result including the calibration information output by the display after the Lth round of data transmission is completed.

[0044] In some embodiments, the interface is an OLDI interface, which is used to connect the control chip and the LCD display. The OLDI interface is based on low-voltage differential signaling (LVDS) technology. The OLDI interface utilizes the differential signaling characteristics of LVDS to transmit high-speed digital signals at very low voltage and current while maintaining signal integrity. Figure 2 shows an application diagram of the OLDI interface, such as Figure 2 As shown in the figure, one end of the OLDI interface is connected to the controller chip, and the other end is connected to the LCD display. In actual application scenarios, the controller chip is the transmitter and the LCD display is the receiver. The controller chip transmits the data to be transmitted from the controller chip to the LCD display via the OLDI interface.

[0045] In some embodiments, an OLDI interface supports multiple data channels to meet the needs of high-speed data transmission. An OLDI interface typically includes multiple data channels for transmitting video, audio, and other control signals. For example, in some applications, an OLDI interface may support eight LVDS data channels plus a clock channel to support high-resolution video transmission. The data channels in an OLDI interface can operate in parallel to transmit video signals at high rates, thereby supporting high-resolution and high-refresh-rate displays. Figure 3 A schematic diagram of the serial clock channel and data channel in the OLDI interface is shown in FIG. Figure 3 As shown, the OLDI interface includes four data channels and one clock channel; wherein the first data channel is denoted as A0, the second data channel is denoted as A1, the third data channel is denoted as A2, and the fourth data channel is denoted as A3.

[0046] In some embodiments, the offset between multiple data channels in an interface can be referred to as a phase offset. During an OLDI interface function test, if the LCD display displays an abnormal result when the control chip sends the Nth data to be transmitted, the control chip reacquires the Nth data to be transmitted as the data to be transmitted for the L+1th data transmission. Before the control chip sends the L+1th data to be transmitted to the LCD, the target instruction in the target processing signal is generated based on the display result of the Lth data transmission. This allows the offset between multiple data channels during testing to be calibrated, minimizing the impact on test items, such as those related to the OLDI interface function test. Furthermore, the offset between multiple data channels can be accurately located.

[0047] In some embodiments, a controller chip, also known as a microcontroller, is an integrated circuit chip. It integrates a processor core, memory, input / output interfaces, and various peripherals. It controls and operates a device or system by receiving input signals, processing and calculating them, and generating corresponding output signals. A controller chip typically consists of one or more processor cores, which can be general-purpose processors or processors designed for specific applications. The high bandwidth between the cores and the memory enables rapid transmission and processing of large amounts of data. The controller chip can control and manage the operations of various devices, including but not limited to smartphones, tablets, home appliances, automobiles, and industrial robots. Specifically, the controller chip includes at least a first register and a second register. The controller chip is connected to a display via an LCD interface. The display can be an LCD.

[0048] In some embodiments, the first data stream is obtained by serializing data to be processed. The data to be processed is obtained from a memory of a control chip. In a test environment for the OLDI interface function, if the LCD display displays an abnormal result when the control chip sends the Nth round of data to be transmitted to the LCD display, the L+1th round of data to be transmitted is obtained from the memory of the control chip; the content of the L+1th round of data to be transmitted is the same as the content of the Lth round of data to be transmitted.

[0049] In some embodiments, the first register and the second register are used to output a target processing signal carrying a target instruction. Specifically, the first register is used to output a target processing signal carrying a standard timing instruction and a delay instruction; the second register is used to output a target processing signal carrying an advance instruction. The first register and the second register are important components of the control chip, used to store and process data, and are important storage units inside the central processing unit (CPU). Registers are used to temporarily store processing objects such as instructions, data, and addresses. In the control chip, the main function of the register is to store instructions and data so that the CPU can quickly access and process these data.

[0050] In some embodiments, the target processing signal is a signal output by a first register or a second register of the control chip. The target processing signal carries a target instruction. The target instruction includes but is not limited to: a delay instruction and an advance instruction.

[0051] Figure 4 A schematic diagram of the first register and the second register is shown, as shown in FIG. Figure 4 As shown, the data[6:0] signal is a 7-bit bus after the parallelization of the data channel, and the Clock signal is a parallel clock; the clock signal passes through the first register and the second register; the clock signal is used to control the working status and timing of each module inside the chip. The data[6:0] signal passes through the first register to become the data_s1[6:0] signal, and then passes through the second register to become the data_s2[6:0] signal. The parallel data data[6:0] is mapped to the serial data channel in the order of the low bit 0 first. Here, each data channel has Figure 4 The first and second register paths are shown, so each data channel can adjust the offset independently.

[0052] In the disclosed embodiment, a first data stream is sequentially input into a first register and a second register of a control chip to obtain a target processing signal output by the first register or the second register. The first data stream is calibrated based on the target instruction in the target processing signal and then input into the corresponding data channel of the OLDI interface. The target instruction is determined based on the display result, including calibration information, output by the display after the Lth round of data transmission. In this way, in a test scenario, by calibrating the offset between multiple data channels in the interface, data transmission errors caused by offset can be effectively eliminated, thereby helping to improve data transmission accuracy and reducing the impact on other test items.

[0053] In an embodiment of the present disclosure, the offset calibration method further includes: obtaining the L+1th round of data to be transmitted from the memory of the control chip for processing to obtain a first data stream; wherein the content of the L+1th round of data to be transmitted is the same as the content of the Lth round of data to be transmitted.

[0054] In some embodiments, the memory refers to a storage element embedded within or closely associated with the control chip, used to store instructions, data, configuration parameters, and other information to support the normal operation and functional implementation of the chip. Specifically, the instructions, data, configuration parameters, and other information stored in the memory can be pre-acquired from other devices (such as sensors) or dynamically generated during chip operation.

[0055] In some embodiments, obtaining the L+1th round of data to be transmitted from the memory of the control chip and processing it to obtain the first data stream may include: encoding and compressing the L+1th round of data to be transmitted to obtain the first data stream.

[0056] In this way, by serializing the data to be transmitted, complex data structures can be simplified into a single data stream, which helps reduce errors and interference in data transmission and improves the accuracy and stability of data transmission.

[0057] In an embodiment of the present disclosure, the calibration information indicates that the first data stream enters the data channel N bits in advance, and the target processing signal is a signal output by the first register; wherein the target instruction in the target processing signal is a delay instruction, and N is an integer not less than 1.

[0058] In some embodiments, the display result corresponding to the calibration information is an abnormally displayed image or video. For example, if the control chip sends a colored line image composed of black, white, and red to the vehicle-mounted LCD display via the OLDI interface, the vehicle-mounted LCD display will display the line image composed of black and white. Figure 5 FIG. 1 shows a schematic diagram of a data channel shifted one bit ahead of the other. Figure 5 As shown in the figure, the OLDI interface contains one serial clock channel (CLK1) and four serial data channels (A0-A3). Figure 5 For example, if data channel A2 has an abnormality of one-bit advance offset and a data transmission error, the vehicle-mounted LCD display outputs a display result including calibration information indicating that the first data stream enters the data channel one bit in advance.

[0059] In some embodiments, the display result corresponding to the calibration information is an abnormal display image or video, such as garbled characters, a black screen, or an error prompt. For example, if the control chip sends a picture of "green radish" to the LCD display of a laptop through the OLDI interface, the display result of the laptop will be garbled characters. Figure 5 For example, the OLDI interface contains one serial clock channel (CLK1) and four serial data channels (A0-A3). Figure 5 For example, if data channel A2 has an abnormality of one-bit advance offset or data transmission error, the display output includes a display result of calibration information indicating that the first data stream enters the data channel N bits in advance.

[0060] In some embodiments, the target instruction is used to adjust an offset in a data channel. Specifically, the delay instruction refers to an anomaly in which the first data stream is offset N bits ahead in the data channel. When the control chip responds to detecting the delay instruction, it delays the first data stream by N bits and inputs it to the corresponding data channel in the OLDI interface, where N is an integer not less than 1.

[0061] In this way, when the calibration information indicates that the first data stream enters the data channel N bits in advance and the first data stream passes through the first register, the target processing signal carrying the delay instruction is obtained from the output of the first register. The offset between multiple data channels is calibrated through the delay instruction, which can ensure the accuracy of data transmission.

[0062] In an embodiment of the present disclosure, calibrating the first data stream based on a target instruction in a target processing signal and then inputting the first data stream into a corresponding data channel in an OLDI interface includes: delaying the first data stream by N bits based on a delay instruction and inputting the first data stream into the corresponding data channel in the OLDI interface, where N is an integer not less than 1.

[0063] by Figure 5 For example, if data channel A2 has an early one-bit offset during the Lth round of data transmission, then during the L+1th round of data transmission, the data to be transmitted in the Lth round is obtained as the data to be transmitted in the L+1th round, and the data to be transmitted in the L+1th round is serialized to obtain a first data stream; the first data stream passes through the first register and the second register to obtain a target processing signal carrying a delay instruction output by the first register; based on the delay instruction, the first data stream is delayed by N bits and input into the corresponding data channel in the OLDI interface, and the calibrated first data stream is transmitted to the display through the data channel.

[0064] In this way, by calibrating the offset between multiple data channels in the interface through delay instructions, data transmission errors caused by the offset can be effectively eliminated, thereby helping to improve the accuracy of data transmission.

[0065] In an embodiment of the present disclosure, the calibration information indicates that the first data stream is delayed by M bits to enter the data channel, and the target processing signal is a signal output by the second register; wherein the target instruction in the target processing signal is an advance instruction, and M is an integer not less than 1.

[0066] In some embodiments, the third display result corresponding to the calibration information is an abnormally displayed image or video, such as garbled characters, a black screen, or an error message. For example, if the control chip sends a 5-second video of "ephemeral cereus blooming" to the LCD display of the mobile phone via the OLDI interface, the mobile phone displays an error message. Figure 6 FIG. 1 shows a schematic diagram of a data channel with a one-bit delay offset, as shown in FIG. Figure 6 As shown in Figure 2, the OLDI interface contains one serial clock channel (CLK1) and four serial data channels (A0-A3). Figure 6 As shown, if the data channel A2 has an abnormality of a one-bit delay offset and a data transmission error, the display outputs a display result including calibration information indicating that the first data stream enters the data channel with a delay of M bits.

[0067] In some embodiments, the target instruction is used to adjust an offset in a data channel. Specifically, the advance instruction refers to an anomaly in which the first data stream experiences a delayed M-bit offset in the data channel. When the control chip detects the advance instruction, the first data stream is input to the corresponding data channel of the OLDI interface in advance by M bits, where M is an integer not less than 1.

[0068] In this way, when the calibration information indicates that the first data stream is delayed by M bits to enter the data channel and the first data stream passes through the second register, the target processing signal carrying the advance instruction is output by the second register. By calibrating the offset between multiple data channels through the advance instruction, the accuracy of data transmission can be guaranteed.

[0069] In an embodiment of the present disclosure, calibrating the first data stream based on a target instruction in a target processing signal and then inputting the first data stream into a corresponding data channel in an OLDI interface includes: based on an advance instruction, inputting the first data stream into the corresponding data channel in the OLDI interface M bits in advance, where M is an integer not less than 1.

[0070] by Figure 6 For example, if a one-bit delay offset occurs in the data channel A2 during the Lth round of data transmission, then during the L+1th round of data transmission, the data to be transmitted in the Lth round is obtained as the data to be transmitted in the L+1th round, and the data to be transmitted in the L+1th round is serialized to obtain a first data stream; the first data stream passes through the first register and the second register to obtain a target processing signal carrying an advance instruction output by the second register; based on the advance instruction, the first data stream is advanced by M bits and input into the corresponding data channel in the OLDI interface, and the calibrated first data stream is transmitted to the display through the data channel.

[0071] Figure 7 shows a schematic diagram of offset calibration, such as Figure 7As shown, the clk_s signal is the serial clock, and the clock signal is the parallel clock. Cycles 0 / 1 / 2 correspond to the parallel clock cycles. During cycles 0 / 1 / 2, the data[6:0] signals are data0[6:0], data1[6:0], and data2[6:0], respectively. After passing through the first register, the data_s1[6:0] signal is delayed by one clock cycle. Similarly, the data_s2[6:0] signal is delayed by one clock cycle. Data channel A2 is transmitted without exception. postA2 is designed to be transmitted with a delay of one serial clock cycle, while preA2 is designed to be transmitted one serial clock cycle early. When no exceptions occur, the parallel signals data_s1[6:0] are serially output from data channel A2. The M[N] format transmitted by A2 represents dataM[N], for example, 0[0] represents data0[0]. In cycle 0, the data_s1[6:0] signal is invalid data, and A2 outputs invalid data; in cycle 1, the data_s1[6:0] signal is data0[6:0], and A2 serially outputs data0[6:0], outputting the low bit first; cycle 2 is similar. Figure 5 When the abnormality of the early offset is shown, the data_post[6:0] signal is used, and the corresponding target processing signal is {data_s1[5:0], data_s2[6]}. Cycle 1 is calibrated to {data0[5:0], x}. The effect of the serial output is like postA2, and cycle 2 is similar. The overall delay is one serial clock cycle. Combined with the occurrence of the early exception, the normal data transmission A2 can be obtained. When the following occurs Figure 6 When the exception is shown, the data_pre[6:0] signal is used, and the corresponding target processing signal is {data[0], data_s1[6:1]}. In cycle0, it is calibrated to {data0[0], 6{x}}. The effect of the serial output is like preA2. Cycle1 and 2 are similar. The whole is advanced by one serial clock cycle. Combined with the delay exception, A2 of normal data transmission can be obtained.

[0072] In this way, by calibrating the offsets between multiple data channels in the interface through advance instructions, data transmission errors caused by the offsets can be effectively eliminated, thereby helping to improve the accuracy of data transmission.

[0073] In the embodiment of the present disclosure, the offset calibration method further includes: sending the first data stream to the display through the OLDI interface, and obtaining a display result of the L+1th round of data transmission output by the display.

[0074] In this way, the accuracy of data transmission can be determined through the display results output by the display, which helps to improve the efficiency of related tests on the OLDI interface.

[0075] Figure 8 FIG. 1 is a flow chart of offset calibration according to an embodiment of the present disclosure. Figure 8 As shown, the method comprises at least the following steps:

[0076] S801: Obtain the data to be transmitted corresponding to the first data stream of the L+1th round;

[0077] S802: Send the data to be transmitted from the control chip to the display through the OLDI interface to test the functions of other OLDI interfaces except the OLDI interface offset.

[0078] The first data stream is obtained through the above-mentioned offset calibration method.

[0079] In some embodiments, other OLDI interface functions include, but are not limited to, boundary value testing, permission control testing, and load testing. Specifically, boundary value testing refers to testing the boundary values ​​of input data, such as maximum, minimum, and null values, to ensure that the interface can be processed correctly. Permission control testing verifies the security and permission control of the interface by testing the access rights of different user roles to the interface, ensuring that the interface is not illegally accessed or abused. Load testing involves developing test scenarios, including parameters such as concurrency and request frequency, to simulate the stress of real-world scenarios; for example, running performance tests to collect metrics such as the interface's response time and throughput.

[0080] The present disclosure provides an offset calibration device, such as Figure 9 As shown, the offset calibration device includes: a first acquisition module 901, which is used to input the first data stream into the first register and the second register of the control chip in sequence to obtain a target processing signal output by the first register or the second register; a calibration module 902, which is used to calibrate the first data stream based on the target instruction in the target processing signal and then input it into the corresponding data channel of the OLDI interface; wherein the target instruction is determined based on the display result including the calibration information output by the display after the Lth round of data transmission is completed.

[0081] In some embodiments, the offset calibration device further includes: a second acquisition module ( Figure 9 (not shown), obtain the data to be transmitted in the L+1th round from the memory of the control chip; wherein the data to be transmitted in the L+1th round is the same as the data to be transmitted in the Lth round; the processing module ( Figure 9 (not shown) is used to serialize the data to be transmitted in the L+1th round to obtain a first data stream.

[0082] In some embodiments, the calibration information indicates that the first data stream enters the data channel N bits in advance, and the target processing signal is a signal output by the first register; wherein the target instruction in the target processing signal is a delay instruction, and N is an integer not less than 1.

[0083] In some embodiments, the calibration module 902 delays the first data stream by N bits and inputs it into a corresponding data channel in the OLDI interface based on the delay instruction, where N is an integer not less than 1.

[0084] In some embodiments, the calibration information indicates that the first data stream is delayed by M bits to enter the data channel, and the target processing signal is a signal output by the second register; wherein the target instruction in the target processing signal is an advance instruction, and M is an integer not less than 1.

[0085] In some embodiments, the calibration module 902 includes: based on the advance instruction, enabling the first data stream to be input into the corresponding data channel in the OLDI interface M bits in advance, where M is an integer not less than 1.

[0086] In some embodiments, the offset calibration device further includes: a sending module ( Figure 9 (not shown) sending the first data stream to the display through the OLDI interface, and obtaining the display result of the L+1th round of data transmission output by the display.

[0087] The offset calibration device of the embodiment of the present disclosure can effectively eliminate data transmission errors caused by offsets by calibrating the offsets between multiple data channels in the interface, thereby helping to improve the accuracy of data transmission.

[0088] The present disclosure provides an offset calibration device, such as Figure 10 As shown, the offset calibration device includes: a third acquisition module, which acquires the data to be transmitted corresponding to the first data stream of the L+1th round; and a testing module, which transmits the data to be transmitted from the control chip to the display via the OLDI interface to test the functions of other OLDI interfaces except the OLDI interface offset; wherein the first data stream is obtained by the above-mentioned offset calibration method.

[0089] In the technical solutions disclosed herein, the acquisition, storage, and application of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0090] Figure 11 FIG. 1 is a structural block diagram of an electronic device according to an embodiment of the present disclosure. Figure 11As shown, the electronic device includes: a memory 1110 and a processor 1120. The memory 1110 stores a computer program that can be executed on the processor 1120. The number of memories 1110 and processors 1120 can be one or more. The memory 1110 can store one or more computer programs. When the one or more computer programs are executed by the electronic device, the electronic device performs the method provided by the above method embodiment. The electronic device may also include: a communication interface 1130 for communicating with external devices and performing data exchange.

[0091] If the memory 1110, processor 1120, and communication interface 1130 are implemented independently, the memory 1110, processor 1120, and communication interface 1130 can be connected to each other via a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 11 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0092] Optionally, in a specific implementation, if the memory 1110, the processor 1120 and the communication interface 1130 are integrated on a chip, the memory 1110, the processor 1120 and the communication interface 1130 can communicate with each other through an internal interface.

[0093] It should be understood that the processor described above may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor. It is worth noting that the processor may be a processor that supports the Advanced RISC Machines (ARM) architecture.

[0094] Furthermore, the aforementioned memory may include read-only memory and random access memory, and may also include non-volatile random access memory. The memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which serves as an external cache memory. By way of example and not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (DR RAM).

[0095] The above embodiments can be implemented in whole or in part using software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. A computer program product comprises one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present disclosure are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, Bluetooth, microwave, etc.) means. A computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. Available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital versatile discs (DVDs)), or semiconductor media (e.g., solid-state drives (SSDs)). It is worth noting that the computer-readable storage media mentioned in this disclosure may be non-volatile storage media, in other words, non-transitory storage media.

[0096] Those skilled in the art will understand that all or part of the steps of implementing the above embodiments may be accomplished by hardware, or by programs instructing related hardware to accomplish the steps. The programs may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk, or an optical disk, etc.

[0097] In the description of the embodiments of the present disclosure, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification, as well as features of different embodiments or examples, unless they are mutually inconsistent.

[0098] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. An offset calibration method, characterized in that: For calibrating offsets between multiple data channels in an OLDI interface, where the OLDI interface is used to connect a control chip and a display, the method comprising: Inputting the first data stream into the first register and the second register of the control chip in sequence to obtain a target processing signal output by the first register or the second register; Calibrate the first data stream based on the target instruction in the target processing signal and input the first data stream into the corresponding data channel of the OLDI interface; wherein the target instruction is determined based on a display result including calibration information output by the display after the Lth round of data transmission is completed; The data to be transmitted in the L+1th round is obtained from the memory of the control chip and processed to obtain a first data stream; wherein the data to be transmitted in the L+1th round has the same content as the data to be transmitted in the Lth round.

2. The method according to claim 1, characterized in that The calibration information indicates that the first data stream enters the data channel N bits in advance, and the target processing signal is a signal output by the first register; wherein the target instruction in the target processing signal is a delay instruction, and N is an integer not less than 1.

3. The method according to claim 2, characterized in that The step of calibrating the first data stream based on the target instruction in the target processing signal and inputting the first data stream into the corresponding data channel in the OLDI interface includes: Based on the delay instruction, the first data stream is delayed by N bits and inputted into the corresponding data channel in the OLDI interface, where N is an integer not less than 1.

4. The method according to claim 1, wherein The calibration information indicates that the first data stream is delayed by M bits to enter the data channel, and the target processing signal is a signal output by the second register; wherein the target instruction in the target processing signal is an advance instruction, and M is an integer not less than 1.

5. The method according to claim 4, characterized in that The step of calibrating the first data stream based on the target instruction in the target processing signal and inputting the first data stream into the corresponding data channel in the OLDI interface includes: Based on the advance instruction, the first data stream is input into the corresponding data channel in the OLDI interface M bits in advance, where M is an integer not less than 1.

6. The method according to claim 1, wherein The method further comprises: The first data stream is sent to the display through the OLDI interface, and a display result of the L+1th round of data transmission is obtained from the display.

7. A method for testing an OLDI interface, characterized in that: The method comprises: Obtaining data to be transmitted corresponding to the first data stream of the L+1th round; the first data stream is obtained by the method according to any one of claims 1 to 6; The data to be transmitted is sent from the control chip to the display through the OLDI interface to test functions of the other OLDI interfaces except the OLDI interface offset.

8. An offset calibration device for calibrating offsets between multiple data channels in an OLDI interface, wherein the OLDI interface is used to connect a control chip and a display, the device comprising: A first acquisition module is used to input the first data stream into the first register and the second register of the control chip in sequence, and obtain a target processing signal output by the first register or the second register; a calibration module, configured to calibrate the first data stream based on a target instruction in the target processing signal and then input the calibrated data stream into a corresponding data channel in the OLDI interface; wherein the target instruction is determined based on a display result including calibration information output by the display after the Lth round of data transmission is completed; a second acquisition module, configured to acquire the data to be transmitted in the L+1th round from the memory of the control chip; wherein the data to be transmitted in the L+1th round has the same content as the data to be transmitted in the Lth round; The processing module is used to process the data to be transmitted in the L+1th round to obtain a first data stream.

9. A test device for an OLDI interface, characterized in that: The device comprises: a third acquisition module, configured to acquire data to be transmitted corresponding to the first data stream of the L+1th round; the first data stream being obtained by the method according to any one of claims 1 to 6; The testing module is configured to send the data to be transmitted from the control chip to the display via the OLDI interface, so as to test functions of the OLDI interfaces other than the OLDI interface offset.

10. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

11. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 7.

12. A computer program product comprising a computer program stored on a storage medium, characterized in that The computer program implements the method according to any one of claims 1 to 7 when executed by a processor.

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