A functional verification method, device and system for linked list caching

Abstract

The present invention discloses a functional verification method, apparatus and system for a linked list cache, which relates to the field of computer technology, and includes: obtaining a to-be-written index number, a to-be-written group number and a to-be-written node corresponding to valid instruction data from a first sampling point set in a circuit to be verified, where the circuit to be verified includes a link building unit, a selection unit and a linked list cache; obtaining a data set corresponding to the to-be-written index number from a preset linked list cache model, where the data set includes data units of all groups corresponding to the to-be-written index number; determining whether there is a functional error in the link building unit or the selection unit based on the to-be-written index number, the to-be-written group number, the to-be-written node and the data set; the preset linked list cache model is a model implementation of the linked list cache; the to-be-written group number is determined by the selection unit from the linked list cache; the to-be-written index number and the to-be-written node are determined after the link building unit encapsulates the valid instruction data with a link; the first sampling point is set at the back ends of the link building unit and the selection unit.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and can also be used in the field of integrated circuits. In particular, it relates to a function verification method, device, and system for a linked list cache. Background Art

[0002] With the development of integrated circuit technologies, in order to accelerate decoding, CORE designs an instruction cache at the front end to store instruction codes that are about to enter the pipeline. Among them, the maintenance of entries in a general cache (cache) in a set-associative form involves writing, replacement, and invalidation. Among them, writing only needs to move the data of the corresponding address memory in the CL dimension; replacement selects a certain eligible entry according to a specific replacement algorithm, and then replaces the data of the selected entry; invalidation removes the corresponding entry for a certain address.

[0003] However, compared with a general cache, the link building, replacement, and invalidation of a linked list cache are more complex and subject to more constraints than those of a general cache. Its writing cannot directly copy the memory content, but needs to first splice and build a chain for entries according to branch history jump information. Similarly, for a linked list cache, it is not possible to directly select an entry for replacement or invalidation, and this operation may damage the linked list information. Therefore, the maintenance and verification of a linked list cache are more difficult, and it is difficult to establish a completely accurate model for a linked list cache in digital verification. For the above problems, no effective solution has been proposed yet. Summary of the Invention

[0004] To solve at least one of the above problems, the present application proposes a function verification method, device, and system for a linked list cache, which can avoid the modeling work of the link building unit logic and the selector unit logic through a method of constraint verification + partial function simulation, and improve the verification efficiency while maintaining the verification accuracy.

[0005] In a first aspect, an embodiment of the present application provides a function verification method for a linked list cache, and the method includes:

[0006] Obtaining a to-be-written index number, a to-be-written group number, and a to-be-written node corresponding to valid instruction data from a first sampling point set in a circuit to be verified, where the circuit to be verified includes a link building unit, a selection unit, and a linked list cache;

[0007] Obtaining a data set corresponding to the to-be-written index number from a preset linked list cache model, where the data set includes data units of all groups corresponding to the to-be-written index number;

[0008] Based on the index number to be written, the group number to be written, the node to be written, and the data set, determine whether there is a functional error in the link building unit or the selection unit;

[0009] Wherein, the preset linked list cache model is the model implementation of the linked list cache; the first sampling point is set at the back end of the link building unit and the selection unit, and the group number to be written is determined by the selection unit from the linked list cache; the index number to be written and the node to be written are determined by the link building unit after building and encapsulating the valid instruction data.

[0010] In some alternative ways of this embodiment, the determining whether there is a functional error in the selection unit based on the position to be written, the node to be written, and the data set includes:

[0011] Determine whether the data set is empty;

[0012] In response to determining that the data set is empty, write the node to be written into the preset linked list cache model according to the index number to be written and the group number to be written.

[0013] In some alternative ways of this embodiment, the determining whether there is a functional error in the selection unit based on the position to be written, the node to be written, and the data set further includes:

[0014] In response to determining that the data set is not empty, determine whether the data set is not full;

[0015] In response to determining that the data set is not full, determine whether the data unit corresponding to the position to be written is occupied;

[0016] In response to determining that the data unit corresponding to the position to be written is occupied, determine that there is a functional error in the selection unit.

[0017] In some alternative ways of this embodiment, the determining whether there is a functional error in the selection unit based on the position to be written, the node to be written, and the data set further includes:

[0018] In response to determining that the data set is full, determine whether the first written node in the data unit corresponding to the position to be written matches the node to be written;

[0019] In response to determining that the first written node matches the node to be written, determine that there is a functional error in the selection unit.

[0020] In some alternative ways of this embodiment, the determining whether there is a functional error in the link building unit based on the position to be written, the node to be written, and the data set includes:

[0021] In response to determining that the first written node does not match the node to be written, delete, from the data set, a second written node that matches the first written node to obtain a first valid node;

[0022] Determine whether there is a first matching node in the first valid node that matches the node to be written;

[0023] In response to the existence of the first matching node, determine whether the first matching node and the node to be written are chained;

[0024] In response to determining that the first matching node and the node to be written are chained, replace the first written node with the node to be written;

[0025] In response to determining that the first matching node and the node to be written are not chained, determine that there is a functional error in the chaining unit;

[0026] In response to the non-existence of the first matching node, replace the first written node with the node to be written.

[0027] In some alternative ways of this embodiment, determining whether there is a functional error in the chaining unit based on the write position to be written, the node to be written, and the data set includes:

[0028] In response to determining that the data unit corresponding to the write position to be written is not occupied, determine a second valid node among the third written nodes in the data set;

[0029] Determine whether there is a second matching node in the second valid node that matches the node to be written;

[0030] In response to the existence of the second matching node, determine whether the second matching node and the node to be written are chained;

[0031] In response to determining that the second matching node and the node to be written are chained, write the node to be written into the preset linked list cache model according to the write index number to be written and the write group number to be written;

[0032] In response to determining that the second matching node and the node to be written are not chained, determine that there is a functional error in the chaining unit;

[0033] In response to the non-existence of the second matching node, write the node to be written into the preset linked list cache model according to the write index number to be written and the write group number to be written.

[0034] In some alternative embodiments of the present embodiment, the circuit to be verified further includes an address query unit, and the functional verification method further includes:

[0035] In response to receiving an invalidation request from the second sampling point, based on a preset address query model, determine the erasure address corresponding to the invalidation request, where the preset address query model is the model implementation of the address query unit;

[0036] Based on the erasure address, erase the linked list cache model to obtain a first erasure result;

[0037] Obtain a second erasure result of the linked list cache from the fifth sampling point, where the fifth sampling point is set at the position corresponding to the erasure address in the linked list cache, and the second erasure result is obtained by the circuit to be verified erasing the linked list cache based on the erasure address;

[0038] Determine whether the first erasure result is the same as the second erasure result;

[0039] In response to determining that the first erasure result is the same as the second erasure result, determine that there is no functional error in the address query unit;

[0040] In response to determining that the first erasure result is different from the second erasure result, determine that there is a functional error in the address query unit.

[0041] In some alternative embodiments of the present embodiment, the circuit to be verified further includes a query decoding unit, and further includes:

[0042] In response to receiving a query request from the third sampling point, based on a preset query decoding model, determine the query address corresponding to the query request, where the preset query decoding model is the model implementation of the query decoding unit;

[0043] Based on the query address, obtain a first query result from the linked list cache model;

[0044] Obtain a second query result set at the fourth sampling point of the circuit to be verified, where the second query result is obtained by the circuit to be verified querying from the linked list cache based on the query address;

[0045] Determine whether the first query result is the same as the second query result;

[0046] In response to determining that the first query result is different from the second query result, determine that there is a functional error in the query decoding unit or the link building unit;

[0047] In response to determining that the first query result is the same as the second query result, it is determined that there is no functional error in the query decoding unit.

[0048] Second, an embodiment of the present application further provides a functional verification device for a linked list cache, including:

[0049] A first acquisition module, configured to acquire a to-be-written index number, a to-be-written group number, and a to-be-written node corresponding to valid instruction data from a first sampling point provided in a circuit to be verified, where the circuit to be verified includes a chain building unit, a selection unit, and a linked list cache;

[0050] A second acquisition module, configured to acquire a data set corresponding to the to-be-written index number from a preset linked list cache model, where the data set includes data units of all groups corresponding to the to-be-written index number;

[0051] A functional verification module, configured to determine whether there is a functional error in the chain building unit or the selection unit based on the to-be-written index number, the to-be-written group number, the to-be-written node, and the data set;

[0052] Wherein, the preset linked list cache model is a model implementation of the linked list cache; the first sampling point is provided at the back end of the chain building unit and the selection unit, the to-be-written group number is determined by the selection unit from the linked list cache; the to-be-written index number and the to-be-written node are determined after the chain building unit encapsulates the valid instruction data into a chain.

[0053] Third, an embodiment of the present application further provides a functional verification system for a linked list cache, including the functional verification device described in the first aspect and the circuit to be verified.

[0054] Fourth, an embodiment of the present application further provides a central processing device, where the central processing device includes a central processing kernel based on instructions, micro-instructions, and macro-instructions, and the central processing kernel applies a functional verification method for a linked list cache described in any one of the first aspects.

[0055] Fifth, an embodiment of the present application further provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where when the processor executes the computer program, it implements a functional verification method for a linked list cache described in any one of the first aspects.

[0056] Sixth, an embodiment of the present application further provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements a functional verification method for a linked list cache described in any one of the first aspects.

[0057] The function verification method, device and system for linked list caching provided by the embodiments of the present application perform constraint verification by combining some internal signals of the circuit under verification with the data in the preset linked list caching model, and avoid the modeling work of the chain building unit logic and the selector unit logic through the method of combining constraint verification with partial function simulation. On the one hand, it can reduce the modeling workload; on the other hand, it can avoid the verification omission caused by directly taking the internal signals of the circuit under verification, so as to improve the verification efficiency while maintaining the verification accuracy.

[0058] Specific embodiments of the present invention are disclosed in detail with reference to the following description and drawings, indicating the ways in which the principles of the present invention can be employed. It should be understood that the embodiments of the present invention are not limited in scope thereby. Features described and / or illustrated for one embodiment can be used in the same or similar way in one or more other embodiments, combined with the features in other embodiments, or replace the features in other embodiments.

[0059] It should be emphasized that the term "comprising / including" when used herein refers to the presence of features, components, steps or elements, but does not exclude the presence or addition of one or more other features, components, steps or elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. In the drawings:

[0061] Figure 1 is one of the structure diagrams of the linked list caching in the embodiments of the present invention;

[0062] Figure 2 is another structure diagram of the linked list caching in the embodiments of the present invention;

[0063] Figure 3 is the structure diagram of the physical arrangement of the instruction chain in the embodiments of the present invention;

[0064] Figure 4 is the schematic diagram of the composition of the linked list node in the embodiments of the present invention;

[0065] Figure 5 is the structure diagram of the function verification system for linked list caching in the embodiments of the present invention;

[0066] Figure 6 is one of the flow diagrams of the function verification method for linked list caching in the embodiments of the present invention;

[0067] Figure 7 This is the second flowchart diagram for the function verification method of linked list caching in the embodiments of the present invention;

[0068] Figure 8 This is the third flowchart diagram for the function verification method of linked list caching in the embodiments of the present invention;

[0069] Figure 9 This is the fourth flowchart diagram for the function verification method of linked list caching in the embodiments of the present invention;

[0070] Figure 10 This is the fifth flowchart diagram for the function verification method of linked list caching in the embodiments of the present invention;

[0071] Figure 11 This is the structural diagram of the function verification device for linked list caching in the embodiments of the present invention;

[0072] Figure 12 This is the entity structural diagram of the electronic device provided by the embodiments of the present invention. Detailed implementation manners

[0073] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer and more understandable, the following further elaborates on the embodiments of the present invention with reference to the accompanying drawings. Herein, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but not to limit the present invention.

[0074] The following will describe the principles and spirit of this specification with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and then implement this specification, rather than to limit the scope of this specification in any way. On the contrary, these embodiments are provided to make this specification disclosure more thorough and complete, and to be able to fully convey the scope of this disclosure to those skilled in the art.

[0075] Those skilled in the art know that the embodiments of this specification can be implemented as a system, device, equipment, method, or computer program product. Therefore, the disclosure of this specification can be specifically implemented in the following forms, namely: completely hardware, completely software (including firmware, resident software, code, etc.), or a combination of hardware and software.

[0076] Combined with the accompanying drawings and the description of the specific embodiments of the present invention, the details of the present invention can be more clearly understood. However, the specific embodiments of the present invention described herein are only for the purpose of explaining the present invention and cannot be construed in any way as a limitation of the present invention. Under the teaching of the present invention, those skilled in the art can conceive any possible variations based on the present invention, and all of these should be regarded as belonging to the scope of the present invention. It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "mounted", "connected" and "connected" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the communication inside two elements. It can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are only for the purpose of illustration and do not represent the only embodiments.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this specification belongs. The terms used in this specification herein are only for the purpose of describing specific embodiments and are not intended to limit this specification. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0078] Most current high-performance CPU architectures support branch instructions. After inserting a branch instruction into the instruction stream, if the branch instruction jumps, the instructions immediately following it in the address arrangement will not be executed, and the program will jump to the instruction at the target address pointed to by the branch instruction and continue to execute, ultimately causing the effective instruction distribution to be discrete. In common programs, there may be a branch instruction at the end of a frequently executed loop code block, which jumps to the beginning of the loop when certain conditions are met; or there may also be a jumping branch instruction within the loop block; for such a loop block, the instruction stream is arranged in a chain form from the perspective of instruction addresses.

[0079] In order to accelerate decoding, CORE generally designs an instruction cache at the front end to store the instruction codes that are about to enter the pipeline. Common instruction caches store all instruction data in the CL dimension because at this time it is not known which of the instruction data are branch instructions and which instructions will jump; while if combined with a branch predictor, the branch information that is about to be taken can be predicted more accurately. For the code of the above loop block, only storing the effective instruction data according to the execution chain can increase the instruction density of the cache.

[0080] A general cache in a set-associative form, the maintenance of its entries involves several operations such as writing, replacement, and invalidation. Among them, writing only requires moving the data of the corresponding address in memory along the CL dimension; replacement selects a qualified entry according to a specific replacement algorithm, such as the LRU algorithm, and then replaces the data of the selected entry; invalidation removes the corresponding entry for a certain address. However, compared with a general cache, the linked list cache cannot directly copy the memory content during writing, but needs to first splice and build a chain of entries according to the branch history jump information. Similarly, for the linked list cache, it is not possible to simply select a certain entry for direct replacement or invalidation, as this operation may damage the linked list information, so its maintenance and verification are more difficult.

[0081] Based on this, the applicant finds that the chain building, replacement, and invalidation of the linked list cache are more complex and subject to more constraints than those of a general instruction cache. The modeling of the entry splicing, chain building, and way selection algorithm in the linked list cache (i.e., the linked list cache) is difficult, and it is deeply bound to the circuit under test (i.e., the verified circuit). It is difficult to establish a completely accurate model for it in digital verification, and the modeling benefit is not high. For this reason, this application proposes a method of combining constraint verification with partial function simulation to verify the function of the linked list cache, which can reduce the difficulty of model development while losing less verification accuracy.

[0082] First, the key terms involved in the context of this application are introduced in advance:

[0083] CPU: Central Processing Unit; CORE: Processor Core; Memory: Memory; Cache: Cache, which refers to a special cache that stores data in a linked list structure in this application (i.e., the linked list cache in this application); CL: Cache Line, which refers to the data that an entry of the cache device can store; Payload: Payload, which refers to the linked list data payload in this application; Taken: When a branch instruction jumps, it is called taken; Target: Branch jump target address; Invalid: It means invalidating or removing a certain entry in the cache; LRU: Least Recently Used, a cache replacement algorithm; Index: Entry index of a single page of the cache; Way: Set-associative cache page number, also called the number of ways or group number; Set: A set of multiple entries with the same index in different ways of the set-associative cache; Hit: Cache hit, which means that the corresponding information can be queried in the cache.

[0084] Secondly, the linked list cache of this application is introduced, as Figure 1As shown below, a 4-way set-associative linked list cache is taken as an example for illustration. Specifically:

[0085] When selecting an entry for writing, the way is selected through a replacement algorithm, and the index is calculated based on the starting address of the cache line where the instruction data chain is located. In this way, instructions in the instruction chains on different cache lines must be located in different Sets (such as EntryA and EntryE), while instructions on the same cache line are located in entries of different ways in the same set (such as EntryA, EntryB, EntryC, and EntryD).

[0086] On the premise of a branch instruction jump, not all instructions in a cache line are necessarily valid instructions. At this time, the entries without data in a set of the linked list cache can be left empty. For example, in Figure 1 the instruction chain starts from EntryA in Way0, the next one selects to fill EntryC in Way2, and the next one selects to fill EntryB in Way1. If the last instruction of EntryB ends with a taken branch instruction, then the filling of the instruction chain in this cache line ends here. The filling address of the next instruction uses the target address of this branch instruction to calculate the index, and EntryD is left empty.

[0087] Similarly, as Figure 2 shown, if the indexes calculated from the addresses of multiple cache lines are the same and the amount of valid instructions is relatively small, they can also be filled into the same set when there are enough spare entries. For example, EntryA and EntryC belong to the instruction chain of one cache line, and EntryB and EntryD belong to the instruction chain of another cache line. The arrangement of the two instruction chains in physical memory can be as Figure 3 shown, and they can be distinguished by the physical addresses stored in the entries during query.

[0088] Furthermore, it should also be noted that in the linked list cache of this application, the composition of each entry is as Figure 4As shown in the figure, the linked list header carries the query information of the node entry, including the valid flag valid, the query tag Tag, and the node offset address offset; the linked list payload carries the valid instruction part that the node can store; the linked list tail carries the chain information, where NextOffset is used to indicate the offset address Offset of the next node, and the end flag EndFlag is used to indicate the real chain tail. Among them, consecutive nodes in the same linked list have the following characteristics: the nodes are all valid; the Tags are the same; the NextOffset of the previous node matches the Offset of the next node; the EndFlag of the previous node is not 0.

[0089] Finally, as Figure 5 shown, an embodiment of the present application provides a function verification system for linked list caching, including: a function verification device (i.e., Figure 5 the verification model in Figure 5 ) and the circuit under verification (i.e., Figure 5 the circuit under test in Figure 5 ), where: the circuit under verification includes a chain building unit, a selection unit, and a linked list cache. The chain building unit is used to determine the index number to be written (i.e., Figure 5 Index in Figure 5 ) and the node to be written (i.e., Figure 5 the node in Figure 5 ) according to the valid instruction data; the selection unit is used to determine the group number to be written (i.e., Figure 5 Way in Figure 5 ) from the linked list cache according to a preset selection algorithm.

[0090] The function verification device implements the function verification method for linked list caching as Figure 6 shown, and the method includes:

[0091] Step 10: Obtain the index number to be written, the group number to be written, and the node to be written corresponding to the valid instruction data from the first sampling point set in the circuit under verification, where the circuit under verification includes a chain building unit, a selection unit, and a linked list cache.

[0092] In this embodiment, a total of 5 sampling points are set, namely the first sampling point ①, which is the cache write port; the second sampling point ②, which is the invalid request input port; the third sampling point ③, which is the query request port; the fourth sampling point ④, which is the query result output port; the fifth sampling point ⑤, which is the invalid result output port. It should also be noted that in the present application, the first sampling point ① is set at the back end of the chain building unit and the selection unit to obtain the index number to be written, the group number to be written, and the node to be written corresponding to the valid instruction data, so as to perform constraint verification and model data writing, ② is used to simulate the invalid function, and ③ and ④ are used to simulate the query and read functions.

[0093] Among them, the index number to be written and the group number to be written are the positions to be written, and the node to be written is the information to be written; the group number to be written is determined by the selection unit from the linked list cache; the index number to be written and the node to be written are determined by the link building unit after link encapsulation of the valid instruction data.

[0094] Step 20: Obtain the data set corresponding to the index number to be written from the preset linked list cache model, where the data set includes data units of all groups corresponding to the index number to be written.

[0095] In this embodiment, the preset linked list cache model is the model implementation of the linked list cache. Specifically, before the start of function verification, based on the current structure and current stored content of the linked list cache, a preset linked list cache model identical to the linked list cache is constructed. After determining the index number to be written, obtain the data set (i.e., the aforementioned Set) corresponding to the index number to be written from this preset linked list cache model. It should be understood that the data set includes data units of all groups corresponding to the index number to be written. Taking the foregoing Figure 1 as an example, the data units of all groups corresponding to index3 are EntryA in Way0, EntryB in Way1, EntryC in Way2, and EntryD in Way3; the data unit corresponding to index5 is EntryE in Way0, and the data units of the remaining groups are empty (not occupied).

[0096] Step 30: Determine whether there is a functional error in the link building unit or the selection unit based on the index number to be written, the group number to be written, the node to be written, and the data set.

[0097] In this embodiment, after determining the position to be written and the information to be written, use the index number to be written, the group number to be written, the node to be written, the data set, and the preset linked list cache model for joint constraint verification. The constraint verification is mainly implemented in the verification unit of the model. This verification unit does not directly perform functional simulation on the link building unit and the selection unit of the linked list cache respectively, but directly uses the position to be written and the information to be written calculated by the two, that is, the signal output at the measured circuit ①, and jointly performs static constraint verification with the node data already stored in all entries corresponding to the set in the preset cache model. If the static constraint verification fails, it indicates that there is a functional error in the link building unit or the selection unit, resulting in incorrect position or information finally determined to be written. At this time, stop the simulation and report an error; otherwise, update the preset linked list cache model according to the specified write position and write information of the measured circuit, complete the write function simulation, and the simulation continues.

[0098] In this application, the internal signals of the circuit under test are used in combination with the data of the preset linked list cache model for constraint verification. Compared with the complete modeling solution, the modeling workload can be reduced. Compared with the solution of directly updating the model by taking the internal signals, the verification omissions caused by lack of verification can be avoided.

[0099] It should be noted that the constraint verification of the selection unit is mainly reflected in whether the write position is appropriate. Generally, when the set is not full, that is, when there is an empty entry, the selection unit should preferentially select the empty entry rather than replace the existing entry. In addition, if the set can accommodate multiple linked lists, the selection unit should not damage the current linked list when selecting the write position. If the selected write position does not meet the above constraints, a constraint violation occurs, indicating that there is a functional problem with the selection unit.

[0100] In some alternative ways of this embodiment, such as Figure 7 shown, determining whether there is a functional error in the selection unit based on the to-be-written position, the to-be-written node, and the data set includes:

[0101] Step 301, determine whether the data set is empty;

[0102] Step 302, in response to determining that the data set is empty, write the to-be-written node into the preset linked list cache model according to the to-be-written index number and the to-be-written group number.

[0103] In this embodiment, as Figure 10 shown, determining whether the data set is empty, that is, whether the Set is empty; when the set is empty, write the to-be-written node into the preset linked list cache model according to the to-be-written index number and the to-be-written group number, that is, write the to-be-written node as the initial node of the new linked list into the model normally.

[0104] It should be noted that when it is determined that the data set is empty, it cannot be determined that the selection unit must not have a functional error. That is to say, when the set is empty, there is also a possibility that the selection unit has a functional error. Specifically, if it is assumed that the selection unit has a functional error, it cannot be detected at the time node when the set is determined to be empty, and a conflict with the previous write result will occur during subsequent writes, indicating that there is an error in the current write or the previous write, thus finally determining that the selection unit has a functional error.

[0105] In some alternative ways of this embodiment, such as Figure 7 shown, determining whether there is a functional error in the selection unit based on the to-be-written position, the to-be-written node, and the data set further includes:

[0106] Step 303: In response to determining that the data set is not empty, determine whether the data set is not full;

[0107] Step 304: In response to determining that the data set is not full, determine whether the data unit corresponding to the to-be-written position is occupied;

[0108] Step 305: In response to determining that the data unit corresponding to the to-be-written position is occupied, determine that there is a functional error in the selection unit.

[0109] In this embodiment, as Figure 10 shown, when it is determined that the data set Set is not empty, further determine whether the data set is not full. If it is determined that it is not full, determine whether the data unit corresponding to the to-be-written position is occupied, that is, determine whether the write position is not empty. If it is not empty (that is, if it is occupied), it means that the to-be-written position provided by the selection unit is incorrect and there is a functional error in the selection unit.

[0110] In some alternative ways of this embodiment, as Figure 7 shown, determining whether there is a functional error in the selection unit based on the to-be-written position, the to-be-written node, and the data set further includes:

[0111] Step 306: In response to determining that the data set is full, determine whether the first written node in the data unit corresponding to the to-be-written position matches the to-be-written node;

[0112] Step 307: In response to determining that the first written node matches the to-be-written node, determine that there is a functional error in the selection unit.

[0113] In this embodiment, as Figure 10 shown, when it is determined that Set is full, that is, when the data set is full, determine whether the first written node in the data unit corresponding to the to-be-written position matches the to-be-written node, that is, determine whether the Tag of the write position node matches the Tag of the to-be-written information. If the match is successful, that is, if it is determined that the first written node matches the to-be-written node, then there is a functional error in the selection unit.

[0114] It should be noted that the link building unit constructs a linked list based on the instruction data and address information input by the valid instruction, and its constraint is mainly reflected in whether the written content forms a chain. The linked list information stored in the preset cache model is consistent with the linked list cache in the circuit under test. When there is already a matching valid linked list in the same set, but the written node is not the expected next node, a constraint violation occurs, indicating that there is a functional problem with the link building unit.

[0115] In some alternative ways of this embodiment, as Figure 8As shown, determining whether there is a functional error in the chain building unit based on the position to be written, the node to be written, and the data set includes:

[0116] Step 308, in response to determining that the first written node does not match the node to be written, delete the second written node that matches the first written node from the data set to obtain the first valid node;

[0117] Step 309, determine whether there is a first matching node in the first valid node that matches the node to be written;

[0118] Step 310, in response to the existence of the first matching node, determine whether the first matching node and the node to be written are chained;

[0119] Step 311, in response to determining that the first matching node and the node to be written are chained, replace the first written node with the node to be written;

[0120] Step 313, in response to determining that the first matching node and the node to be written are not chained, determine that there is a functional error in the chain building unit;

[0121] Step 312, in response to the non-existence of the first matching node, replace the first written node with the node to be written.

[0122] In this embodiment, as Figure 10 shown, when it is determined that the first written node does not match the node to be written, prepare for linked list replacement, query all nodes in the set that match the tag of the node to be replaced and delete them. Specifically:

[0123] When it is determined that the first written node does not match the node to be written, delete the second written node that matches the first written node from the data set set, and the remaining nodes are used as the first valid nodes. That is to say, the present application performs a relatively strict chain deletion process in the replacement scenario, rather than only removing the current entry.

[0124] Furthermore, use the tag of the information to be written to match the valid nodes in the set to determine whether there is a first matching node in the first valid nodes that matches the node to be written;

[0125] If the match is successful, that is, it is determined that there is the first matching node and there is a matching linked list, it is necessary to verify the chaining relationship, that is, determine whether the first matching node and the node to be written are chained.

[0126] If the verification is successful, that is, it is determined that the first matching node and the node to be written can form a chain, replace the first written node with the node to be written, and write the node to be written into the preset linked list cache model as a non-initial node of the linked list.

[0127] It should be noted that when it is determined that the first matching node and the node to be written can form a chain, it only indicates that there is no chain building error between the valid instruction data of the current pen and the valid instruction data of the previous pen, and it cannot be determined from this that the chain building unit must have no functional error.

[0128] If the verification fails, that is, it is determined that neither the first matching node nor the node to be written can form a chain, indicating that the chain building unit has a functional error.

[0129] If the matching fails, that is, it is determined that there is no first matching node, replace the first written node with the node to be written, and write the node to be written into the model as the initial node of the same Set multi-linked list.

[0130] It should be noted that when it is determined that there is no first matching node, it cannot be determined from this that the chain building unit must have no functional error.

[0131] In some optional ways of this embodiment, as Figure 9 shown, determining whether the chain building unit has a functional error based on the position to be written, the node to be written, and the data set includes:

[0132] Step 314: In response to determining that the data unit corresponding to the position to be written is not occupied, determine the second valid node among the third written nodes in the data set;

[0133] Step 315: Determine whether there is a second matching node in the second valid nodes that matches the node to be written;

[0134] Step 316: In response to the existence of the second matching node, determine whether the second matching node and the node to be written can form a chain;

[0135] Step 317: In response to determining that the second matching node and the node to be written can form a chain, write the node to be written into the preset linked list cache model according to the index number to be written and the group number to be written;

[0136] Step 319: In response to determining that the second matching node and the node to be written cannot form a chain, determine that the chain building unit has a functional error;

[0137] Step 318: In response to the non-existence of the second matching node, write the node to be written into the preset linked list cache model according to the index number to be written and the group number to be written.

[0138] In this embodiment, as Figure 10 shown, when it is determined that the data unit corresponding to the position to be written is not occupied, that is, when it is determined that the position to be written is empty, further, determine the second valid node among the third written nodes in the data set, for example, by using the Tag of the write information to match the valid nodes in the Set.

[0139] If the match is successful, that is, it is determined that there is the second matching node and there is a matching linked list, it is necessary to verify the chaining relationship, that is, to determine whether the second matching node and the node to be written are chained.

[0140] If the verification is successful, that is, it is determined that the second matching node and the node to be written can be chained. According to the index number to be written and the group number to be written, this node to be written is normally written into the preset linked list cache model as a non-initial node of the linked list.

[0141] It should be noted that when it is determined that the second matching node and the node to be written can be chained, it only means that there is no chaining error between the valid instruction data of the current pen and the valid instruction data of the previous pen, and it cannot be determined from this that the chaining unit must have no functional error.

[0142] If the verification fails, that is, it is determined that the second matching node and the node to be written are not chained, indicating that the chaining unit has a functional error.

[0143] If the match fails, that is, it is determined that there is no second matching node, according to the index number to be written and the group number to be written, this node to be written is normally written into the model as the initial node of the multi-linked list in the same Set.

[0144] It should be noted that when it is determined that there is no first matching node, it cannot be determined from this that the chaining unit must have no functional error.

[0145] So far, the verification unit can verify the functional correctness of the basic chaining unit and the selection unit. The verification of the linked list node load data converted by the chaining unit is performed by function simulation. The verification model simulates the cache storage part according to the expected specifications of the circuit design under test, and responds to write / replace / read and invalid requests, and performs corresponding data operations respectively. Among them, the response to write / replace is carried out according to the operation on the entry in the verification unit flowchart as Figure 10 shown.

[0146] In some alternative ways of this embodiment, as Figure 5 shown, the circuit under verification further includes an address query unit, and the functional verification method further includes:

[0147] In response to receiving an invalidation request from a second sampling point, based on a preset address query model, determine an erasure address corresponding to the invalidation request, where the preset address query model is a model implementation of the address query unit;

[0148] Based on the erasure address, perform erasure on the linked list cache model to obtain a first erasure result;

[0149] Obtain a second erasure result of the linked list cache from a fifth sampling point, where the fifth sampling point is set at a position corresponding to the erasure address in the linked list cache, and the second erasure result is obtained by the verified circuit performing erasure on the linked list cache based on the erasure address;

[0150] Determine whether the first erasure result is the same as the second erasure result;

[0151] In response to determining that the first erasure result is the same as the second erasure result, determine that there is no functional error in the address query unit;

[0152] In response to determining that the first erasure result is different from the second erasure result, determine that there is a functional error in the address query unit.

[0153] In this embodiment, for the invalid operation, the verification environment models the function of the address query unit according to the design expectation of the circuit under test to obtain a preset address query model. After receiving an invalid request, the preset address query model calculates the matching linked list position information and clears the corresponding nodes in the matching linked list in the preset linked list cache model. It should be noted that the invalid operation can remove one or more nodes at a time. This solution performs a relatively strict chain deletion process in the replacement scenario, rather than only removing the current entry. That is to say, when performing replacement, the entire chain is directly deleted to prevent valid output still being performed when a query hits an invalid node, and it does not support a complete backdoor comparison such as setting the fifth sampling point for each replacement request.

[0154] In some alternative ways of this embodiment, as Figure 5 shown, the verified circuit further includes a query decoding unit, and further includes:

[0155] In response to receiving a query request from a third sampling point, based on a preset query decoding model, determine a query address corresponding to the query request, where the preset query decoding model is a model implementation of the query decoding unit;

[0156] Based on the query address, obtain a first query result from the linked list cache model;

[0157] Obtain a second query result set at a fourth sampling point of the circuit under verification, where the second query result is obtained by the circuit under verification from the linked list cache based on the query address;

[0158] Through an exclusive-OR gate as shown in Figure 5 Determine whether the first query result is the same as the second query result;

[0159] In response to determining that the first query result is different from the second query result, determine that there is a functional error in the query decoding unit or the chain building unit;

[0160] In response to determining that the first query result is the same as the second query result, determine that there is no functional error in the query decoding unit.

[0161] In this embodiment, for the query operation, the verification device models the function of the query decoding unit according to the design expectation of the circuit under test to obtain a preset query decoding model. After receiving a query request, the preset query decoding model first calculates the index information where the linked list node is located, and the calculation method is the same as that of the chain building unit and the address query unit; then finds the head of the linked list in the set and sequentially returns the subsequent node information in the chain building order, and at the same time compares the query result with the query result of the ④ circuit under test item by item. If there is a mismatch, it means that the query results are inconsistent, and after reporting an error, the simulation stops. For the scenario of incorrect query results, it may be introduced by an error in the query decoding unit or an error in the chain building unit. Additionally, if there are errors in the write / replace and invalid operations, such as incorrect write / replace or erase positions, and the write / replace or erase operations fail to update the storage unit successfully, it will also cause a mismatch in the read result during the query, thus indirectly reporting an error to complete the verification.

[0162] It should be noted that during use, the randomness of the incentive can be enhanced by cooperating with functional coverage. Additionally, in the foregoing functional verification method, other verification methods can also be superimposed. For example, fuzzy backdoor comparison for each request can also be added, that is, each time the linked list model is updated, the storage part in the circuit under test is checked using the backdoor, and it is ensured that the nodes existing in the preset linked list cache model must exist in the circuit under test, otherwise an error is reported; and it is ensured that the nodes existing in the circuit under test but not existing in the preset linked list cache model must not be chained, otherwise an error is reported.

[0163] The function verification method for linked list caching provided by the embodiments of the present application uses some internal signals of the circuit under verification and data in a preset linked list caching model for joint constraint verification, and avoids the modeling work of the chain building unit logic and the selector unit logic through the combination of constraint verification and partial function simulation. On the one hand, it can reduce the modeling workload; on the other hand, it can avoid verification omissions that may be caused by directly taking the internal signals of the circuit under verification, thereby improving the verification efficiency while maintaining the verification accuracy.

[0164] In the embodiments of the present application, a function verification device for linked list caching is also provided, as described in the following embodiments. Since the principle of the function verification device for solving problems is similar to that of the function verification method, the implementation of the device can refer to the implementation of the function verification method, and the repeated parts will not be described again.

[0165] As Figure 11 shown, a function verification device for linked list caching includes:

[0166] A first acquisition module 601, configured to acquire the index number to be written, the group number to be written, and the node to be written corresponding to the valid instruction data from a first sampling point set in the circuit under verification, where the circuit under verification includes a chain building unit, a selection unit, and a linked list cache;

[0167] A second acquisition module 602, configured to acquire a data set corresponding to the index number to be written from a preset linked list caching model, where the data set includes data units of all groups corresponding to the index number to be written;

[0168] A first function verification module 603, configured to determine whether there is a function error in the chain building unit or the selection unit based on the index number to be written, the group number to be written, the node to be written, and the data set;

[0169] Wherein, the preset linked list caching model is a model implementation of the linked list cache; the first sampling point is set at the back ends of the chain building unit and the selection unit, and the group number to be written is determined by the selection unit from the linked list cache; the index number to be written and the node to be written are determined by the chain building unit after building and encapsulating the valid instruction data.

[0170] In some alternative ways of this embodiment, the first function verification module includes a selector unit function verification sub-module and a chain building unit function verification sub-module, where the selector unit function verification sub-module is used for:

[0171] Determine whether the data set is empty;

[0172] In response to determining that the data set is empty, write the node to be written into the preset linked list cache model according to the index number to be written and the group number to be written.

[0173] In some alternative embodiments of the present embodiment, the selection unit function verification sub-module is further configured to:

[0174] In response to determining that the data set is not empty, determine whether the data set is not full;

[0175] In response to determining that the data set is not full, determine whether the data unit corresponding to the write position to be written is occupied;

[0176] In response to determining that the data unit corresponding to the write position to be written is occupied, determine that there is a functional error in the selection unit.

[0177] In some alternative embodiments of the present embodiment, the selection unit function verification sub-module is further configured to:

[0178] In response to determining that the data set is full, determine whether the first written node in the data unit corresponding to the write position to be written matches the node to be written;

[0179] In response to determining that the first written node matches the node to be written, determine that there is a functional error in the selection unit.

[0180] In some alternative embodiments of the present embodiment, the link building unit function verification sub-module is configured to:

[0181] In response to determining that the first written node does not match the node to be written, delete the second written node that matches the first written node from the data set to obtain a first valid node;

[0182] Determine whether there is a first matching node that matches the node to be written in the first valid node;

[0183] In response to the existence of the first matching node, determine whether the first matching node and the node to be written are chained;

[0184] In response to determining that the first matching node and the node to be written are chained, replace the first written node with the node to be written;

[0185] In response to determining that the first matching node and the node to be written are not chained, determine that there is a functional error in the link building unit;

[0186] In response to the non-existence of the first matching node, replace the first written node with the node to be written.

[0187] In some alternative embodiments of the present embodiment, the link establishment unit function verification sub-module is configured to:

[0188] In response to determining that the data unit corresponding to the to-be-written position is not occupied, determine the second valid node among the third written nodes in the data set;

[0189] Determine whether there is a second matching node among the second valid nodes that matches the to-be-written node;

[0190] In response to the existence of the second matching node, determine whether the second matching node and the to-be-written node are chained;

[0191] In response to determining that the second matching node and the to-be-written node are chained, write the to-be-written node into the preset linked list cache model according to the to-be-written index number and the to-be-written group number;

[0192] In response to determining that the second matching node and the to-be-written node are not chained, determine that there is a functional error in the link establishment unit;

[0193] In response to the non-existence of the second matching node, write the to-be-written node into the preset linked list cache model according to the to-be-written index number and the to-be-written group number.

[0194] In some alternative embodiments of the present embodiment, the circuit under verification further includes an address query unit, and the function verification device further includes a second function verification module, which is configured to:

[0195] In response to receiving an invalidation request from a second sampling point, determine the erasure address corresponding to the invalidation request based on a preset address query model, where the preset address query model is the model implementation of the address query unit;

[0196] Erase the linked list cache model based on the erasure address to obtain a first erasure result;

[0197] Obtain a second erasure result of the linked list cache from a fifth sampling point, where the fifth sampling point is set at the position corresponding to the erasure address in the linked list cache, and the second erasure result is obtained by the circuit under verification erasing the linked list cache based on the erasure address;

[0198] Determine whether the first erasure result is the same as the second erasure result;

[0199] In response to determining that the first erasure result is the same as the second erasure result, determine that there is no functional error in the address query unit;

[0200] In response to determining that the first erasure result is different from the second erasure result, it is determined that there is a functional error in the address query unit.

[0201] In some alternative embodiments of this embodiment, the circuit to be verified further includes a query decoding unit, and the function verification device further includes a third function verification module for:

[0202] In response to receiving a query request from a third sampling point, based on a preset query decoding model, determine the query address corresponding to the query request, where the preset query decoding model is the model implementation of the query decoding unit;

[0203] Based on the query address, obtain a first query result from the linked list cache model;

[0204] Obtain a second query result set at a fourth sampling point of the circuit to be verified, where the second query result is obtained by the circuit to be verified from the linked list cache based on the query address;

[0205] Determine whether the first query result is the same as the second query result;

[0206] In response to determining that the first query result is different from the second query result, determine that there is a functional error in the query decoding unit or the link building unit;

[0207] In response to determining that the first query result is the same as the second query result, determine that there is no functional error in the query decoding unit.

[0208] According to the embodiments of the present application, the present application also provides a central processing device, an electronic device, and a readable storage medium.

[0209] A central processing device, the central processing device includes a central processing core based on instructions, micro-instructions, and macro-instructions, and the central processing core applies the function verification method for linked list caching in the foregoing embodiments.

[0210] An electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the function verification method for linked list caching in the foregoing embodiments.

[0211] A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the function verification method for linked list caching in the foregoing embodiments.

[0212] Figure 12FIG. shows a schematic block diagram of an exemplary electronic device 900 that may be used to implement embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, for example, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as, for example, personal digital processors, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0213] As Figure 12 shown, the device 900 includes a computing unit 901 that can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0214] A plurality of components in the device 900 are connected to the I / O interface 905, including: an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a magnetic disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0215] The computing unit 901 may be various general-purpose and / or special-purpose processing components having processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 901 executes the various methods and processes described above, such as a functional verification method for a linked list cache.

[0216] For example, in some embodiments, a functional verification method for a linked list cache can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed onto device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by computing unit 901, one or more steps of the functional verification method for the linked list cache described above can be performed. Alternatively, in other embodiments, computing unit 901 may be configured to perform a functional verification method for a linked list cache by any other suitable means (e.g., by means of firmware).

[0217] The various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, field-programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), systems-on-chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0218] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0219] In the context of this disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0220] To provide for interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide for interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic, speech, or tactile input).

[0221] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of a communication network include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0222] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

[0223] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this disclosure can be achieved, and no limitation is imposed herein.

[0224] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the existence of additional identical elements in the process, method, article, or device comprising the said element.

[0225] The above specific embodiments do not constitute a limitation on the protection scope of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the protection scope of this disclosure.

Claims

1. A functional verification method for linked list caching, characterized in that The function verification method includes: Obtaining a to-be-written position and a to-be-written node corresponding to valid instruction data from a first sampling point provided in a circuit to be verified, where the circuit to be verified includes a link establishment unit, a selection unit, and a linked list cache, and the to-be-written position includes a to-be-written index number and a to-be-written group number; Obtaining a data set corresponding to the to-be-written index number from a preset linked list cache model, where the data set includes data units of all groups corresponding to the to-be-written index number; Determining whether there is a functional error in the link establishment unit or the selection unit based on the to-be-written position, the to-be-written node, and the data set; Wherein, the preset linked list cache model is a model implementation of the linked list cache; the first sampling point is provided at the back ends of the link establishment unit and the selection unit, and the to-be-written group number is determined by the selection unit from the linked list cache; the to-be-written index number and the to-be-written node are determined after the link establishment unit encapsulates the valid instruction data into a link; Wherein, determining whether there is a functional error in the selection unit based on the to-be-written position, the to-be-written node, and the data set includes: Determining whether the data set is empty; In response to determining that the data set is not empty, determining whether the data set is not full; In response to determining that the data set is not full, determining whether the data unit corresponding to the to-be-written position is occupied; In response to determining that the data unit corresponding to the to-be-written position is occupied, determining that there is a functional error in the selection unit; Wherein, determining whether there is a functional error in the link establishment unit based on the to-be-written position, the to-be-written node, and the data set includes: In response to determining that the data unit corresponding to the to-be-written position is not occupied, determining a second valid node among third written nodes in the data set; Determining whether there is a second matching node in the second valid nodes that matches the to-be-written node; In response to the existence of the second matching node, determining whether the second matching node and the to-be-written node form a link; In response to determining that the second matching node and the to-be-written node do not form a link, determining that there is a functional error in the link establishment unit.

2. The method according to claim 1, characterized in that, Determining whether there is a functional error in the selection unit based on the to-be-written position, the to-be-written node, and the data set further includes: In response to determining that the data set is empty, writing the to-be-written node into the preset linked list cache model according to the to-be-written index number and the to-be-written group number.

3. The method according to claim 1, characterized in that, Determining whether there is a functional error in the selection unit based on the to-be-written position, the to-be-written node, and the data set further includes: In response to determining that the data set is full, determining whether a first written node in the data unit corresponding to the to-be-written position matches the to-be-written node; In response to determining that the first written node and the to-be-written node match, determining that there is a functional error in the selection unit.

4. The method according to claim 3, wherein Determining whether there is a functional error in the link establishment unit based on the to-be-written position, the to-be-written node, and the data set further includes: In response to determining that the first written node does not match the node to be written, delete the second written node that matches the first written node from the data set to obtain a first valid node; Determine whether there is a first matching node in the first valid node that matches the node to be written; In response to the existence of the first matching node, determine whether the first matching node and the node to be written are chained; In response to determining that the first matching node and the node to be written are chained, replace the first written node with the node to be written; In response to determining that the first matching node and the node to be written are not chained, determine that there is a functional error in the chaining unit; In response to the non-existence of the first matching node, replace the first written node with the node to be written.

5. The method according to claim 1, wherein The determining whether there is a functional error in the chaining unit based on the position to be written, the node to be written, and the data set further includes: In response to determining that the second matching node and the node to be written are chained, write the node to be written into the preset linked list cache model according to the index number to be written and the group number to be written; And in response to the non-existence of the second matching node, write the node to be written into the preset linked list cache model according to the index number to be written and the group number to be written.

6. The method according to claim 1, characterized in that The verified circuit further includes an address query unit, and the function verification method further includes: In response to receiving an invalidation request from a second sampling point, determine the erasure address corresponding to the invalidation request based on a preset address query model, where the preset address query model is a model implementation of the address query unit; Erase the linked list cache model based on the erasure address to obtain a first erasure result; Obtain a second erasure result of the linked list cache from a fifth sampling point, where the fifth sampling point is set at a position corresponding to the erasure address in the linked list cache, and the second erasure result is obtained by the verified circuit erasing the linked list cache based on the erasure address; Determine whether the first erasure result is the same as the second erasure result; In response to determining that the first erasure result is the same as the second erasure result, determine that there is no functional error in the address query unit; In response to determining that the first erasure result is different from the second erasure result, determine that there is a functional error in the address query unit.

7. The method according to claim 1, characterized in that, The verified circuit further includes a query decoding unit, and further includes: In response to receiving a query request from a third sampling point, determine the query address corresponding to the query request based on a preset query decoding model, where the preset query decoding model is a model implementation of the query decoding unit; Obtain a first query result from the linked list cache model based on the query address; Obtain a second query result set at a fourth sampling point of the verified circuit, where the second query result is obtained by the verified circuit querying the linked list cache based on the query address; Determine whether the first query result and the second query result are the same; In response to determining that the first query result is different from the second query result, it is determined that there is a functional error in the query decoding unit or the link establishment unit; In response to determining that the first query result is the same as the second query result, it is determined that there is no functional error in the query decoding unit.

8. A functional verification device for a linked list cache, characterized in that, Comprising: A first acquisition module, configured to acquire a to-be-written position and a to-be-written node corresponding to valid instruction data from a first sampling point provided in a circuit under verification, where the circuit under verification includes a link establishment unit, a selection unit, and a linked list cache, and the to-be-written position includes a to-be-written index number and a to-be-written group number; A second acquisition module, configured to acquire a data set corresponding to the to-be-written index number from a preset linked list cache model, where the data set includes data units of all groups corresponding to the to-be-written index number; A first function verification module, configured to determine whether there is a functional error in the link establishment unit or the selection unit based on the to-be-written position, the to-be-written node, and the data set; Wherein, the preset linked list cache model is a model implementation of the linked list cache; the first sampling point is provided at the back ends of the link establishment unit and the selection unit, and the to-be-written group number is determined by the selection unit from the linked list cache; the to-be-written index number and the to-be-written node are determined after the link establishment unit encapsulates the valid instruction data in a link; Wherein, the first function verification module includes a selection unit function verification sub-module and a link establishment unit function verification sub-module, and the selection unit function verification sub-module is configured to: Determine whether the data set is empty; In response to determining that the data set is not empty, determine whether the data set is not full; In response to determining that the data set is not full, determine whether the data unit corresponding to the to-be-written position is occupied; In response to determining that the data unit corresponding to the to-be-written position is occupied, determine that there is a functional error in the selection unit; Wherein, the link establishment unit function verification sub-module is configured to: In response to determining that the data unit corresponding to the to-be-written position is not occupied, determine a second valid node among third already-written nodes in the data set; Determine whether there is a second matching node in the second valid nodes that matches the to-be-written node; In response to the existence of the second matching node, determine whether the second matching node and the to-be-written node are in a link; In response to determining that the second matching node and the to-be-written node are not in a link, determine that there is a functional error in the link establishment unit.

9. A functional verification system for linked list caching, characterized in that, Comprising the function verification device according to claim 8 and the circuit under verification.

10. A central processing unit, the central processing unit comprising a central processing core based on instructions, microinstructions, and macroinstructions, characterized in that, The central processing core applies the function verification method for linked list cache according to any one of claims 1 to 7.

11. A computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the function verification method for linked list cache according to any one of claims 1 to 7.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the function verification method for linked list cache according to any one of claims 1 to 7.

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