An analog computer chip with an on-chip training system

Abstract

The present invention relates to the field of artificial intelligence technology, and discloses an analog computer chip with an on-chip training system. In the computing structure of the analog computer chip, the input end of the analog computer chip is connected to the output end of the analog computer chip through n-layer memories and n-layer operators, and two adjacent layers of operators are connected through a layer of memory; the on-chip training system includes an error threshold comparator, an n-layer trainer, and an n-layer updater; the output end of the analog computer chip is also connected to the error threshold comparator; the error threshold comparator is used to control the working state of the on-chip training system according to the difference between the actual output value and the expected output value of the output end of the analog computer chip. The on-chip training system is set in the analog computer chip of the present application, and the computing model is generated autonomously, and self-learning updates are performed, thereby improving the accuracy of the artificial intelligence chip and expanding the application scope of the artificial intelligence chip.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to an analog computer chip with an on-chip training system. Background Art

[0002] Artificial intelligence chips in the prior art are generally digital chips, which are usually composed of a graphics processor, a field programmable gate array, and other digital circuits.

[0003] However, since the computing units of the graphics processors in the prior art all use digital computing, the computing units in the artificial intelligence chips in the prior art usually require tens of thousands to hundreds of thousands of transistors, so that the artificial intelligence chips in the prior art can usually only contain thousands of computing units, which makes the computing power of the artificial intelligence chips limited. At the same time, the computing model in the artificial intelligence chips in the prior art is usually input from the outside. Therefore, when the artificial intelligence chip is used, the computing model can only be a fixed model input from the outside, and it cannot be updated by self-learning, which leads to low accuracy and narrow application range of the artificial intelligence chip. Summary of the invention

[0004] In view of this, the present application provides an analog computer chip with an on-chip training system, which improves the accuracy and scope of application of artificial intelligence chips. The technical solution is as follows.

[0005] In a first aspect, an analog computer chip with an on-chip training system is provided, wherein the analog computer chip includes a computing structure and an on-chip training system;

[0006] In the operation structure, the input end of the analog computer chip is connected to the output end of the analog calculator chip through n-layer memories and n-layer operators, and two adjacent layers of operators are connected through one layer of memory; the transfer function relationship between the input end of the memory and the output end of the memory corresponds to the parameters of the memory;

[0007] The on-chip training system comprises an error threshold comparator, an n-layer trainer and an n-layer updater; the output end of the analog computer chip is also connected to the error threshold comparator; the error threshold comparator is used to control the working state of the on-chip training system according to the difference between the actual output value and the expected output value of the output end of the analog computer chip;

[0008] The t-th layer trainer is used to generate the update parameters of the t-th layer and transmit them to the t-th layer updater according to the actual output value of the t-th layer memory, the actual output value of the t-th layer operator and the expected output value of the t-th layer operator; the t-th layer updater is used to update the parameters of the t-th layer memory according to the update parameters of the t-th layer, where n≥t≥1.

[0009] In a possible implementation, the error threshold comparator includes a plurality of comparison subcircuits; the plurality of comparison subcircuits are the same in number as the plurality of output interfaces at the output end of the analog calculator chip, and correspond one to one; each comparison subcircuit is used to compare an actual output value of a corresponding output interface with an expected output value of the corresponding output interface;

[0010] The output end of each comparison sub-circuit is connected to the input end of the first follower through the corresponding comparison resistor; the output end of the first follower is connected to the non-inverting input end of the fourth operational amplifier; the inverting input end of the fourth operational amplifier is connected to the error threshold voltage; the output end of the fourth operational amplifier is the output end of the error threshold comparator.

[0011] In a possible implementation, the comparison subcircuit includes a fifth operational amplifier, a first inverter, a sixth operational amplifier, and a first switch;

[0012] The expected output value of the output interface corresponding to the comparison subcircuit is connected to the non-inverting input terminal of the fifth operational amplifier; the actual output value of the output interface corresponding to the comparison subcircuit is connected to the inverting input terminal of the fifth operational amplifier;

[0013] The output end of the fifth operational amplifier is connected to the first node of the first switch; the output end of the fifth operational amplifier is also connected to the second node of the first switch through the first inverter; the output end of the fifth operational amplifier is also connected to the non-inverting input end of the sixth operational amplifier; the inverting input end of the sixth operational amplifier is grounded; the third node of the first switch is the output end of the comparison sub-circuit;

[0014] The output end of the sixth operational amplifier is connected to the control end of the first switch; when the output end of the sixth operational amplifier is at a high level, the first node of the first switch is connected to the third node; when the output end of the sixth operational amplifier is at a low level, the second node of the first switch is connected to the third node.

[0015] In a possible implementation, the number of the t-th layer trainers is the same as that of the t-th layer memories and they correspond one to one; the updated voltage value output by each trainer is used to update the parameters of the corresponding memory.

[0016] In one possible implementation, the transfer function relationship between the input end of the memory and the output end of the memory corresponds to the storage data of the non-volatile storage unit in the memory; the updater of the tth layer is used to update the storage data of the non-volatile storage unit in the corresponding memory according to the update voltage value output by each trainer of the tth layer.

[0017] In a possible implementation, the trainer includes a correction parameter extractor, an initial parameter extractor, and a seventh operational amplifier;

[0018] The initial parameter extractor is used to extract and output the initial value of the parameter of the memory corresponding to the trainer; the revised parameter extractor is used to extract and output the revised value of the parameter of the memory corresponding to the trainer;

[0019] The output end of the initial parameter extractor is connected to the non-inverting input end of the seventh operational amplifier; the output end of the revised parameter extractor is connected to the inverting input end of the seventh operational amplifier; the output end of the seventh operational amplifier is used to output the updated voltage value.

[0020] In a possible implementation, the initial parameter extractor includes a first resistor, a second resistor, a third resistor, a fourth resistor, and an eighth operational amplifier;

[0021] The inverting input terminal of the eighth operational amplifier is connected to the first fixed voltage through the third resistor; the non-inverting input terminal of the eighth operational amplifier is connected to the second fixed voltage through the second resistor; the second fixed voltage is greater than the first fixed voltage; the non-inverting input terminal of the eighth operational amplifier is also grounded through the first resistor; the inverting input terminal of the eighth operational amplifier is also connected to the output terminal of the eighth operational amplifier through the fourth resistor; the output terminal of the eighth operational amplifier is the output terminal of the initial parameter extractor;

[0022] The topological structure of the memory corresponding to the initial parameter extractor and the trainer, the parameters of each resistor and the parameters of the operational amplifier are all the same.

[0023] In a possible implementation, the correction parameter extractor includes a first subtraction circuit, a second subtraction circuit, and a first multiplier;

[0024] The first input end of the first multiplier is connected to the output end of the first subtraction circuit; the second input end of the first multiplier is connected to the output end of the second subtraction circuit; the third input end of the first multiplier is connected to the output end of the initial parameter extractor; the output end of the first multiplier is the output end of the modified parameter extractor;

[0025] The first subtraction circuit includes a tenth operational amplifier; the inverting input terminal of the tenth operational amplifier is connected to the first fixed voltage of the memory corresponding to the trainer; the non-inverting input terminal of the tenth operational amplifier is connected to the input voltage of the memory corresponding to the trainer; the output terminal of the tenth operational amplifier is connected to the first input terminal of the first multiplier;

[0026] The second subtraction circuit includes an eleventh operational amplifier, a twelfth operational amplifier and a thirteenth operational amplifier;

[0027] The in-phase input terminal of the twelfth operational amplifier is connected to the actual output value of the first target operator; the inverting input terminal of the twelfth operational amplifier is connected to the actual output value of the memory corresponding to the trainer; the first target operator is the operator connected to the output terminal of the memory corresponding to the trainer;

[0028] The non-inverting input terminal of the thirteenth operational amplifier is connected to the expected output value of the first target operator; the inverting input terminal of the thirteenth operational amplifier is connected to the output terminal of the twelfth operational amplifier;

[0029] The output terminal of the thirteenth operational amplifier is connected to the inverting input terminal of the eleventh operational amplifier; the non-inverting input terminal of the eleventh operational amplifier is connected to the output terminal of the tenth operational amplifier; the output terminal of the eleventh operational amplifier is connected to the second input terminal of the first multiplier.

[0030] In a possible implementation, the on-chip training system further includes an n-1 layer expected output value generator;

[0031] After the updater of the p+1th layer updates the parameters of the p+1th layer memory, the expected output value generator of the pth layer is used to generate the expected output values ​​of each operator of the pth layer according to the expected output values ​​of each operator of the p+1th layer and the actual output values ​​of each memory of the p+1th layer after the updated parameters; the number of the expected output value generators of the pth layer is the same as the number of operators of the pth layer, and they correspond one to one; wherein n-1≥p≥1.

[0032] In a possible implementation, the expected output value of the n-th layer operator is the expected output value of the output end of the analog computer chip.

[0033] In a possible implementation, each expected output value generator includes a plurality of generating subcircuits, and the number of generating subcircuits in each expected output value generator of the p-th layer is the same as the number of operators of the p+1-th layer, and they correspond one to one;

[0034] In the target expected output value generator of the p-th layer, the output end of each generating sub-circuit is connected to the input end of the second follower through the corresponding generating resistor; the output end of the second follower is the output end of the expected output value generator.

[0035] In a possible implementation, in the target generation subcircuit of the target expected output value generator of the p-th layer, each target output voltage is connected to the non-inverting input terminal of the fifteenth operational amplifier through a corresponding storage resistor; each target output voltage is an output voltage of a memory other than the target memory of the p+1-th layer, which is connected to the second target operator in the p+1-th layer, after updating parameters;

[0036] The inverting input terminal of the fifteenth operational amplifier is grounded through a seventeenth resistor; the inverting input terminal of the fifteenth operational amplifier is also connected to the output terminal of the fifteenth operational amplifier through an eighteenth resistor; the output terminal of the fifteenth operational amplifier is connected to the inverting input terminal of the sixteenth operational amplifier; the non-inverting input terminal of the sixteenth operational amplifier is connected to the expected output value of the second target operator in the p+1th layer operator;

[0037] The output end of the sixteenth operational amplifier is connected to the first input end of the first divider; the voltage value corresponding to the updated parameter of the target memory is input to the second input end of the first divider; the output end of the first divider is connected to the non-inverting input end of the seventeenth operational amplifier through the nineteenth resistor; the first fixed voltage is connected to the non-inverting input end of the seventeenth operational amplifier through the twentieth resistor;

[0038] The inverting input terminal of the seventeenth operational amplifier is grounded through a twenty-first resistor; the inverting input terminal of the seventeenth operational amplifier is also connected to the output terminal of the seventeenth operational amplifier through a twenty-second resistor; the output terminal of the seventeenth operational amplifier is the output terminal of the target generation sub-circuit;

[0039] The second target operator is an operator in the p+1th layer of operators corresponding to the target generation subcircuit; the target memory is a memory between the second target operator in the p+1th layer and the third target operator in the pth layer; the third target operator in the pth layer is an operator in the pth layer of operators corresponding to the target expected output value generator; the target generation subcircuit is used to obtain the expected input value of the target memory.

[0040] The technical solution provided by this application may have the following beneficial effects:

[0041] The present application provides an analog computer chip with an on-chip training system, wherein the operation unit is composed of a memory and an operator, and the operation unit is composed of analog devices to perform analog operations, so that a single operation unit of the analog computer chip only requires a very small number of analog devices to realize the operation, thereby reducing the size of the single operation unit, improving the computing power of the artificial intelligence chip, and reducing the power consumption of the analog computer chip; and because the memory and the operator are both composed of analog devices, the analog computer chip in the present application has sufficient space to set up an on-chip training system while meeting the computing power. Therefore, at this time, an on-chip training system can be set in the analog computer chip of the present application to autonomously generate a computing model and perform self-learning updates, thereby improving the accuracy of the artificial intelligence chip and expanding the application scope of the artificial intelligence chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 is a schematic structural diagram of an analog computer chip with an on-chip training system according to an exemplary embodiment;

[0044] Figure 2 A network architecture diagram of an upstream structure of a simulated computer chip involved in an embodiment of the present application is shown;

[0045] Figure 3 A schematic diagram of the structure of a memory involved in an embodiment of the present application is shown;

[0046] Figure 4 A schematic diagram of the structure of an operator involved in an embodiment of the present application is shown;

[0047] Figure 5 A circuit structure diagram of an error threshold comparator involved in an embodiment of the present application is shown;

[0048] Figure 6 A circuit structure diagram of a comparison subcircuit in an error threshold comparator is shown;

[0049] Figure 7 A circuit structure diagram of a training device involved in an embodiment of the present application is shown;

[0050] Figure 8 A schematic diagram of the circuit structure of an initial parameter extractor involved in an embodiment of the present application is shown;

[0051] Fig. 9 A schematic diagram of the circuit structure of a correction parameter extractor involved in an embodiment of the present application is shown;

[0052] Fig.10 A schematic diagram of the structure of a first subtraction circuit involved in an embodiment of the present application is shown;

[0053] Fig.11 A schematic diagram of the structure of a second subtraction circuit involved in an embodiment of the present application is shown;

[0054] Fig.12 A schematic diagram of the structure of an expected output value generator involved in an embodiment of the present application is shown;

[0055] Fig.13 A schematic diagram of the structure of a generating sub-circuit involved in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0057] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between two items, or an association relationship between the two items, or a relationship between indication and being indicated, configuration and being configured, and the like.

[0058] Figure 1 It is a schematic diagram of the structure of an analog computer chip with an on-chip training system according to an exemplary embodiment.

[0059] The network architecture of the analog computer chip with an on-chip training system in the present application is a bidirectional structure, and the analog computer chip includes an operation structure and an on-chip training system, wherein the operation structure is an uplink structure and the on-chip training system is a downlink structure.

[0060] like Figure 1 As shown, in the operation structure, the input end of the analog computer chip is connected to the output end of the analog calculator chip through n-layer memories and n-layer operators, and two adjacent layers of operators are connected through one layer of memory; the transfer function relationship between the input end of the memory and the output end of the memory corresponds to the parameters of the memory;

[0061] The on-chip training system includes an error threshold comparator, an n-layer trainer, and an n-layer updater; the output end of the analog computer chip is also connected to the error threshold comparator; the error threshold comparator is used to control the working state of the on-chip training system according to the difference between the actual output value and the expected output value of the output end of the analog computer chip;

[0062] The t-layer trainer is used to generate update parameters of the t-layer according to the actual output value of the t-layer memory, the actual output value of the t-layer operator and the expected output value of the t-layer operator, and transmit them to the t-layer updater; the t-layer updater is used to update the parameters of the t-layer memory according to the update parameters of the t-layer, where n≥t≥1.

[0063] Specifically, Figure 1 As shown, in the on-chip training system, the trainers from the 1st layer to the n-1th layer are correspondingly provided with expected output value generators, that is, the on-chip training system is also provided with an expected output value generator of the n-1th layer, and when the updater of the p+1th layer updates the parameters of the p+1th layer memory, the expected output value generator of the pth layer is used to generate the expected output values ​​of each operator of the pth layer according to the expected output values ​​of each operator of the p+1th layer and the actual output values ​​of each memory of the p+1th layer after the parameter update; the number of the expected output value generators of the pth layer is the same as the number of operators of the pth layer, and they correspond one to one; wherein n-1≥p≥1.

[0064] And the expected output value of the operator in the nth layer is also input into the expected output value generator in the n-1th layer (the expected output value of the operator in the nth layer is the expected output value of the output end of the analog computer chip). Similarly, the output of the expected output value generator in each layer is not only input into the trainer in the corresponding layer, but also into the expected output value generator in the previous layer. However, the expected output value obtained by the expected output value generator in the first layer is only input into the trainer in the first layer.

[0065] First, in the embodiments of the present application, the upstream structure in the analog computer chip is introduced.

[0066] like Figure 2 As shown, it shows a network architecture diagram of the uplink structure of the analog computer chip involved in the embodiment of the present application.

[0067] The uplink structure, that is, the computing structure of the analog computer chip, also includes the input and output ends of the analog calculator chip; the input end of the analog calculator chip includes a plurality of input interfaces in1, in2, in3, etc., and external data is input into the analog computer chip through the plurality of input interfaces; each input interface is connected to each operator in the first layer of operators through different memories in the first layer of memories;

[0068] Each operator in the yth layer of operators is connected to each operator in the y+1th layer of operators through different memories in the y+1th layer of memories; where n-1≥y≥1;

[0069] The output end of the analog calculator chip also includes a plurality of output interfaces (respectively used to output out1, out2, out3, ...); the number of the output interfaces is the same as the number of operators in the n-th layer of operators; the plurality of output interfaces are connected one-to-one with each operator in the n-th layer of operators.

[0070] That is, external data is input into the analog computer chip, and after being calculated by the first layer memory and the first layer operator (including operator 11, operator 12 and operator 13, etc.), the calculation result is input into the second layer memory and the second layer operator (including operator 21, operator 22 and operator 23, etc.) for calculation, and so on, after being calculated by n layers of memory and operators, the calculation result of the nth layer operator (including operator n1, operator n2 and operator n3, etc.) is output through a plurality of output interfaces at the output end;

[0071] The number of input interfaces, the number of first-layer operators, the number of second-layer operators, and even the number of n-layer operators may be the same or different. Meanwhile, the number of n-layer operators is the same as the number of output interfaces.

[0072] In the embodiment of the present application, the transfer function relationship between the input terminal of the memory and the output terminal of the memory corresponds to the parameters of the memory, that is, the memory can convert the voltage input to the input terminal according to the transfer function corresponding to the parameters of the memory and then output it. Figure 3 , which shows a schematic diagram of the structure of a memory involved in an embodiment of the present application. Figure 3 As shown, VIN is the input voltage of the memory, the input voltage VIN is the independent variable x of the function, VOUT is the output voltage of the memory, the output voltage is input into the same layer operator, the output voltage VOUT is the dependent variable y of the function, VR is the first fixed voltage input to the memory, the first fixed voltage VR is the constant c of the function, the memory is composed of an operational amplifier with a non-infinite gain, and the gain of the operational amplifier can be obtained by calculation or measurement. It can be seen that when the resistance value of the first resistor R1 is equal to the resistance value of the fourth resistor R4, the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3, and when the gain of the first operational amplifier A1 is represented by AZ, Figure 3 The memory shown , that is, at this time, Expressed in W, the transfer function is ;

[0073] At this time, when the memory in the embodiment of the present application is as follows Figure 3 The transfer function of the circuit structure shown is , so at this time, changing the value of parameter W can adjust the transfer function. Figure 3 The resistance values ​​of the first resistor R1 and the fourth resistor R4 in the Figure 3 The transfer function can be adjusted by adjusting the resistance values ​​of the second resistor R2 and the third resistor R3. Therefore, at this time, the non-volatile memory unit can be used as a resistor, that is, the first resistor R1 and the fourth resistor R4, or the second resistor R2 and the third resistor R3 are all composed of non-volatile memory units. At this time, the resistance value of the non-volatile memory unit can be changed by adjusting the storage data of the non-volatile memory unit (such as the floating gate charge of the MOS tube of the non-volatile memory unit), so as to obtain the transfer function required by the memory.

[0074] correspond Figure 3 The memory structure shown in the embodiment of the present application also provides an operator structure, so that the operator can sum the input values ​​of each memory connected to the input end of the operator to realize the function of an adder. Please refer to Figure 4 , which shows a schematic diagram of the structure of an operator involved in an embodiment of the present application. Figure 4 As shown, V1 and V2 are voltages of the output terminals of the memories connected to the input terminals of the operator, the fifth resistor R5 and the sixth resistor R6 have the same resistance value, the seventh resistor R7 and the eighth resistor R8 have the same resistance value, VD is the output voltage of the operator, and VD is input to the next layer of memory connected to the operator;

[0075] And, the voltage quantity outputted to the operator by the same layer memory is given by Figure 2 The network architecture of the mid-upstream structure determines that the two voltages V1 and V2 are only examples.

[0076] By the attached Figure 4 It can be seen that after the voltage output from the same layer memory to the operator is input into the second operational amplifier A2, the voltage at the non-inverting input terminal of the second operational amplifier A2 is At this time, according to the virtual-off characteristic of the operational amplifier, the voltage at the inverting input terminal of the second operational amplifier A2 is , and from the virtual short characteristics of the operational amplifier, we know that , so we can get ;

[0077] It can be seen that according to the network architecture of the upstream structure, the number of voltages output by the same layer of memory to the operator can be known, and the corresponding setting is , it is ensured that the output voltage VD of the operator is equal to the sum of the voltages output to the operator by the same layer of memory, and the output voltage VD of the operator is used as the input voltage VIN of the next layer of memory.

[0078] In the above-mentioned uplink structure, since it includes n layers of operators and n layers of memories, and two adjacent layers of operators are connected by a layer of memory, in the working process of the uplink structure of the analog computer chip, after receiving the input data, each layer of operators can process the input data through different memories respectively, so as to transfer it to the operators of the next layer until the output value of the analog computer chip is obtained. In the uplink structure of the analog computer chip, since the transfer function of the memory between the two layers of operators can change within a certain range with the parameters, as long as there is a specific output target, the parameters of each memory are continuously adjusted, so that the uplink structure of the analog computer chip can show the mapping relationship between specific input data and specific output data. Therefore, the uplink structure of the analog computer chip has characteristics similar to the neural network model, and can process the input data after the parameters are adjusted to obtain an output result that is close to the expected output value.

[0079] In order to achieve the above purpose, the analog computer chip in the embodiment of the present application also includes an on-chip training system (that is, a downlink structure) to implement parameter updates for the computing structure (that is, an uplink structure) of the analog computer chip. The downlink structure (that is, the on-chip training system) in the embodiment of the present application includes an output terminal, an error threshold comparator, a trainer, an updater, an expected output value generator, and an expected output value input terminal. The downlink structure involved in the embodiment of the present application is specifically introduced below.

[0080] Please refer to Figure 5 , which shows a circuit structure diagram of an error threshold comparator involved in an embodiment of the present application. Figure 5 As shown, the error threshold comparator includes a plurality of comparison subcircuits, for example, the plurality of comparison subcircuits include comparison subcircuits 1 to comparison subcircuits i; the plurality of comparison subcircuits are the same in number as the plurality of output interfaces at the output end of the analog calculator chip, and correspond one to one; each comparison subcircuit is used to compare the actual output value of the corresponding output interface with the expected output value of the corresponding output interface;

[0081] The output end of each comparison sub-circuit is connected to the input end of the first follower through the corresponding comparison resistor; the output end of the first follower is connected to the non-inverting input end of the fourth operational amplifier; the inverting input end of the fourth operational amplifier is connected to the error threshold voltage; the output end of the fourth operational amplifier is the output end of the error threshold comparator.

[0082] like Figure 5As shown, the two input terminals of the comparison subcircuit 1 are respectively connected to the actual output value out1 of the corresponding output interface and the expected output value 1 of the corresponding output interface. At this time, the output terminal of the comparison subcircuit 1 is connected to the input terminal of the first follower through the corresponding comparison resistor (the ninth resistor R9 at this time);

[0083] The two input terminals of the comparison subcircuit 2 are respectively connected to the actual output value out2 of the corresponding output interface and the expected output value 2 of the corresponding output interface; at this time, the output terminal of the comparison subcircuit 2 is connected to the input terminal of the first follower through the corresponding comparison resistor (the tenth resistor R10 at this time);

[0084] By analogy, the two input terminals of the comparison sub-circuit i are respectively connected to the actual output value outi of the corresponding output interface and the expected output value i of the corresponding output interface; at this time, the output terminal of the comparison sub-circuit i is connected to the input terminal of the first follower through the corresponding comparison resistor (the eleventh resistor R11 at this time).

[0085] Optional, such as Figure 5 As shown, the first follower is composed of a third operational amplifier A3, and the inverting input terminal of the third operational amplifier A3 is connected to the output terminal of the third operational amplifier A3.

[0086] For further information, please refer to Figure 6 , which shows the circuit structure diagram of the comparison subcircuit in the error threshold comparator. Figure 6 As shown, the comparison sub-circuit includes a fifth operational amplifier A5, a first inverter F1, a sixth operational amplifier A6 and a first switch S1;

[0087] The expected output value of the output interface corresponding to the comparison subcircuit is connected to the non-inverting input terminal of the fifth operational amplifier A5; the actual output value of the output interface corresponding to the comparison subcircuit is connected to the inverting input terminal of the fifth operational amplifier A5;

[0088] The output terminal of the fifth operational amplifier A5 is connected to the first node of the first switch S1; the output terminal of the fifth operational amplifier A5 is also connected to the second node of the first switch S1 through the first inverter F1; the output terminal of the fifth operational amplifier A5 is also connected to the non-inverting input terminal of the sixth operational amplifier A6; the inverting input terminal of the sixth operational amplifier A6 is grounded; the third node of the first switch S1 is the output terminal of the comparison sub-circuit;

[0089] The output end of the sixth operational amplifier A6 is connected to the control end of the first switch S1; when the output end of the sixth operational amplifier A6 is at a high level, the first node of the first switch S1 is connected to the third node; when the output end of the sixth operational amplifier A6 is at a low level, the second node of the first switch is connected to the third node.

[0090] Combine the following Figure 6 ,right Figure 5 The working principle of the error threshold comparator is described in detail:

[0091] The expected output value input terminal inputs i expected output values ​​equal to the number of output interfaces into the error threshold comparator, and each expected output value corresponds to the actual output value of the output interface one by one. At this time, Figure 6 It can be seen that each expected output value and the actual output value are input into the fifth operational amplifier A5, and in the embodiment of the present application, the gain of the fifth operational amplifier A5 is designed to be 1, so at this time, the output value of the fifth operational amplifier A5 is the difference between the expected output value and the actual output value. When the difference is greater than or equal to 0, the sixth operational amplifier A6 outputs a high level, the first switch S1 is directly connected to the output end of the fifth operational amplifier A5, and the comparison subcircuit outputs the difference. When the difference is less than 0, the sixth operational amplifier A6 outputs a low level, the first switch S1 is connected to the output end of the fifth operational amplifier A5 through the first inverter F1, and the comparison subcircuit outputs the opposite value of the difference. Therefore, the output value of the comparison subcircuit is the difference between the expected output value and the actual output value, and the difference is also the error value after the upstream structure operation is completed. At the same time, the error value output by the comparison subcircuit is always a positive voltage value, thereby ensuring the correctness of the subsequent logic;

[0092] At this time, return to Figure 5 It can be seen that the output values ​​VP1, VP2, ..., VPi of each comparison sub-circuit are input into the follower formed by the third operational amplifier A3 through comparison resistors of the same size. Therefore, at this time, the voltage at the non-inverting input terminal of the third operational amplifier A3 is , the voltage at the inverting input of the third operational amplifier A3 is , from the virtual short characteristics of the operational amplifier, we know that ;

[0093] It can be seen that the output voltage VPS of the third operational amplifier A3 is the average value of the errors between each expected output value and its corresponding actual output value, and the average value of the error is a positive voltage value. At this time, the voltage VPS is input into the fourth operational amplifier A4 and compared with the error threshold voltage VPD. When the voltage VPS is less than the error threshold voltage VPD, the fourth operational amplifier A4 outputs a low level, and each trainer stops working, that is, when the output voltage VP of the error threshold comparator is a low level, it is considered that the model training has reached the target and the training is stopped. When the voltage VPS is greater than or equal to the error threshold voltage VPD, the fourth operational amplifier A4 outputs a high level, and each trainer continues to work, that is, when the output voltage VP of the error threshold comparator is a high level, it is considered that the error of the actual output value of the upstream structure relative to the expected output value is still large, and the model training needs to be continued.

[0094] In the embodiment of the present application, the number of the t-th layer trainers and the t-th layer memory is the same and corresponds one to one; the update voltage value output by each trainer is used to update the parameters of the corresponding memory, that is, one memory corresponds to one trainer. Figure 2 For example, if Figure 2 Each layer has 9 memories, so the number of trainers in each layer is also 9. Figure 5 In the memory shown, non-volatile memory cells are used as resistors. At this time, the transfer function relationship between the input end of the memory and the output end of the memory corresponds to the storage data of the non-volatile memory cells in the memory; at this time, the updater of the tth layer is used to update the storage data of the non-volatile memory cells in the corresponding memory according to the output update voltage value of each trainer of the tth layer.

[0095] Please refer to Figure 7 , which shows a circuit structure diagram of a training device involved in an embodiment of the present application. Figure 7 As shown, the trainer includes a correction parameter extractor, an initial parameter extractor and a seventh operational amplifier A7;

[0096] The initial parameter extractor is used to extract and output the initial value VW of the parameter of the memory corresponding to the trainer; the correction parameter extractor is used to extract and output the correction value VX of the parameter of the memory corresponding to the trainer;

[0097] The output end of the initial parameter extractor is connected to the non-inverting input end of the seventh operational amplifier A7; the output end of the modified parameter extractor is connected to the inverting input end of the seventh operational amplifier A7; and the output end of the seventh operational amplifier A7 is used to output the updated voltage value VG.

[0098] Since the initial parameter extractor is used to extract the initial value VW of the parameter to be updated, and the modified parameter extractor is used to extract the modified value VX of the parameter to be updated, at this time, the initial value VW and the modified value VX are input into the seventh operational amplifier A7 with a gain of 1, and the updated voltage value can be obtained. .

[0099] Please refer to Figure 8 , which shows a schematic diagram of the circuit structure of an initial parameter extractor involved in an embodiment of the present application. Figure 8 As shown, the initial parameter extractor includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and an eighth operational amplifier A8;

[0100] The inverting input terminal of the eighth operational amplifier A8 is connected to the first fixed voltage VR through the third resistor R3; the non-inverting input terminal of the eighth operational amplifier is connected to the second fixed voltage VR1 through the second resistor; the second fixed voltage VR1 is greater than the first fixed voltage VR; the non-inverting input terminal of the eighth operational amplifier A8 is also grounded through the first resistor R1; the inverting input terminal of the eighth operational amplifier A8 is also connected to the output terminal of the eighth operational amplifier A8 through the fourth resistor R4; the output terminal of the eighth operational amplifier A8 is the output terminal of the initial parameter extractor;

[0101] The topological structure of the memory, the parameters of each resistor and the parameters of the operational amplifier corresponding to the initial parameter extractor and the trainer are all the same.

[0102] Each memory corresponds to an initial parameter extractor, wherein the eighth operational amplifier A8 in the initial parameter extractor has the same parameters as the first operational amplifier A1 in the memory, and the gains are both AZ. The resistance parameters and settings in the initial parameter extractor and the memory are also exactly the same. The first fixed voltage VR of the initial parameter extractor is also the same as the first fixed voltage VR of the memory, and the second fixed voltage VR1 of the initial parameter extractor is equal to VR+1. Therefore, it can be obtained that the initial value output by the initial parameter extractor is , it can be seen that the initial value VW output by the initial parameter extractor is the voltage value corresponding to the parameter W of the memory transfer function;

[0103] Taking the nth layer as an example, assuming that the expected output values ​​of the nth layer operators are , , … , the actual output values ​​of the nth layer operators are , … , so the error between each expected output value of the n-th layer operator and each actual output value of the n-th layer operator can be expressed as: At this time, by the attached Figure 2 From the network architecture of the middle and upper structures, we can see that ;

[0104] Therefore, the error , at this time, The following calculation method is explained. Specifically, except The values ​​of other parameters except for EL are substituted into the error EL, and the formula of error EL is obtained. After that, Substitute the initial parameter value into the derived formula and we get The corresponding derivative value Similarly, the derivative values ​​corresponding to other W parameters are obtained in turn. At the same time, in order to take into account both training speed and training accuracy, it is also necessary to set the correction coefficient , the correction factor is a constant, so at this time, we can get Corresponding correction value ;

[0105] From the above analysis, we can see that except Substitute the values ​​of other parameters except After taking the derivative;

[0106] Available, .

[0107] Among them, i is a known fixed value when designing the circuit, for The parameter corresponds to the input voltage value of the memory. is the value of the first fixed voltage VR, is the expected output value of the operator at this layer corresponding to the memory, is the sum of the outputs of all memories connected to the operator in this layer except the corresponding memory. is the initial parameter of the corresponding memory; therefore, the correction value can be obtained .

[0108] Please refer to Fig. 9 , which shows a schematic diagram of the circuit structure of a correction parameter extractor involved in an embodiment of the present application. Fig. 9 As shown, the correction parameter extractor includes a first subtraction circuit, a second subtraction circuit and a first multiplier A9;

[0109] The first input end of the first multiplier A9 is connected to the output end of the first subtraction circuit; the second input end of the first multiplier is connected to the output end of the second subtraction circuit; the third input end of the first multiplier A9 is connected to the output end of the initial parameter extractor; the output end of the first multiplier A9 is the output end of the modified parameter extractor.

[0110] Please refer to Fig.10 , which shows a schematic diagram of the structure of a first subtraction circuit involved in an embodiment of the present application. The first subtraction circuit includes a tenth operational amplifier A10; the inverting input terminal of the tenth operational amplifier A10 is connected to the first fixed voltage of the memory corresponding to the trainer; the non-inverting input terminal of the tenth operational amplifier A10 is connected to the input voltage of the memory corresponding to the trainer; the output terminal of the tenth operational amplifier A10 is connected to the first input terminal of the first multiplier A9.

[0111] Fig.11 A schematic structural diagram of a second subtraction circuit involved in an embodiment of the present application is shown.

[0112] The second subtraction circuit includes an eleventh operational amplifier A11, a twelfth operational amplifier A12, and a thirteenth operational amplifier A13;

[0113] The in-phase input terminal of the twelfth operational amplifier A12 is connected to the actual output value of the first target operator; the inverting input terminal of the twelfth operational amplifier A12 is connected to the actual output value of the memory corresponding to the trainer; the first target operator is the operator connected to the output terminal of the memory corresponding to the trainer;

[0114] The non-inverting input terminal of the thirteenth operational amplifier A13 is connected to the expected output value of the first target operator; the inverting input terminal of the thirteenth operational amplifier A13 is connected to the output terminal of the twelfth operational amplifier A12;

[0115] The output of the thirteenth operational amplifier A13 is connected to the inverting input of the eleventh operational amplifier A11; the non-inverting input of the eleventh operational amplifier A11 is connected to the output of the tenth operational amplifier A10; the output of the eleventh operational amplifier A11 is connected to the second input of the first multiplier.

[0116] like Fig.10 As shown, VIN is the input voltage of the corresponding memory, VR is the first fixed voltage of the corresponding memory, and the gain of the tenth operational amplifier A10 is 1. Therefore, the output voltage VJ1 of the first subtraction circuit is The value of

[0117] like Fig.11 As shown, VJ1 is The value of VD is the actual output value of the operator in this layer connected to the corresponding memory, and VOUT1 is the actual output value of the corresponding memory. Therefore, after the gain of the twelfth operational amplifier A12 is designed to be 1, the output voltage of the twelfth operational amplifier A12 is the sum of the actual output values ​​of other memories connected to the operator in this layer except the corresponding memory. At this time, the output end of the twelfth operational amplifier A12 inputs the inverting input end of the thirteenth operational amplifier A13, and the non-inverting input end of the thirteenth operational amplifier A13 inputs the expected output value of the operator in this layer connected to the corresponding memory. Therefore, at this time, the output voltage of the thirteenth operational amplifier A13 is Therefore, when the output terminal of the thirteenth operational amplifier A13 is connected to the inverting input terminal of the eleventh operational amplifier A11, the output voltage of the eleventh operational amplifier A11, that is, the output voltage of the second subtraction circuit ;

[0118] From the above analysis, it can be seen that when VJ1, VJ2 and VW are all input into the first multiplier A9, and when the multiplication coefficient of the first multiplier A9 is designed to be When the output voltage of the first multiplier A9, that is, the correction value output by the correction parameter extractor, is ;

[0119] At this time, return to Figure 7 It can be seen that the updated voltage value output by the trainer is That is, the voltage value corresponding to the W value after the transfer function is updated. The updated voltage value VG is input into the corresponding updater to update the parameters of the corresponding memory.

[0120] Combined with the above analysis, it can be seen that the update voltage value VG output by the trainer is input into the corresponding updater, and the updater adjusts the storage data of the corresponding non-volatile storage unit according to the size of the update voltage value VG, such as the floating gate charge of the MOS tube of the non-volatile storage unit, thereby changing the size of the corresponding resistance to achieve the adjustment of the transfer function W value;

[0121] The updater in the embodiment of the present application adopts the adjustment circuit of the non-volatile storage unit in the prior art, which will not be repeated in this application; at the same time, the number of updaters in each layer in the present application can be one, or it can correspond one-to-one with the memory of this layer, and the number is the same.

[0122] In the embodiment of the present application, the expected output values ​​of the operators in each layer except the operator in the nth layer are obtained through the expected output value generator. Taking the expected output value generator in the pth layer as an example, after the updater in the p+1 layer updates all the parameters in the p+1 layer memory, the p-layer expected output value generator starts to work, and generates the expected output value of the p-layer operator according to the expected output value of the p+1 layer operator and the actual output value of the memory after the p+1 layer parameter update. The expected output value of the p-layer operator is input into the p-layer trainer to train the transfer function of the p-layer memory. The expected output value of the p-layer operator is also input into the p-1 layer expected output value generator to generate the expected output value of the p-1 layer operator.

[0123] Specifically, each updated parameter value is brought into the transfer function of each memory of the p+1th layer, and then according to each expected output value of the p+1th layer operator, the corresponding expected input value of each memory of the p+1th layer is obtained. The expected input value of each memory of the p+1th layer is the expected output value of each p-th layer operator.

[0124] Based on the above principles, Fig.12 As shown, it shows a structural schematic diagram of an expected output value generator involved in an embodiment of the present application.

[0125] like Fig.12As shown, taking the expected output value generator of the p-th layer as an example, each of the expected output value generators includes a plurality of generating subcircuits, such as a first generating subcircuit, a second generating subcircuit, ..., an M-th generating subcircuit, and the number of generating subcircuits in each expected output value generator of the p-th layer is the same as the number of operators of the p+1-th layer, and they correspond one to one, that is, the value of M of the generating subcircuit is the number of operators of the p+1-th layer corresponding to the expected output value generator;

[0126] In the target expected output value generator of the pth layer, the output end of each generating sub-circuit is connected to the input end of the second follower through the corresponding generating resistor (for example, including the twelfth resistor R12, the thirteenth resistor R13 and the fourteenth resistor R14); the output end of the second follower is the output end of the expected output value generator.

[0127] Optionally, the second follower is composed of a fourteenth operational amplifier A14, in which case the input end of the second follower is the non-inverting input end of the fourteenth operational amplifier A14, and the inverting input end of the fourteenth operational amplifier A14 is connected to the output end of the fourteenth operational amplifier A14.

[0128] By the attached Figure 2 It can be seen that the number of p+1-layer memories connected to each operator of the P layer is the same as the number of p+1-layer operators, that is, if the number of p+1-layer operators is M, then each operator of the P layer is connected to M p+1-layer memories. It can be seen that the output voltages VY1, VY2...VYM respectively related to the expected input values ​​of the M p+1-layer memories (the M p+1-layer memories are connected to the same operator of the p layer) can be obtained through the first generation subcircuit, the second generation subcircuit...the Mth generation subcircuit. Specifically, VY1=the expected input value of memory 1, VY2=the expected input value of memory 2, VYM=the expected input value of memory M, so at this time, the output voltage obtained by the expected output value generator is , the output voltage VY of the expected output value generator can be considered to be the expected output value of the operator of the p layer connected to the M p+1 layer memories;

[0129] It can be seen that the p-layer operators correspond one-to-one to the p-layer expected output value generators. Therefore, the number of operators in the p-layer needs to be the same as the number of expected output value generators.

[0130] Combination Figure 2For example, if the expected output value of the operator 11 needs to be calculated at this time, the expected input value of the memory between the operator 11 and the operator 21 needs to be obtained through the first generation subcircuit, the expected input value of the memory between the operator 11 and the operator 22 needs to be obtained through the second generation subcircuit, and the expected input value of the memory between the operator 11 and the operator 23 needs to be obtained through the third generation subcircuit;

[0131] The expected input value of the memory between the operator 11 and the operator 21 is calculated by first subtracting the output value of the memory between the operator 12 and the operator 21 after the parameters are updated from the expected output value of the operator 21, and then subtracting the output value of the memory between the operator 13 and the operator 21 after the parameters are updated, thereby obtaining the output value of the memory between the operator 11 and the operator 21 after the parameters are updated, and then using the formula It can be seen that the expected input value of the memory is ,in, is the parameter after the memory between the operator 11 and the operator 21 is updated. Therefore, the generation subcircuit in the present application can be obtained according to this method;

[0132] Please refer to Fig.13 , which shows a schematic diagram of the structure of a generation subcircuit involved in an embodiment of the present application. Fig.13 As shown, in the target generation subcircuit of the target expected output value generator of the p-th layer, each target output voltage is connected to the non-inverting input terminal of the fifteenth operational amplifier A15 through a corresponding storage resistor; each target output voltage is an output voltage after the parameters of the memory other than the target memory of the p+1-th layer, which is connected to the second target operator in the p+1-th layer, are updated;

[0133] The inverting input terminal of the fifteenth operational amplifier A15 is grounded through the seventeenth resistor R17; the inverting input terminal of the fifteenth operational amplifier A15 is also connected to the output terminal of the fifteenth operational amplifier A15 through the eighteenth resistor R18; the output terminal of the fifteenth operational amplifier A15 is connected to the inverting input terminal of the sixteenth operational amplifier A16; the non-inverting input terminal of the sixteenth operational amplifier A16 is connected to the expected output value of the second target operator in the p+1th layer operator;

[0134] The output end of the sixteenth operational amplifier A16 is connected to the first input end of the first divider A18; the voltage value corresponding to the updated parameter of the target memory is input to the second input end of the first divider A18; the output end of the first divider A18 is connected to the non-inverting input end of the seventeenth operational amplifier A17 through the nineteenth resistor R19; the first fixed voltage VR is connected to the non-inverting input end of the seventeenth operational amplifier A17 through the twentieth resistor R20;

[0135] The inverting input terminal of the seventeenth operational amplifier A17 is grounded through a twenty-first resistor R21; the inverting input terminal of the seventeenth operational amplifier A17 is also connected to the output terminal of the seventeenth operational amplifier through a twenty-second resistor R22; the output terminal of the seventeenth operational amplifier A17 is the output terminal of the target generation sub-circuit;

[0136] The second target operator is the operator in the p+1th layer of operators corresponding to the target generation subcircuit; the target memory is the memory between the second target operator in the p+1th layer and the third target operator in the pth layer; the third target operator in the pth layer is the operator in the pth layer of operators corresponding to the target expected output value generator; the target generation subcircuit is used to obtain the expected input value of the target memory.

[0137] Combination Fig.13 For example, the target output voltage includes and wait, and = is the output voltage of the memory (hereinafter referred to as other memory) in the p+1th layer memory, which is connected to the second target operator in the p+1th layer, but excluding the target memory (the memory between the second target operator in the p+1th layer and the third target operator in the pth layer) after the parameters are updated (wherein the input voltage of other memory adopts the input voltage when the uplink structure was last run), and the number of other memories excluding the target memory is the number of operators in the pth layer minus 1. At this time The corresponding storage resistor is the fifteenth resistor R15; at this time The corresponding storage resistor is the sixteenth resistor R16 (in the embodiment of the present application, multiple target output voltages and corresponding storage resistors may also be included, Fig.13 China-Israel and as an example).

[0138] Therefore, the resistance values ​​of the seventeenth resistor R17 and the eighteenth resistor R18 are designed according to the number of the other memories, so that the output voltage of the fifteenth operational amplifier A15 is equal to the sum of the output voltages of the other memories after the parameters are updated; at the same time, the expected output value of the second target operator in the p+1th layer operator is input to the in-phase input terminal of the sixteenth operational amplifier A16, so at this time, the output of the sixteenth operational amplifier A16 is the expected output value of the target memory after the parameters are updated. At this time, the updated parameters of the target memory are input into the first divider A18. The corresponding voltage value , then the resistance values ​​of the nineteenth resistor R19 and the twentieth resistor R20 are designed to be equal, and the resistance values ​​of the twenty-first resistor R21 and the twenty-second resistor R22 are designed to be equal, so the output voltage VY1 of the seventeenth operational amplifier A17 is the expected input value of the target memory;

[0139] It can be seen from this that since the number of operators in the p+1 layer is M, each operator in the P layer is connected to M memories in the p+1 layer. Therefore, by setting up M of the above-mentioned generating subcircuits accordingly, the expected input values ​​of the M memories in the p+1 layer can be obtained, that is, the expected output value VY of an operator in the pth layer can be obtained through the expected output value generator. At this time, by setting the same number of expected output value generators as the operators in the pth layer, the expected output value of each operator in the pth layer can be obtained.

[0140] Therefore, from the above analysis, it can be seen that the trainer, updater and expected output value generator in the downstream structure work forward layer by layer, so that each memory in the upstream structure can be updated through self-learning;

[0141] At the same time, by Figure 3 It can be seen that since the memory is composed of an operational amplifier, the output voltage VOUT of the memory should be between the positive input power supply and the negative input power supply of the operational amplifier. Generally speaking, the positive input power supply of the operational amplifier is a conventional power supply such as 5V or 3.3V, and the negative input power supply is GND, that is, 0V. At this time, assuming that the positive input power supply is 5V, it can be obtained that the accurate transfer function of the memory is However, during actual training, in order to simplify the circuit, the limitations of the positive and negative input power supplies on the transfer function were not considered. Obviously, at this time, the error can be adjusted back by increasing the number of training times. Therefore, not considering the limitations of the positive and negative input power supplies on the transfer function will not affect the accuracy of the artificial intelligence chip. Although the number of training times will increase, it will obviously greatly reduce the circuit volume in the downstream structure.

[0142] In summary, the present application provides an analog computer chip with an on-chip training system, wherein the operation unit is composed of a memory and an operator, and the operation unit is composed of analog devices to perform analog operations, so that a single operation unit of the analog computer chip only requires a very small number of analog devices to realize the operation, thereby reducing the volume of a single operation unit, improving the computing power of the artificial intelligence chip, and reducing the power consumption of the analog computer chip;

[0143] And because the memory and the operator are both composed of analog devices, the analog computer chip in this application has sufficient space to set up an on-chip training system while meeting the computing power requirements. Therefore, at this time, an on-chip training system can be set up in the analog computer chip of this application to autonomously generate a computing model and perform self-learning updates, thereby improving the accuracy of the artificial intelligence chip and expanding the application scope of the artificial intelligence chip.

[0144] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. An analog computer chip with an on-chip training system, characterized in that: Analog computer chips include computing structures and on-chip training systems; In the operation structure, the input end of the analog computer chip is connected to the output end of the analog calculator chip through n-layer memory and n-layer operator, and two adjacent layers of operators are connected through one layer of memory; the transfer function relationship between the input end of the memory and the output end of the memory corresponds to the parameters of the memory; The on-chip training system includes an error threshold comparator, an n-layer trainer, and an n-layer updater; the output end of the analog computer chip is also connected to the error threshold comparator; the error threshold comparator is used to control the working state of the on-chip training system according to the difference between the actual output value and the expected output value of the output end of the analog computer chip; The t-th layer trainer is used to generate the update parameters of the t-th layer according to the actual output value of the t-th layer memory, the actual output value of the t-th layer operator and the expected output value of the t-th layer operator, and transmit them to the t-th layer updater; the t-th layer updater is used to update the parameters of the t-th layer memory according to the update parameters of the t-th layer, wherein n≥t≥1; The trainer includes a revised parameter extractor, an initial parameter extractor, and a seventh operational amplifier; The initial parameter extractor is used to extract and output the initial values ​​of the parameters of the memory corresponding to the trainer; The correction parameter extractor is used to extract and output the correction value of the parameter of the memory corresponding to the trainer; The output terminal of the initial parameter extractor is connected to the non-inverting input terminal of the seventh operational amplifier; The output terminal of the correction parameter extractor is connected to the inverting input terminal of the seventh operational amplifier; the output terminal of the seventh operational amplifier is used to output an update voltage value to update the parameters of the corresponding memory.

2. The analog computer chip according to claim 1, characterized in that: The error threshold comparator includes a plurality of comparison subcircuits; the plurality of comparison subcircuits are the same in number as the plurality of output interfaces at the output end of the analog calculator chip, and correspond one to one; each comparison subcircuit is used to compare the actual output value of the corresponding output interface with the expected output value of the corresponding output interface; The output end of each comparison sub-circuit is connected to the input end of the first follower through the corresponding comparison resistor; the output end of the first follower is connected to the non-inverting input end of the fourth operational amplifier; the inverting input end of the fourth operational amplifier is connected to the error threshold voltage; the output end of the fourth operational amplifier is the output end of the error threshold comparator.

3. The analog computer chip according to claim 2, characterized in that: The comparison subcircuit includes a fifth operational amplifier, a first inverter, a sixth operational amplifier and a first switch; The non-inverting input terminal of the fifth operational amplifier is connected to the expected output value of the output interface corresponding to the comparison sub-circuit; The inverting input terminal of the fifth operational amplifier is connected to the actual output value of the output interface corresponding to the comparison sub-circuit; The output end of the fifth operational amplifier is connected to the first node of the first switch; the output end of the fifth operational amplifier is also connected to the second node of the first switch through the first inverter; the output end of the fifth operational amplifier is also connected to the non-inverting input end of the sixth operational amplifier; the inverting input end of the sixth operational amplifier is grounded; the third node of the first switch is the output end of the comparison sub-circuit; The output end of the sixth operational amplifier is connected to the control end of the first switch; when the output end of the sixth operational amplifier is at a high level, the first node of the first switch is connected to the third node; when the output end of the sixth operational amplifier is at a low level, the second node of the first switch is connected to the third node.

4. The analog computer chip according to claim 1, characterized in that: The number of the t-th layer trainers is the same as that of the t-th layer memories and they correspond one to one; the updated voltage value output by each trainer is used to update the parameters of the corresponding memory.

5. The analog computer chip according to claim 4, characterized in that: The transfer function relationship between the input end of the memory and the output end of the memory corresponds to the storage data of the non-volatile storage unit in the memory; the updater of the tth layer is used to update the storage data of the non-volatile storage unit in the corresponding memory according to the update voltage value output by each trainer of the tth layer.

6. The analog computer chip according to claim 5, characterized in that: The initial parameter extractor includes a first resistor, a second resistor, a third resistor, a fourth resistor and an eighth operational amplifier; The inverting input terminal of the eighth operational amplifier is connected to the first fixed voltage through the third resistor; the non-inverting input terminal of the eighth operational amplifier is connected to the second fixed voltage through the second resistor; the second fixed voltage is greater than the first fixed voltage; the non-inverting input terminal of the eighth operational amplifier is also grounded through the first resistor; the inverting input terminal of the eighth operational amplifier is also connected to the output terminal of the eighth operational amplifier through the fourth resistor; the output terminal of the eighth operational amplifier is the output terminal of the initial parameter extractor; The topological structure of the memory corresponding to the initial parameter extractor and the trainer, the parameters of each resistor and the parameters of the operational amplifier are all the same.

7. The analog computer chip according to claim 5, characterized in that: The correction parameter extractor includes a first subtraction circuit, a second subtraction circuit and a first multiplier; The first input end of the first multiplier is connected to the output end of the first subtraction circuit; the second input end of the first multiplier is connected to the output end of the second subtraction circuit; the third input end of the first multiplier is connected to the output end of the initial parameter extractor; the output end of the first multiplier is the output end of the modified parameter extractor; The first subtraction circuit includes a tenth operational amplifier; the inverting input terminal of the tenth operational amplifier is connected to the first fixed voltage of the memory corresponding to the trainer; the non-inverting input terminal of the tenth operational amplifier is connected to the input voltage of the memory corresponding to the trainer; the output terminal of the tenth operational amplifier is connected to the first input terminal of the first multiplier; The second subtraction circuit includes an eleventh operational amplifier, a twelfth operational amplifier and a thirteenth operational amplifier; The in-phase input terminal of the twelfth operational amplifier is connected to the actual output value of the first target operator; the inverting input terminal of the twelfth operational amplifier is connected to the actual output value of the memory corresponding to the trainer; the first target operator is the operator connected to the output terminal of the memory corresponding to the trainer; The non-inverting input terminal of the thirteenth operational amplifier is connected to the expected output value of the first target operator; The inverting input terminal of the thirteenth operational amplifier is connected to the output terminal of the twelfth operational amplifier; The output terminal of the thirteenth operational amplifier is connected to the inverting input terminal of the eleventh operational amplifier; the non-inverting input terminal of the eleventh operational amplifier is connected to the output terminal of the tenth operational amplifier; the output terminal of the eleventh operational amplifier is connected to the second input terminal of the first multiplier.

8. The analog computer chip according to any one of claims 1 to 7, characterized in that: The on-chip training system also includes an n-1 layer expected output value generator; After the updater of the p+1th layer updates the parameters of the memory of the p+1th layer, the expected output value generator of the pth layer is used to generate the expected output values ​​of each operator of the pth layer according to the expected output values ​​of each operator of the p+1th layer and the actual output values ​​of each memory of the p+1th layer after the updated parameters; The number of expected output value generators in the p-th layer is the same as the number of operators in the p-th layer, and corresponds one to one; wherein n-1≥p≥1.

9. The analog computer chip according to claim 8, characterized in that: The expected output value of the nth layer operator is the expected output value of the output terminal of the analog computer chip.

10. The analog computer chip according to claim 9, characterized in that: Each expected output value generator includes a plurality of generating subcircuits, and the number of generating subcircuits in each expected output value generator of the p-th layer is the same as the number of operators of the p+1-th layer, and they correspond one to one; In the target expected output value generator of the p-th layer, the output end of each generating sub-circuit is connected to the input end of the second follower through the corresponding generating resistor; the output end of the second follower is the output end of the expected output value generator.

11. The analog computer chip according to claim 10, characterized in that: In the target generation subcircuit of the target expected output value generator of the p-th layer, each target output voltage is connected to the non-inverting input terminal of the fifteenth operational amplifier through a corresponding storage resistor; each target output voltage is an output voltage of a memory other than the target memory of the p+1-th layer, which is connected to the second target operator in the p+1-th layer, after updating parameters; The inverting input terminal of the fifteenth operational amplifier is grounded through a seventeenth resistor; the inverting input terminal of the fifteenth operational amplifier is also connected to the output terminal of the fifteenth operational amplifier through an eighteenth resistor; the output terminal of the fifteenth operational amplifier is connected to the inverting input terminal of the sixteenth operational amplifier; the non-inverting input terminal of the sixteenth operational amplifier is connected to the expected output value of the second target operator in the p+1th layer operator; The output end of the sixteenth operational amplifier is connected to the first input end of the first divider; the voltage value corresponding to the updated parameter of the target memory is input to the second input end of the first divider; the output end of the first divider is connected to the non-inverting input end of the seventeenth operational amplifier through the nineteenth resistor; the first fixed voltage is connected to the non-inverting input end of the seventeenth operational amplifier through the twentieth resistor; The inverting input terminal of the seventeenth operational amplifier is grounded through a twenty-first resistor; the inverting input terminal of the seventeenth operational amplifier is also connected to the output terminal of the seventeenth operational amplifier through a twenty-second resistor; the output terminal of the seventeenth operational amplifier is the output terminal of the target generation sub-circuit; The second target operator is an operator in the p+1th layer of operators corresponding to the target generation subcircuit; the target memory is a memory between the second target operator in the p+1th layer and the third target operator in the pth layer; the third target operator in the pth layer is an operator in the pth layer of operators corresponding to the target expected output value generator; the target generation subcircuit is used to obtain the expected input value of the target memory.

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