A method for generating a model of a simulated computer chip

Abstract

The present invention relates to the field of artificial intelligence technology, and discloses a method for generating a model of a simulated computer chip. The method includes: obtaining a training data set; iteratively updating a neural network model according to the training data set until an iteration condition is met, so as to obtain target parameter values of various transfer functions in the neural network model; wherein, the neural network model includes n layers of computing nodes, and any computing node in each layer of computing nodes is connected to each node in the upper layer through different transfer functions; the target parameter values of the transfer functions between the computing nodes are used to correspondingly set the parameters of the computing units between the adders in the model of the simulated computer chip, thereby generating the model of the simulated computer chip; the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model. The above solution enables the simulated computer chip to have stronger computing power and faster computing speed when having the same volume.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and particularly relates to a method for generating a model of an analog computer chip. Background Art

[0002] With the rise of artificial intelligence technology, artificial intelligence chips that can implement certain specific functions have received extensive attention and applications.

[0003] However, the artificial intelligence chips in the prior art are usually digital computer chips, which are generally composed of a graphics processing unit, a field programmable gate array, and other module circuits. Therefore, the arithmetic units in the artificial intelligence chips in the prior art are digital arithmetic units. A single arithmetic unit in an artificial intelligence chip requires a large number of transistors. For example, each arithmetic unit may have tens of thousands of transistors, and usually there are only thousands of arithmetic units in the model of the artificial intelligence chips in the prior art. At this time, if it is necessary to perform calculations on tens of thousands or even hundreds of millions of data simultaneously, a large number of artificial intelligence chips must be used to perform calculations on the data in parallel.

[0004] Therefore, in the above solution, when using a digital computer chip as an artificial intelligence chip, there are disadvantages such as a large volume, slow speed, and high power consumption. Summary of the Invention

[0005] In view of this, the present invention provides a method for generating a model of an analog computer chip, which overcomes the disadvantages of large volume, slow speed, and high power consumption of artificial intelligence chips.

[0006] In a first aspect, the present invention provides a method for generating a model of an analog computer chip, and the method includes:

[0007] Obtain a training data set;

[0008] Iteratively update a neural network model according to the training data set until an iteration condition is satisfied, so as to obtain target parameter values of various transfer functions in the neural network model;

[0009] The neural network model includes n layers of arithmetic nodes, and any arithmetic node in each layer of arithmetic nodes is connected to each node in the upper layer through different transfer functions; the target parameter values of the transfer functions between the arithmetic nodes are used to correspondingly set the parameters of the arithmetic units between each adder in the model of the analog computer chip, so as to generate a model of the analog computer chip;

[0010] Wherein, the model of the analog computer chip includes n layers of adder layers, and any adder in each layer of adder layers is connected to each adder in the upper layer of adder layers through different arithmetic units; the topological structure of the model of the analog computer chip is the same as the topological structure of the neural network model.

[0011] In an alternative embodiment, the training data set includes input data and label values; the label values are the expected output values of the output nodes of the neural network model after inputting the input data into the neural network model.

[0012] Iteratively updating the neural network model according to the training data set includes:

[0013] Inputting the input data into the neural network model to obtain the actual operation value of the neural network model.

[0014] Updating the parameters of each transfer function in the neural network model according to the error between the actual operation value and the label value.

[0015] In an alternative embodiment, before iteratively updating the neural network model according to the training data set, it further includes:

[0016] Obtaining the topological structure of the model of the analog computer chip and the circuit structure of the arithmetic unit.

[0017] Determining the connection relationship of each operation node in the neural network model according to the topological structure of the model of the analog computer chip.

[0018] Determining the formula of the transfer function in the neural network model according to the circuit structure of the arithmetic unit.

[0019] In an alternative embodiment, the neural network model further includes an output layer; the output nodes in the output layer are connected to the last layer of operation nodes in one-to-one correspondence; the output nodes are used to output the actual output value of the last layer of operation nodes as the actual operation value of the neural network model.

[0020] In an alternative embodiment, updating the parameters of each transfer function in the neural network model according to the error between the actual operation value and the label value includes:

[0021] Obtaining the node error between the actual output value and the expected output value of each operation node in the j-th layer; 2 ≥ j ≥ n.

[0022] Taking the node error between the actual output value and the expected output value of each operation node in the j-th layer as the dependent variable, and taking the parameters of each transfer function between the (j - 1)-th layer of operation nodes and the j-th layer of operation nodes as independent variables respectively for derivation, to obtain the derivative values corresponding to each transfer function between the (j - 1)-th layer of operation nodes and the j-th layer of operation nodes.

[0023] Based on the update coefficient and the derivative values corresponding to the transfer functions between the operation nodes of the (j - 1)-th layer and the operation nodes of the j-th layer, update the parameters of the transfer functions between the operation nodes of the (j - 1)-th layer and the operation nodes of the j-th layer respectively;

[0024] According to the updated transfer functions between the operation nodes of the (j - 1)-th layer and the operation nodes of the j-th layer, and the expected output values of the operation nodes of the j-th layer, calculate the expected output values of the operation nodes of the (j - 1)-th layer.

[0025] In an alternative embodiment, there are k operation nodes in the j-th layer; where k ≥ 1;

[0026] The calculating the expected output values of the operation nodes of the (j - 1)-th layer according to the updated transfer functions between the operation nodes of the (j - 1)-th layer and the operation nodes of the j-th layer, and the expected output values of the operation nodes of the j-th layer includes:

[0027] For any target node in the operation nodes of the (j - 1)-th layer, obtain k updated values of the target node according to the transfer functions between the target node and the k operation nodes in the j-th layer, and the expected output values of the k operation nodes in the j-th layer;

[0028] Take the mean value of the k updated values of the target node as the expected output value of the target node.

[0029] In an alternative embodiment, the upper layer nodes of the operation nodes of the first layer include each input node;

[0030] The method further includes:

[0031] Obtain the node error between the actual output value and the expected output value of each operation node of the first layer;

[0032] Take the node error between the actual output value and the expected output value of each operation node of the first layer as the dependent variable, and take the parameters of the transfer functions between each input node and each operation node of the first layer as independent variables respectively to perform derivative calculation, and obtain the derivative values corresponding to the transfer functions between each input node and each operation node of the first layer;

[0033] Based on the update coefficient and the derivative values corresponding to the transfer functions between each input node and each operation node of the first layer, update the parameters of the transfer functions between each input node and each operation node of the first layer respectively.

[0034] In an alternative embodiment, the method further includes:

[0035] Set the output values of the respective transfer functions greater than or equal to the first threshold to the first threshold, and set the output values of the respective transfer functions less than or equal to the second threshold to the second threshold; the first threshold is greater than the second threshold.

[0036] In an alternative embodiment, the transfer function is:

[0037]

[0038] where x is the input value of the transfer function; y is the output value of the transfer function; W is the first adjustable parameter of the transfer function; c is a constant; VV is the first threshold of the transfer function; 0 is the second threshold of the transfer function.

[0039] In an alternative embodiment, the transfer function is:

[0040]

[0041] where x is the input value of the transfer function; y is the output value of the transfer function; B is the second adjustable parameter of the transfer function; A22 is the gain constant; VV is the first threshold of the transfer function; 0 is the second threshold of the transfer function.

[0042] In an alternative embodiment, the iteration condition includes at least one of the following:

[0043] The number of iterations is greater than a preset number;

[0044] The error between the actual output value and the label value of the neural network model is less than the error preset threshold.

[0045] In a possible embodiment, before iteratively updating the neural network model according to the training data set until the iteration condition is satisfied, it further includes:

[0046] Obtain an initial parameter set; the initial parameter set includes the initial parameter values of the respective transfer functions;

[0047] Set the parameters of the respective transfer functions to the corresponding initial parameter values.

[0048] In a possible embodiment, the initial parameter values of the respective transfer functions are preset;

[0049] Alternatively, the initial parameter values of the respective transfer functions are randomly selected within a specified range.

[0050] In a possible embodiment, the method further includes:

[0051] Obtain a validation data set; the validation data set includes validation data and corresponding label values;

[0052] Process the validation data through the iteratively updated neural network model to obtain validation prediction values;

[0053] According to the validation prediction values and the label values corresponding to the validation data, obtain the prediction accuracy of the neural network model.

[0054] In a possible implementation, the method further includes,

[0055] Determine the addresses of the arithmetic units corresponding to the transfer functions between the respective arithmetic nodes;

[0056] According to the target parameter values of the transfer functions between the respective arithmetic nodes, set the parameters of the arithmetic units between the respective adders in the model of the analog computer chip according to the addresses of the arithmetic units corresponding to the transfer functions, so as to generate a model of the analog computer chip.

[0057] In a possible implementation, a non-volatile storage unit is provided in the arithmetic unit;

[0058] The step of setting the parameters of the arithmetic units between the respective adders in the model of the analog computer chip according to the target parameter values of the transfer functions between the respective arithmetic nodes, according to the addresses of the arithmetic units corresponding to the transfer functions, so as to generate a model of the analog computer chip, includes:

[0059] According to the target parameter values of the transfer functions between the respective arithmetic nodes, set the stored data of the non-volatile storage units in the arithmetic units between the respective adders in the model of the analog computer chip according to the addresses of the arithmetic units corresponding to the transfer functions, so as to generate a model of the analog computer chip.

[0060] In a second aspect, the present invention provides a device for generating a model of an analog computer chip, the device including:

[0061] A dataset acquisition module, configured to acquire a training dataset;

[0062] A training module, configured to iteratively update a neural network model according to the training dataset until an iteration condition is satisfied, so as to obtain the target parameter values of the respective transfer functions in the neural network model;

[0063] The neural network model includes n layers of arithmetic nodes, and any arithmetic node in each layer of arithmetic nodes is connected to each node in the upper layer through different transfer functions; the target parameter values of the transfer functions between the respective arithmetic nodes are used to correspondingly set the parameters of the arithmetic units between the respective adders in the model of the analog computer chip, thereby generating a model of the analog computer chip;

[0064] Among them, the model of the analog computer chip includes n addition layers, and any adder in each addition layer is connected to each adder in the upper addition layer through different arithmetic units; the topological structure of the model of the analog computer chip is the same as the topological structure of the neural network model.

[0065] In a possible implementation manner, the device further includes:

[0066] An address determination module, configured to determine the addresses of the arithmetic units corresponding to the transfer functions between the respective arithmetic nodes;

[0067] A parameter setting module, configured to set the parameters of the arithmetic units between the respective adders in the model of the analog computer chip according to the target parameter values of the transfer functions between the respective arithmetic nodes and according to the addresses of the arithmetic units corresponding to the transfer functions, so as to generate a model of the analog computer chip.

[0068] In a third aspect, the present invention provides a computer device, including: a memory and a processor, which are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to execute the method for generating a model of an analog computer chip according to the first aspect or any corresponding implementation manner thereof.

[0069] In a fourth aspect, the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute the method for generating a model of an analog computer chip according to the first aspect or any corresponding implementation manner thereof.

[0070] In a fifth aspect, the present invention provides a computer program product, including computer instructions, and the computer instructions are used to cause a computer to execute the method for generating a model of an analog computer chip according to the first aspect or any corresponding implementation manner thereof.

[0071] In summary, the present application provides a method for generating a model of a simulated computer chip, which uses an external computer in combination with the simulated computer chip. An artificial intelligence model is trained in the external computer, and then the stored data of the non-volatile storage units of each arithmetic unit in the model of the simulated computer chip is set and adjusted according to the parameters of the artificial intelligence model, so as to set and adjust the parameters of the arithmetic unit, thereby generating a model of the simulated computer chip, and the model of the simulated computer chip can implement the same or similar functions as the trained artificial intelligence model. At the same time, since the arithmetic units in the present application are all composed of analog circuits, in the case of the same chip volume, the generated model of the simulated computer chip has tens of thousands or even hundreds of millions of arithmetic units, greatly improving the computing power of the artificial intelligence chip, and can perform calculations on tens of thousands or even hundreds of millions of data simultaneously, so that the simulated computer chip has stronger computing power and faster computing speed at the same volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0073] Figure 1 is a flowchart of a method for generating a model of a simulated computer chip according to an embodiment of the present invention;

[0074] Figure 2 shows an application schematic diagram of a neural network model involved in an embodiment of the present application;

[0075] Figure 3 shows a schematic flowchart of a method for generating a model of a simulated computer chip involved in an embodiment of the present application;

[0076] Figure 4 shows a topological structure diagram of a model of a simulated computer chip involved in an embodiment of the present application;

[0077] Figure 5 shows a schematic circuit structure diagram of a first arithmetic unit involved in an embodiment of the present application;

[0078] Figure 6 shows a schematic circuit structure diagram of a second arithmetic unit involved in an embodiment of the present application;

[0079] Figure 7 is a schematic diagram of an adjustment circuit corresponding to the circuit structure of the first arithmetic unit;

[0080] Figure 8 It is a schematic structural diagram of a model generation device for simulating a computer chip;

[0081] Figure 9 It is a schematic hardware structure diagram of the computer device according to the embodiment of the present invention. Detailed implementation manners

[0082] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0083] This application provides a method for generating a model of a simulated computer chip. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0084] In this embodiment, a method for generating a model of a simulated computer chip is provided. In this model generation method, first, according to the application scenario corresponding to the simulated computer chip, a neural network model (i.e., an artificial intelligence model) is trained, and then, according to the parameters of the trained neural network model, the parameters of the operation units between the adders in the model of the simulated computer chip are adjusted, so as to generate a model of the simulated computer chip. At this time, the model of the simulated computer chip can represent the connection relationship between modules such as adders and operation units of the finally generated simulated computer chip, as well as the specific parameters of each module in the simulated computer chip.

[0085] The training process of the above neural network model can be executed by a computer device with high computing performance such as a server or a personal computer; and the adjustment of the parameters of the operation units between the adders in the model of the simulated computer chip can be realized by a specially designed adjustment circuit.

[0086] Figure 1 It is a flowchart of the method for generating a model of a simulated computer chip according to the embodiment of the present invention. As Figure 1 shown, the process includes the following steps:

[0087] Step 101, obtain a training data set.

[0088] Among them, the training data set includes input data and label values; optionally, the input data may be data in one of the fields such as machine translation, speech recognition, image recognition, and text-to-image generation, and the label value is the expected output value of the output node of the neural network model after the input data is input into the neural network model. Optionally, the label value may be obtained by manual annotation after relevant technical personnel perform recognition processing on the input data.

[0089] At this time, according to the application scenario of the simulated computer chip, input data that meets the processing conditions of the neural network model is selected. For example, when the computer chip needs to perform recognition processing on image data, the image data can be converted according to a specified rule (such as through normalization, etc.) to obtain input data that meets the processing conditions of the neural network model. At this time, the input data can be input into the computer device where the neural network model is deployed as the training data required for the computer device to perform neural network model training.

[0090] Step 102, iteratively update the neural network model according to the training data set until the iteration condition is met to obtain the target parameter values of each transfer function in the neural network model.

[0091] The application scenario of the simulated computer chip is relatively wide and can be applied to fields such as machine translation, speech recognition, image recognition, or text-to-image generation. However, no matter what scenario the simulated computer chip is applied to, as long as the corresponding input data is input into the simulated computer chip, the corresponding output data should necessarily be obtained. Therefore, the neural network model corresponding to the simulated computer chip should also have the same function. As Figure 2 shown, it shows an application schematic diagram of the neural network model involved in the embodiments of the present application. After the input data in the training data set is used as training data and input into the neural network model, the ideal output data obtained should be equal to the label value. However, the actual output data of the neural network model often differs from the label value. Therefore, according to the error between the label value and the actual output data, the neural network model can be trained so that the actual output result of the trained neural network model is closer to the label value.

[0092] In the embodiments of the present application, the neural network model includes n layers of operation nodes, and any operation node in each layer of operation nodes is connected to each node in the upper layer through different transfer functions.

[0093] At this time, during the operation of the neural network model, after each operation node receives the input data, it can process the input data through different transfer functions respectively, and then transfer it to the operation nodes of the next layer until the output value of the neural network model is obtained. In this neural network model, since the target parameters of the transfer functions between two layers of nodes can vary within a certain range, during the training process, adjusting the target parameters of each transfer function in the neural network model can enable the neural network model to fit various mapping relationships between input data and output data, so that the neural network model can process the input data and obtain an output result close to the label value.

[0094] Correspondingly, the model of this analog computer chip includes n adder layers, and any adder in each adder layer is connected to each adder in the upper adder layer through different arithmetic units.

[0095] Step 103: Determine the addresses of the arithmetic units corresponding to the transfer functions between these operation nodes.

[0096] Step 104: According to the target parameter values of the transfer functions between these operation nodes, set the parameters of the arithmetic units between each adder in the model of this analog computer chip according to the addresses of the arithmetic units corresponding to the transfer functions, so as to generate the model of the analog computer chip.

[0097] In the embodiments of this application, the target parameter values of the transfer functions between each operation node are used to correspondingly set the parameters of the arithmetic units between each adder in the model of the analog computer chip, so as to generate the model of the analog computer chip.

[0098] That is to say, the topological structure of the model of this analog computer chip is the same as that of the neural network model. Since the trained neural network model can process the input data and obtain an output result close to the label value, and since the topological structure of the model of the analog computer chip is the same as that of the neural network model, at this time, only by correspondingly setting the parameters of the arithmetic units in the model of the analog computer chip and the parameters of the transfer functions in the neural network model, the model of the analog computer chip can be obtained. At this time, the model in this analog computer chip can achieve the same or similar data processing effect as the neural network model.

[0099] In summary, the present application provides a method for generating a model of a simulated computer chip, which uses an external computer in combination with the simulated computer chip to train an artificial intelligence model (i.e., a neural network model) in the external computer, and then adjusts the parameters of each arithmetic unit in the model of the simulated computer chip according to the parameters of the artificial intelligence model, so as to generate a model of the simulated computer chip. At this time, the model of the simulated computer chip can achieve the same or similar functions as the trained artificial intelligence model. At the same time, since the arithmetic units in the present application are all composed of analog circuits, in the case of the same chip volume, the generated model of the simulated computer chip has tens of thousands or even hundreds of millions of arithmetic units, greatly improving the computing power of the artificial intelligence chip, and can perform calculations on tens of thousands or even hundreds of millions of data simultaneously, so that the simulated computer chip has stronger computing power and faster computing speed when having the same volume.

[0100] Please refer to Figure 3 , which shows a schematic flowchart of a method for generating a model of a simulated computer chip according to an embodiment of the present application. As Figure 3 shown, the method for generating a model of the simulated computer chip includes the following steps:

[0101] Step 301, obtain the topological structure of the model of the simulated computer chip and the circuit structure of the arithmetic unit.

[0102] In the embodiment of the present application, since the topological structure of the model of the simulated computer chip is the same as that of the neural network model, it is necessary to construct a neural network model according to the topological structure of the model of the simulated computer chip after obtaining the topological structure of the model of the simulated computer chip actually used.

[0103] And since the arithmetic unit in the model of the simulated computer chip is used to transfer data between the adders of adjacent layers, which is similar to the function of the transfer function in the neural network model, the computer device also needs to determine the circuit structure of the arithmetic unit of the model of the simulated computer chip, so as to determine what transfer function the neural network model adopts.

[0104] Step 302, determine the connection relationship of each arithmetic node in the neural network model according to the topological structure of the model of the simulated computer chip.

[0105] Please refer to Figure 4 , which shows a topological structure diagram of a model of a simulated computer chip according to an embodiment of the present application. As Figure 4As shown, the model of the analog computer chip includes n adder layers. Any adder in each adder layer is connected to each adder in the upper adder layer through different arithmetic units. The model of the analog computer chip also includes an output layer. The output nodes in the output layer are connected to the adders in the last layer in a one-to-one correspondence. The output nodes are used to output the actual output value of the last layer of adders as the actual operation value of the model of the analog computer chip.

[0106] Further, after obtaining the topological structure of the model of the analog computer chip, the arithmetic units in the analog computer chip can be correspondingly replaced with transfer functions, and the adders in the model of the analog computer chip can be replaced with arithmetic nodes, so as to construct a neural network model with the same topological structure as the model of the analog computer chip shown in Figure 4 As shown.

[0107] Step 303, determine the formula of the transfer function in the neural network model according to the circuit structure of the arithmetic unit.

[0108] Please refer to Figure 5 , which shows a schematic diagram of the circuit structure of the first arithmetic unit involved in the embodiments of the present application. As shown in Figure 5 As shown, where VIN is the input voltage, the input voltage VIN is the x of the transfer function, VOUT is the output voltage, the output voltage VOUT is the y of the transfer function, VR is the fixed voltage, and the fixed voltage VR is the constant c of the transfer function. It can be seen that when the resistance value of the first resistor R1 is equal to the resistance value of the fourth resistor R4, the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3, and the gain of the first operational amplifier A1 is represented by A11, Figure 3 In the circuit structure of the first arithmetic unit shown in , that is, at this time, when is represented by the first adjustable parameter W, the transfer function corresponding to the circuit of the first arithmetic unit is .

[0109] Please refer to Figure 6 , which shows a schematic diagram of the circuit structure of the second arithmetic unit involved in the embodiments of the present application. Where VIN is the input voltage, the input voltage VIN is the x of the transfer function, VOUT is the output voltage, the output voltage VOUT is the y of the transfer function, VR is the fixed voltage of the circuit, and the fixed voltage VR is the constant c of the transfer function. It can be seen that when the gain of the second operational amplifier A2 is represented by A22, Figure 6 In the circuit structure of the second arithmetic unit shown in , that is, at this time, when is represented by the second adjustable parameter B, the transfer function corresponding to the circuit of the second arithmetic unit is .

[0110] At this time, when the first operation unit is adopted, that is, the corresponding transfer function is , changing the value of the first adjustable parameter W can set and adjust the first operation unit. Similarly, when the second operation unit is adopted, that is, the corresponding transfer function is , changing the value of the second adjustable parameter B can set and adjust the second operation unit; at the same time, since both the first operation unit circuit and the second operation unit circuit are composed of operational amplifiers, therefore, the output voltage VOUT of both the first operation unit circuit and the second operation unit circuit should be between the positive input power supply and the negative input power supply of the operational amplifier. Generally speaking, the positive input power supply is a power supply value such as 5V or 3.3V, and the negative input power supply is GND, that is, 0V. Thus, it can be obtained that the accurate transfer function corresponding to the first operation unit circuit is , and the accurate transfer function corresponding to the second operation unit circuit is ; where, VV is the first threshold of the transfer function; 0 is the second threshold of the transfer function; therefore, at this time, the external computer in the present application can, based on the input training data, on the basis of the transfer function , train to obtain the value of the first adjustable parameter W corresponding to each transfer function, or on the basis of the transfer function , train to obtain the value of the second adjustable parameter B corresponding to each transfer function.

[0111] Preferably, in the above transfer function, the first threshold VV of the transfer function is actually the voltage of the positive input power supply of the operational amplifier (the first operational amplifier or the second operational amplifier), for example, it can be 5V; optionally, the first threshold VV of the transfer function can also be 3.3V or other values.

[0112] Step 304, obtain the initial parameter set; the initial parameter set includes the initial parameter values of each transfer function.

[0113] After determining in step 303 that the neural network model selects the transfer function corresponding to the first operation unit or the transfer function corresponding to the second operation unit, the computer device also needs to set the initial parameter values of each transfer function in the neural network model, so as to initialize the neural network model.

[0114] Optionally, the initial parameter value can be preset or set manually;

[0115] Optionally, the initial parameter value can also be randomly selected within a preset range.

[0116] Step 305, set the parameters of each transfer function to the corresponding initial parameter values.

[0117] Step 306, obtain a training data set.

[0118] Step 307, iteratively update the neural network model according to the training data set until the iteration condition is met, so as to obtain the target parameter values of each transfer function in the neural network model.

[0119] In a possible implementation, the computer device inputs the input data into the neural network model to obtain the actual operation value of the neural network model; according to the error between the actual operation value and the label value, the parameters of each transfer function in the neural network model are updated.

[0120] Specifically, taking a neural network model with the same topological structure as the model of the analog computer chip shown in Figure 4 as an example, the neural network model has an input layer, and each input node is included in the input layer. The input data in the training data set ( ) is input from each input node into each transfer function and reaches each operation node in the first layer after calculation. In the embodiments of the present application, each operation node serves as an adder to add the calculation results of each transfer function.

[0121] At this time, after adding the i data obtained by calculation through the transfer function input by each operation node in the first layer, it is used as the input data of the second layer and input into each transfer function in the second layer, and reaches each operation node in the second layer after calculation, and so on, until reaching each operation node in the nth layer. Each operation node in the nth layer adds the i data obtained by calculation through the transfer function in the nth layer and inputs them into each output node as the actually calculated output value;

[0122] Taking the transfer function corresponding to the circuit of the first operation unit as an example, when the number of input nodes and operation nodes in each layer is 3 and the number of operation nodes is 2 layers, the calculation result of operation node 11 is: , where is the value of the transfer function between operation node op and the qth node in the previous layer, where o, p, q are all positive integers greater than or equal to 1 and less than or equal to 3. For example is the value of W of the transfer function between in1 and operation node 11, is the value of W of the transfer function between in2 and operation node 11, is the value of W of the transfer function between in3 and operation node 11. Similarly, the calculation result of operation node 12 is: , and the calculation result of operation node 13 is: , and then it can be obtained that the calculation result of operation node 21 is: , and the calculation result of operation node 22 is: , the calculation result of the operation node 23 , at this time, it can be obtained that the actual output value calculated by the neural network model includes , and ;

[0123] Assume that the label values corresponding to the input data ( ) are respectively , , ... , and the actual output values calculated by the neural network model are respectively , ... , the error between the actual output value and the label value is obtained;

[0124] Specifically, the error is: ;

[0125] At this time, if the error EL is less than the preset error threshold, the training ends, and the first adjustable parameter W in each transfer function is stored in the external computer as the target parameter value in a certain order.

[0126] If the error EL is greater than the preset error threshold, it is necessary to update the first adjustable parameter W in each transfer function between the nth layer operation node and the (n - 1)th layer operation node according to the error between the operation value and the expected output value.

[0127] Specifically, in the embodiment of the present application, the computer device obtains the node error between the actual output value and the expected output value of each operation node in the jth layer; 2≥i≥n;

[0128] Taking the node error between the actual output value and the expected output value of each operation node in the jth layer as the dependent variable, and taking the parameters of each transfer function between the (j - 1)th layer operation node and the jth layer operation node as the independent variables respectively for derivation, the derivative values corresponding to each transfer function between the (j - 1)th layer operation node and the jth layer operation node are obtained;

[0129] Based on the update coefficient and the derivative values corresponding to each transfer function between the (j - 1)th layer operation node and the jth layer operation node, the parameters of each transfer function between the (j - 1)th layer operation node and the jth layer operation node are updated respectively;

[0130] According to the updated transfer functions between the (j - 1)th layer operation node and the jth layer operation node, and the expected output value of the jth layer operation node, calculate the expected output value of the (j - 1)th layer operation node.

[0131] Taking the nth-layer operation node and the (n - 1)th-layer operation node, that is, j = n as an example, the parsing process of the execution steps of the above steps is as follows:

[0132] Since the actual output value of the neural network model , therefore, the corresponding label value is used as the expected output value of the output node of the neural network model. At this time, the error between the actual output value and the expected output value of the output node of the neural network model , at this time, the first adjustable parameter W of each transfer function is respectively differentiated to obtain the value at this moment, and the derivative value DEL of the function. If the derivative value DEL is larger at this time, it means that the error corresponding to the value at this moment is larger. If the derivative value DEL is smaller at this time, it means that the error corresponding to the value at this moment is smaller;

[0133] For example, when the number of input nodes and operation nodes of each layer is 3 and the number of operation layers is 2, the calculation result of operation node 21 is: , the calculation result of operation node 22 is: , the calculation result of operation node 23 , the error between the actual output value and the expected output value , at this time, after substituting the values of other parameters except into the error EL, differentiate , and then, substitute the parameter value of into the differentiated formula, and finally obtain the corresponding derivative value , similarly, the derivative values corresponding to other Ws are obtained in turn;

[0134] It should be noted that in the embodiments of the present application, a limiting condition needs to be added during the calculation process of the transfer function. For example, the actual output value of each transfer function greater than or equal to the first threshold is set to the first threshold, and the actual output value of each transfer function less than or equal to the second threshold is set to the second threshold; the first threshold is greater than the second threshold, where the first threshold is the voltage value of the positive input power supply of the operational amplifier in the operation unit corresponding to the transfer function; the second threshold is the voltage value of the negative input power supply of the operational amplifier in the operation unit corresponding to the transfer function.

[0135] Since the transfer function corresponds to the first operation unit circuit, and the output value of the first operation unit circuit should be greater than 0V and less than the voltage of the positive input power supply of the operational amplifier, such as 5V. At this time, in the embodiments of the present application, when is greater than 5, the value of is taken as 5. When is less than 0, the value of The value is taken as 0.

[0136] At this time, according to the derivative values DEL corresponding to each of the first adjustable parameters W obtained by calculation, the first adjustable parameter W is updated to , where is an update coefficient, which can be set according to the training accuracy and training speed The specific value of, where, The larger, the faster the training speed but the lower the accuracy, The smaller, the slower the training speed but the higher the accuracy.

[0137] Substitute the updated values of each W into the respective transfer functions between the operation nodes of the nth layer and the operation nodes of the (n - 1)th layer. At the same time, according to each expected output value, obtain the operation update values of each operation node in the (n - 1)th layer operation node, and use this operation update value as the expected output value of the (n - 1)th layer operation node;

[0138] Specifically, each operation node in the (n - 1)th layer corresponds to i transfer functions. It is necessary to add up all the operation update values calculated by the i transfer functions and then divide by i. The obtained average value is the operation update value of each operation node in the corresponding (n - 1)th layer operation node, and use this operation update value as the expected output value of the (n - 1)th layer operation node.

[0139] After obtaining the expected output value of the (n - 1)th layer operation node, that is, the first adjustable parameter W of the transfer function between the operation nodes of the (n - 2)th layer and the operation nodes of the (n - 1)th layer can be updated by the update method of the first adjustable parameter W as shown above, and this step is iterated until the expected output value of the first layer operation node is obtained.

[0140] For example, when the number of input nodes and the number of operation nodes in each layer are both 3 and there are 2 layers of operation nodes, after substituting the updated value of W, the calculation result of operation node 21 is , at this time, substitute and The initial values of into the above formula to obtain the first operation update value of operation node 11 in the first layer. Similarly, according to the calculation results of operation node 22 and operation node 23, obtain the second operation update value of operation node 11 in the first layer and the third operation update value of operation node 11 in the first layer. Finally, it can be obtained that the operation update value of operation node 11 in the first layer; then, use the same method to obtain the operation update value of operation node 12 in the first layer and the operation update value of operation node 13 in the first layer, and, substitute and They are respectively the expected output values of the first-layer operation nodes 11, operation node 12, and operation node 13.

[0141] After obtaining the expected output values of the first-layer operation nodes, at this time, the computer device can obtain the node errors between the actual output values and the expected output values of each operation node in the first layer.

[0142] Taking the node errors between the actual output values and the expected output values of each operation node in the first layer as the dependent variables, and taking the parameters of the transfer functions between each input node and each operation node in the first layer as the independent variables respectively for derivation, to obtain the derivative values corresponding to the transfer functions between each input node and each operation node in the first layer.

[0143] Based on the update coefficient and the derivative values corresponding to the transfer functions between each input node and each operation node in the first layer, update the parameters of the transfer functions between each input node and each operation node in the first layer respectively.

[0144] Since the parameter update process of the transfer functions between each input node and each operation node in the first layer is similar to the parameter update process of the transfer functions between the nth-layer operation node and each operation node in the (n - 1)th layer, it will not be elaborated here.

[0145] If the parameter update process of the transfer functions between each input node and each operation node in the first layer is completed, then an iterative training process for the neural network model is completed, and at this time, the iteration count is incremented by 1.

[0146] During the iteration process, if the iteration count is greater than the preset count, or during the iteration process, the error between the actual output value of the output node and the label value is less than the error threshold, then the training ends, and the first adjustable parameter W in each updated transfer function is stored in the external computer as the target parameter value in a certain order.

[0147] If the iteration count is less than the preset count, then substitute the updated first adjustable parameter W into all transfer functions to obtain the updated transfer functions, and thus continue to execute the iteration process.

[0148] Optionally, in the embodiments of the present application, after the computer device completes the iteration process, it can also obtain a validation data set; the validation data set includes validation data and corresponding label values.

[0149] The computer device processes the validation data through the iteratively updated neural network model to obtain validation prediction values.

[0150] According to the predicted value of the verification and the label value corresponding to the verification data, obtain the prediction accuracy of the neural network model, so as to determine whether the neural network model can be used to set the model of the analog computer chip; if the prediction accuracy is greater than or equal to the accuracy threshold, the parameters of the arithmetic units between the adders in the model of the analog computer chip can be correspondingly set according to the target parameter values of the transfer functions between the arithmetic nodes of the neural network model; if the prediction accuracy is less than the accuracy threshold, continue the iterative training through the training data set.

[0151] Step 308: Determine the addresses of the arithmetic units of the transfer functions between the arithmetic nodes in the neural network model corresponding to the model of the analog computer chip.

[0152] Step 309: According to the target parameter values of the transfer functions between the arithmetic nodes, set the parameters of the arithmetic units between the adders in the model of the analog computer chip according to the addresses of the arithmetic units, so as to generate the model of the analog computer chip.

[0153] After the neural network model is trained, the computer device can determine the addresses of the arithmetic units corresponding to the transfer functions between the arithmetic nodes of the neural network model in the model of the analog computer chip, and then set the parameters of the arithmetic units between the adders in the model of the analog computer chip according to the target parameter values of the transfer functions between the arithmetic nodes, so as to generate the model of the analog computer chip.

[0154] Specifically, the computer device inputs the target parameter values and their order relationships in each transfer function (that is, the order relationship stored in the external computer in a certain order in the above text, and this order relationship is the address information of the arithmetic units corresponding to each transfer function in the model of the analog computer chip) into the adjustment circuit of the analog computer chip; among them, the adjustment circuit can be located in the analog computer chip or an independent circuit externally connected to the analog computer chip.

[0155] The adjustment circuit can set and adjust the parameters of each arithmetic unit in the model of the analog computer chip according to the input target parameter values and their order relationships, so that the generated model of the analog computer chip has the same or similar functions as the trained neural network model shown in the embodiments of the present application.

[0156] Specifically, please refer to Figure 5 and Figure 6 . Such as Figure 5As shown, when the first arithmetic unit circuit is adopted, by changing the resistance values of the first resistor R1 and the fourth resistor R4 or changing the resistance values of the second resistor R2 and the third resistor R3, the value of the first adjustable parameter W can be changed, thereby realizing the setting and adjustment of the arithmetic unit. In a possible implementation manner, a non-volatile storage unit is provided in the arithmetic unit of the model of the analog computer chip. For example, the non-volatile storage unit can be used as a resistor, that is, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are all composed of non-volatile storage units, or the first resistor R1 and the fourth resistor R4 are composed of non-volatile storage units, or the second resistor R2 and the third resistor R3 are composed of non-volatile storage units. At this time, by adjusting the stored data of the non-volatile storage unit (such as the floating gate charge of the MOS transistor of the non-volatile storage unit), its resistance value can be changed. Therefore, according to the target parameter value of the transfer function between each arithmetic node, and according to the address of the arithmetic unit corresponding to the transfer function, the stored data of the non-volatile storage unit in the arithmetic unit between each adder in the model of the analog computer chip is set, thereby generating the model of the analog computer chip.

[0157] Specifically, the two non-volatile storage units constituting the first resistor R1 and the fourth resistor R4 or the two non-volatile storage units constituting the second resistor R2 and the third resistor R3 are used as an adjustment point and connected to the adjustment circuit. When it is necessary to set and adjust the parameters of which arithmetic unit, the adjustment circuit finds the non-volatile storage unit of the adjustment point corresponding to the arithmetic unit, and according to the value of the first adjustable parameter W, sets and adjusts the stored data of the non-volatile storage unit (such as charging and discharging the floating gate of the MOS transistor of the non-volatile storage unit to change its resistance value), thereby obtaining the parameters of the required arithmetic unit.

[0158] Such as Figure 6As shown, when the second arithmetic unit circuit is adopted, by changing the resistance value of the fifth resistor R5 or the resistance value of the sixth resistor R6, the value of the second adjustable parameter B can be changed, so as to realize the setting and adjustment of the arithmetic unit. Therefore, at this time, the non-volatile memory cell can be used as a resistor, that is, both the fifth resistor R5 and the sixth resistor R6 are composed of non-volatile memory cells, or the fifth resistor R5 is composed of a non-volatile memory cell, or the sixth resistor R6 is composed of a non-volatile memory cell. At this time, by adjusting the stored data of the non-volatile memory cell (such as the floating gate charge of the MOS transistor of the non-volatile memory cell), its resistance value can be changed. Therefore, the non-volatile memory cell constituting the fifth resistor R5 or the sixth resistor R6 is used as an adjustment point and connected to the adjustment circuit. When it is necessary to set and adjust the parameters of which arithmetic unit, the adjustment circuit finds the non-volatile memory cell corresponding to the adjustment point of the arithmetic unit, and sets and adjusts the stored data of the non-volatile memory cell according to the value of the second adjustable parameter B (such as charging and discharging the floating gate of the MOS transistor of the non-volatile memory cell to change its resistance value), so as to obtain the parameters of the required arithmetic unit.

[0159] The adjustment circuit is designed as Figure 7 the structure shown.

[0160] Among them, the target parameter value and its sequence relationship are input into the adjustment circuit. The adjustment circuit charges and discharges the gate capacitance of the MOS transistors in the corresponding nodes in sequence according to the target parameter value and its sequence relationship to set and adjust its resistance value, so as to set and adjust the parameters of each arithmetic unit. After all the arithmetic units in the model of the analog computer chip are set and adjusted, the model of the analog computer chip can have the same or similar functions as the above-mentioned trained neural network model.

[0161] In summary, the present application provides a method for generating a model of an analog computer chip, which uses an external computer in combination with an analog computer chip, trains an artificial intelligence model in the external computer, and then sets and adjusts the stored data of the non-volatile memory cells of each arithmetic unit in the model of the analog computer chip according to the parameters of the artificial intelligence model, so as to realize the setting and adjustment of the parameters of the arithmetic unit, thereby generating a model of the analog computer chip, and the model of the analog computer chip can realize the same or similar functions as the trained artificial intelligence model; at the same time, since the arithmetic units in the present application are all composed of analog circuits, in the case of the same chip volume, the generated model of the analog computer chip has tens of thousands or even hundreds of millions of arithmetic units, greatly improving the computing power of the artificial intelligence chip, and can perform calculations on tens of thousands or even hundreds of millions of data at the same time, so that the analog computer chip has stronger computing power and faster computing speed when having the same volume.

[0162] In this embodiment, a model generation device for simulating a computer chip is further provided. This device is used to implement the above-mentioned embodiments and preferred implementation manners, and those that have been described will not be repeated here. As used hereinafter, the term "module" can be a combination of software and / or hardware that can achieve a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0163] This embodiment provides a model generation device for simulating a computer chip, as Figure 8 shown, including:

[0164] A dataset acquisition module 801, configured to acquire a training dataset;

[0165] A training module 802, configured to iteratively update a neural network model according to the training dataset until an iteration condition is met, so as to obtain target parameter values of various transfer functions in the neural network model;

[0166] The neural network model includes n layers of operation nodes, and any operation node in each layer of operation nodes is connected to each node in the upper layer through different transfer functions; the target parameter values of the transfer functions between the operation nodes are used to correspondingly set the parameters of the operation units between the adders in the model of the simulated computer chip, thereby generating a model of the simulated computer chip;

[0167] Among them, the model of the simulated computer chip includes n layers of adder layers, and any adder in each layer of adder layers is connected to each adder in the upper layer of adder layers through different operation units; the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model.

[0168] In a possible implementation manner, the device further includes:

[0169] An address determination module 803, configured to determine the addresses of the operation units corresponding to the transfer functions between the operation nodes;

[0170] A parameter setting module 804, configured to set the parameters of the operation units between the adders in the model of the simulated computer chip according to the target parameter values of the transfer functions between the operation nodes and according to the addresses of the operation units corresponding to the transfer functions, so as to generate a model of the simulated computer chip.

[0171] The further function descriptions of the above-mentioned various modules and units are the same as those in the corresponding above-mentioned embodiments, and will not be repeated here.

[0172] The model generation device of the analog computer chip in this embodiment is presented in the form of functional units, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0173] An embodiment of the present invention further provides a computer device having the above Figure 8 model generation device of the analog computer chip shown.

[0174] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of a computer device provided by an alternative embodiment of the present invention. As shown in Figure 9 , the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi-processor system). Figure 9 In

[0175] a single processor 10 is taken as an example.

[0176] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0177] The memory 20 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely disposed relative to the processor 10, and these remote memories may be connected to the computer device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0178] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive; the memory 20 may further include a combination of the above-mentioned types of memories.

[0179] Embodiments of the present invention also provide a computer-readable storage medium. The methods according to the embodiments of the present invention may be implemented in hardware, firmware, or may be implemented as computer code that can be recorded on a storage medium, or may be implemented as computer code originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and to be stored in a local storage medium, so that the methods described herein may be stored as such software processed on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium may also include a combination of the above-mentioned types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0180] A part of the present invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the present invention through the operations of the computer. Those skilled in the art should understand that the forms of existence of computer program instructions in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.

[0181] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for generating a model of an analog computer chip, characterized in that, The method includes: Obtain a training data set; Iteratively update the neural network model according to the training data set until the iteration condition is satisfied, so as to obtain the target parameter values of each transfer function in the neural network model; The neural network model includes n layers of computing nodes, and any computing node in each layer of computing nodes is connected to each node in the upper layer through different transfer functions; Among them, the model of the analog computer chip includes n layers of adder layers, and any adder in each layer of adder layers is connected to each adder in the upper layer of adder layers through different arithmetic units; the topological structure of the model of the analog computer chip is the same as the topological structure of the neural network model; The method further includes, Determine the addresses of the arithmetic units corresponding to the transfer functions between each computing node; a non-volatile storage unit is provided in the arithmetic unit, and the non-volatile storage unit is used as a resistor; the arithmetic unit is composed of an analog circuit; According to the target parameter values of the transfer functions between each computing node, set the stored data of the non-volatile storage units in the arithmetic units between each adder in the model of the analog computer chip according to the addresses of the arithmetic units corresponding to the transfer functions, so as to generate the model of the analog computer chip; Setting the stored data of the non-volatile storage units in the arithmetic units between each adder in the model of the analog computer chip includes: Charge and discharge the floating gate of the MOS transistor of the non-volatile storage unit to change the resistance value; The transfer function is: Among them, x is the input value of the transfer function; y is the output value of the transfer function; W is the first adjustable parameter of the transfer function; c is a constant; VV is the first threshold of the transfer function; 0 is the second threshold of the transfer function; Alternatively, the transfer function is: Among them, x is the input value of the transfer function; y is the output value of the transfer function; B is the second adjustable parameter of the transfer function; A22 is the gain constant; VV is the first threshold of the transfer function; 0 is the second threshold of the transfer function.

2. The model generation method according to claim 1, wherein The training data set includes input data and label values; the label value is the expected output value of the output node of the neural network model after the input data is input into the neural network model; Iteratively updating the neural network model according to the training data set includes: Input the input data into the neural network model to obtain the actual operation value of the neural network model; Update the parameters of each transfer function in the neural network model according to the error between the actual operation value and the label value.

3. The model generation method according to claim 2, wherein Before iteratively updating the neural network model according to the training data set, it further includes: Obtain the topological structure of the model of the analog computer chip and the circuit structure of the arithmetic unit; Determine the connection relationship of each computing node in the neural network model according to the topological structure of the model of the analog computer chip; Determine the formula of the transfer function in the neural network model according to the circuit structure of the arithmetic unit.

4. The model generation method according to claim 2, wherein The neural network model further includes an output layer; the output nodes in the output layer are connected to the last-layer operation nodes in a one-to-one correspondence; the output nodes are used to output the actual output values of the last-layer operation nodes as the actual operation values of the neural network model.

5. The model generation method according to claim 4, wherein Updating the parameters of each transfer function in the neural network model according to the error between the actual operation value and the label value includes: Obtaining the node error between the actual output value and the expected output value of each operation node in the j-th layer; 2≥j≥n; Taking the node error between the actual output value and the expected output value of each operation node in the j-th layer as the dependent variable, and taking the parameters of each transfer function between the (j-1)-th layer operation nodes and the j-th layer operation nodes as independent variables respectively to perform derivation, so as to obtain the derivative values corresponding to each transfer function between the (j-1)-th layer operation nodes and the j-th layer operation nodes; Based on the update coefficient and the derivative values corresponding to each transfer function between the (j-1)-th layer operation nodes and the j-th layer operation nodes, updating the parameters of each transfer function between the (j-1)-th layer operation nodes and the j-th layer operation nodes respectively; According to the updated transfer functions between the (j-1)-th layer operation nodes and the j-th layer operation nodes, and the expected output value of the j-th layer operation nodes, calculating the expected output value of the (j-1)-th layer operation nodes.

6. The model generation method according to claim 5, wherein There are k operation nodes in the j-th layer; where k≥1; Calculating the expected output value of the (j-1)-th layer operation nodes according to the updated transfer functions between the (j-1)-th layer operation nodes and the j-th layer operation nodes, and the expected output value of the j-th layer operation nodes includes: For any target node in the (j-1)-th layer operation nodes, obtaining k updated values of the target node according to the transfer functions between the target node and the k operation nodes in the j-th layer, and the expected output values of the k operation nodes in the j-th layer; Taking the average value of the k updated values of the target node as the expected output value of the target node.

7. The model generation method according to claim 6, wherein The upper-layer nodes of the first-layer operation nodes include each input node; The method further includes: Obtaining the node error between the actual output value and the expected output value of each operation node in the first layer; Taking the node error between the actual output value and the expected output value of each operation node in the first layer as the dependent variable, and taking the parameters of the transfer functions between each input node and each operation node in the first layer as independent variables respectively to perform derivation, so as to obtain the derivative values corresponding to the transfer functions between each input node and each operation node in the first layer; Based on the update coefficient and the derivative values corresponding to the transfer functions between each input node and each operation node in the first layer, updating the parameters of the transfer functions between each input node and each operation node in the first layer respectively.

8. The model generation method according to claim 7, wherein The method further includes: Set the output values of the respective transfer functions greater than or equal to the first threshold to the first threshold, and set the output values of the respective transfer functions less than or equal to the second threshold to the second threshold; the first threshold is greater than the second threshold.

9. The model generation method according to any one of claims 1 to 8, characterized in that The iteration condition includes at least one of the following: The number of iterations is greater than a preset number; The error between the actual output value and the label value of the neural network model is less than the preset error threshold.

10. The model generation method according to any one of claims 1 to 8, characterized in that, Before iteratively updating the neural network model according to the training data set until the iteration condition is satisfied, it further includes: Obtain an initial parameter set; the initial parameter set includes the initial parameter values of the respective transfer functions; Set the parameters of the respective transfer functions to the corresponding initial parameter values.

11. The model generation method according to claim 10, characterized in that, The initial parameter values of the respective transfer functions are preset; Alternatively, the initial parameter values of the respective transfer functions are randomly selected within a specified range.

12. The model generation method according to any one of claims 1 to 8, characterized in that, The method further includes: Obtain a validation data set; the validation data set includes validation data and corresponding label values; Process the validation data through the iteratively updated neural network model to obtain validation prediction values; According to the validation prediction values and the label values corresponding to the validation data, obtain the prediction accuracy of the neural network model.

13. A model generation device for simulating a computer chip, characterized in that, The apparatus includes: A data set acquisition module for acquiring a training data set; A training module for iteratively updating the neural network model according to the training data set until the iteration condition is satisfied to obtain the target parameter values of the respective transfer functions in the neural network model; The neural network model includes n layers of computing nodes, and any computing node in each layer of computing nodes is connected to each node in the upper layer through different transfer functions; Among them, the model of the analog computer chip includes n layers of adder layers, and any adder in each layer of adder layers is connected to each adder in the upper layer of adder layers through different arithmetic units; the topological structure of the model of the analog computer chip is the same as the topological structure of the neural network model; An address determination module for determining the address of the arithmetic unit corresponding to the transfer function between the respective computing nodes; a non-volatile storage unit is provided in the arithmetic unit and the non-volatile storage unit is used as a resistor; the arithmetic unit is composed of an analog circuit; A parameter setting module for setting the stored data of the non-volatile storage unit in the arithmetic unit between the respective adders in the model of the analog computer chip according to the target parameter values of the transfer functions between the respective computing nodes according to the address of the arithmetic unit corresponding to the transfer function, so as to generate the model of the analog computer chip; Setting the stored data of the non-volatile storage unit in the arithmetic unit between the respective adders in the model of the analog computer chip includes: Charging and discharging the floating gate of the MOS transistor of the non-volatile storage unit to change the resistance value; The transfer function is: Where x is the input value of the transfer function; y is the output value of the transfer function; W is the first adjustable parameter of the transfer function; c is a constant; VV is the first threshold of the transfer function; 0 is the second threshold of the transfer function; Alternatively, the transfer function is: Among them, x is the input value of the transfer function; y is the output value of the transfer function; B is the second adjustable parameter of the transfer function; A22 is the gain constant; VV is the first threshold of the transfer function; 0 is the second threshold of the transfer function.

Images