Timing control circuit of display device and display device

Abstract

The application discloses a timing control circuit of a display device and the display device, wherein the timing control circuit of the display device comprises a frequency detection circuit, a cache circuit and a clock generation circuit; the frequency detection circuit is configured to perform frequency detection on a synchronization signal corresponding to image data sent by an image processor to obtain a frequency flag signal, and the frequency flag signal represents a frame rate of the image data; the cache circuit is configured to cache the image data; and the clock generation circuit is coupled to the frequency detection circuit and is configured to generate a target pixel clock according to the frequency flag signal, and the target pixel clock is used to make a display panel display the image data at a refresh rate corresponding to the target pixel clock. In this way, the frame rate of the image data can be dynamically detected, the refresh rate of the display panel can be dynamically updated / switched, the power consumption of the timing control circuit can be reduced, and the matching between the frame rate and the refresh rate can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a timing control circuit of a display device and the display device. BACKGROUND

[0002] In a display system, the frame rate of image data output by an image processor to a display panel is affected by the load of the image processor itself and fluctuates all the time. When the load of the image processor is high, the frame rate of the output image data is low, and when the load of the image processor is low, the frame rate of the output image data is high. At this time, phenomena such as frame freezing and frame tearing are likely to occur due to the mismatch between the refresh rate of the display panel and the frame rate of the image data, which greatly affects the user experience.

[0003] Current technologies for solving the mismatch between the frame rate and the refresh rate mainly include VRR (Variable Refresh Rate) technology and SDRRS (Seamless Dynamic Refresh Rate Switching) technology. The VRR technology controls the frame rate of the image processor output by stretching and contracting the V blank time while keeping the Active frame length unchanged, during which the pixel clock remains unchanged. The SDRRS technology changes the refresh rate and reduces the power consumption by changing the pixel clock of the image processor through the image processor sending a command to the timing control circuit. Although the VRR technology can solve the problem of mismatch between the frame rate and the refresh rate, it only simply prolongs the V blank, and when the frame rate is low, the pixel clock is still the same as the frequency at the highest frame rate, which cannot achieve the purpose of greatly reducing the power consumption for mobile application scenarios such as notebook computers. The SDRRS technology can change the timing control circuit by changing the pixel clock of the image processor, but when the clock of the image processor changes during the interface operation in the receiving circuit, the initialization step of the receiving circuit needs to be re-performed, so it is only suitable for some specific applications.

[0004] Therefore, it is urgent to provide a technical solution to solve the problems of high power consumption of the VRR technology and the need to re-initialize the receiving circuit when the clock of the image processor changes in the SDRRS technology. SUMMARY

[0005] The present application provides a timing control circuit of a display device and the display device, which can dynamically detect the frame rate of image data, dynamically update / switch the refresh rate of the display panel, reduce the power consumption of the timing control circuit, and realize the matching between the frame rate and the refresh rate.

[0006] To solve the above technical problems, one technical scheme adopted by the present application is to provide a timing control circuit of a display device, which comprises a frequency detection circuit, a cache circuit and a clock generation circuit; wherein the frequency detection circuit is configured to perform frequency detection on a synchronization signal corresponding to image data sent by an image processor to obtain a frequency flag signal, the frequency flag signal representing a frame rate of the image data; the cache circuit is configured to cache the image data; and the clock generation circuit is coupled to the frequency detection circuit and is configured to generate a target pixel clock according to the frequency flag signal, the target pixel clock being used to make the display panel display the image data at a refresh rate corresponding to the target pixel clock.

[0007] The synchronization signal comprises a frame synchronization signal and a line synchronization signal; the frequency detection circuit comprises: a first frequency detection circuit configured to perform frequency detection on a frame synchronization signal corresponding to image data sent by the image processor in a first frame rate control mode to obtain a first frequency flag signal; and a second frequency detection circuit configured to perform frequency detection on a line synchronization signal corresponding to image data sent by the image processor in a second frame rate control mode to obtain a second frequency flag signal; and the clock generation circuit is coupled to the first frequency detection circuit and the second frequency detection circuit and is configured to generate the target pixel clock according to the first frequency flag signal or the second frequency flag signal.

[0008] The timing control circuit further comprises a receiving circuit coupled to the first frequency detection circuit and the second frequency detection circuit and configured to receive the image data sent by the image processor and select the first frequency detection circuit or the second frequency detection circuit to perform frequency detection on a synchronization signal corresponding to the image data according to a frame rate control mode corresponding to the image data.

[0009] The cache circuit comprises: a first cache circuit coupled to the receiving circuit and the first frequency detection circuit and configured to cache the image data when the receiving circuit selects the first frequency detection circuit to perform frequency detection; and a second cache circuit coupled to the receiving circuit and the second frequency detection circuit and configured to cache the image data when the receiving circuit selects the second frequency detection circuit to perform frequency detection.

[0010] The first cache circuit adopts frame caching and the second cache circuit adopts double-line caching.

[0011] The timing control circuit further comprises a first selection circuit coupled to the first cache circuit and the second cache circuit and configured to select the image data cached from the first cache circuit or the second cache circuit according to a first control signal according to the target pixel clock.

[0012] The timing control circuit further includes a second selection circuit, a first input end of the second selection circuit is coupled with the first frequency detection circuit, a second input end of the second selection circuit is coupled with the second frequency detection circuit, and an output end of the second selection circuit is coupled with the clock generation circuit, and the second selection circuit is configured to select the first frequency flag signal or the second frequency flag signal to output according to the second control signal.

[0013] The clock generation circuit is configured to generate the current target pixel clock with a frequency less than a frequency of a previous target pixel clock when a frame rate deviation corresponding to the current first frequency flag signal and a previous first frequency flag signal is greater than a threshold value or a frame rate deviation corresponding to the current second frequency flag signal and a previous second frequency flag signal is greater than the threshold value, and generate the current target pixel clock with a frequency equal to the frequency of the previous target pixel clock when the frame rate deviation corresponding to the current first frequency flag signal and the previous first frequency flag signal is less than the threshold value or the frame rate deviation corresponding to the current second frequency flag signal and the previous second frequency flag signal is less than the threshold value.

[0014] The first frequency detection circuit is further configured to determine the first frequency flag signal corresponding to the current synchronization signal according to a time difference between adjacent synchronization signals based on the reference clock, and the second frequency detection circuit is further configured to determine the second frequency flag signal corresponding to the current synchronization signal according to the time difference between adjacent synchronization signals based on the reference clock.

[0015] To solve the above technical problems, another technical solution adopted by the present application is to provide a display device including the timing control circuit described above.

[0016] The present application has the following beneficial effects: Different from the prior art, the timing control circuit of the present application includes a frequency detection circuit, a cache circuit and a clock generation circuit. The frequency detection circuit is configured to perform frequency detection on a synchronization signal corresponding to image data sent by an image processor to obtain a frequency flag signal, the frequency flag signal representing a frame rate of the image data. The cache circuit is configured to cache the image data. The clock generation circuit is coupled with the frequency detection circuit, and the clock generation circuit is configured to generate a target pixel clock according to the frequency flag signal. The target pixel clock is used to make a display panel display the image data according to a refresh rate corresponding to the target pixel clock. In the above manner, compared with the image processor actively sending a corresponding command to the timing control circuit to update the refresh rate of the display panel, the present application uses the frequency detection circuit to dynamically detect the frame rate of the image data, and then generates a corresponding pixel clock according to the detected frame rate, and then dynamically updates / switches the refresh rate of the display device according to the pixel clock. This can reduce the power consumption of the timing control circuit when the frame rate of the image data decreases, and realize the matching between the frame rate of the image data and the refresh rate of the display device. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings also belong to the protection scope of the present application.

[0018] Figure 1 is a structural schematic diagram of a first embodiment of a timing control circuit provided by the present application;

[0019] Figure 2 is a structural schematic diagram of a second embodiment of a timing control circuit provided by the present application;

[0020] Figure 3 is a schematic diagram of a first frame rate control mode provided by the present application;

[0021] Figure 4 is a schematic diagram of a second frame rate control mode provided by the present application;

[0022] Figure 5 is a structural schematic diagram of a third embodiment of a timing control circuit provided by the present application;

[0023] Figure 6 is a schematic diagram of a first embodiment of frequency transition provided by the present application;

[0024] Figure 7 is a schematic diagram of a second embodiment of frequency transition provided by the present application;

[0025] Figure 8 is a structural schematic diagram of a first embodiment of a display device provided by the present application;

[0026] Figure 9 is a structural schematic diagram of a second embodiment of a display device provided by the present application;

[0027] Figure 10 is a structural schematic diagram of a third embodiment of a display device provided by the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments only constitute some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort also belong to the protection scope of the present application.

[0029] Reference is made to Figure 1 , Figure 1is a structural schematic diagram of a first embodiment of a timing control circuit provided by the present application. The timing control circuit 10 includes a frequency detection circuit 101, a buffer circuit 102, and a clock generation circuit 103.

[0030] The frequency detection circuit 101 is configured to perform frequency detection on a synchronization signal corresponding to image data sent by an image processor, to obtain a frequency flag signal representing a frame rate of the image data. The buffer circuit 102 is configured to buffer the image data, and performs data buffering according to a signal of the frequency detection circuit 101. When a frame rate change occurs after the frequency detection circuit 101 performs frequency detection, the buffer circuit 102 is controlled to buffer. The clock generation circuit 103 is coupled to the frequency detection circuit 101, and is configured to generate a target pixel clock according to the frequency flag signal. The target pixel clock is used to cause a display panel to display the image data at a refresh rate corresponding to the target pixel clock.

[0031] In some embodiments, the image processor is a GPU (Graphics Processing Unit), and the timing control circuit 10 is a TCON (Timing Controller).

[0032] In some embodiments, the synchronization signal includes a frame synchronization signal and a line synchronization signal. Referring to Figure 2 , the frequency detection circuit 101 includes a first frequency detection circuit 201 and a second frequency detection circuit 202. The first frequency detection circuit 201 is configured to perform frequency detection on a frame synchronization signal corresponding to image data sent by an image processor in a first frame rate control mode, to obtain a first frequency flag signal. The second frequency detection circuit 202 is configured to perform frequency detection on a line synchronization signal corresponding to image data sent by the image processor in a second frame rate control mode, to obtain a second frequency flag signal. At this time, the clock generation circuit 103 is coupled to the first frequency detection circuit 201 and the second frequency detection circuit 202, respectively, and is configured to generate a target pixel clock according to the first frequency flag signal or the second frequency flag signal.

[0033] In some embodiments, the first frame rate control mode is a mode in which the effective data length of original image data remains unchanged, and a frame rate change is achieved by extending or shortening the time of VBlank (field blanking), to obtain new image data. VBlank refers to a time interval during which a scanning point returns from the lower right corner of an image to the upper left corner of the image after scanning a frame, and starts scanning a new frame.

[0034] As Figure 3As shown, to change from 60 FPS (Frames Per Second) to 30 FPS, the length of the next valid data frame at 30 FPS must be the same as that at 60 FPS. This is achieved by extending the time of VFP (Vertical Synchronizing Front Porch) and VBP (Vertical Synchronizing Back Porch). Conversely, to change from 30 FPS to 60 FPS, the length of the next valid data frame at 30 FPS must be the same as that at 60 FPS. This is achieved by shortening the time of VFP and VBP. Here, "Active frame" refers to the valid frame, and 1920×1200 represents the resolution of the display device / panel.

[0035] The second frame rate control method keeps the effective data length of the image data constant, and changes the frame rate by extending or shortening the H Blank (line blanking) time to obtain the image data. Here, H Blank refers to the time difference between the end of the previous line and the beginning of the next line.

[0036] like Figure 4 As shown, to change from 60FPS to 30FPS, the length of the next line of valid data in 30FPS must be the same as that in 60FPS. This is achieved by increasing the duration of VFP, VBP, and Active frame. Conversely, to change from 30FPS to 60FPS, the length of the next line of valid data in 30FPS must be the same as that in 60FPS. This is achieved by decreasing the duration of VFP, VBP, and Active frame.

[0037] It can be understood that the first frame rate control method changes the frame rate by extending or shortening the time of VFP and VBP; the second frame rate control method changes the frame rate by extending or shortening the time of VFP, VBP and Active Frame. Both the first and second frame rate control methods belong to the control methods of the image processor to control the frame rate of the output image data. In other words, the frame rate of the image data is determined by the image processor, which can control the frame rate of the image data to increase or decrease.

[0038] Differently from the prior art, the timing control circuit 10 provided in the application comprises a frequency detection circuit 101, a buffer circuit 102 and a clock generation circuit 103. The frequency detection circuit 101 is configured to perform frequency detection on a synchronization signal corresponding to image data sent by an image processor, to obtain a frequency mark signal, which represents a frame rate of the image data. The buffer circuit 102 is configured to buffer the image data. The clock generation circuit 103 is coupled to the frequency detection circuit 101, and is configured to generate a target pixel clock according to the frequency mark signal. The target pixel clock is used to make the display panel display the image data at a refresh rate corresponding to the target pixel clock. In the foregoing manner, a dynamic frame rate detection mechanism is adopted, so that the frame rate of the current image processor can be learned and the refresh rate of the display panel can be switched without sending a command from the image processor end, thereby reducing the power consumption of the timing control circuit 10.

[0039] Further, the V Blank extension and H Blank extension frame rate control modes provided in the application are processed respectively, so that a plurality of image processors can be adapted.

[0040] In some embodiments, referring to Figure 2 , the timing control circuit 10 further comprises a receiving circuit 104 coupled to the first frequency detection circuit 201 and the second frequency detection circuit 202. The receiving circuit 104 is configured to receive image data sent by an image processor, and select the first frequency detection circuit 201 or the second frequency detection circuit 202 to perform frequency detection on a synchronization signal corresponding to the image data according to a frame rate control mode corresponding to the image data.

[0041] In the embodiment, the receiving circuit 104 and the image processor are connected through an eDP (Embedded DisplayPort) interface. The eDP interface has the characteristics of high bandwidth, good integration and reduced device complexity. In other embodiments, other interfaces can be used for connection, which are not limited herein.

[0042] Optionally, when the synchronization signal is a frame synchronization signal, the first frequency detection circuit 201 is selected to perform frequency detection on the frame synchronization signal corresponding to the image data. When the synchronization signal is a line synchronization signal, the second frequency detection circuit 202 is selected to perform frequency detection on the line synchronization signal corresponding to the image data.

[0043] In some embodiments, the first frequency detection circuit 201 is further configured to determine the first frequency flag signal corresponding to the current synchronization signal according to a time difference between adjacent synchronization signals based on a reference clock; and the second frequency detection circuit 202 is further configured to determine the second frequency flag signal corresponding to the current synchronization signal according to a time difference between adjacent synchronization signals based on the reference clock. The reference clock is provided in the timing control circuit 10, which can be an oscillator of the timing control circuit 10.

[0044] Specifically, the first frequency detection circuit 201 performs frequency detection on the frame synchronization signal corresponding to the image data, and the specific process of obtaining the first frequency flag signal includes: determining a first time based on the reference clock when receiving the current frame synchronization signal, determining a second time based on the reference clock when receiving the next frame synchronization signal, determining a time difference between the two frame synchronization signals based on the first time and the second time, and then determining the first frequency flag signal corresponding to the current frame synchronization signal according to the time difference. The first frequency flag signal can be set according to the corresponding frame rate, for example, the first frequency flag signal corresponding to 60FPS is 0, the first frequency flag signal corresponding to 45FPS is 1, and the first frequency flag signal corresponding to 30FPS is 2.

[0045] For example, for the case of the first frame rate control mode (i.e., V Blank extension), using OSC (Oscillator, oscillator) to represent the reference clock and Vsync to represent the frame synchronization signal, the timing control circuit 10 measures the time difference between two Vsyncs using the internal OSC as the reference clock. When Vsync is pulled high, the counter starts counting, and when the next Vsync arrives, the counter stops counting, and then the frame rate of the current frame is calculated according to the count value, and the counter is cleared after the frame rate is calculated to start counting again.

[0046] Specifically, the second frequency detection circuit 202 performs frequency detection on the line synchronization signal corresponding to the image data to obtain the second frequency flag signal, and the specific process includes: determining a first time based on the reference clock when receiving the current line synchronization signal, determining a second time based on the reference clock when receiving the next line synchronization signal, determining a time difference between the two line synchronization signals based on the first time and the second time, and then determining the second frequency flag signal corresponding to the current line synchronization signal according to the time difference. The second frequency flag signal can be set according to the corresponding frame rate, for example, the second frequency flag signal corresponding to 60FPS is 0, the second frequency flag signal corresponding to 45FPS is 1, and the second frequency flag signal corresponding to 30FPS is 2.

[0047] For example, for the case of the second frame rate control mode (i.e. H blank extension), using OSC to represent the reference clock and Hsync to represent the line synchronization signal, the timing control circuit 10 measures the time difference between two Hsyncs using the internal OSC as the reference clock. When the Hsync is pulled high, the counter starts counting, and stops counting until the next Hsync arrives. Then, the frame rate of the current frame is calculated according to the count value, and the counter is cleared to start counting again after the frame rate is calculated.

[0048] In some embodiments, referring to Figure 2 , the buffer circuit 102 includes a first buffer circuit 203 and a second buffer circuit 204. The first buffer circuit 203 is coupled to the receiving circuit 104 and the first frequency detection circuit 201, and is configured to buffer the image data when the receiving circuit 104 selects the first frequency detection circuit 201 for frequency detection. The second buffer circuit 204 is coupled to the receiving circuit 104 and the second frequency detection circuit 202, and is configured to buffer the image data when the receiving circuit 104 selects the second frequency detection circuit 202 for frequency detection. The image data is RGB data.

[0049] The first buffer circuit 203 uses frame buffering, and the second buffer circuit 204 uses double-line buffering. The frame buffering is a write-in and read-out cycle buffering method. The double-line buffering is a write-in buffering method in which write-in buffer 1 is followed by write-in buffer 2, and read-out from buffer 1 is followed by read-out from buffer 2, i.e. in an alternating and reciprocal manner. At this time, the process of writing into buffer 2 and reading from buffer 1 can overlap in time, and even the process of writing into buffer 1 and reading from buffer 2 can overlap in time.

[0050] It is worth noting that in other embodiments, when the synchronization signal is a frame synchronization signal, the first frequency detection circuit 201 and the first buffer circuit 203 correspond; when the synchronization signal is a line synchronization signal, the first frequency detection circuit 201 and the second frequency detection circuit 202 correspond, as well as the second buffer circuit 204. That is, when the second buffer circuit 204 is used, the first frequency detection circuit 201 and the second frequency detection circuit 202 need to be used at the same time, and when the first buffer circuit 203 is used, only the first frequency detection circuit 201 needs to be used. At this time, the receiving circuit 104 can process the image data to obtain parallel RGB data, and send the parallel RGB data to the first detection circuit 101 and / or the second detection circuit, and the corresponding buffer circuit.

[0051] In addition, for the first frame rate control mode, when the frame rate of the image data output by the image processor is reduced to below 30 FPS, the frame buffer is used to buffer the valid frame data; for the second frame rate control mode, when the frame rate of the image data output by the image processor is reduced to below 30 FPS, the double-row buffer is used to store the valid row data, thereby avoiding problems such as data loss caused by fast writing and slow reading.

[0052] Different from the prior art, the timing control circuit 10 provided in the application can use a dynamic frame rate detection mechanism, without the need to send a command from the image processor end to complete the acquisition of the frame rate of the current image processor and the switching of the refresh rate of the display panel, thereby reducing the power consumption of the timing control circuit 10.

[0053] In some embodiments, referring to Figure 5 The timing control circuit 10 further includes a first selection circuit 105 and a second selection circuit 106. The first selection circuit 105 is coupled to the first buffer circuit 203 and the second buffer circuit 204, respectively, and is configured to read the buffered image frame data from the first buffer circuit 203 or the second buffer circuit 204 according to a target pixel clock according to a first control signal. The first input end of the second selection circuit 106 is coupled to the first frequency detection circuit 201, the second input end of the second selection circuit 106 is coupled to the second frequency detection circuit 202, and the output end of the second selection circuit 106 is coupled to the clock generation circuit 103. The second selection circuit 106 is configured to output the first frequency flag signal or the second frequency flag signal according to a second control signal. The first control signal and the second control signal come from a command register, and the first selection circuit 105 and the second selection circuit 106 are multiplexers.

[0054] Specifically, the first buffer circuit 203 / second buffer circuit 204 writes image data at a first speed, and the first selection circuit 105 reads the buffered image data from the first buffer circuit 203 / second buffer circuit 204 at a second speed different from the first speed.

[0055] In actual applications, in order to avoid problems such as image data loss caused by fast writing and slow reading when the frame rate of the image data changes, the first speed is set to be greater than the second speed. For example, the first speed is x, and the second speed is 0.5x, 0.25x, or 0.2x, etc.

[0056] Notably, the clock generation circuit 103 is configured to generate a current target pixel clock with a frequency less than a frequency of a previous target pixel clock when a frame rate deviation corresponding to a current first frequency flag signal and a previous first frequency flag signal is greater than a threshold value, or a frame rate deviation corresponding to a current second frequency flag signal and a previous second frequency flag signal is greater than a threshold value; and generate a current target pixel clock with a frequency equal to a frequency of a previous target pixel clock when a frame rate deviation corresponding to a current first frequency flag signal and a previous first frequency flag signal is less than a threshold value, or a frame rate deviation corresponding to a current second frequency flag signal and a previous second frequency flag signal is less than a threshold value. The threshold value can be set according to actual conditions.

[0057] For example, the frequency detection circuit 101 detects that the frame rate of the image data output by the image processor decreases from 60 FPS to 30 FPS or lower, referring to FIG. 2. Figure 3 At this time, the frequency detection circuit 101 controls the clock generation circuit 103 to automatically generate a target pixel clock. When the frequency (0.5T) of the target pixel clock is half of the frequency (T) of a previous target pixel clock, the frame rate of the image data remains unchanged, but this will cause a problem of writing fast and reading slow, which is likely to cause image data loss. Therefore, the buffer circuit 102 is used for buffering.

[0058] When the buffer circuit 102 is a first buffer circuit 203, i.e., a frame buffer, the frame buffer is enabled when the frequency of the target pixel clock decreases to half of the frequency of a previous target pixel clock (i.e., 0.5T). The receiving circuit 104 writes image data at a speed of x, and the timing control circuit 10 reads out image data from the receiving circuit 104 at a speed of 0.5x. Since the Vblank is expanded to twice the original at 30 Hz, the timing control circuit 10 has enough time to read out all valid data and display it on the control panel, ensuring data continuity. When the frequency detection circuit 101 detects that the frame rate of the image data has a small deviation from 60 Hz, the frequency of the current target pixel clock is not changed, and only the Vblank is extended or shortened to synchronize the frequency of the input frame.

[0059] When the timing control circuit 10 changes from 60 Hz to 30 Hz, there is a frame buffer, so image data will not be lost at this time. When the timing control circuit 10 changes from 30 Hz to 60 Hz, it can only read half of the valid image data, because the frame rate of the current frame has increased to 60 FPS, and the frequency in the timing control circuit 10 needs to be switched to 60 Hz when the frame synchronization signal of the next frame arrives, which results in that the target pixel clock (0.5T) used in the current frame time can only read half of the valid image data. However, for image display, the loss of one frame of image data will not have a great impact on the senses.

[0060] When the cache circuit 102 is a second cache circuit 204, both row cache, when the frequency of the target pixel clock (0.5T) is reduced to half of the frequency of the previous target pixel clock (T), the double row cache is enabled, including cache 1 and cache 2, the receiving circuit 104 writes image data to cache 1 at a speed of x, the timing control circuit 10 reads data from cache 1 at a speed of 0.5x, when cache 1 is written, then write cache 2, when the timing control circuit 10 finishes reading data from cache 1, it immediately reads data from cache 2, and alternately reciprocates until the entire frame data is read, since at 30Hz, the H blank is expanded to twice the original, the timing control circuit 10 has enough time to read out all valid data and display on the control panel, ensuring data continuity. When the frequency detection circuit 101 detects that the frame rate of the image data deviates from 60Hz by a small amount, the frequency of the current target pixel clock is not changed, only the H blank is extended or shortened to synchronize the frequency of the input frame.

[0061] When the timing control circuit 10 changes from 60Hz to 30Hz, due to the presence of double row cache, the frequency detection circuit 101 detects that the frame rate of the current frame is 30FPS when the first row of valid data ends, so the frequency of the timing control circuit 10 is set to 30Hz before the second row of valid data starts. Since the frequency of the timing control circuit 10 is still at 60Hz when the first row of valid data arrives, the target pixel clock does not change and can still read the first row of valid data completely. When the second row of valid data arrives, the target pixel clock (0.5T) has been reduced to half of the previous target pixel clock (T), but through double row cache, the timing control circuit 10 can read all valid data completely until the end of the frame. When the working frequency of the timing control circuit 10 is 30Hz, the frame rate of the image processor will increase to 60Hz, and the frequency detection circuit 101 detects that the current frame rate becomes 60FPS when the first row of valid data ends, so the frequency of the timing control circuit 10 is switched to 60Hz before the second row of valid data starts. Since the timing control circuit 10 is still at 30Hz when the first row of valid data arrives, the target pixel clock is 1 / 2 of the 60Hz state, and cannot read the first row of valid data completely, the first row display will appear abnormal, when the second row of valid data arrives, the frequency of the target pixel clock is switched back to 60Hz, and all valid data from the second row to the end of the frame can be read completely.

[0062] In some embodiments, for the first frame rate control mode, such as Figure 6As shown in the figure, 30hz_vsync_flag, 45hz_vsync_flag and 60hz_vsync_flag all belong to the frequency flag signal, and idle, 30Hz State, 45Hz State and 60Hz State all belong to the state of the timing control circuit 10, where idle represents an idle state, and the timing control circuit 10 can perform frequency conversion according to the received frequency flag signal.

[0063] In some embodiments, for the second frame rate control mode, as shown in the figure, 30hz_hsync_flag, 45hz_hsync_flag and 60hz_hsync_flag all belong to the frequency flag signal, and idle, 30Hz State, 45Hz State and 60Hz State all belong to the state of the timing control circuit 10, where idle represents an idle state, and the timing control circuit 10 can perform frequency conversion according to the received frequency flag signal. Figure 7

[0064] Referring to Figure 8 , Figure 8 is a structural schematic diagram of a first embodiment of a display device provided by the present application. The display device 80 includes the timing control circuit 10 described in any of the above embodiments, which will not be described again here.

[0065] Further, referring to Figure 9 , Figure 9 is a structural schematic diagram of a second embodiment of a display device 80 provided by the present application. The display device 80 includes an image processor 801, a timing control circuit 10, an image quality IP management module 107, a sending circuit 108 and a display panel 109. The timing control circuit 10 at least includes a frequency detection circuit 101, a buffer circuit 102, a clock generation circuit 103, a receiving circuit 104, a first selection circuit 105 and a second selection circuit 106. The frequency detection circuit 101 includes a first frequency detection circuit 201 and a second frequency detection circuit 202; the buffer circuit 102 includes a first buffer circuit 203 and a second buffer circuit 204.

[0066] ​The input end of the receiving circuit 104 is connected to the image processor 801, the output end of the receiving circuit 104 is connected to the first frequency detection circuit 201, the second frequency detection circuit 202, the first buffer circuit 203 and the second buffer circuit 204 respectively, and the receiving circuit 104 is configured to receive image data sent by the image processor 801, and when the frame rate control mode is the first frame rate control mode, input the image data into the first frequency detection circuit 201 to utilize the first frequency detection circuit 201 to perform frequency detection on the frame synchronization signal corresponding to the image data to obtain a first frequency flag signal; or when the frame rate control mode is the second frame rate control mode, input the image data into the second frequency detection circuit 202 to utilize the second frequency detection circuit 202 to perform frequency detection on the line synchronization signal corresponding to the image data to obtain a second frequency flag signal.

[0067] The input end of the first selection circuit 105 is coupled to the first buffer circuit 203, the second buffer circuit 204 and the command register, and the output end is coupled to the image quality IP management module 107. The first selection circuit 105 is configured to select the image data read from the buffer according to the pixel clock in the first buffer circuit 203 or the second buffer circuit 204 according to the first control signal sent by the command register. The command register can be arranged in the display device 80 or the timing control circuit 10.

[0068] The input end of the second selection circuit 106 is coupled to the first frequency detection circuit 201, the second frequency detection circuit 202 and the command register, and the output end is coupled to the clock generation circuit 103. The second selection circuit 106 is configured to select the first frequency flag signal or the second frequency flag signal output according to the second control signal sent by the command register.

[0069] The functions / roles of the first buffer circuit 203, the second buffer circuit 204 and the clock generation circuit 103 in the display device 80 can refer to the above-mentioned embodiments, which will not be repeated here.

[0070] The output end of the image quality IP management module 107 is also coupled to the clock generation circuit 103, and the output end of the image quality IP management module 107 is coupled to the sending circuit 108. The image quality IP management module 107 contains an IP for processing image data.

[0071] In some embodiments, referring to Figure 10The timing control circuit 10 further comprises a read-write control circuit 110 and a video signal generation circuit 111, the read-write control circuit 110 is coupled to the receiving circuit 104 and the image quality IP management module 107, and the video signal generation circuit 111 is coupled to the receiving circuit 104 and the image quality IP management module 107. The read-write control circuit 110 can be built in the cache circuit 102, or independent of the cache circuit 102, that is, the read-write control circuit 110 is coupled to the cache circuit 102; the video signal generation circuit 111 can be independent of the cache circuit 102, that is, the video signal generation circuit 111 is coupled to the cache circuit 102. In other words, the read-write control circuit 110, the video signal generation circuit 111 and the cache circuit 102 can be integrated on one chip.

[0072] In some embodiments, referring to Figure 10 The timing control circuit 10 further comprises a clock switching circuit 112, the clock switching circuit 112 is coupled to the frequency detection circuit 101 and the clock generation circuit 103, and is used for receiving the target pixel clock sent by the clock generation circuit 103, and sending the target pixel clock to the display panel 109, so that the display panel 109 displays the image data according to the refresh rate corresponding to the target pixel clock. The proportion of the pixel clock transmitted between the clock switching circuit 112 and the clock generation circuit 103 at least includes 1, 1 / 2, 1 / 4 and 1 / 8, that is, when the cache circuit 102 writes the image data into the corresponding pixel clock x, the target pixel clock generated by the clock generation circuit 103 is x, 1 / 2x, 1 / 4x or 1 / 8x.

[0073] In some embodiments, the timing control circuit 10 further comprises a first data gating circuit and a second data gating circuit (not shown in the figure). The first data gating circuit is coupled to the frequency detection circuit 101, the cache circuit 102, the receiving circuit 104, the read-write control circuit 110 and the video signal generation circuit 111, and is used for selecting the corresponding synchronization signal according to the selected frame rate control mode, and sending the synchronization signal to the frequency detection circuit 101, so that the frequency detection circuit 101 performs frequency detection on the synchronization signal to obtain the frequency flag signal; the second data gating circuit is coupled to the image quality IP management module 107, the first selection circuit 105, the clock generation circuit 103 / the clock switching circuit 112, the cache circuit 102, the read-write control circuit 110 and the video signal generation circuit 111, and is used for generating an effective data signal.

[0074] Different from the prior art, the display device 80 provided by the application at least comprises an image processor 801, a timing control circuit 10, an image quality IP management module 107, a sending circuit 108 and a display panel 109, and the display panel 109 of the display device 80 will not appear phenomena such as frame freezing and frame tearing.

[0075] To sum up, the timing control circuit 10 provided by the application can adjust the target pixel clock when detecting that the frame rate of the image data output by the image processor 801 decreases / increases, so as to reduce the power consumption of the timing control circuit 10, and the target pixel clock is restored when detecting that the frame rate of the image data recovers, which can realize dynamic detection of the frame rate of the image data, and further dynamically update / switch the refresh rate of the display panel 109, reduce the power consumption of the timing control circuit 10, realize matching of the frame rate and the refresh rate, and ensure that the display panel 109 displays images uninterruptedly. Moreover, two frame rate control modes are provided, which can be suitable for various image processors 801.

[0076] The above description is only an embodiment of the application, and does not limit the patent scope of the application, and any equivalent structure or equivalent process transformation obtained by using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the application.

Claims

1. A timing control circuit of a display device, characterized by comprising: The timing control circuit comprises: a frequency detection circuit configured to perform frequency detection on a synchronization signal corresponding to image data sent by an image processor to obtain a frequency flag signal; the frequency flag signal represents a frame rate of the image data; a buffer circuit configured to buffer the image data; a clock generation circuit coupled to the frequency detection circuit and configured to generate a target pixel clock according to the frequency flag signal, the target pixel clock being used to cause a display panel to display the image data at a refresh rate corresponding to the target pixel clock; the synchronization signal comprises a frame synchronization signal and a line synchronization signal; the frequency detection circuit comprises: a first frequency detection circuit configured to perform frequency detection on a frame synchronization signal corresponding to image data sent by the image processor in a first frame rate control mode to obtain a first frequency flag signal; the first frame rate control mode is to change the frame rate by lengthening or shortening the time of field blanking while keeping the effective data length of original image data unchanged to obtain new image data; a second frequency detection circuit configured to perform frequency detection on a line synchronization signal corresponding to image data sent by the image processor in a second frame rate control mode to obtain a second frequency flag signal; the second frame rate control mode is to change the frame rate by lengthening or shortening the time of line blanking while keeping the effective data length of image data unchanged to obtain image data; the clock generation circuit is coupled to the first frequency detection circuit and the second frequency detection circuit respectively and configured to generate the target pixel clock according to the first frequency flag signal or the second frequency flag signal.

2. The timing control circuit of claim 1, wherein, The timing control circuit further comprises: a receiving circuit coupled to the first frequency detection circuit and the second frequency detection circuit and configured to receive the image data sent by the image processor and select the first frequency detection circuit or the second frequency detection circuit to perform frequency detection on the synchronization signal corresponding to the image data according to a frame rate control mode corresponding to the image data.

3. The timing control circuit of claim 2, wherein, The buffer circuit comprises: a first buffer circuit coupled to the receiving circuit and the first frequency detection circuit and configured to buffer the image data when the receiving circuit selects the first frequency detection circuit to perform frequency detection; a second buffer circuit coupled to the receiving circuit and the second frequency detection circuit and configured to buffer the image data when the receiving circuit selects the second frequency detection circuit to perform frequency detection.

4. The timing control circuit of claim 3, wherein, The first buffer circuit adopts frame buffer and the second buffer circuit adopts double line buffer.

5. The timing control circuit of claim 3, wherein, The timing control circuit further comprises a first selection circuit coupled to the first buffer circuit and the second buffer circuit respectively and configured to select the image data buffered from the first buffer circuit or the second buffer circuit according to the target pixel clock according to a first control signal.

6. The timing control circuit of claim 2, wherein, The timing control circuit further comprises a second selection circuit, a first input end of the second selection circuit is coupled with the first frequency detection circuit, a second input end of the second selection circuit is coupled with the second frequency detection circuit, and an output end of the second selection circuit is coupled with the clock generation circuit, and the second selection circuit is configured to select the first frequency flag signal or the second frequency flag signal to output according to a second control signal.

7. The timing control circuit of claim 6, wherein, The clock generation circuit is configured to generate a current target pixel clock with a frequency less than a last target pixel clock when a frame rate deviation corresponding to a current first frequency flag signal and a last first frequency flag signal is greater than a threshold value, or when a frame rate deviation corresponding to a current second frequency flag signal and a last second frequency flag signal is greater than the threshold value. And generate the current target pixel clock with a frequency equal to the last target pixel clock when the frame rate deviation corresponding to the current first frequency flag signal and the last first frequency flag signal is less than the threshold value, or when the frame rate deviation corresponding to the current second frequency flag signal and the last second frequency flag signal is less than the threshold value.

8. The timing control circuit of claim 1, wherein, The first frequency detection circuit is further configured to determine the first frequency flag signal corresponding to the current synchronization signal according to a time difference between adjacent synchronization signals determined according to a reference clock; The second frequency detection circuit is further configured to determine the second frequency flag signal corresponding to the current synchronization signal according to a time difference between adjacent synchronization signals determined according to the reference clock.

9. A display device, characterized by The display device comprises the timing control circuit according to any one of claims 1-8.

Images