Display panel and driving method thereof, driving circuit and display device

Abstract

The present invention proposes a display panel and its driving method, driving circuit and display device, wherein the display panel includes multiple scan lines, multiple data lines and array-arranged pixel units, the pixel units include pixel electrodes, storage capacitors, first transistors, comparison circuits and switch logic circuits, the comparison circuits compare the signals input by the data lines with a first reference voltage and output comparison signals corresponding to high and low levels, the switch logic circuits perform logical judgments on the levels of the signals input by the scan lines and the comparison signals and switch them on and off accordingly, thereby realizing the input of row scan signals and data signals to the first transistor to control whether the data signals of the pixel electrodes and the storage capacitors are written and refreshed, and by inputting data signals and row scan signals of different sizes to the data lines and scan lines, the pixel units can be controlled to maintain the current picture and switch the display picture, and independent control of a single pixel unit can be realized to meet display requirements with different refresh rates.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and in particular relates to a display panel and a driving method, a driving circuit and a display device thereof. Background Art

[0002] With the development of display technology and market demand, high refresh rate display devices have gradually come into people's view. Compared with traditional display devices, high refresh rate display devices have the advantages of smoother visual experience, faster response speed, and reduced visual fatigue. But at the same time, high refresh rate also brings higher power consumption requirements.

[0003] In response to the contradiction between the pursuit of visual images and power consumption requirements, a technology of differentiated local refresh rate FFR (freeframe rate) is proposed. When displaying a static image, when it is judged that the local display content of the image remains unchanged, the refresh rate is low here. When the image content changes in the next frame, the image has a high refresh rate here.

[0004] However, the current FRR technologies are all based on the timing adjustment of multiple GOA units in the gate drive circuit, which has great limitations. First, in the gate drive circuit, the GOA unit controls the picture in units of at least one line, and the local adjustment requirements of the refresh rate based on the changes in the picture content are complex. For example, when different positions on the same line of the picture require different refresh rates, it cannot be achieved.

[0005] In addition, due to the design characteristics of the GOA unit, the FFR technology based on GOA timing adjustment requires that the refresh rate of the previous row in the refresh direction is higher than that of the next row, which greatly limits the application scenarios of this technology. Summary of the invention

[0006] The object of the present invention is to provide a display panel, aiming to solve the problem that the driving architecture in the traditional display device cannot meet the requirements of different refresh rates at different positions.

[0007] A first aspect of an embodiment of the present invention provides a display panel, comprising a plurality of scan lines, a plurality of data lines and pixel units arranged in an array, wherein the pixel units are respectively connected to one of the scan lines and one of the data lines;

[0008] The pixel unit comprises:

[0009] Pixel electrode;

[0010] A storage capacitor, wherein a first end of the storage capacitor is connected to the pixel electrode, and a second end of the storage capacitor is connected to a common signal terminal;

[0011] A first transistor connected between the data line and the pixel electrode;

[0012] A comparison circuit connected to the data line and the first reference voltage terminal, the comparison circuit is used to compare the signal on the data line with the first reference voltage of the first reference voltage terminal and output a comparison signal;

[0013] A switch logic circuit is connected to the output end of the comparison circuit, the control end of the first transistor and the scan line. The switch logic circuit triggers the connection between the scan line and the first transistor when the comparison signal and the signal on the scan line are both at a high level, or triggers the disconnection between the scan line and the first transistor when one of the comparison signal and the signal on the scan line is at a low level.

[0014] Optionally, the switch logic circuit includes:

[0015] An AND gate, wherein a first input terminal of the AND gate is connected to the scan line, and a second input terminal of the AND gate is connected to an output terminal of the comparison circuit;

[0016] A switch circuit is connected in series between the scan line and the first transistor, a control end of the switch circuit is connected to the output end of the AND gate, and the switch circuit is turned on by a high level trigger and turned off by a low level trigger.

[0017] Optionally, the AND gate includes a first diode and a second diode;

[0018] The cathode of the first diode is connected to the scan line, the anode of the first diode, the anode of the second diode and the second reference voltage terminal are connected to form the signal output terminal of the AND gate, the cathode of the second diode is connected to the output terminal of the comparison circuit, and the second reference voltage of the second reference voltage terminal is less than the voltage of the row start signal input to the scan line.

[0019] Optionally, the switch circuit includes a second transistor and a bootstrap capacitor;

[0020] The first end of the second transistor is connected to the scan line, the second end of the second transistor is connected to the control end of the first transistor, the control end of the second transistor and the first end of the bootstrap capacitor are connected to form the control end of the switch circuit, and the second end of the bootstrap capacitor is grounded.

[0021] Optionally, the comparison circuit includes a third transistor, a fourth transistor, a fifth transistor and a resistor;

[0022] The first end of the third transistor is connected to the first reference voltage end, the second end of the third transistor, the first end of the resistor, the control end of the fourth transistor and the control end of the fifth transistor are connected, the control end of the third transistor is connected to the data line, the first end of the fourth transistor is connected to the second reference voltage end, the second end of the fourth transistor and the first end of the fifth transistor are connected to form the output end of the comparison circuit, and the second end of the fifth transistor is grounded.

[0023] A second aspect of an embodiment of the present invention provides a method for driving a display panel, which is used to drive the display panel as described above. The method for driving a display panel includes:

[0024] Determining whether the picture content of the next frame of the target partial picture of the display panel changes;

[0025] When the picture content of the next frame of the target partial picture remains unchanged, switching to the maintenance mode, and outputting a first data signal and a row start signal of corresponding magnitude to the target pixel unit corresponding to the target partial picture during the next frame scanning drive, and controlling the pixel electrode of the target pixel unit to maintain the data signal of the previous frame;

[0026] When the picture content of the next frame of the target local picture changes, it switches to the working mode, and during the next frame scanning drive, outputs a second data signal and a row start signal of corresponding size to the target pixel unit corresponding to the target local picture, and controls the pixel electrode of the target pixel unit to input the data signal of the current frame.

[0027] Optionally, when the picture content of the next frame of the target partial picture remains unchanged, switching to the maintenance mode, and outputting a first data signal of a corresponding size and a row start signal to a target pixel unit corresponding to the target partial picture during the next frame scan drive, comprises:

[0028] In a first period of the sustain mode, a high-level row start signal is output to the scan line, and a first enable signal is output or no signal is output to the data line, wherein the voltage of the first enable signal is less than a first reference voltage;

[0029] In the second period of the sustain mode, a row start signal is output to the scan line, and a data signal of the next frame is output to the data line or no signal is output to the data line.

[0030] Optionally, when the picture content of the next frame of the target partial picture changes, switching to the working mode, and outputting a second data signal of a corresponding size and a row start signal to the target pixel unit corresponding to the target partial picture during the next frame scan drive, includes:

[0031] In a first period of the working mode, a row start signal is output to the scan line, and a second enable signal is output to the data line, wherein a voltage of the second enable signal is greater than the first reference voltage;

[0032] In the second period of the working mode, a row start signal is output to the scan line, and a data signal of the next frame is output to the data line, and the data signal of the next frame is output to the pixel electrode of the target pixel unit through the first transistor;

[0033] In the third period of the working mode, a low-level row closing signal is output to the scan line, and the pixel electrode of the target pixel unit is controlled to maintain the data signal of the current frame.

[0034] A third aspect of an embodiment of the present invention provides a driving circuit of a display panel, comprising a source driving circuit, a gate driving circuit and a timing controller, wherein the source driving circuit is respectively connected to a plurality of data lines of the display panel, and the gate driving circuit is respectively connected to a plurality of data lines of the display panel;

[0035] The timing controller is connected to the source driving circuit and the gate driving circuit respectively, and is used to output control signals to the source driving circuit and the gate driving circuit to implement the display panel driving method as described above.

[0036] A fourth aspect of the embodiments of the present invention provides a display device, comprising the display panel as described above and a driving circuit for the display panel as described above, wherein the driving circuit for the display panel is connected to the display panel.

[0037] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned display panel includes multiple scan lines, multiple data lines and pixel units arranged in an array, the pixel unit includes a pixel electrode, a storage capacitor, a first transistor, a comparison circuit and a switching logic circuit, the comparison circuit compares the signal input by the data line with the first reference voltage, and outputs a comparison signal corresponding to the high and low levels, the switching logic circuit performs logical judgment on the level of the signal input by the scan line and the comparison signal and switches on and off accordingly, thereby realizing the input of the row scan signal and the data signal to the first transistor to control whether the data signal of the pixel electrode and the storage capacitor is written and refreshed, and by inputting data signals and row scan signals of different sizes to the data line and the scan line, the pixel unit can be controlled to maintain the current picture and switch the display picture, and independent control of a single pixel unit can be realized to meet the display requirements of different refresh rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 A schematic diagram of the structure of a display panel provided in Embodiment 1 of the present invention;

[0040] Figure 2 A first circuit diagram of a pixel unit provided in Embodiment 1 of the present invention;

[0041] Figure 3 A second circuit diagram of a pixel unit provided in the first embodiment of the present invention;

[0042] Figure 4 A third circuit diagram of a pixel unit provided in the first embodiment of the present invention;

[0043] Figure 5 A schematic diagram of a flow chart of a method for driving a display panel provided in Embodiment 2 of the present invention;

[0044] Figure 6 for Figure 5 The schematic flow chart of step S20 of the method for driving the display panel is shown;

[0045] Figure 7 A schematic diagram of a first signal timing sequence of a pixel unit provided in the second embodiment of the present invention;

[0046] Figure 8 A schematic diagram of a second signal timing sequence of a pixel unit provided in the second embodiment of the present invention;

[0047] Fig. 9 for Figure 5 The schematic flow chart of step S30 of the method for driving the display panel is shown;

[0048] Fig.10 A third signal timing diagram of a pixel unit provided in the second embodiment of the present invention;

[0049] Fig.11 A schematic diagram of a first structure of a display panel provided in Embodiment 2 of the present invention;

[0050] Fig.12 A schematic diagram of a fourth signal timing sequence of a pixel unit provided in the second embodiment of the present invention;

[0051] Fig.13 A second structural schematic diagram of a display panel provided in Embodiment 2 of the present invention;

[0052] Fig.14 A fifth signal timing diagram of a pixel unit provided in the second embodiment of the present invention;

[0053] Fig.15 This is a schematic structural diagram of a display panel driving circuit and a display device provided in Embodiment 3 and Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0054] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0056] Embodiment 1

[0057] A first aspect of an embodiment of the present invention provides a display panel 100, such as Figure 1 As shown, the display panel 100 includes a plurality of scan lines G, a plurality of data lines S and array-arranged pixel units 10, and the pixel units 10 are respectively connected to a scan line G and a data line S. The display panel 100 also includes an array substrate, a color filter substrate and a liquid crystal layer disposed between the array substrate and the color filter substrate. The scan lines G, the data lines S and the array-arranged pixel units 10 are disposed on the array substrate. Figure 2 As shown, the pixel unit 10 includes a pixel electrode 11, a color filter layer and a common electrode layer are arranged on the color filter substrate, the common electrode layer has a first common electrode voltage, the data signal Vdata input to the pixel electrode 11 and the first common electrode voltage form a driving voltage, and drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color filter layer to control the pixel unit 10 to display corresponding image information.

[0058] In order to independently control each pixel unit 10 of the target partial screen or the target pixel unit to meet the requirements of different refresh rates, the pixel unit 10 further includes:

[0059] A storage capacitor Cst, wherein a first end of the storage capacitor Cst is connected to the pixel electrode 11, and a second end of the storage capacitor Cst is connected to the common signal terminal;

[0060] A first transistor Q1 is connected between the data line S and the pixel electrode 11;

[0061] A comparison circuit 12 is connected to the data line S and the first reference voltage terminal, and the comparison circuit 12 is used to compare the signal on the data line S with the first reference voltage Vref1 of the first reference voltage terminal, and output a comparison signal;

[0062] The switch logic circuit 13 is connected to the output end of the comparison circuit 12, the control end of the first transistor Q1 and the scan line G. The switch logic circuit 13 triggers the connection between the scan line G and the first transistor Q1 when the comparison signal and the signal on the scan line G are both at a high level, or triggers the disconnection between the scan line G and the first transistor Q1 when one of the comparison signal and the signal on the scan line G is at a low level.

[0063] Among them, the storage capacitor Cst is connected to the common point end of the pixel electrode 11 and the array substrate, the common electrode end is used to input the second common electrode voltage Vcom, and the storage capacitor Cst is used to store the data signal Vdata of the current frame and store the refreshed data signal Vdata when the data signal Vdata of the next frame is written.

[0064] The first transistor Q1 constitutes a driving transistor in the pixel unit 10, and is used to implement writing control of the data signal Vdata. The pixel unit 10 can operate in a working mode and a maintaining mode. The working mode can refresh the input data signal Vdata, and the maintaining mode can maintain the data signal Vdata of the previous frame.

[0065] In the progressive scanning, when scanning reaches a plurality of target pixel units of the target partial picture, the number of the target pixel units may include one or more.

[0066] In the working mode, when the target pixel unit receives the row start signal VGH, the row start signal VGH is input to the switch logic circuit 13. When the selected input data signal Vdata is greater than the first reference voltage Vref1, the comparison circuit 12 outputs a high-level comparison signal. After receiving the high levels of the two paths, the switch logic circuit 13 triggers the connection of the scan line G and the first transistor Q1. The row start signal VGH is input to the first transistor Q1. The first transistor Q1 is triggered to turn on by the row start signal VGH. At this time, the data signal Vdata can be input to the pixel electrode 11 and the storage capacitor Cst through the first transistor Q1. The storage capacitor Cst can be charged, and its terminal voltage is refreshed to the voltage of the input data signal Vdata, and the voltage of the pixel electrode 11 is maintained stable at the refreshed data signal Vdata. The data signal Vdata and the common electrode layer form a driving voltage to drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color filter layer to control the pixel unit 10 to display the corresponding image information, thereby achieving a high refresh rate of the local picture.

[0067] And in the maintenance mode, when the selected input data signal Vdata is less than the first reference voltage Vref1 and / or the row start signal VGH is not input, the comparison circuit 12 outputs a low-level comparison signal, and the switch logic circuit 13 is triggered to shut down. At this time, the first transistor Q1 has no control signal input, and the data signal Vdata cannot be written. The storage capacitor Cst maintains the voltage of the pixel electrode 11 stable at the data signal Vdata input in the previous frame. The data signal Vdata and the common electrode layer form a driving voltage to drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color film layer to control the pixel unit 10 to display the corresponding image information, thereby achieving a low refresh rate of the local picture.

[0068] Therefore, the pixel unit 10 can refresh or maintain the data signal Vdata under the control of the dual signals of the data signal Vdata and the input row scanning signal, so as to achieve the control of the refresh rate of the target pixel unit.

[0069] For example, when it is necessary to control two pixel units 10 in adjacent columns in the same row to have different refresh rates, the same row start signal VGH can be input to the two pixel units 10 in the row, and data signals Vdata of different sizes can be input respectively. For example, the pixel units 10 in the first column input the data signal Vdata higher than the first reference voltage Vref1, and the pixel units 10 in the second column input the data signal Vdata lower than the first reference voltage Vref1. The pixel units 10 in the first column can store the data signal Vdata written in the frame refresh to achieve a high refresh rate, and the pixel units 10 in the second column store the data signal Vdata written in the previous frame to achieve a low refresh rate.

[0070] Similarly, when it is necessary to control two adjacent pixel units 10 in the same column to have different refresh rates, the row start signal VGH can be input row by row to the two pixel units 10 in the column, and data signals Vdata of different sizes can be input respectively during row scanning. For example, when scanning the pixel unit 10 in the first row, a data signal Vdata higher than the first reference voltage Vref1 is input, and when scanning the pixel unit 10 in the second row, a data signal Vdata lower than the first reference voltage Vref1 is input. The pixel unit 10 in the first row can store the data signal Vdata written by the frame refresh to achieve a high refresh rate, and the pixel unit 10 in the second row stores the data signal Vdata written in the previous frame to achieve a low refresh rate.

[0071] Among them, in order to ensure that the written data signal Vdata meets the current grayscale data requirements and avoid display abnormalities, the data signal Vdata written by the data line S inputs data signals Vdata of different sizes according to different time periods. The data signal Vdata input each time includes the enable signal and the target data signal Vdata of the previous and next time periods. In the first time period when the row start signal VGH is written, an enable signal greater than or less than the first reference voltage Vref1 is input. The enable signal controls the on and off of the switching logic circuit 13, and realizes the writing control of the row start signal VGH of the first transistor Q1. In the second time period when the row start signal VGH is written, the target data signal Vdata that meets the current grayscale requirements is input. The target data signal Vdata is selected to be written into the pixel electrode 11 or the output pixel electrode 11 is cut off through the first transistor Q1, thereby driving the pixel unit 10 to display the target grayscale and picture.

[0072] The switch logic circuit 13 may adopt corresponding logic gates, switches and the like. In an optional embodiment, Figure 3 As shown, the switch logic circuit 13 includes:

[0073] An AND gate 131, wherein a first input terminal of the AND gate 131 is connected to the scan line G, and a second input terminal of the AND gate 131 is connected to the output terminal of the comparison circuit 12;

[0074] The switch circuit 132 is connected in series between the scan line G and the first transistor Q1. The control end of the switch circuit 132 is connected to the output end of the AND gate 131. The switch circuit 132 is turned on by a high level trigger and turned off by a low level trigger.

[0075] In this embodiment, when the input data signal Vdata is greater than the first reference voltage Vref1, the comparison circuit 12 outputs a high-level comparison signal, and when the row start signal VGH is input, the AND gate 131 outputs a high level, the switch circuit 132 is triggered to turn on together with the scan line G and the first transistor Q1. At this time, the row start signal VGH can be written into the first transistor Q1 and control the first transistor Q1 to trigger conduction. At this time, the data signal Vdata can be written, and the pixel unit 10 can store the data signal Vdata written by the frame refresh to achieve a high refresh rate.

[0076] And when the input data signal Vdata is less than the first reference voltage Vref1, the comparison circuit 12 outputs a low level, and / or the scan line G inputs a low-level row close signal VGL, the AND gate 131 outputs a low level, and the switch circuit 132 is triggered to shut down. At this time, the first transistor Q1 has no control signal input, and the first transistor Q1 remains turned off. At this time, the data signal Vdata cannot be written, and the pixel unit 10 stores the data signal Vdata written in the previous frame to achieve a low refresh rate.

[0077] In order to simplify the circuit structure, the AND gate 131, the switch circuit 132 and the comparison circuit 12 can be composed of corresponding transistors. In an optional embodiment, Figure 4 As shown, the AND gate 131 includes a first diode D1 and a second diode D2;

[0078] The cathode of the first diode D1 is connected to the scan line G, the anode of the first diode D1, the anode of the second diode D2 and the second reference voltage terminal are connected to form the signal output terminal of the AND gate 131, the cathode of the second diode D2 is connected to the output terminal of the comparison circuit 12, and the second reference voltage Vref2 of the second reference voltage terminal is less than the voltage of the row start signal VGH input to the scan line G.

[0079] The switch circuit 132 includes a second transistor Q2 and a bootstrap capacitor Cboost;

[0080] The first end of the second transistor Q2 is connected to the scan line G, the second end of the second transistor Q2 is connected to the control end of the first transistor Q1, the control end of the second transistor Q2 and the first end of the bootstrap capacitor Cboost are connected to form the control end of the switch circuit 132, and the second end of the bootstrap capacitor Cboost is grounded.

[0081] The comparison circuit 12 includes a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5 and a resistor R1;

[0082] A first end of the third transistor Q3 is connected to the first reference voltage end, a second end of the third transistor Q3, a first end of the resistor R1, a control end of the fourth transistor Q4 and a control end of the fifth transistor Q5 are connected, the control end of the third transistor Q3 is connected to the data line S, a first end of the fourth transistor Q4 is connected to the second reference voltage end, a second end of the fourth transistor Q4 and a first end of the fifth transistor Q5 are connected to form an output end of the comparison circuit 12, and a second end of the fifth transistor Q5 is grounded.

[0083] In this embodiment, the pixel unit 10 can operate in an operating mode and a maintaining mode. When in the operating mode, the initial input enable signal is greater than the first reference voltage Vref1, the third transistor Q3 is triggered to turn on, the fourth transistor Q4 is triggered to turn on, and the fifth transistor Q5 is triggered to turn off. The comparison circuit 12 outputs a high level, the first diode D1 is cut off, and a high level is input to the control end of the second transistor Q2, and the second transistor Q2 is triggered to turn on. At this time, the on and off of the first transistor Q1 is triggered by the row start signal VGH input by the scan line G. In the second stage of the operating mode, the control end of the second transistor Q2 maintains a high level due to the presence of the bootstrap capacitor Cboost, the second transistor Q2 and the first transistor Q1 remain turned on, and the target data signal Vdata can be written into the pixel electrode 11 and the storage capacitor Cst through the first transistor Q1. The pixel unit 10 can store the data signal Vdata written by the frame refresh to achieve a high refresh rate.

[0084] In the maintenance mode, an enable signal less than the first reference voltage Vref1 can be input in the first time period T11 of the maintenance mode, the third transistor Q3 is triggered to turn off, the fourth transistor Q4 and the fifth transistor Q5 are triggered to turn off, the first diode D1 is turned off, the control end of the second transistor Q2 is at a low level due to the reset of the previous frame, the second diode D2 is turned on or off, the second transistor Q2 is triggered to turn off, the first transistor Q1 is not controlled by the row scan signal input by the scan line G, and the first transistor Q1 remains in the off state.

[0085] In the second time period T12 of the maintenance mode, it is in the data writing period. Since the first transistor Q1 remains in the off state, at this time, the data signal Vdata can be written or not written directly. The storage capacitor Cst and the pixel electrode 11 maintain the data signal Vdata of the previous frame to achieve high and low refresh rates.

[0086] Embodiment 2

[0087] A second aspect of an embodiment of the present invention provides a method for driving a display panel 100, which is used to drive the display panel 100. Figure 5 As shown, the driving method of the display panel 100 includes:

[0088] S10, determining whether the picture content of the next frame of the target partial picture of the display panel 100 changes;

[0089] S20. When the picture content of the next frame of the target partial picture remains unchanged, switch to the maintenance mode, and during the next frame scan drive, output the first data signal Vdata and the row start signal VGH of the corresponding size to the target pixel unit corresponding to the target partial picture, and control the pixel electrode 11 of the target pixel unit to maintain the data signal Vdata of the previous frame.

[0090] In this embodiment, when the target local screen displays a static screen, the characteristic values ​​of the subsequent screens can be analyzed to determine whether the target local screen has changed. When it is determined that the display content of the target local screen remains unchanged, the target local screen has a low refresh rate. At this time, it is switched to the maintenance mode, and the data signal Vdata output to the pixel unit 10 can be selected to be less than the first reference voltage Vref1 and / or the row start signal VGH is not output to the pixel unit 10. The comparison circuit 12 of the pixel unit 10 outputs a low-level comparison signal, and the switch logic circuit 13 of the pixel unit 10 is triggered to shut down. At this time, the first transistor Q1 of the pixel unit 10 has no control signal input, and the data signal Vdata cannot be written. The storage capacitor Cst maintains the voltage of the pixel electrode 11 stable at the data signal Vdata input in the previous frame. The data signal Vdata and the common electrode layer form a driving voltage to drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color film layer to control the pixel unit 10 to display the corresponding image information, thereby achieving a low refresh rate of the local screen.

[0091] In order to ensure that the written data signal Vdata meets the current grayscale data requirements and avoid display abnormalities, the data signal Vdata written by the data line S inputs data signals Vdata of different sizes according to different time periods. Each input data signal Vdata may include an enable signal and a target data signal Vdata in the previous and next time periods. Correspondingly, Figures 6 to 8 As shown, S20 includes:

[0092] S21, in the first period T11 of the sustain mode, outputting a high level row start signal VGH to the scan line G, and outputting a first enable signal EN1 or not outputting a signal to the data line S, wherein the voltage of the first enable signal EN1 is less than the first reference voltage Vref1;

[0093] S22 . In the second period T12 of the sustain mode, the row start signal VGH is output to the scan line G, and the data signal Vdata of the next frame is output to the data line S or no signal is output to the data line S.

[0094] In this embodiment, the first enable signal EN1 is less than the first reference voltage Vref1, and the first enable signal EN1 may have a voltage value of a corresponding magnitude or a voltage value of zero. In the first period T11 of the maintenance mode, the comparison circuit 12 of the pixel unit 10 outputs a low-level comparison signal, and the switch logic circuit 13 of the pixel unit 10 is triggered to turn off. At this time, the first transistor Q1 of the pixel unit 10 has no control signal input, and the data signal Vdata cannot be written. In the second period T12 of the maintenance mode, the row start signal VGH maintains a high level. At this time, Figure 7 As shown, the data signal Vdata of the next frame can be selected to be output, or as Figure 8As shown, the data signal Vdata of the next frame is not output, and the storage capacitor Cst maintains the voltage of the pixel electrode 11 stable at the data signal Vdata input in the previous frame. The data signal Vdata of the previous frame forms a driving voltage with the common electrode layer to drive the liquid crystal deflection of the liquid crystal layer, and cooperates with the color filter layer to control the pixel unit 10 to display the corresponding image information, thereby achieving a low refresh rate of the local picture.

[0095] S30. When the picture content of the next frame of the target local picture changes, switch to the working mode, and during the next frame scanning drive, output the second data signal Vdata and the row start signal VGH of the corresponding size to the target pixel unit corresponding to the target local picture, and control the pixel electrode 11 of the target pixel unit to input the data signal Vdata of the current frame.

[0096] When it is determined that the target local picture changes in the next frame, the target local picture has a high refresh rate. At this time, it is switched to the working mode, and the row start signal VGH can be selected to be output and the data signal Vdata greater than the first reference voltage Vref1 can be selected to be output to the target pixel unit of the target local picture. The row start signal VGH is input to the switch logic circuit 13, and the comparison circuit 12 outputs a high-level comparison signal. After receiving the high levels of the two paths, the switch logic circuit 13 triggers the connection of the scan line G and the first transistor Q1. The row start signal VGH is input to the first transistor Q1, and the first transistor Q1 is triggered to be turned on by the row start signal VGH. At this time, the data signal Vdata can be input to the pixel electrode 11 and the storage capacitor Cst through the first transistor Q1, and the storage capacitor Cst can be charged, and the voltage of the pixel electrode 11 is switched and maintained stable at the data signal Vdata refreshed in the next frame. The data signal Vdata and the common electrode layer form a driving voltage to drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color filter layer to control the pixel unit 10 to display the corresponding image information, so as to achieve a high refresh rate of the local picture.

[0097] In order to ensure that the written data signal Vdata meets the current grayscale data requirements and avoid display abnormalities, the data signal Vdata written by the data line S inputs data signals Vdata of different sizes according to different time periods. Each input data signal Vdata may include an enable signal and a target data signal Vdata of the previous and next time periods. Correspondingly, in an optional embodiment, as Fig. 9 and Fig.10 As shown, S30 includes:

[0098] S31, in the first period T21 of the working mode, outputting a row start signal VGH to the scan line G, and outputting a second enable signal EN2 to the data line S, wherein the voltage of the second enable signal EN2 is greater than the first reference voltage Vref1;

[0099] S32, in the second period T22 of the working mode, outputting the row start signal VGH to the scan line G, and outputting the data signal Vdata of the next frame to the data line S, and the data signal Vdata of the next frame is output to the pixel electrode 11 of the target pixel unit through the first transistor Q1;

[0100] S33 , in the third period T23 of the working mode, outputting a low-level line-off signal VGL to the scan line G, and controlling the pixel electrode 11 of the target pixel unit to maintain the data signal Vdata of the current frame.

[0101] In the first time period T21 of the working mode, the row start signal VGH is at a high level, the second enable signal EN2 is greater than the first reference voltage Vref1, the comparison circuit 12 outputs a high level comparison signal, the switch logic circuit 13 triggers the connection between the scan line G and the first transistor Q1, the row start signal VGH is input to the first transistor Q1, and the first transistor Q1 is triggered to turn on by the row start signal VGH.

[0102] In the second time period T22 of the working mode, the data signal Vdata of the next frame is output to the pixel electrode 11 and the storage capacitor Cst through the turned-on first transistor Q1. The storage capacitor Cst can be charged to switch and maintain the voltage of the pixel electrode 11 stable at the data signal Vdata refreshed in the next frame. The data signal Vdata and the common electrode layer form a driving voltage to drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color filter layer to control the pixel unit 10 to display the corresponding image information, thereby achieving a high refresh rate of the local picture.

[0103] In the third period T23 of the working mode, the row start signal VGH scans to the next row, the row scan signal of the target pixel unit is switched to the row close signal VGL, the potential of the control end of the second transistor Q2 drops, the second transistor Q2 and the first transistor Q1 are triggered to turn off, and the storage capacitor Cst in the target pixel unit latches the data signal Vdata of the current frame until the next data refresh.

[0104] Therefore, the pixel unit 10 can be controlled to be turned on or off correspondingly by inputting a data signal Vdata of corresponding magnitude and an input row scanning signal, thereby refreshing or maintaining the data signal Vdata to achieve control of the refresh rate of the target pixel unit.

[0105] When it is necessary to control different pixel units 10 in the same column to switch to different refresh rates, for example Fig.11 and Fig.12As shown, when the pixel units 10 of the first row to the third row of the same column are switched to different refresh rates in different frames, in the first frame, when the pixel units 10 of the first row are scanned, the second enable signal EN2 and the data signal Vdata of the first frame are output, and the pixel units 10 of the first row can write the data signal Vdata of the first frame and switch to a high refresh rate, and when the pixel units 10 of the second row are scanned, the first enable signal EN1 is output. At this time, the pixel units 10 of the second row cannot write the data signal Vdata, maintain the data signal Vdata of the previous frame and switch to a low refresh rate, and when the pixel units 10 of the third row are scanned, the first enable signal EN1 is output. At this time, the pixel units 10 of the third row cannot write the data signal Vdata, maintain the data signal Vdata of the previous frame and switch to a low refresh rate.

[0106] Similarly, when refreshing to the second frame, when scanning the pixel units 10 of the first row, the first enable signal EN1 is output, at this time, the pixel units 10 of the first row cannot write the data signal Vdata, maintain the data signal Vdata in the first frame and switch to a low refresh rate, and when scanning the pixel units 10 of the second row, the first enable signal EN1 is output, at this time, the pixel units 10 of the second row cannot write the data signal Vdata, maintain the data signal Vdata in the first frame and switch to a low refresh rate, when scanning the pixel units 10 of the third row, the first enable signal EN1 is output, at this time, the pixel units 10 of the third row cannot write the data signal Vdata, maintain the data signal Vdata in the first frame and switch to a low refresh rate.

[0107] When refreshing to the third frame, when scanning the pixel units 10 of the first row, the second enable signal EN2 and the data signal Vdata of the third frame are output, and the pixel units 10 of the first row can write the data signal Vdata of the third frame and switch to a high refresh rate, and when scanning the pixel units 10 of the second row, the first enable signal EN1 is output. At this time, the pixel units 10 of the second row cannot write the data signal Vdata, maintain the data signal Vdata of the first frame and switch to a low refresh rate, and when scanning the pixel units 10 of the third row, the second enable signal EN2 and the data signal Vdata of the third frame are output, and the pixel units 10 of the third row can write the data signal Vdata of the third frame and switch to a high refresh rate.

[0108] Therefore, in different frames, the refresh rates of different target pixel units in the same row can be adjusted and switched.

[0109] When it is necessary to control different pixel units 10 in the same row to switch to different refresh rates, such as Fig.13 and Fig.14As shown, in the first frame, the first scan line G1 inputs the row start signal VGH. At this time, the first data line S1 writes the second enable signal EN2 and the data signal Vdata of the first frame, and the pixel unit 10 in the first row and the first column can write the data signal Vdata of the first frame and switch to a high refresh rate, and the second data line S2 writes the first enable signal EN1, and the pixel unit 10 in the second column of the first row cannot write the data signal Vdata, maintains the data signal Vdata of the previous frame and switches to a low refresh rate.

[0110] Then scan to the second row, the second scan line G2 inputs the row start signal VGH, at this time, the first data line S1 writes the first enable signal EN1, the pixel unit 10 in the first column of the second row cannot write the data signal Vdata, maintains the data signal Vdata of the previous frame and switches to a low refresh rate, and the second data line S2 writes the second enable signal EN2 and the data signal Vdata of the first frame, the pixel unit 10 in the second row and the second column can write the data signal Vdata of the first frame and switch to a high refresh rate, and so on. When scanning row by row, the writing of the data signal Vdata can be switched by switching the size of the enable signal to switch or maintain the refresh rate of the pixel unit 10.

[0111] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0112] Embodiment 3

[0113] A third aspect of an embodiment of the present invention provides a driving circuit 200 for a display panel, such as Fig.15 As shown, the driving circuit 200 of the display panel includes a source driving circuit 210, a gate driving circuit 220 and a timing controller 230, the source driving circuit 210 is respectively connected to a plurality of data lines S of the display panel 100, and the gate driving circuit 220 is respectively connected to a plurality of data lines S of the display panel 100;

[0114] The timing controller 230 is connected to the source driving circuit 210 and the gate driving circuit 220 respectively. The timing controller 230 is used to output control signals to the source driving circuit 210 and the gate driving circuit 220 to implement the above driving method of the display panel 100.

[0115] In this embodiment, the source driver circuit 210 is used to output an enable signal and a data signal Vdata. The source enable signal and the data signal Vdata can be output by different driver chips or by a single source driver chip in the source driver circuit 210. The gate driver circuit 220 is used to output a row start signal VGH row by row.

[0116] When the target local screen displays a static picture, the timing controller 230 analyzes the characteristic values ​​of the subsequent pictures to determine whether the target local screen has changed. When it is determined that the display content of the target local screen remains unchanged, the target local screen has a low refresh rate. At this time, it switches to the maintenance mode. The timing controller 230 controls the source driver circuit 210 to output the first enable signal EN1 to the target pixel unit of the target local screen, thereby controlling the target pixel unit to maintain the data signal Vdata and display picture of the previous frame to achieve a low refresh rate.

[0117] When it is determined that the target local picture changes in the next frame, the target local picture has a high refresh rate. At this time, it switches to the working mode, and the timing controller 230 controls the source driving circuit 210 to output the second enable signal EN2 to the target pixel unit of the target local picture, and outputs the data signal Vdata required by the target pixel unit, thereby controlling the target pixel unit to switch to the data signal Vdata and display picture of the next frame to achieve a high refresh rate.

[0118] Embodiment 4

[0119] The present invention also provides a display device, such as Fig.15 As shown, the display device includes a display panel 100 and a display panel driving circuit 200. The specific structures of the display panel 100 and the display panel driving circuit 200 refer to the above embodiments. Since the display device adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the display panel driving circuit 200 is connected to the display panel 100.

[0120] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: It comprises a plurality of scan lines, a plurality of data lines and pixel units arranged in an array, wherein the pixel units are respectively connected to one of the scan lines and one of the data lines; The pixel unit comprises: Pixel electrode; A storage capacitor, wherein a first end of the storage capacitor is connected to the pixel electrode, and a second end of the storage capacitor is connected to a common signal terminal; A first transistor connected between the data line and the pixel electrode; A comparison circuit connected to the data line and the first reference voltage terminal, the comparison circuit is used to compare the signal on the data line with the first reference voltage of the first reference voltage terminal and output a comparison signal; a switch logic circuit connected to the output end of the comparison circuit, the control end of the first transistor and the scan line, wherein the switch logic circuit triggers the connection between the scan line and the first transistor when the comparison signal and the signal on the scan line are both at a high level, or triggers the disconnection between the scan line and the first transistor when one of the comparison signal and the signal on the scan line is at a low level; Wherein, the pixel unit operates in a maintenance mode or a working mode. In the maintenance mode and during the next frame scanning drive, the target pixel unit corresponding to the target partial screen inputs a first data signal and a row start signal of a corresponding size, and controls the pixel electrode of the target pixel unit to maintain the data signal of the previous frame; In the working mode and during the next frame scanning drive, the target pixel unit corresponding to the target partial picture inputs the second data signal and the row start signal of corresponding magnitude, and controls the pixel electrode of the target pixel unit to input the data signal of the current frame.

2. The display panel according to claim 1, wherein: The switch logic circuit comprises: An AND gate, wherein a first input terminal of the AND gate is connected to the scan line, and a second input terminal of the AND gate is connected to an output terminal of the comparison circuit; A switch circuit is connected in series between the scan line and the first transistor, a control end of the switch circuit is connected to the output end of the AND gate, and the switch circuit is turned on by a high level trigger and turned off by a low level trigger.

3. The display panel according to claim 2, wherein: The AND gate includes a first diode and a second diode; The cathode of the first diode is connected to the scan line, the anode of the first diode, the anode of the second diode and the second reference voltage terminal are connected to form the signal output terminal of the AND gate, the cathode of the second diode is connected to the output terminal of the comparison circuit, and the second reference voltage of the second reference voltage terminal is less than the voltage of the row start signal input to the scan line.

4. The display panel according to claim 2, wherein: The switch circuit includes a second transistor and a bootstrap capacitor; The first end of the second transistor is connected to the scan line, the second end of the second transistor is connected to the control end of the first transistor, the control end of the second transistor and the first end of the bootstrap capacitor are connected to form the control end of the switch circuit, and the second end of the bootstrap capacitor is grounded.

5. The display panel according to any one of claims 1 to 4, characterized in that: The comparison circuit includes a third transistor, a fourth transistor, a fifth transistor and a resistor; The first end of the third transistor is connected to the first reference voltage end, the second end of the third transistor, the first end of the resistor, the control end of the fourth transistor and the control end of the fifth transistor are connected, the control end of the third transistor is connected to the data line, the first end of the fourth transistor is connected to the second reference voltage end, the second end of the fourth transistor and the first end of the fifth transistor are connected to form the output end of the comparison circuit, and the second end of the fifth transistor is grounded.

6. A method for driving a display panel, for driving the display panel according to any one of claims 1 to 5, characterized in that: The driving method of the display panel includes: Determining whether the picture content of the next frame of the target partial picture of the display panel changes; When the picture content of the next frame of the target partial picture remains unchanged, switching to the maintenance mode, and outputting a first data signal and a row start signal of corresponding magnitude to the target pixel unit corresponding to the target partial picture during the next frame scanning drive, and controlling the pixel electrode of the target pixel unit to maintain the data signal of the previous frame; When the picture content of the next frame of the target local picture changes, it switches to the working mode, and during the next frame scanning drive, outputs a second data signal and a row start signal of corresponding size to the target pixel unit corresponding to the target local picture, and controls the pixel electrode of the target pixel unit to input the data signal of the current frame.

7. The method for driving a display panel according to claim 6, wherein: When the picture content of the next frame of the target partial picture remains unchanged, the mode is switched to the maintenance mode, and when the next frame is scanned and driven, a first data signal of a corresponding size and a row start signal are output to a target pixel unit corresponding to the target partial picture, including: In a first period of the sustain mode, a high-level row start signal is output to the scan line, and a first enable signal is output or no signal is output to the data line, wherein the voltage of the first enable signal is less than a first reference voltage; In the second period of the sustain mode, a row start signal is output to the scan line, and a data signal of the next frame is output to the data line or no signal is output to the data line.

8. The method for driving a display panel according to claim 6, wherein: When the picture content of the next frame of the target partial picture changes, switching to the working mode, and outputting a second data signal of a corresponding size and a row start signal to the target pixel unit corresponding to the target partial picture during the next frame scanning drive, comprises: In a first period of the working mode, a row start signal is output to the scan line, and a second enable signal is output to the data line, wherein a voltage of the second enable signal is greater than the first reference voltage; In the second period of the working mode, a row start signal is output to the scan line, and a data signal of the next frame is output to the data line, and the data signal of the next frame is output to the pixel electrode of the target pixel unit through the first transistor; In the third period of the working mode, a low-level row closing signal is output to the scan line, and the pixel electrode of the target pixel unit is controlled to maintain the data signal of the current frame.

9. A driving circuit for a display panel, characterized in that: It includes a source driving circuit, a gate driving circuit and a timing controller, wherein the source driving circuit is respectively connected to a plurality of data lines of the display panel, and the gate driving circuit is respectively connected to a plurality of data lines of the display panel; The timing controller is connected to the source driving circuit and the gate driving circuit respectively, and the timing controller is used to output control signals to the source driving circuit and the gate driving circuit to implement the driving method of the display panel as described in any one of claims 6 to 8.

10. A display device, characterized in that: The invention comprises a display panel as claimed in any one of claims 1 to 5 and a driving circuit of the display panel as claimed in claim 9, wherein the driving circuit of the display panel is connected to the display panel.

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