Error correction capability evaluation method and data storage system

Abstract

The invention provides an error correction capability evaluation method and a data storage system. The method comprises the following steps: establishing an automatic test script, wherein the automatic test script performs programming based on a Shell script; and running the automated test script to execute an automated test program for the error correction circuit of the storage device. Therefore, the management efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to an error correction capability evaluation method and a data storage system. Background Art

[0002] NAND flash is a non-volatile storage solution that is widely used in a variety of electronic products such as solid-state drives and mobile devices. It is well-known for its high-density storage, low power consumption, and fast read and write characteristics. However, with the advancement of technology, the storage capacity per unit area in storage devices has been greatly improved, but it has also brought about higher bit error rates and lower data durability problems. Data errors mainly come from natural phenomena such as physical wear, read interference, and charge loss over time. These factors work together to make it difficult for unprocessed data to maintain its accuracy for a long time.

[0003] In order to solve the above problems and improve data reliability, modern NAND flash devices are usually integrated with advanced error correction coding mechanisms. Through the application of these error correction technologies, not only errors in the data transmission process are effectively detected and corrected, but also the actual service life of the storage medium is greatly extended, ensuring that good performance can be maintained even after long-term use.

[0004] In summary, an excellent error correction circuit is an indispensable part of building a high-performance, high-reliability NAND flash device. Therefore, when developing new storage solutions, choosing a suitable error correction strategy is an important topic that needs to be studied by those skilled in the art. Summary of the invention

[0005] The present invention provides an error correction capability evaluation method and a data storage system, which can efficiently and accurately evaluate the error correction capability of an error correction circuit in a storage device, thereby improving the subsequent management efficiency of the storage device.

[0006] An embodiment of the present invention provides an error correction capability evaluation method for a storage device, wherein the storage device includes a memory module, and the error correction capability evaluation method includes: establishing an automated test script, wherein the automated test script is programmed based on a Shell script; and running the automated test script to execute an automated test program for an error correction circuit, wherein the automated test program includes: generating an error correction code corresponding to first test data through the error correction circuit; storing the first test data and the error correction code in the cache memory; reading the first test data from the cache memory; and inserting the first test data into the first test data read; The invention relates to a method for generating a second test data by reducing a pseudo error bit; setting the control bit corresponding to the error correction circuit to a first value to turn off the error correction circuit; storing the second test data in the cache memory when the error correction circuit is turned off; reading the second test data and the error correction code from the cache memory; setting the control bit corresponding to the error correction circuit to a second value to start the error correction circuit, wherein the second value is different from the second value; decoding the second test data through the error correction circuit based on the error correction code and obtaining a decoding result; and evaluating the error correction capability of the error correction circuit according to the decoding result.

[0007] Another embodiment of the present invention provides a data storage system, which includes a host system and a storage device. The host system is connected to the storage device. The host system is used to: establish an automated test script, wherein the automated test script is programmed based on a Shell script; and run the automated test script to execute an automated test program for the storage device, wherein the automated test program includes: generating an error correction code corresponding to first test data through an error correction circuit of the storage device; storing the first test data and the error correction code in a cache memory; reading the first test data from the cache memory of the storage device; inserting at least one pseudo error bit into the read first test data to generate second test data; setting the control bit corresponding to the error correction circuit to a first value to turn off the error correction circuit; storing the second test data in the cache memory when the error correction circuit is turned off; reading the second test data and the error correction code from the cache memory; setting the control bit corresponding to the error correction circuit to a second bit value to start the error correction circuit, wherein the second bit value is different from the second bit value; decoding the second test data through the error correction circuit based on the error correction code and obtaining a decoding result; and evaluating the error correction capability of the error correction circuit according to the decoding result. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of an operation flow of error correction capability evaluation according to an embodiment of the present invention;

[0012] Figures 5 to 7 is a schematic diagram of the operation flow of an automated testing program according to an embodiment of the present invention;

[0013] Figure 8 is a flow chart of an error correction capability evaluation method according to an embodiment of the present invention;

[0014] Fig. 9 is a flow chart of a method for evaluating error correction capability according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0017] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (embedded Multi-Media Card, eMMC), a universal flash storage (Universal Flash Storage, UFS), a fast peripheral component interconnect (Peripheral Component Interconnect Express, PCIExpress), a fast non-volatile memory (Non-Volatile Memory Express, NVM express), a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), a universal serial bus (Universal Serial Bus, USB) or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (for example, exchange signals, instructions and / or data).

[0018] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0020] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0021] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0024] In one embodiment, the memory controller 123 may further include an error correction circuit (also referred to as a decoding circuit) 25. The error correction circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the error correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0025] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile storage of data.

[0026] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0027] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0028] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0029] In one embodiment, a physical erase unit may include a plurality of physical programming units. A plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to a plurality of physical programming units in the physical erase unit to change the threshold voltage of at least a portion of the storage cells in these physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared. In one embodiment, a physical erase unit may be regarded as a physical block.

[0030] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0031] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0032] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0033] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0034] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0035] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0036] In one embodiment, the host system 11 can create a script (also called an automated test script). A script is a specific type of program or code snippet, which is usually used to automate simple tasks. Scripts are usually written in an interpreted language, which means that they can be run directly without going through a compilation process. Scripting languages ​​are designed to be relatively simple and easy to learn, suitable for rapid development and execution of small-scale tasks. For example, the automated test script can be programmed based on a Shell script. In one embodiment, the automated test script can also be programmed based on Python, Bash, Perl or other types of scripting languages, which are not limited by the present invention.

[0037] In one embodiment, after the automated test script is established, the host system 11 may run the automated test script to execute an automated test program for the storage device 12 (or the error correction circuit 25). The automated test program may be used to detect and evaluate the error correction capability of the storage device 12 (or the error correction circuit 25). For example, the error correction capability of the error correction circuit 25 may be positively correlated to the error correction capability of the error correction circuit 25 for data read from the memory module 122. That is, if the error correction capability of the error correction circuit 25 is stronger, it means that the error correction capability of the error correction circuit 25 for data read from the memory module 122 is stronger.

[0038] In one embodiment, before executing the automated test program, the host system 11 may obtain test data (also referred to as first test data). After obtaining the first test data, the host system 11 may execute the automated test program based on the first test data through the automated test script.

[0039] In one embodiment, the host system 11 can create another script (also called a test data generation script). AWK is a programming language originally developed by Alfred Aho, Peter Weinberger and Brian Kernighan in the late 1970s. It is designed for text processing, especially for processing data and generating reports in the Unix operating system. The name of AWK comes from the first letters of the surnames of these three developers. AWK is very suitable for processing structured text data, such as log file analysis, data cleaning, simple statistical analysis, etc. Due to its concise syntax and powerful text processing capabilities, AWK has become one of the common tools for many system administrators and developers. For example, the test data generation script can be programmed based on an AWK script. Similar to an automated test script, a test data generation script can also be programmed based on Python, Bash, Perl or other types of scripting languages, which are not limited by the present invention.

[0040] In one embodiment, after the test data generation script is established, the host system 11 can generate the first test data through the test data generation script. For example, the first test data can be random data or regular data (ie, non-random data), which is not limited in the present invention.

[0041] Figure 4 FIG. 1 is a schematic diagram of the operation flow of the error correction capability evaluation method according to an embodiment of the present invention. Figure 4 In one embodiment, the host system 11 may pre-establish a test data generation script 41 and an automated test script 42. The host system 11 may run the test data generation script 41 and generate test data 401 (i.e., first test data) through the test data generation script 41. After generating the test data 401, the host system 11 may run the automated test script 42 and execute an automated test program 402 for the storage device 12 (or the error correction circuit 25) through the automated test script 42.

[0042] In one embodiment, the host system 11 may pre-establish a plurality of test data (also referred to as candidate test data) through the test data generation script 41. Then, the host system 11 may generate first test data according to at least one of the plurality of candidate test data through the test data generation script 41. For example, the plurality of candidate test data may be stored in a test data pool. When necessary, the host system 11 may obtain at least one test data from the test data pool as the first test data through the test data generation script 41.

[0043] In one embodiment, the host system 11 may select one of the plurality of candidate test data as the first test data through the test data generation script 41. Alternatively, in one embodiment, the host system 11 may perform a logic operation on at least one of the plurality of candidate test data to generate the first test data through the test data generation script 41. For example, the logic operation may include an exclusive OR (XOR) operation, a modulus (mod) operation, and / or other operations, which are not limited by the present invention. For example, the logic operation may be defined in the test data generation script 41.

[0044] In one embodiment, after obtaining the first test data, the host system 11 may automatically start the error correction circuit 25 through the automated test script 42. When the error correction circuit 25 is started, the host system 11 may generate an error correction code corresponding to the first test data through the error correction circuit 25. For example, the error correction code may be generated by encoding the first test data through the error correction circuit 25. The error correction code may be used to protect the first test data and / or detect errors in the first test data.

[0045] In one embodiment, the format of the error correction code may match the encoding and decoding algorithm used by the error correction circuit 25. For example, assuming that the encoding and decoding algorithm used by the error correction circuit 25 is a low-density parity check code, the format of the error correction code may match the low-density parity check code. However, the error correction circuit 25 may also use other types of encoding and decoding algorithms, and the present invention is not limited thereto.

[0046] In one embodiment, the host system 11 can automatically generate a write instruction (also referred to as a first write instruction) through the automated test script 42. The host system 11 can transmit the first write instruction to the storage device 12 through the automated test script 42. The first write instruction is used to instruct the storage device 12 to store the first test data and the error correction code in the cache memory in the memory module 122. For example, the data lengths of the first test data and the error correction code can be 1024 Bytes and 128 Bytes respectively, and the data lengths of the first test data and the error correction code can be adjusted according to practical requirements.

[0047] In one embodiment, the automated test script 42 may define the row address (ROW_ADDRESS) to be written by the first write instruction, the data file (DATA_FILE) to be written, and the path of the cache memory for caching data.

[0048] It should be noted that the cache memory does not belong to the memory array (also called memory cell array) inside the memory module 122. For example, a memory array may include multiple memory cells and be used to store data in a non-volatile manner. For example, multiple memory cells located on the same word line in the memory array may be used to store data belonging to the same physical programming unit (e.g., physical page). In addition, a physical erase unit (e.g., physical block) in the memory array may include memory cells located on multiple word lines.

[0049] In one embodiment, the cache memory may be used to cache data to be written to the memory array in the memory module 122 and / or data read from the memory array. For example, the cache memory may include cache registers, page registers and / or other types of registers (or buffers), and the present invention is not limited thereto.

[0050] In one embodiment, before writing the data to be written to the memory array in the memory module 122, the data to be written transmitted to the memory module 122 may be first cached in the cache register of the memory module 122. Then, the memory controller 123 may send a program command to the memory module 122 to instruct the memory module 122 to write the data currently cached in the cache register to the memory array in the memory module 122. On the other hand, when reading data from the memory array in the memory module 122, the data read from the memory array may be first cached in the cache register. Then, the memory controller 123 may send a read command to the memory module 122 to instruct the memory module 122 to transmit the data currently cached in the cache register to the memory controller 123 or the host system 11.

[0051] In one embodiment, the page register may be arranged between the cache register and the memory array. In one embodiment, after the data to be written is cached in the cache register, when the page register in the memory module 122 is idle, the data may be further moved to the page register in the memory module 122. Then, the memory module 122 may write the data currently cached in the page register to the memory array in the memory module 122. On the other hand, when reading data from the memory array in the memory module 122, the data read from the memory array may be first cached in the page register of the memory module 122. Then, when the cache register is idle, the data currently cached in the page register may be moved to the cache register. Then, the memory controller 123 may send a read command to the memory module 122 to instruct the memory module 122 to transmit the data currently cached in the cache register to the memory controller 123 or the host system 11.

[0052] In one embodiment, after the first test data and the error correction code are stored in the cache memory, the first test data and the error correction code may be temporarily saved (e.g., cached) in the cache memory. It should be noted that the first test data and the error correction code will not be further written to any memory array inside the memory module 122. Thus, the wear of the memory array may be prevented from increasing rapidly due to the execution of the automated test program 402. Thus, the service life of the storage device 12 may be extended.

[0053] In one embodiment, after storing the first test data and the error correction code in the cache memory, the host system 11 can automatically generate a read instruction (also referred to as a first read instruction) through the automated test script 42. The host system 11 can transmit the first read instruction to the storage device 12 through the automated test script 42. The first read instruction is used to instruct the storage device 12 to read the first test data from the cache memory. For example, the first read instruction can point to the storage location of the first test data in the cache memory. It should be noted that the reading of the first test data here can also be used to simulate the same reading environment (or reading condition) as the subsequent reading of the second test data to improve the accuracy of the test.

[0054] In one embodiment, after reading the first test data from the cache memory, the host system 11 may insert at least one error bit (also referred to as a pseudo error bit) into the read first test data to generate another test data (also referred to as second test data) through the automated test script 42. In particular, due to the influence of the pseudo error bit, the data content of the second test data may be different from the (original) data content of the first test data.

[0055] In one embodiment, during the process of inserting the at least one pseudo error bit, the host system 11 can automatically perform bit flipping on at least one bit of the read first test data to generate the second test data through the automated test script 42. Each flipped bit can be regarded as a pseudo error bit. In addition, the total number of the pseudo error bits can be one or more, which is not limited by the present invention.

[0056] In one embodiment, the host system 11 may also record the distribution (i.e., location) of the pseudo errors in the second test data through the automated test script 42. For example, the host system 11 may record the distribution of the pseudo errors in the second test data in reference data. Thereafter, the reference data may also be used to evaluate the error correction capability of the error correction circuit 25.

[0057] In one embodiment, the host system 11 can determine a target rule from at least one flip rule (also referred to as a candidate rule) through the automated test script 42. The host system 11 can insert the at least one false error bit into the first test data read according to the target rule through the automated test script 42.

[0058] In one embodiment, the at least one candidate rule may include at least one of the following rules: the total number of the at least one pseudo error bit must be greater than a first critical value, the total number of the at least one pseudo error bit must be less than a second critical value, the total number of the at least one pseudo error bit must be equal to a third critical value, the arrangement of the at least one pseudo error bit must meet a first preset condition, or the bit value distribution of the at least one pseudo error bit must meet a second preset condition. The first critical value, the second critical value, and the third critical value can be set to any positive integer according to practical requirements, and the present invention is not limited thereto.

[0059] In one embodiment, the first preset condition can be used to define the arrangement rule of the at least one pseudo error in the second test data, for example, the at least one pseudo error bit needs to be arranged continuously and / or discontinuously in the second test data, etc. In one embodiment, the second preset condition can be used to define the bit value distribution of the at least one pseudo error in the second test data, for example, the at least one pseudo error in the second test data needs to be arranged in a manner of "0" and "1" interlaced, continuous "0" and / or continuous "1", etc. In addition, the candidate rules can also be adjusted according to practical needs, and the present invention is not limited thereto.

[0060] In one embodiment, the at least one candidate rule includes a first rule and a second rule. In particular, at least one pseudo error bit (also referred to as a first pseudo error bit) inserted according to the first rule is different from at least one pseudo error bit (also referred to as a second pseudo error bit) inserted according to the second rule. For example, when the target rule is the first rule, the total number, arrangement and / or bit value distribution of the first pseudo error bits inserted into the first test data may be different from the total number, arrangement and / or bit value distribution of the second pseudo error bits inserted into the first test data when the target rule is the second rule.

[0061] In one embodiment, the host system 11 can automatically turn off the error correction circuit 25 through the automated test script 42. For example, through the automated test script 42, the host system 11 can automatically set (e.g., update) the control bit corresponding to the error correction circuit 25 to a certain bit value (also referred to as the first bit value) to turn off the error correction circuit 25. For example, the control bit can be stored in a register (also referred to as a control register) inside or outside the error correction circuit 25. The control bit can be used to control the activation or deactivation of the error correction circuit 25. In particular, when the error correction circuit 25 is turned off, the error correction circuit 25 will not operate (e.g., will not generate an error correction code corresponding to the second test data).

[0062] In one embodiment, when the error correction circuit 25 is turned off, the host system 11 can automatically generate a write instruction (also referred to as a second write instruction). Through the automated test script 42, the host system 11 can transmit the second write instruction to the storage device 12. The second write instruction is used to instruct the storage device 12 to store the second test data in the cache memory.

[0063] In one embodiment, the automated test script 42 may define the row address (ROW_ADDRESS) to be written by the second write instruction, the data file (DATA_FILE) to be written, and the path of the cache memory for caching data.

[0064] It should be noted that, similar to the first test data and the error correction code, the second test data can be temporarily stored (e.g., cached) in the cache memory. However, the second test data will not be further written to any memory array inside the memory module 122. Thus, the wear of the memory array can be quickly increased due to the execution of the automated test program 402. Thus, the service life of the storage device 12 can be extended.

[0065] In one embodiment, the second test data cached in the cache memory may be used to replace the first test data previously cached in the cache memory. For example, the second test data may cover (e.g., overwrite) the first test data previously cached in the cache memory. Alternatively, in one embodiment, the first test data and the second test data may be cached in different storage areas in the cache memory at the same time, and the present invention is not limited thereto. In one embodiment, if the first test data is not overwritten by the second test data, the same first test data may be read multiple times and used to generate different second test data in multiple test procedures.

[0066] In one embodiment, after storing the second test data in the cache memory, the host system 11 may automatically generate a read instruction (also referred to as a second read instruction) through the automated test script 42. The host system 11 may transmit the second read instruction to the storage device 12 through the automated test script 42. The second read instruction is used to instruct the storage device 12 to read the second test data and the error correction code from the cache memory. For example, the second read instruction may point to the storage location of the second test data and the error correction code in the cache memory.

[0067] In one embodiment, the host system 11 can automatically start the error correction circuit 25 through the automated test script 42. For example, through the automated test script 42, the host system 11 can automatically set (e.g., update) the control bit corresponding to the error correction circuit 25 to a certain bit value (also referred to as a second bit value) to start the error correction circuit 25. The second bit value is different from the first bit value. For example, when the control bit is the first bit value, the error correction circuit 25 is automatically in a closed state. When the control bit is the second bit value, the error correction circuit 25 is automatically in an activated state. Therefore, by setting (e.g., updating) the control bit, the error correction circuit 25 can be switched between a closed state and an activated state.

[0068] In one embodiment, the host system 11 can also control or change the operation mode of the error correction circuit 25 through the automated test script 42. For example, through the automated test script 42, the host system 11 can automatically adjust the operation mode of the error correction circuit 25 from a certain operation mode (also referred to as the first operation mode) to another operation mode (also referred to as the second operation mode). Thus, through the automated test script 42, the host system 11 can evaluate the error correction capability of the error correction circuit 25 in the second operation mode. Alternatively, in one embodiment, through the automated test script 42, the host system 11 can also maintain the operation mode of the error correction circuit 25 in the first operation mode to evaluate the error correction capability of the error correction circuit 25 in the first operation mode.

[0069] In one embodiment, the operation mode of the error correction circuit 25 may include a hard decoding mode, a soft decoding mode and / or other types of custom decoding modes, which are not limited by the present invention. For example, compared to the hard decoding mode, in the soft decoding mode, the error correction circuit 25 may use more auxiliary information to decode the data (such as the second test data) to improve the error correction capability of the error correction circuit 25. However, compared to the hard decoding mode, in the soft decoding mode, the error correction circuit 25 needs to spend more time to perform the decoding process.

[0070] In one embodiment, after reading the second test data and the error correction code, when the error correction circuit 25 is activated (and operates in a specific operation mode), the host system 11 can decode the second test data based on the error correction code through the error correction circuit 25 and obtain a decoding result through the automated test script 42. For example, the decoding result can reflect whether the decoding of the second test data by the error correction circuit 25 is successful or failed. In one embodiment, when the decoding of the second test data by the error correction circuit 25 fails, the decoding result can also reflect which bits in the second test data are flipped (i.e., corrected) when the decoding of the second test data by the error correction circuit 25 is performed.

[0071] In one embodiment, after obtaining the decoding result, the host system 11 can automatically evaluate the error correction capability of the error correction circuit 25 according to the decoding result through the automated test script 42. For example, the host system 11 can automatically generate evaluation information related to the error correction capability of the error correction circuit 25 according to the decoding result through the automated test script 42. For example, the evaluation information can be provided to the administrator as a reference or basis for managing the storage device 12 (for example, modifying the firmware used by the error correction circuit 25 and / or the hardware of the error correction circuit 25).

[0072] In one embodiment, through the automated test script 42, if the decoding result is a successful decoding, the host system 11 can automatically generate a certain evaluation information (also referred to as the first evaluation information). For example, the first evaluation information can reflect that the error correction circuit 25 has successfully detected all errors (including the inserted pseudo error bits) in the current second test data. In this case, the management personnel can know based on the first evaluation information that the error correction capability of the current error correction circuit 25 is higher than a specific level. At the same time, the management personnel can consider reducing the firmware and / or hardware performance of the error correction circuit 25 to save system resources or maintain the configuration of the current error correction circuit 25, etc., which is not limited by the present invention.

[0073] On the other hand, through the automated test script 42, if the decoding result is a decoding failure, the host system 11 can automatically generate another evaluation information (also referred to as the second evaluation information). For example, the second evaluation information can reflect that the error correction circuit 25 cannot completely detect all errors (including the inserted pseudo error bits) in the current second test data. In this case, the management personnel can know based on the second evaluation information that the error correction capability of the current error correction circuit 25 is lower than a specific level. At the same time, the management personnel can consider adjusting the firmware and / or hardware configuration of the error correction circuit 25 to improve the error correction capability of the error correction circuit 25.

[0074] In one embodiment, through the automated test script 42, if the decoding result is a decoding failure, the host system 11 can also automatically compare the decoding result with the reference data to obtain a comparison result. For example, the reference data can reflect the distribution of the at least one pseudo error previously inserted in the second test data. Then, through the automated test script 42, the memory control circuit 23 can automatically generate the second evaluation information according to the comparison result.

[0075] In one embodiment, compared to the second evaluation information that only reflects the decoding failure, the second evaluation information generated according to the comparison result may carry more information. For example, the second evaluation information generated according to the comparison result may reflect which error bits are detected and / or which error bits are not detected (i.e., omitted) in the second test data. All of this information can be obtained by comparing the decoding result with the reference data. As a result, the management personnel can manage or adjust the storage device 12 more accurately to effectively improve the error correction capability of the error correction circuit 25.

[0076] Figures 5 to 7 Schematic diagram of the operation flow of the automated testing program according to an embodiment of the present invention. Figure 5 , assuming that the memory module 122 includes a cache memory 510 and a memory array 520. In general, the cache memory 510 can be used to cache data between the memory control circuit 23 and the memory array 520. However, in the automated test procedure proposed by the present invention, the test data (i.e., the first test data and the second test data) and the related error correction code can be cached in the cache memory 510, but will not be further stored in the memory array 520.

[0077] In one embodiment, it is assumed that the first test data includes data 51. It should be noted that the data length of data 51 is only an example and is not intended to limit the present invention. Figure 4 According to the automated test script 42, the error correction code 501 corresponding to the data 51 can be automatically generated through the error correction circuit 25. Then, the data 51 and the error correction code 501 can be stored (e.g., cached) in the cache memory 510. It should be noted that the data 51 and the error correction code 501 will not be further stored in the memory array 520.

[0078] Please refer to Figure 6 , continued by Figure 5 In the embodiment, after storing the data 51 and the error correction code 501 in the cache memory 510, based on Figure 4 According to the automated test script 42, data 51 may be read from the cache memory 510. After reading the data 51 from the cache memory 510, the host system 11 may automatically insert at least one false error bit into the read data 51 to generate the second test data. For example, the second test data includes data 61. Figure 6 For example, the difference between data 51 and data 61 (eg, the third bit in data 61 changes from “0” to “1”) is generated by inserting the at least one false error bit into data 51 .

[0079] On the other hand, the host system 11 can automatically disable the error correction circuit 25. When the error correction circuit 25 is disabled, the host system 11 can store the uncoded data 61 in the cache memory 510. It should be noted that, similar to the data 51 and the error correction code 501, the data 61 will not be further stored in the memory array 520.

[0080] Please refer to Figure 7 , continued by Figure 6 In the embodiment, after storing the data 61 in the cache memory 510, based on Figure 4 According to the automated test script 42 , the data 61 and the error correction code 501 can be read from the cache memory 510 .

[0081] On the other hand, the host system 11 can automatically start the error correction circuit 25. In the started state, the error correction circuit 25 can automatically decode the data 61 based on the error correction code 501 and obtain the decoding result 71. Thereafter, the host system 11 can evaluate the error correction capability of the error correction circuit 25 based on the decoding result 71. It should be noted that Figures 5 to 7 The relevant operation details have been described above and will not be repeated here.

[0082] In one embodiment, the operations performed by the host system 11 may be performed by a processor in the host system 11. For example, the processor in the host system 11 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations of these devices. In one embodiment, the error correction circuit 25 may also be disposed in the host system 11.

[0083] Figure 8 is a flow chart of an error correction capability evaluation method according to an embodiment of the present invention. Figure 8 In step S801, an automated test script is established, wherein the automated test script is programmed based on a Shell script. In step S802, the automated test script is run to execute an automated test program for an error correction circuit of a storage device.

[0084] Fig. 9 is a flow chart of an error correction capability evaluation method according to an embodiment of the present invention. Fig. 9In step S901, an error correction code corresponding to the first test data is generated by an error correction circuit. In step S902, the first test data and the error correction code are stored in a cache memory. In step S903, the first test data is read from the cache memory. In step S904, at least one pseudo error bit is inserted into the read first test data to generate second test data. In step S905, the second test data is stored in the cache memory when the error correction circuit is turned off. In step S906, the second test data and the error correction code are read from the cache memory. In step S907, based on the error correction code, the second test data is decoded by the error correction circuit and a decoding result is obtained. In step S908, the error correction capability of the error correction circuit is evaluated according to the decoding result.

[0085] However, Figure 8 and Fig. 9 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 8 and Fig. 9 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 8 and Fig. 9 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0086] In summary, the error correction capability evaluation method and data storage system proposed in the embodiments of the present invention can automatically execute the automated test program for the error correction circuit of the storage device through a pre-established automated test script, and will not increase the wear of the memory array in the storage device, which helps to extend the service life of the storage device. Furthermore, the automated test script can quickly, repeatedly, and accurately verify the error correction probability of the error correction circuit in the storage device for one or more distribution patterns of erroneous data one or more times, and then realize the analysis of the error correction capability of the error correction circuit through a big data model.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for evaluating error correction capability, characterized in that: For use in a storage device, wherein the storage device comprises a memory module, and the error correction capability evaluation method comprises: Establishing an automated test script, wherein the automated test script is programmed based on a Shell script; and Running the automated test script to execute an automated test program for the error correction circuit, The automated testing procedures include: generating an error correction code corresponding to the first test data by the error correction circuit; storing the first test data and the error correction code in a cache memory; reading the first test data from the cache memory; inserting at least one false error bit into the first test data read to generate second test data; setting a control bit corresponding to the error correction circuit to a first value to turn off the error correction circuit; storing the second test data in the cache memory when the error correction circuit is turned off; reading the second test data and the error correction code from the cache memory; setting the control bit corresponding to the error correction circuit to a second bit value to enable the error correction circuit, wherein the second bit value is different from the first bit value; Based on the error correction code, the second test data is decoded by the error correction circuit to obtain a decoding result; and The error correction capability of the error correction circuit is evaluated according to the decoding result.

2. The error correction capability evaluation method according to claim 1, further comprising: Establishing a test data generation script, wherein the test data generation script is programmed based on an AWK script; as well as The first test data is generated by generating a script using the test data.

3. The error correction capability evaluation method according to claim 2, wherein the step of generating the first test data by generating a script through the test data comprises: Pre-establishing a plurality of candidate test data by generating a script based on the test data; as well as The first test data is generated according to at least one of the plurality of candidate test data.

4. The error correction capability evaluation method according to claim 1 , wherein the step of inserting the at least one dummy error bit into the read first test data to generate the second test data comprises: determining a target rule from at least one candidate rule; as well as According to the target rule, the at least one dummy error bit is inserted into the read first test data.

5. The error correction capability evaluation method according to claim 4, wherein the at least one candidate rule comprises at least one of the following rules: The total number of the at least one pseudo error bit must be greater than a first critical value, the total number of the at least one pseudo error bit must be less than a second critical value, the total number of the at least one pseudo error bit must be equal to a third critical value, the arrangement of the at least one pseudo error bit must meet a first preset condition, or the bit value distribution of the at least one pseudo error bit must meet a second preset condition.

6. The error correction capability evaluation method according to claim 4, wherein the at least one candidate rule comprises a first rule and a second rule, and the at least one first pseudo error bit inserted according to the first rule is different from the at least one second pseudo error bit inserted according to the second rule.

7. The error correction capability evaluation method according to claim 1, wherein the step of setting the control bit corresponding to the error correction circuit to the second bit value to start the error correction circuit comprises: The operation mode of the error correction circuit is adjusted from a first operation mode to a second operation mode to evaluate the error correction capability of the error correction circuit in the second operation mode.

8. The error correction capability evaluation method according to claim 1, wherein the step of evaluating the error correction capability of the error correction circuit according to the decoding result comprises: If the decoding result is successful, generating first evaluation information; If the decoding result is a decoding failure, second evaluation information is generated.

9. The error correction capability evaluation method according to claim 8, wherein the step of generating the second evaluation information comprises: Comparing the decoding result with reference data to obtain a comparison result, wherein the reference data reflects the distribution of the at least one pseudo error in the second test data; as well as The second evaluation information is generated according to the comparison result.

10. The error correction capability evaluation method according to claim 1, wherein the cache memory does not belong to a memory array inside the memory module.

11. A data storage system, characterized in that: include: Host system; as well as a storage device, connected to the host system, The host system is used to: Establishing an automated test script, wherein the automated test script is programmed based on a Shell script; as well as Running the automated test script to execute an automated test program for the storage device, The automated testing procedures include: generating an error correction code corresponding to the first test data by an error correction circuit of the storage device; storing the first test data and the error correction code in a cache memory of the storage device; reading the first test data from the cache memory; inserting at least one false error bit into the first test data read to generate second test data; setting a control bit corresponding to the error correction circuit to a first value to turn off the error correction circuit; storing the second test data in the cache memory when the error correction circuit is turned off; reading the second test data and the error correction code from the cache memory; setting the control bit corresponding to the error correction circuit to a second bit value to enable the error correction circuit, wherein the second bit value is different from the first bit value; Based on the error correction code, the second test data is decoded by the error correction circuit to obtain a decoding result; and The error correction capability of the error correction circuit is evaluated according to the decoding result.

12. The data storage system according to claim 11, wherein the host system is further configured to: Establishing a test data generation script, wherein the test data generation script is programmed based on an AWK script; and The first test data is generated by generating a script using the test data.

13. The data storage system according to claim 12, wherein the operation of generating the first test data by the test data generation script comprises: Pre-establishing a plurality of candidate test data by generating a script based on the test data; as well as The first test data is generated according to at least one of the plurality of candidate test data.

14. The data storage system according to claim 11, wherein the operation of inserting the at least one dummy error bit into the read first test data to generate the second test data comprises: determining a target rule from at least one candidate rule; as well as According to the target rule, the at least one dummy error bit is inserted into the read first test data.

15. The data storage system according to claim 14, wherein the at least one candidate rule comprises at least one of the following rules: The total number of the at least one pseudo error bit must be greater than a first critical value, the total number of the at least one pseudo error bit must be less than a second critical value, the total number of the at least one pseudo error bit must be equal to a third critical value, the arrangement of the at least one pseudo error bit must meet a first preset condition, or the bit value distribution of the at least one pseudo error bit must meet a second preset condition. 16 . The data storage system of claim 14 , wherein the at least one candidate rule comprises a first rule and a second rule, and at least one first pseudo error bit inserted according to the first rule is different from at least one second pseudo error bit inserted according to the second rule.

17. The data storage system of claim 11, wherein setting the control bit corresponding to the error correction circuit to the second bit value to enable operation of the error correction circuit comprises: The operation mode of the error correction circuit is adjusted from a first operation mode to a second operation mode to evaluate the error correction capability of the error correction circuit in the second operation mode.

18. The data storage system according to claim 11, wherein the operation of evaluating the error correction capability of the error correction circuit according to the decoding result comprises: If the decoding result is successful, generating first evaluation information; If the decoding result is a decoding failure, second evaluation information is generated.

19. The data storage system according to claim 18, wherein the step of generating the second evaluation information comprises: Comparing the decoding result with reference data to obtain a comparison result, wherein the reference data reflects the distribution of the at least one pseudo error in the second test data; as well as The second evaluation information is generated according to the comparison result.

20. The data storage system of claim 11, wherein the cache memory does not belong to a memory array inside a memory module of the storage device.

Images